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ARM: dts: omap: correct indentation

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Link: https://lore.kernel.org/r/20221002092002.68880-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Krzysztof Kozlowski 8ae9c7a6 eab1e910

+97 -97
+3 -3
arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
··· 8 8 9 9 / { 10 10 vddvario: regulator-vddvario { 11 - compatible = "regulator-fixed"; 12 - regulator-name = "vddvario"; 13 - regulator-always-on; 11 + compatible = "regulator-fixed"; 12 + regulator-name = "vddvario"; 13 + regulator-always-on; 14 14 }; 15 15 16 16 vdd33a: regulator-vdd33a {
+3 -3
arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
··· 12 12 13 13 / { 14 14 vddvario: regulator-vddvario { 15 - compatible = "regulator-fixed"; 16 - regulator-name = "vddvario"; 17 - regulator-always-on; 15 + compatible = "regulator-fixed"; 16 + regulator-name = "vddvario"; 17 + regulator-always-on; 18 18 }; 19 19 20 20 vdd33a: regulator-vdd33a {
+6 -6
arch/arm/boot/dts/omap3-cm-t3517.dts
··· 11 11 model = "CompuLab CM-T3517"; 12 12 compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; 13 13 14 - vmmc: regulator-vmmc { 15 - compatible = "regulator-fixed"; 16 - regulator-name = "vmmc"; 17 - regulator-min-microvolt = <3300000>; 18 - regulator-max-microvolt = <3300000>; 19 - }; 14 + vmmc: regulator-vmmc { 15 + compatible = "regulator-fixed"; 16 + regulator-name = "vmmc"; 17 + regulator-min-microvolt = <3300000>; 18 + regulator-max-microvolt = <3300000>; 19 + }; 20 20 21 21 wl12xx_vmmc2: wl12xx_vmmc2 { 22 22 compatible = "regulator-fixed";
+3 -3
arch/arm/boot/dts/omap3-gta04.dtsi
··· 332 332 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ 333 333 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ 334 334 >; 335 - }; 335 + }; 336 336 337 337 gps_pins: pinmux_gps_pins { 338 338 pinctrl-single,pins = < ··· 853 853 }; 854 854 855 855 &hdqw1w { 856 - pinctrl-names = "default"; 857 - pinctrl-0 = <&hdq_pins>; 856 + pinctrl-names = "default"; 857 + pinctrl-0 = <&hdq_pins>; 858 858 }; 859 859 860 860 /* image signal processor within OMAP3 SoC */
+1 -1
arch/arm/boot/dts/omap3-ldp.dts
··· 301 301 302 302 &vaux1 { 303 303 /* Needed for ads7846 */ 304 - regulator-name = "vcc"; 304 + regulator-name = "vcc"; 305 305 };
+19 -19
arch/arm/boot/dts/omap3-n900.dts
··· 236 236 pinctrl-single,pins = < 237 237 238 238 /* address lines */ 239 - OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ 240 - OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ 241 - OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ 239 + OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ 240 + OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ 241 + OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ 242 242 243 243 /* data lines, gpmc_d0..d7 not muxable according to TRM */ 244 - OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ 245 - OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ 246 - OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ 247 - OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ 248 - OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ 249 - OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ 250 - OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ 251 - OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ 244 + OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ 245 + OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ 246 + OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ 247 + OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ 248 + OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ 249 + OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ 250 + OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ 251 + OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ 252 252 253 253 /* 254 254 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable 255 255 * according to TRM. OneNAND seems to require PIN_INPUT on clock. 256 256 */ 257 - OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ 258 - OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ 259 - >; 257 + OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ 258 + OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ 259 + >; 260 260 }; 261 261 262 262 i2c1_pins: pinmux_i2c1_pins { ··· 738 738 739 739 si4713: si4713@63 { 740 740 compatible = "silabs,si4713"; 741 - reg = <0x63>; 741 + reg = <0x63>; 742 742 743 - interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ 744 - reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ 745 - vio-supply = <&vio>; 746 - vdd-supply = <&vaux1>; 743 + interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ 744 + reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ 745 + vio-supply = <&vio>; 746 + vdd-supply = <&vaux1>; 747 747 }; 748 748 749 749 bq24150a: bq24150a@6b {
+22 -22
arch/arm/boot/dts/omap3-zoom3.dts
··· 23 23 }; 24 24 25 25 vddvario: regulator-vddvario { 26 - compatible = "regulator-fixed"; 27 - regulator-name = "vddvario"; 28 - regulator-always-on; 26 + compatible = "regulator-fixed"; 27 + regulator-name = "vddvario"; 28 + regulator-always-on; 29 29 }; 30 30 31 31 vdd33a: regulator-vdd33a { ··· 84 84 85 85 uart1_pins: pinmux_uart1_pins { 86 86 pinctrl-single,pins = < 87 - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ 88 - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ 89 - OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ 90 - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ 87 + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ 88 + OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ 89 + OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ 90 + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ 91 91 >; 92 92 }; 93 93 94 94 uart2_pins: pinmux_uart2_pins { 95 95 pinctrl-single,pins = < 96 - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ 97 - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ 98 - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 99 - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 96 + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ 97 + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ 98 + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 99 + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 100 100 >; 101 101 }; 102 102 103 103 uart3_pins: pinmux_uart3_pins { 104 104 pinctrl-single,pins = < 105 - OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ 106 - OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ 107 - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 108 - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 105 + OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ 106 + OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ 107 + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 108 + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 109 109 >; 110 110 }; 111 111 ··· 205 205 }; 206 206 207 207 &uart1 { 208 - pinctrl-names = "default"; 209 - pinctrl-0 = <&uart1_pins>; 208 + pinctrl-names = "default"; 209 + pinctrl-0 = <&uart1_pins>; 210 210 }; 211 211 212 212 &uart2 { 213 - pinctrl-names = "default"; 214 - pinctrl-0 = <&uart2_pins>; 213 + pinctrl-names = "default"; 214 + pinctrl-0 = <&uart2_pins>; 215 215 }; 216 216 217 217 &uart3 { 218 - pinctrl-names = "default"; 219 - pinctrl-0 = <&uart3_pins>; 218 + pinctrl-names = "default"; 219 + pinctrl-0 = <&uart3_pins>; 220 220 }; 221 221 222 222 &uart4 { 223 - status = "disabled"; 223 + status = "disabled"; 224 224 }; 225 225 226 226 &usb_otg_hs {
+12 -12
arch/arm/boot/dts/omap4-cpu-thermal.dtsi
··· 13 13 polling-delay = <1000>; /* milliseconds */ 14 14 15 15 /* sensor ID */ 16 - thermal-sensors = <&bandgap 0>; 16 + thermal-sensors = <&bandgap 0>; 17 17 18 18 cpu_trips: trips { 19 - cpu_alert0: cpu_alert { 20 - temperature = <100000>; /* millicelsius */ 21 - hysteresis = <2000>; /* millicelsius */ 22 - type = "passive"; 23 - }; 24 - cpu_crit: cpu_crit { 25 - temperature = <125000>; /* millicelsius */ 26 - hysteresis = <2000>; /* millicelsius */ 27 - type = "critical"; 28 - }; 29 - }; 19 + cpu_alert0: cpu_alert { 20 + temperature = <100000>; /* millicelsius */ 21 + hysteresis = <2000>; /* millicelsius */ 22 + type = "passive"; 23 + }; 24 + cpu_crit: cpu_crit { 25 + temperature = <125000>; /* millicelsius */ 26 + hysteresis = <2000>; /* millicelsius */ 27 + type = "critical"; 28 + }; 29 + }; 30 30 31 31 cpu_cooling_maps: cooling-maps { 32 32 map0 {
+28 -28
arch/arm/boot/dts/omap5-cm-t54.dts
··· 84 84 }; 85 85 86 86 lcd0: display { 87 - compatible = "startek,startek-kd050c", "panel-dpi"; 88 - label = "lcd"; 87 + compatible = "startek,startek-kd050c", "panel-dpi"; 88 + label = "lcd"; 89 89 90 - pinctrl-names = "default"; 91 - pinctrl-0 = <&lcd_pins>; 90 + pinctrl-names = "default"; 91 + pinctrl-0 = <&lcd_pins>; 92 92 93 - enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; 93 + enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; 94 94 95 - panel-timing { 96 - clock-frequency = <33000000>; 97 - hactive = <800>; 98 - vactive = <480>; 99 - hfront-porch = <40>; 100 - hback-porch = <40>; 101 - hsync-len = <43>; 102 - vback-porch = <29>; 103 - vfront-porch = <13>; 104 - vsync-len = <3>; 105 - hsync-active = <0>; 106 - vsync-active = <0>; 107 - de-active = <1>; 108 - pixelclk-active = <1>; 109 - }; 95 + panel-timing { 96 + clock-frequency = <33000000>; 97 + hactive = <800>; 98 + vactive = <480>; 99 + hfront-porch = <40>; 100 + hback-porch = <40>; 101 + hsync-len = <43>; 102 + vback-porch = <29>; 103 + vfront-porch = <13>; 104 + vsync-len = <3>; 105 + hsync-active = <0>; 106 + vsync-active = <0>; 107 + de-active = <1>; 108 + pixelclk-active = <1>; 109 + }; 110 110 111 - port { 112 - lcd_in: endpoint { 113 - remote-endpoint = <&dpi_lcd_out>; 114 - }; 115 - }; 116 - }; 111 + port { 112 + lcd_in: endpoint { 113 + remote-endpoint = <&dpi_lcd_out>; 114 + }; 115 + }; 116 + }; 117 117 118 118 hdmi0: connector0 { 119 119 compatible = "hdmi-connector"; ··· 644 644 }; 645 645 646 646 &usb3 { 647 - extcon = <&extcon_usb3>; 648 - vbus-supply = <&smps10_out1_reg>; 647 + extcon = <&extcon_usb3>; 648 + vbus-supply = <&smps10_out1_reg>; 649 649 }; 650 650 651 651 &cpu0 {