tjh.dev / kernel
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scsi/NCR5380: adopt NCR5380_dprint() and NCR5380_dprint_phase()

All NCR5380 drivers already include the NCR5380.h header. Better to
adopt those macros rather than have three variations on them.

Moreover, the macros in NCR5380.h are preferable anyway: the atari_NCR5380
and sun3_NCR5380 versions are inflexible. For example, they can't accomodate
NCR5380_dprint(NDEBUG_MAIN | NDEBUG_QUEUES, ...)

Replace the NCR_PRINT* macros from atari_NCR5380.h and sun3_NCR5380.h with
the equivalent macros from NCR5380.h.

Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
Acked-by: Sam Creasey <sammy@sammy.net>
Acked-by: Michael Schmitz <schmitz@debian.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>

authored by

Finn Thain and committed by
Christoph Hellwig 8ad3a593 52a6a1cb

+22 -22
+11 -11
drivers/scsi/atari_NCR5380.c
··· 739 739 Scsi_Cmnd *ptr; 740 740 unsigned long flags; 741 741 742 - NCR_PRINT(NDEBUG_ANY); 743 - NCR_PRINT_PHASE(NDEBUG_ANY); 742 + NCR5380_dprint(NDEBUG_ANY, instance); 743 + NCR5380_dprint_phase(NDEBUG_ANY, instance); 744 744 745 745 hostdata = (struct NCR5380_hostdata *)instance->hostdata; 746 746 ··· 1268 1268 INT_PRINTK("scsi%d: BASR=%02x\n", HOSTNO, basr); 1269 1269 /* dispatch to appropriate routine if found and done=0 */ 1270 1270 if (basr & BASR_IRQ) { 1271 - NCR_PRINT(NDEBUG_INTR); 1271 + NCR5380_dprint(NDEBUG_INTR, instance); 1272 1272 if ((NCR5380_read(STATUS_REG) & (SR_SEL|SR_IO)) == (SR_SEL|SR_IO)) { 1273 1273 done = 0; 1274 1274 ENABLE_IRQ(); ··· 1396 1396 unsigned long flags; 1397 1397 1398 1398 hostdata->restart_select = 0; 1399 - NCR_PRINT(NDEBUG_ARBITRATION); 1399 + NCR5380_dprint(NDEBUG_ARBITRATION, instance); 1400 1400 ARB_PRINTK("scsi%d: starting arbitration, id = %d\n", HOSTNO, 1401 1401 instance->this_id); 1402 1402 ··· 1617 1617 printk(KERN_ERR "scsi%d: weirdness\n", HOSTNO); 1618 1618 if (hostdata->restart_select) 1619 1619 printk(KERN_NOTICE "\trestart select\n"); 1620 - NCR_PRINT(NDEBUG_ANY); 1620 + NCR5380_dprint(NDEBUG_ANY, instance); 1621 1621 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); 1622 1622 return -1; 1623 1623 } ··· 1742 1742 /* Check for phase mismatch */ 1743 1743 if ((tmp & PHASE_MASK) != p) { 1744 1744 PIO_PRINTK("scsi%d: phase mismatch\n", HOSTNO); 1745 - NCR_PRINT_PHASE(NDEBUG_PIO); 1745 + NCR5380_dprint_phase(NDEBUG_PIO, instance); 1746 1746 break; 1747 1747 } 1748 1748 ··· 1764 1764 if (!(p & SR_IO)) { 1765 1765 if (!((p & SR_MSG) && c > 1)) { 1766 1766 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA); 1767 - NCR_PRINT(NDEBUG_PIO); 1767 + NCR5380_dprint(NDEBUG_PIO, instance); 1768 1768 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | 1769 1769 ICR_ASSERT_DATA | ICR_ASSERT_ACK); 1770 1770 } else { 1771 1771 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | 1772 1772 ICR_ASSERT_DATA | ICR_ASSERT_ATN); 1773 - NCR_PRINT(NDEBUG_PIO); 1773 + NCR5380_dprint(NDEBUG_PIO, instance); 1774 1774 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | 1775 1775 ICR_ASSERT_DATA | ICR_ASSERT_ATN | ICR_ASSERT_ACK); 1776 1776 } 1777 1777 } else { 1778 - NCR_PRINT(NDEBUG_PIO); 1778 + NCR5380_dprint(NDEBUG_PIO, instance); 1779 1779 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK); 1780 1780 } 1781 1781 ··· 1997 1997 phase = (tmp & PHASE_MASK); 1998 1998 if (phase != old_phase) { 1999 1999 old_phase = phase; 2000 - NCR_PRINT_PHASE(NDEBUG_INFORMATION); 2000 + NCR5380_dprint_phase(NDEBUG_INFORMATION, instance); 2001 2001 } 2002 2002 2003 2003 if (sink && (phase != PHASE_MSGOUT)) { ··· 2451 2451 break; 2452 2452 default: 2453 2453 printk("scsi%d: unknown phase\n", HOSTNO); 2454 - NCR_PRINT(NDEBUG_ANY); 2454 + NCR5380_dprint(NDEBUG_ANY, instance); 2455 2455 } /* switch(phase) */ 2456 2456 } /* if (tmp * SR_REQ) */ 2457 2457 } /* while (1) */
+11 -11
drivers/scsi/sun3_NCR5380.c
··· 681 681 Scsi_Cmnd *ptr; 682 682 unsigned long flags; 683 683 684 - NCR_PRINT(NDEBUG_ANY); 685 - NCR_PRINT_PHASE(NDEBUG_ANY); 684 + NCR5380_dprint(NDEBUG_ANY, instance); 685 + NCR5380_dprint_phase(NDEBUG_ANY, instance); 686 686 687 687 hostdata = (struct NCR5380_hostdata *)instance->hostdata; 688 688 ··· 1196 1196 INT_PRINTK("scsi%d: BASR=%02x\n", HOSTNO, basr); 1197 1197 /* dispatch to appropriate routine if found and done=0 */ 1198 1198 if (basr & BASR_IRQ) { 1199 - NCR_PRINT(NDEBUG_INTR); 1199 + NCR5380_dprint(NDEBUG_INTR, instance); 1200 1200 if ((NCR5380_read(STATUS_REG) & (SR_SEL|SR_IO)) == (SR_SEL|SR_IO)) { 1201 1201 done = 0; 1202 1202 // ENABLE_IRQ(); ··· 1338 1338 unsigned long flags; 1339 1339 1340 1340 hostdata->restart_select = 0; 1341 - NCR_PRINT(NDEBUG_ARBITRATION); 1341 + NCR5380_dprint(NDEBUG_ARBITRATION, instance); 1342 1342 ARB_PRINTK("scsi%d: starting arbitration, id = %d\n", HOSTNO, 1343 1343 instance->this_id); 1344 1344 ··· 1559 1559 printk(KERN_ERR "scsi%d: weirdness\n", HOSTNO); 1560 1560 if (hostdata->restart_select) 1561 1561 printk(KERN_NOTICE "\trestart select\n"); 1562 - NCR_PRINT(NDEBUG_ANY); 1562 + NCR5380_dprint(NDEBUG_ANY, instance); 1563 1563 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); 1564 1564 return -1; 1565 1565 } ··· 1685 1685 /* Check for phase mismatch */ 1686 1686 if ((tmp & PHASE_MASK) != p) { 1687 1687 PIO_PRINTK("scsi%d: phase mismatch\n", HOSTNO); 1688 - NCR_PRINT_PHASE(NDEBUG_PIO); 1688 + NCR5380_dprint_phase(NDEBUG_PIO, instance); 1689 1689 break; 1690 1690 } 1691 1691 ··· 1708 1708 if (!((p & SR_MSG) && c > 1)) { 1709 1709 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | 1710 1710 ICR_ASSERT_DATA); 1711 - NCR_PRINT(NDEBUG_PIO); 1711 + NCR5380_dprint(NDEBUG_PIO, instance); 1712 1712 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | 1713 1713 ICR_ASSERT_DATA | ICR_ASSERT_ACK); 1714 1714 } else { 1715 1715 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | 1716 1716 ICR_ASSERT_DATA | ICR_ASSERT_ATN); 1717 - NCR_PRINT(NDEBUG_PIO); 1717 + NCR5380_dprint(NDEBUG_PIO, instance); 1718 1718 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | 1719 1719 ICR_ASSERT_DATA | ICR_ASSERT_ATN | ICR_ASSERT_ACK); 1720 1720 } 1721 1721 } else { 1722 - NCR_PRINT(NDEBUG_PIO); 1722 + NCR5380_dprint(NDEBUG_PIO, instance); 1723 1723 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK); 1724 1724 } 1725 1725 ··· 1931 1931 phase = (tmp & PHASE_MASK); 1932 1932 if (phase != old_phase) { 1933 1933 old_phase = phase; 1934 - NCR_PRINT_PHASE(NDEBUG_INFORMATION); 1934 + NCR5380_dprint_phase(NDEBUG_INFORMATION, instance); 1935 1935 } 1936 1936 1937 1937 if(phase == PHASE_CMDOUT) { ··· 2416 2416 break; 2417 2417 default: 2418 2418 printk("scsi%d: unknown phase\n", HOSTNO); 2419 - NCR_PRINT(NDEBUG_ANY); 2419 + NCR5380_dprint(NDEBUG_ANY, instance); 2420 2420 } /* switch(phase) */ 2421 2421 } /* if (tmp * SR_REQ) */ 2422 2422 } /* while (1) */