Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

sh: dmaengine support for SH7757

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

authored by

Yoshihiro Shimoda and committed by
Paul Mundt
8ac53ed5 53bc18ef

+554 -1
+5
arch/sh/include/cpu-sh4/cpu/dma-register.h
··· 40 40 #define CHCR_TS_LOW_SHIFT 3 41 41 #define CHCR_TS_HIGH_MASK 0 42 42 #define CHCR_TS_HIGH_SHIFT 0 43 + #elif defined(CONFIG_CPU_SUBTYPE_SH7757) 44 + #define CHCR_TS_LOW_MASK 0x00000018 45 + #define CHCR_TS_LOW_SHIFT 3 46 + #define CHCR_TS_HIGH_MASK 0x00100000 47 + #define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ 43 48 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) 44 49 #define CHCR_TS_LOW_MASK 0x00000018 45 50 #define CHCR_TS_LOW_SHIFT 3
+32
arch/sh/include/cpu-sh4/cpu/sh7757.h
··· 251 251 GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0, 252 252 }; 253 253 254 + enum { 255 + SHDMA_SLAVE_SDHI_TX, 256 + SHDMA_SLAVE_SDHI_RX, 257 + SHDMA_SLAVE_MMCIF_TX, 258 + SHDMA_SLAVE_MMCIF_RX, 259 + SHDMA_SLAVE_SCIF2_TX, 260 + SHDMA_SLAVE_SCIF2_RX, 261 + SHDMA_SLAVE_SCIF3_TX, 262 + SHDMA_SLAVE_SCIF3_RX, 263 + SHDMA_SLAVE_SCIF4_TX, 264 + SHDMA_SLAVE_SCIF4_RX, 265 + SHDMA_SLAVE_RIIC0_TX, 266 + SHDMA_SLAVE_RIIC0_RX, 267 + SHDMA_SLAVE_RIIC1_TX, 268 + SHDMA_SLAVE_RIIC1_RX, 269 + SHDMA_SLAVE_RIIC2_TX, 270 + SHDMA_SLAVE_RIIC2_RX, 271 + SHDMA_SLAVE_RIIC3_TX, 272 + SHDMA_SLAVE_RIIC3_RX, 273 + SHDMA_SLAVE_RIIC4_TX, 274 + SHDMA_SLAVE_RIIC4_RX, 275 + SHDMA_SLAVE_RIIC5_TX, 276 + SHDMA_SLAVE_RIIC5_RX, 277 + SHDMA_SLAVE_RIIC6_TX, 278 + SHDMA_SLAVE_RIIC6_RX, 279 + SHDMA_SLAVE_RIIC7_TX, 280 + SHDMA_SLAVE_RIIC7_RX, 281 + SHDMA_SLAVE_RIIC8_TX, 282 + SHDMA_SLAVE_RIIC8_RX, 283 + SHDMA_SLAVE_RIIC9_TX, 284 + SHDMA_SLAVE_RIIC9_RX, 285 + }; 254 286 #endif /* __ASM_SH7757_H__ */
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arch/sh/kernel/cpu/sh4a/setup-sh7757.c
··· 1 1 /* 2 2 * SH7757 Setup 3 3 * 4 - * Copyright (C) 2009 Renesas Solutions Corp. 4 + * Copyright (C) 2009, 2011 Renesas Solutions Corp. 5 5 * 6 6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt 7 7 * ··· 16 16 #include <linux/io.h> 17 17 #include <linux/mm.h> 18 18 #include <linux/sh_timer.h> 19 + #include <linux/sh_dma.h> 20 + 21 + #include <cpu/dma-register.h> 22 + #include <cpu/sh7757.h> 19 23 20 24 static struct plat_sci_port scif2_platform_data = { 21 25 .mapbase = 0xfe4b0000, /* SCIF2 */ ··· 140 136 }, 141 137 }; 142 138 139 + /* DMA */ 140 + static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = { 141 + { 142 + .slave_id = SHDMA_SLAVE_SDHI_TX, 143 + .addr = 0x1fe50030, 144 + .chcr = SM_INC | 0x800 | 0x40000000 | 145 + TS_INDEX2VAL(XMIT_SZ_16BIT), 146 + .mid_rid = 0xc5, 147 + }, 148 + { 149 + .slave_id = SHDMA_SLAVE_SDHI_RX, 150 + .addr = 0x1fe50030, 151 + .chcr = DM_INC | 0x800 | 0x40000000 | 152 + TS_INDEX2VAL(XMIT_SZ_16BIT), 153 + .mid_rid = 0xc6, 154 + }, 155 + { 156 + .slave_id = SHDMA_SLAVE_MMCIF_TX, 157 + .addr = 0x1fcb0034, 158 + .chcr = SM_INC | 0x800 | 0x40000000 | 159 + TS_INDEX2VAL(XMIT_SZ_32BIT), 160 + .mid_rid = 0xd3, 161 + }, 162 + { 163 + .slave_id = SHDMA_SLAVE_MMCIF_RX, 164 + .addr = 0x1fcb0034, 165 + .chcr = DM_INC | 0x800 | 0x40000000 | 166 + TS_INDEX2VAL(XMIT_SZ_32BIT), 167 + .mid_rid = 0xd7, 168 + }, 169 + }; 170 + 171 + static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = { 172 + { 173 + .slave_id = SHDMA_SLAVE_SCIF2_TX, 174 + .addr = 0x1f4b000c, 175 + .chcr = SM_INC | 0x800 | 0x40000000 | 176 + TS_INDEX2VAL(XMIT_SZ_8BIT), 177 + .mid_rid = 0x21, 178 + }, 179 + { 180 + .slave_id = SHDMA_SLAVE_SCIF2_RX, 181 + .addr = 0x1f4b0014, 182 + .chcr = SM_INC | 0x800 | 0x40000000 | 183 + TS_INDEX2VAL(XMIT_SZ_8BIT), 184 + .mid_rid = 0x22, 185 + }, 186 + { 187 + .slave_id = SHDMA_SLAVE_SCIF3_TX, 188 + .addr = 0x1f4c000c, 189 + .chcr = SM_INC | 0x800 | 0x40000000 | 190 + TS_INDEX2VAL(XMIT_SZ_8BIT), 191 + .mid_rid = 0x29, 192 + }, 193 + { 194 + .slave_id = SHDMA_SLAVE_SCIF3_RX, 195 + .addr = 0x1f4c0014, 196 + .chcr = SM_INC | 0x800 | 0x40000000 | 197 + TS_INDEX2VAL(XMIT_SZ_8BIT), 198 + .mid_rid = 0x2a, 199 + }, 200 + { 201 + .slave_id = SHDMA_SLAVE_SCIF4_TX, 202 + .addr = 0x1f4d000c, 203 + .chcr = SM_INC | 0x800 | 0x40000000 | 204 + TS_INDEX2VAL(XMIT_SZ_8BIT), 205 + .mid_rid = 0x41, 206 + }, 207 + { 208 + .slave_id = SHDMA_SLAVE_SCIF4_RX, 209 + .addr = 0x1f4d0014, 210 + .chcr = SM_INC | 0x800 | 0x40000000 | 211 + TS_INDEX2VAL(XMIT_SZ_8BIT), 212 + .mid_rid = 0x42, 213 + }, 214 + }; 215 + 216 + static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = { 217 + { 218 + .slave_id = SHDMA_SLAVE_RIIC0_TX, 219 + .addr = 0x1e500012, 220 + .chcr = SM_INC | 0x800 | 0x40000000 | 221 + TS_INDEX2VAL(XMIT_SZ_8BIT), 222 + .mid_rid = 0x21, 223 + }, 224 + { 225 + .slave_id = SHDMA_SLAVE_RIIC0_RX, 226 + .addr = 0x1e500013, 227 + .chcr = SM_INC | 0x800 | 0x40000000 | 228 + TS_INDEX2VAL(XMIT_SZ_8BIT), 229 + .mid_rid = 0x22, 230 + }, 231 + { 232 + .slave_id = SHDMA_SLAVE_RIIC1_TX, 233 + .addr = 0x1e510012, 234 + .chcr = SM_INC | 0x800 | 0x40000000 | 235 + TS_INDEX2VAL(XMIT_SZ_8BIT), 236 + .mid_rid = 0x29, 237 + }, 238 + { 239 + .slave_id = SHDMA_SLAVE_RIIC1_RX, 240 + .addr = 0x1e510013, 241 + .chcr = SM_INC | 0x800 | 0x40000000 | 242 + TS_INDEX2VAL(XMIT_SZ_8BIT), 243 + .mid_rid = 0x2a, 244 + }, 245 + { 246 + .slave_id = SHDMA_SLAVE_RIIC2_TX, 247 + .addr = 0x1e520012, 248 + .chcr = SM_INC | 0x800 | 0x40000000 | 249 + TS_INDEX2VAL(XMIT_SZ_8BIT), 250 + .mid_rid = 0xa1, 251 + }, 252 + { 253 + .slave_id = SHDMA_SLAVE_RIIC2_RX, 254 + .addr = 0x1e520013, 255 + .chcr = SM_INC | 0x800 | 0x40000000 | 256 + TS_INDEX2VAL(XMIT_SZ_8BIT), 257 + .mid_rid = 0xa2, 258 + }, 259 + { 260 + .slave_id = SHDMA_SLAVE_RIIC3_TX, 261 + .addr = 0x1e530012, 262 + .chcr = SM_INC | 0x800 | 0x40000000 | 263 + TS_INDEX2VAL(XMIT_SZ_8BIT), 264 + .mid_rid = 0xab, 265 + }, 266 + { 267 + .slave_id = SHDMA_SLAVE_RIIC3_RX, 268 + .addr = 0x1e530013, 269 + .chcr = SM_INC | 0x800 | 0x40000000 | 270 + TS_INDEX2VAL(XMIT_SZ_8BIT), 271 + .mid_rid = 0xaf, 272 + }, 273 + { 274 + .slave_id = SHDMA_SLAVE_RIIC4_TX, 275 + .addr = 0x1e540012, 276 + .chcr = SM_INC | 0x800 | 0x40000000 | 277 + TS_INDEX2VAL(XMIT_SZ_8BIT), 278 + .mid_rid = 0xc1, 279 + }, 280 + { 281 + .slave_id = SHDMA_SLAVE_RIIC4_RX, 282 + .addr = 0x1e540013, 283 + .chcr = SM_INC | 0x800 | 0x40000000 | 284 + TS_INDEX2VAL(XMIT_SZ_8BIT), 285 + .mid_rid = 0xc2, 286 + }, 287 + }; 288 + 289 + static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = { 290 + { 291 + .slave_id = SHDMA_SLAVE_RIIC5_TX, 292 + .addr = 0x1e550012, 293 + .chcr = SM_INC | 0x800 | 0x40000000 | 294 + TS_INDEX2VAL(XMIT_SZ_8BIT), 295 + .mid_rid = 0x21, 296 + }, 297 + { 298 + .slave_id = SHDMA_SLAVE_RIIC5_RX, 299 + .addr = 0x1e550013, 300 + .chcr = SM_INC | 0x800 | 0x40000000 | 301 + TS_INDEX2VAL(XMIT_SZ_8BIT), 302 + .mid_rid = 0x22, 303 + }, 304 + { 305 + .slave_id = SHDMA_SLAVE_RIIC6_TX, 306 + .addr = 0x1e560012, 307 + .chcr = SM_INC | 0x800 | 0x40000000 | 308 + TS_INDEX2VAL(XMIT_SZ_8BIT), 309 + .mid_rid = 0x29, 310 + }, 311 + { 312 + .slave_id = SHDMA_SLAVE_RIIC6_RX, 313 + .addr = 0x1e560013, 314 + .chcr = SM_INC | 0x800 | 0x40000000 | 315 + TS_INDEX2VAL(XMIT_SZ_8BIT), 316 + .mid_rid = 0x2a, 317 + }, 318 + { 319 + .slave_id = SHDMA_SLAVE_RIIC7_TX, 320 + .addr = 0x1e570012, 321 + .chcr = SM_INC | 0x800 | 0x40000000 | 322 + TS_INDEX2VAL(XMIT_SZ_8BIT), 323 + .mid_rid = 0x41, 324 + }, 325 + { 326 + .slave_id = SHDMA_SLAVE_RIIC7_RX, 327 + .addr = 0x1e570013, 328 + .chcr = SM_INC | 0x800 | 0x40000000 | 329 + TS_INDEX2VAL(XMIT_SZ_8BIT), 330 + .mid_rid = 0x42, 331 + }, 332 + { 333 + .slave_id = SHDMA_SLAVE_RIIC8_TX, 334 + .addr = 0x1e580012, 335 + .chcr = SM_INC | 0x800 | 0x40000000 | 336 + TS_INDEX2VAL(XMIT_SZ_8BIT), 337 + .mid_rid = 0x45, 338 + }, 339 + { 340 + .slave_id = SHDMA_SLAVE_RIIC8_RX, 341 + .addr = 0x1e580013, 342 + .chcr = SM_INC | 0x800 | 0x40000000 | 343 + TS_INDEX2VAL(XMIT_SZ_8BIT), 344 + .mid_rid = 0x46, 345 + }, 346 + { 347 + .slave_id = SHDMA_SLAVE_RIIC9_TX, 348 + .addr = 0x1e590012, 349 + .chcr = SM_INC | 0x800 | 0x40000000 | 350 + TS_INDEX2VAL(XMIT_SZ_8BIT), 351 + .mid_rid = 0x51, 352 + }, 353 + { 354 + .slave_id = SHDMA_SLAVE_RIIC9_RX, 355 + .addr = 0x1e590013, 356 + .chcr = SM_INC | 0x800 | 0x40000000 | 357 + TS_INDEX2VAL(XMIT_SZ_8BIT), 358 + .mid_rid = 0x52, 359 + }, 360 + }; 361 + 362 + static const struct sh_dmae_channel sh7757_dmae_channels[] = { 363 + { 364 + .offset = 0, 365 + .dmars = 0, 366 + .dmars_bit = 0, 367 + }, { 368 + .offset = 0x10, 369 + .dmars = 0, 370 + .dmars_bit = 8, 371 + }, { 372 + .offset = 0x20, 373 + .dmars = 4, 374 + .dmars_bit = 0, 375 + }, { 376 + .offset = 0x30, 377 + .dmars = 4, 378 + .dmars_bit = 8, 379 + }, { 380 + .offset = 0x50, 381 + .dmars = 8, 382 + .dmars_bit = 0, 383 + }, { 384 + .offset = 0x60, 385 + .dmars = 8, 386 + .dmars_bit = 8, 387 + } 388 + }; 389 + 390 + static const unsigned int ts_shift[] = TS_SHIFT; 391 + 392 + static struct sh_dmae_pdata dma0_platform_data = { 393 + .slave = sh7757_dmae0_slaves, 394 + .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves), 395 + .channel = sh7757_dmae_channels, 396 + .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 397 + .ts_low_shift = CHCR_TS_LOW_SHIFT, 398 + .ts_low_mask = CHCR_TS_LOW_MASK, 399 + .ts_high_shift = CHCR_TS_HIGH_SHIFT, 400 + .ts_high_mask = CHCR_TS_HIGH_MASK, 401 + .ts_shift = ts_shift, 402 + .ts_shift_num = ARRAY_SIZE(ts_shift), 403 + .dmaor_init = DMAOR_INIT, 404 + }; 405 + 406 + static struct sh_dmae_pdata dma1_platform_data = { 407 + .slave = sh7757_dmae1_slaves, 408 + .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves), 409 + .channel = sh7757_dmae_channels, 410 + .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 411 + .ts_low_shift = CHCR_TS_LOW_SHIFT, 412 + .ts_low_mask = CHCR_TS_LOW_MASK, 413 + .ts_high_shift = CHCR_TS_HIGH_SHIFT, 414 + .ts_high_mask = CHCR_TS_HIGH_MASK, 415 + .ts_shift = ts_shift, 416 + .ts_shift_num = ARRAY_SIZE(ts_shift), 417 + .dmaor_init = DMAOR_INIT, 418 + }; 419 + 420 + static struct sh_dmae_pdata dma2_platform_data = { 421 + .slave = sh7757_dmae2_slaves, 422 + .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves), 423 + .channel = sh7757_dmae_channels, 424 + .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 425 + .ts_low_shift = CHCR_TS_LOW_SHIFT, 426 + .ts_low_mask = CHCR_TS_LOW_MASK, 427 + .ts_high_shift = CHCR_TS_HIGH_SHIFT, 428 + .ts_high_mask = CHCR_TS_HIGH_MASK, 429 + .ts_shift = ts_shift, 430 + .ts_shift_num = ARRAY_SIZE(ts_shift), 431 + .dmaor_init = DMAOR_INIT, 432 + }; 433 + 434 + static struct sh_dmae_pdata dma3_platform_data = { 435 + .slave = sh7757_dmae3_slaves, 436 + .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves), 437 + .channel = sh7757_dmae_channels, 438 + .channel_num = ARRAY_SIZE(sh7757_dmae_channels), 439 + .ts_low_shift = CHCR_TS_LOW_SHIFT, 440 + .ts_low_mask = CHCR_TS_LOW_MASK, 441 + .ts_high_shift = CHCR_TS_HIGH_SHIFT, 442 + .ts_high_mask = CHCR_TS_HIGH_MASK, 443 + .ts_shift = ts_shift, 444 + .ts_shift_num = ARRAY_SIZE(ts_shift), 445 + .dmaor_init = DMAOR_INIT, 446 + }; 447 + 448 + /* channel 0 to 5 */ 449 + static struct resource sh7757_dmae0_resources[] = { 450 + [0] = { 451 + /* Channel registers and DMAOR */ 452 + .start = 0xff608020, 453 + .end = 0xff60808f, 454 + .flags = IORESOURCE_MEM, 455 + }, 456 + [1] = { 457 + /* DMARSx */ 458 + .start = 0xff609000, 459 + .end = 0xff60900b, 460 + .flags = IORESOURCE_MEM, 461 + }, 462 + { 463 + .start = 34, 464 + .end = 34, 465 + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 466 + }, 467 + }; 468 + 469 + /* channel 6 to 11 */ 470 + static struct resource sh7757_dmae1_resources[] = { 471 + [0] = { 472 + /* Channel registers and DMAOR */ 473 + .start = 0xff618020, 474 + .end = 0xff61808f, 475 + .flags = IORESOURCE_MEM, 476 + }, 477 + [1] = { 478 + /* DMARSx */ 479 + .start = 0xff619000, 480 + .end = 0xff61900b, 481 + .flags = IORESOURCE_MEM, 482 + }, 483 + { 484 + /* DMA error */ 485 + .start = 34, 486 + .end = 34, 487 + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 488 + }, 489 + { 490 + /* IRQ for channels 4 */ 491 + .start = 46, 492 + .end = 46, 493 + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 494 + }, 495 + { 496 + /* IRQ for channels 5 */ 497 + .start = 46, 498 + .end = 46, 499 + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 500 + }, 501 + { 502 + /* IRQ for channels 6 */ 503 + .start = 88, 504 + .end = 88, 505 + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 506 + }, 507 + { 508 + /* IRQ for channels 7 */ 509 + .start = 88, 510 + .end = 88, 511 + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 512 + }, 513 + { 514 + /* IRQ for channels 8 */ 515 + .start = 88, 516 + .end = 88, 517 + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 518 + }, 519 + { 520 + /* IRQ for channels 9 */ 521 + .start = 88, 522 + .end = 88, 523 + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 524 + }, 525 + { 526 + /* IRQ for channels 10 */ 527 + .start = 88, 528 + .end = 88, 529 + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 530 + }, 531 + { 532 + /* IRQ for channels 11 */ 533 + .start = 88, 534 + .end = 88, 535 + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 536 + }, 537 + }; 538 + 539 + /* channel 12 to 17 */ 540 + static struct resource sh7757_dmae2_resources[] = { 541 + [0] = { 542 + /* Channel registers and DMAOR */ 543 + .start = 0xff708020, 544 + .end = 0xff70808f, 545 + .flags = IORESOURCE_MEM, 546 + }, 547 + [1] = { 548 + /* DMARSx */ 549 + .start = 0xff709000, 550 + .end = 0xff70900b, 551 + .flags = IORESOURCE_MEM, 552 + }, 553 + { 554 + /* DMA error */ 555 + .start = 323, 556 + .end = 323, 557 + .flags = IORESOURCE_IRQ, 558 + }, 559 + { 560 + /* IRQ for channels 12 to 16 */ 561 + .start = 272, 562 + .end = 276, 563 + .flags = IORESOURCE_IRQ, 564 + }, 565 + { 566 + /* IRQ for channel 17 */ 567 + .start = 279, 568 + .end = 279, 569 + .flags = IORESOURCE_IRQ, 570 + }, 571 + }; 572 + 573 + /* channel 18 to 23 */ 574 + static struct resource sh7757_dmae3_resources[] = { 575 + [0] = { 576 + /* Channel registers and DMAOR */ 577 + .start = 0xff718020, 578 + .end = 0xff71808f, 579 + .flags = IORESOURCE_MEM, 580 + }, 581 + [1] = { 582 + /* DMARSx */ 583 + .start = 0xff719000, 584 + .end = 0xff71900b, 585 + .flags = IORESOURCE_MEM, 586 + }, 587 + { 588 + /* DMA error */ 589 + .start = 324, 590 + .end = 324, 591 + .flags = IORESOURCE_IRQ, 592 + }, 593 + { 594 + /* IRQ for channels 18 to 22 */ 595 + .start = 280, 596 + .end = 284, 597 + .flags = IORESOURCE_IRQ, 598 + }, 599 + { 600 + /* IRQ for channel 23 */ 601 + .start = 288, 602 + .end = 288, 603 + .flags = IORESOURCE_IRQ, 604 + }, 605 + }; 606 + 607 + static struct platform_device dma0_device = { 608 + .name = "sh-dma-engine", 609 + .id = 0, 610 + .resource = sh7757_dmae0_resources, 611 + .num_resources = ARRAY_SIZE(sh7757_dmae0_resources), 612 + .dev = { 613 + .platform_data = &dma0_platform_data, 614 + }, 615 + }; 616 + 617 + static struct platform_device dma1_device = { 618 + .name = "sh-dma-engine", 619 + .id = 1, 620 + .resource = sh7757_dmae1_resources, 621 + .num_resources = ARRAY_SIZE(sh7757_dmae1_resources), 622 + .dev = { 623 + .platform_data = &dma1_platform_data, 624 + }, 625 + }; 626 + 627 + static struct platform_device dma2_device = { 628 + .name = "sh-dma-engine", 629 + .id = 2, 630 + .resource = sh7757_dmae2_resources, 631 + .num_resources = ARRAY_SIZE(sh7757_dmae2_resources), 632 + .dev = { 633 + .platform_data = &dma2_platform_data, 634 + }, 635 + }; 636 + 637 + static struct platform_device dma3_device = { 638 + .name = "sh-dma-engine", 639 + .id = 3, 640 + .resource = sh7757_dmae3_resources, 641 + .num_resources = ARRAY_SIZE(sh7757_dmae3_resources), 642 + .dev = { 643 + .platform_data = &dma3_platform_data, 644 + }, 645 + }; 646 + 143 647 static struct platform_device spi0_device = { 144 648 .name = "sh_spi", 145 649 .id = 0, ··· 665 153 &scif4_device, 666 154 &tmu0_device, 667 155 &tmu1_device, 156 + &dma0_device, 157 + &dma1_device, 158 + &dma2_device, 159 + &dma3_device, 668 160 &spi0_device, 669 161 }; 670 162