Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

sh: Remove SH5-based Cayman platform

Since the removal of core support for SH5, Cayman support can no longer
be selected.

Fixes: 37744feebc086908 ("sh: remove sh5 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Rich Felker <dalias@libc.org>

authored by

Geert Uytterhoeven and committed by
Rich Felker
8a8e5462 7dfaa9ea

+2 -540
+2 -3
arch/sh/Kconfig
··· 123 123 124 124 config NO_IOPORT_MAP 125 125 def_bool !PCI 126 - depends on !SH_CAYMAN && !SH_SH4202_MICRODEV && !SH_SHMIN && \ 127 - !SH_HP6XX && !SH_SOLUTION_ENGINE 126 + depends on !SH_SH4202_MICRODEV && !SH_SHMIN && !SH_HP6XX && \ 127 + !SH_SOLUTION_ENGINE 128 128 129 129 config IO_TRAPPED 130 130 bool ··· 726 726 config BOOT_LINK_OFFSET 727 727 hex 728 728 default "0x00210000" if SH_SHMIN 729 - default "0x00400000" if SH_CAYMAN 730 729 default "0x00810000" if SH_7780_SOLUTION_ENGINE 731 730 default "0x009e0000" if SH_TITAN 732 731 default "0x01800000" if SH_SDK7780
-5
arch/sh/Makefile
··· 15 15 endif 16 16 endif 17 17 18 - ifeq ($(ARCH),sh) 19 18 KBUILD_DEFCONFIG := shx3_defconfig 20 - else 21 - KBUILD_DEFCONFIG := cayman_defconfig 22 - endif 23 19 24 20 isa-y := any 25 21 isa-$(CONFIG_SH_DSP) := sh ··· 139 143 machdir-$(CONFIG_SH_SH4202_MICRODEV) += mach-microdev 140 144 machdir-$(CONFIG_SH_LANDISK) += mach-landisk 141 145 machdir-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2 142 - machdir-$(CONFIG_SH_CAYMAN) += mach-cayman 143 146 machdir-$(CONFIG_SH_RSK) += mach-rsk 144 147 145 148 ifneq ($(machdir-y),)
-6
arch/sh/boards/Kconfig
··· 340 340 help 341 341 Select Magic Panel R2 if configuring for Magic Panel R2. 342 342 343 - config SH_CAYMAN 344 - bool "Hitachi Cayman" 345 - depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103 346 - select HAVE_PCI 347 - select ARCH_MIGHT_HAVE_PC_SERIO 348 - 349 343 config SH_POLARIS 350 344 bool "SMSC Polaris" 351 345 select CPU_HAS_IPR_IRQ
-5
arch/sh/boards/mach-cayman/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - # 3 - # Makefile for the Hitachi Cayman specific parts of the kernel 4 - # 5 - obj-y := setup.o irq.o panic.o
-148
arch/sh/boards/mach-cayman/irq.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * arch/sh/mach-cayman/irq.c - SH-5 Cayman Interrupt Support 4 - * 5 - * This file handles the board specific parts of the Cayman interrupt system 6 - * 7 - * Copyright (C) 2002 Stuart Menefy 8 - */ 9 - #include <linux/io.h> 10 - #include <linux/irq.h> 11 - #include <linux/interrupt.h> 12 - #include <linux/signal.h> 13 - #include <cpu/irq.h> 14 - #include <asm/page.h> 15 - 16 - /* Setup for the SMSC FDC37C935 / LAN91C100FD */ 17 - #define SMSC_IRQ IRQ_IRL1 18 - 19 - /* Setup for PCI Bus 2, which transmits interrupts via the EPLD */ 20 - #define PCI2_IRQ IRQ_IRL3 21 - 22 - unsigned long epld_virt; 23 - 24 - #define EPLD_BASE 0x04002000 25 - #define EPLD_STATUS_BASE (epld_virt + 0x10) 26 - #define EPLD_MASK_BASE (epld_virt + 0x20) 27 - 28 - /* Note the SMSC SuperIO chip and SMSC LAN chip interrupts are all muxed onto 29 - the same SH-5 interrupt */ 30 - 31 - static irqreturn_t cayman_interrupt_smsc(int irq, void *dev_id) 32 - { 33 - printk(KERN_INFO "CAYMAN: spurious SMSC interrupt\n"); 34 - return IRQ_NONE; 35 - } 36 - 37 - static irqreturn_t cayman_interrupt_pci2(int irq, void *dev_id) 38 - { 39 - printk(KERN_INFO "CAYMAN: spurious PCI interrupt, IRQ %d\n", irq); 40 - return IRQ_NONE; 41 - } 42 - 43 - static void enable_cayman_irq(struct irq_data *data) 44 - { 45 - unsigned int irq = data->irq; 46 - unsigned long flags; 47 - unsigned long mask; 48 - unsigned int reg; 49 - unsigned char bit; 50 - 51 - irq -= START_EXT_IRQS; 52 - reg = EPLD_MASK_BASE + ((irq / 8) << 2); 53 - bit = 1<<(irq % 8); 54 - local_irq_save(flags); 55 - mask = __raw_readl(reg); 56 - mask |= bit; 57 - __raw_writel(mask, reg); 58 - local_irq_restore(flags); 59 - } 60 - 61 - static void disable_cayman_irq(struct irq_data *data) 62 - { 63 - unsigned int irq = data->irq; 64 - unsigned long flags; 65 - unsigned long mask; 66 - unsigned int reg; 67 - unsigned char bit; 68 - 69 - irq -= START_EXT_IRQS; 70 - reg = EPLD_MASK_BASE + ((irq / 8) << 2); 71 - bit = 1<<(irq % 8); 72 - local_irq_save(flags); 73 - mask = __raw_readl(reg); 74 - mask &= ~bit; 75 - __raw_writel(mask, reg); 76 - local_irq_restore(flags); 77 - } 78 - 79 - struct irq_chip cayman_irq_type = { 80 - .name = "Cayman-IRQ", 81 - .irq_unmask = enable_cayman_irq, 82 - .irq_mask = disable_cayman_irq, 83 - }; 84 - 85 - int cayman_irq_demux(int evt) 86 - { 87 - int irq = intc_evt_to_irq[evt]; 88 - 89 - if (irq == SMSC_IRQ) { 90 - unsigned long status; 91 - int i; 92 - 93 - status = __raw_readl(EPLD_STATUS_BASE) & 94 - __raw_readl(EPLD_MASK_BASE) & 0xff; 95 - if (status == 0) { 96 - irq = -1; 97 - } else { 98 - for (i=0; i<8; i++) { 99 - if (status & (1<<i)) 100 - break; 101 - } 102 - irq = START_EXT_IRQS + i; 103 - } 104 - } 105 - 106 - if (irq == PCI2_IRQ) { 107 - unsigned long status; 108 - int i; 109 - 110 - status = __raw_readl(EPLD_STATUS_BASE + 3 * sizeof(u32)) & 111 - __raw_readl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff; 112 - if (status == 0) { 113 - irq = -1; 114 - } else { 115 - for (i=0; i<8; i++) { 116 - if (status & (1<<i)) 117 - break; 118 - } 119 - irq = START_EXT_IRQS + (3 * 8) + i; 120 - } 121 - } 122 - 123 - return irq; 124 - } 125 - 126 - void init_cayman_irq(void) 127 - { 128 - int i; 129 - 130 - epld_virt = (unsigned long)ioremap(EPLD_BASE, 1024); 131 - if (!epld_virt) { 132 - printk(KERN_ERR "Cayman IRQ: Unable to remap EPLD\n"); 133 - return; 134 - } 135 - 136 - for (i = 0; i < NR_EXT_IRQS; i++) { 137 - irq_set_chip_and_handler(START_EXT_IRQS + i, 138 - &cayman_irq_type, handle_level_irq); 139 - } 140 - 141 - /* Setup the SMSC interrupt */ 142 - if (request_irq(SMSC_IRQ, cayman_interrupt_smsc, 0, "Cayman SMSC Mux", 143 - NULL)) 144 - pr_err("Failed to register Cayman SMSC Mux interrupt\n"); 145 - if (request_irq(PCI2_IRQ, cayman_interrupt_pci2, 0, "Cayman PCI2 Mux", 146 - NULL)) 147 - pr_err("Failed to register Cayman PCI2 Mux interrupt\n"); 148 - }
-46
arch/sh/boards/mach-cayman/panic.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * Copyright (C) 2003 Richard Curnow, SuperH UK Limited 4 - */ 5 - 6 - #include <linux/kernel.h> 7 - #include <linux/io.h> 8 - #include <cpu/registers.h> 9 - 10 - /* THIS IS A PHYSICAL ADDRESS */ 11 - #define HDSP2534_ADDR (0x04002100) 12 - 13 - static void poor_mans_delay(void) 14 - { 15 - int i; 16 - 17 - for (i = 0; i < 2500000; i++) 18 - cpu_relax(); 19 - } 20 - 21 - static void show_value(unsigned long x) 22 - { 23 - int i; 24 - unsigned nibble; 25 - for (i = 0; i < 8; i++) { 26 - nibble = ((x >> (i * 4)) & 0xf); 27 - 28 - __raw_writeb(nibble + ((nibble > 9) ? 55 : 48), 29 - HDSP2534_ADDR + 0xe0 + ((7 - i) << 2)); 30 - } 31 - } 32 - 33 - void 34 - panic_handler(unsigned long panicPC, unsigned long panicSSR, 35 - unsigned long panicEXPEVT) 36 - { 37 - while (1) { 38 - /* This piece of code displays the PC on the LED display */ 39 - show_value(panicPC); 40 - poor_mans_delay(); 41 - show_value(panicSSR); 42 - poor_mans_delay(); 43 - show_value(panicEXPEVT); 44 - poor_mans_delay(); 45 - } 46 - }
-181
arch/sh/boards/mach-cayman/setup.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - /* 3 - * arch/sh/mach-cayman/setup.c 4 - * 5 - * SH5 Cayman support 6 - * 7 - * Copyright (C) 2002 David J. Mckay & Benedict Gaster 8 - * Copyright (C) 2003 - 2007 Paul Mundt 9 - */ 10 - #include <linux/init.h> 11 - #include <linux/io.h> 12 - #include <linux/kernel.h> 13 - #include <cpu/irq.h> 14 - 15 - /* 16 - * Platform Dependent Interrupt Priorities. 17 - */ 18 - 19 - /* Using defaults defined in irq.h */ 20 - #define RES NO_PRIORITY /* Disabled */ 21 - #define IR0 IRL0_PRIORITY /* IRLs */ 22 - #define IR1 IRL1_PRIORITY 23 - #define IR2 IRL2_PRIORITY 24 - #define IR3 IRL3_PRIORITY 25 - #define PCA INTA_PRIORITY /* PCI Ints */ 26 - #define PCB INTB_PRIORITY 27 - #define PCC INTC_PRIORITY 28 - #define PCD INTD_PRIORITY 29 - #define SER TOP_PRIORITY 30 - #define ERR TOP_PRIORITY 31 - #define PW0 TOP_PRIORITY 32 - #define PW1 TOP_PRIORITY 33 - #define PW2 TOP_PRIORITY 34 - #define PW3 TOP_PRIORITY 35 - #define DM0 NO_PRIORITY /* DMA Ints */ 36 - #define DM1 NO_PRIORITY 37 - #define DM2 NO_PRIORITY 38 - #define DM3 NO_PRIORITY 39 - #define DAE NO_PRIORITY 40 - #define TU0 TIMER_PRIORITY /* TMU Ints */ 41 - #define TU1 NO_PRIORITY 42 - #define TU2 NO_PRIORITY 43 - #define TI2 NO_PRIORITY 44 - #define ATI NO_PRIORITY /* RTC Ints */ 45 - #define PRI NO_PRIORITY 46 - #define CUI RTC_PRIORITY 47 - #define ERI SCIF_PRIORITY /* SCIF Ints */ 48 - #define RXI SCIF_PRIORITY 49 - #define BRI SCIF_PRIORITY 50 - #define TXI SCIF_PRIORITY 51 - #define ITI TOP_PRIORITY /* WDT Ints */ 52 - 53 - /* Setup for the SMSC FDC37C935 */ 54 - #define SMSC_SUPERIO_BASE 0x04000000 55 - #define SMSC_CONFIG_PORT_ADDR 0x3f0 56 - #define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR 57 - #define SMSC_DATA_PORT_ADDR 0x3f1 58 - 59 - #define SMSC_ENTER_CONFIG_KEY 0x55 60 - #define SMSC_EXIT_CONFIG_KEY 0xaa 61 - 62 - #define SMCS_LOGICAL_DEV_INDEX 0x07 63 - #define SMSC_DEVICE_ID_INDEX 0x20 64 - #define SMSC_DEVICE_REV_INDEX 0x21 65 - #define SMSC_ACTIVATE_INDEX 0x30 66 - #define SMSC_PRIMARY_BASE_INDEX 0x60 67 - #define SMSC_SECONDARY_BASE_INDEX 0x62 68 - #define SMSC_PRIMARY_INT_INDEX 0x70 69 - #define SMSC_SECONDARY_INT_INDEX 0x72 70 - 71 - #define SMSC_IDE1_DEVICE 1 72 - #define SMSC_KEYBOARD_DEVICE 7 73 - #define SMSC_CONFIG_REGISTERS 8 74 - 75 - #define SMSC_SUPERIO_READ_INDEXED(index) ({ \ 76 - outb((index), SMSC_INDEX_PORT_ADDR); \ 77 - inb(SMSC_DATA_PORT_ADDR); }) 78 - #define SMSC_SUPERIO_WRITE_INDEXED(val, index) ({ \ 79 - outb((index), SMSC_INDEX_PORT_ADDR); \ 80 - outb((val), SMSC_DATA_PORT_ADDR); }) 81 - 82 - #define IDE1_PRIMARY_BASE 0x01f0 83 - #define IDE1_SECONDARY_BASE 0x03f6 84 - 85 - unsigned long smsc_superio_virt; 86 - 87 - int platform_int_priority[NR_INTC_IRQS] = { 88 - IR0, IR1, IR2, IR3, PCA, PCB, PCC, PCD, /* IRQ 0- 7 */ 89 - RES, RES, RES, RES, SER, ERR, PW3, PW2, /* IRQ 8-15 */ 90 - PW1, PW0, DM0, DM1, DM2, DM3, DAE, RES, /* IRQ 16-23 */ 91 - RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 24-31 */ 92 - TU0, TU1, TU2, TI2, ATI, PRI, CUI, ERI, /* IRQ 32-39 */ 93 - RXI, BRI, TXI, RES, RES, RES, RES, RES, /* IRQ 40-47 */ 94 - RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 48-55 */ 95 - RES, RES, RES, RES, RES, RES, RES, ITI, /* IRQ 56-63 */ 96 - }; 97 - 98 - static int __init smsc_superio_setup(void) 99 - { 100 - unsigned char devid, devrev; 101 - 102 - smsc_superio_virt = (unsigned long)ioremap(SMSC_SUPERIO_BASE, 1024); 103 - if (!smsc_superio_virt) { 104 - panic("Unable to remap SMSC SuperIO\n"); 105 - } 106 - 107 - /* Initially the chip is in run state */ 108 - /* Put it into configuration state */ 109 - outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); 110 - outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); 111 - 112 - /* Read device ID info */ 113 - devid = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_ID_INDEX); 114 - devrev = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_REV_INDEX); 115 - printk("SMSC SuperIO devid %02x rev %02x\n", devid, devrev); 116 - 117 - /* Select the keyboard device */ 118 - SMSC_SUPERIO_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX); 119 - 120 - /* enable it */ 121 - SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); 122 - 123 - /* Select the interrupts */ 124 - /* On a PC keyboard is IRQ1, mouse is IRQ12 */ 125 - SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_PRIMARY_INT_INDEX); 126 - SMSC_SUPERIO_WRITE_INDEXED(12, SMSC_SECONDARY_INT_INDEX); 127 - 128 - /* 129 - * Only IDE1 exists on the Cayman 130 - */ 131 - 132 - /* Power it on */ 133 - SMSC_SUPERIO_WRITE_INDEXED(1 << SMSC_IDE1_DEVICE, 0x22); 134 - 135 - SMSC_SUPERIO_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX); 136 - SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); 137 - 138 - SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE >> 8, 139 - SMSC_PRIMARY_BASE_INDEX + 0); 140 - SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE & 0xff, 141 - SMSC_PRIMARY_BASE_INDEX + 1); 142 - 143 - SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE >> 8, 144 - SMSC_SECONDARY_BASE_INDEX + 0); 145 - SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE & 0xff, 146 - SMSC_SECONDARY_BASE_INDEX + 1); 147 - 148 - SMSC_SUPERIO_WRITE_INDEXED(14, SMSC_PRIMARY_INT_INDEX); 149 - 150 - SMSC_SUPERIO_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, 151 - SMCS_LOGICAL_DEV_INDEX); 152 - 153 - SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */ 154 - SMSC_SUPERIO_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */ 155 - SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */ 156 - SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */ 157 - 158 - /* Exit the configuration state */ 159 - outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); 160 - 161 - return 0; 162 - } 163 - device_initcall(smsc_superio_setup); 164 - 165 - static void __iomem *cayman_ioport_map(unsigned long port, unsigned int len) 166 - { 167 - if (port < 0x400) { 168 - extern unsigned long smsc_superio_virt; 169 - return (void __iomem *)((port << 2) | smsc_superio_virt); 170 - } 171 - 172 - return (void __iomem *)port; 173 - } 174 - 175 - extern void init_cayman_irq(void); 176 - 177 - static struct sh_machine_vector mv_cayman __initmv = { 178 - .mv_name = "Hitachi Cayman", 179 - .mv_ioport_map = cayman_ioport_map, 180 - .mv_init_irq = init_cayman_irq, 181 - };
-66
arch/sh/configs/cayman_defconfig
··· 1 - CONFIG_POSIX_MQUEUE=y 2 - CONFIG_LOG_BUF_SHIFT=14 3 - # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 4 - CONFIG_SLAB=y 5 - CONFIG_MODULES=y 6 - CONFIG_MODULE_UNLOAD=y 7 - # CONFIG_BLK_DEV_BSG is not set 8 - CONFIG_FORCE_MAX_ZONEORDER=11 9 - CONFIG_MEMORY_START=0x80000000 10 - CONFIG_MEMORY_SIZE=0x00400000 11 - CONFIG_FLATMEM_MANUAL=y 12 - CONFIG_CACHE_OFF=y 13 - CONFIG_SH_PCLK_FREQ=50000000 14 - CONFIG_HEARTBEAT=y 15 - CONFIG_PREEMPT=y 16 - CONFIG_NET=y 17 - CONFIG_PACKET=y 18 - CONFIG_UNIX=y 19 - CONFIG_INET=y 20 - CONFIG_IP_PNP=y 21 - # CONFIG_IPV6 is not set 22 - # CONFIG_FW_LOADER is not set 23 - CONFIG_BLK_DEV_LOOP=y 24 - CONFIG_BLK_DEV_RAM=y 25 - CONFIG_SCSI=y 26 - CONFIG_BLK_DEV_SD=y 27 - CONFIG_SCSI_MULTI_LUN=y 28 - CONFIG_SCSI_SPI_ATTRS=y 29 - CONFIG_NETDEVICES=y 30 - CONFIG_NET_ETHERNET=y 31 - # CONFIG_INPUT_MOUSEDEV_PSAUX is not set 32 - # CONFIG_INPUT_KEYBOARD is not set 33 - # CONFIG_INPUT_MOUSE is not set 34 - # CONFIG_SERIO is not set 35 - CONFIG_HW_RANDOM=y 36 - CONFIG_I2C=m 37 - CONFIG_WATCHDOG=y 38 - CONFIG_FB=y 39 - CONFIG_FIRMWARE_EDID=y 40 - CONFIG_FB_MODE_HELPERS=y 41 - CONFIG_FB_SH_MOBILE_LCDC=m 42 - CONFIG_FRAMEBUFFER_CONSOLE=y 43 - CONFIG_FONTS=y 44 - CONFIG_FONT_8x16=y 45 - CONFIG_LOGO=y 46 - # CONFIG_LOGO_LINUX_MONO is not set 47 - # CONFIG_LOGO_LINUX_VGA16 is not set 48 - # CONFIG_LOGO_LINUX_CLUT224 is not set 49 - # CONFIG_LOGO_SUPERH_MONO is not set 50 - # CONFIG_LOGO_SUPERH_VGA16 is not set 51 - CONFIG_EXT2_FS=y 52 - CONFIG_EXT3_FS=y 53 - # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 54 - CONFIG_MINIX_FS=y 55 - CONFIG_ROMFS_FS=y 56 - CONFIG_NFS_FS=y 57 - CONFIG_NFS_V3=y 58 - CONFIG_ROOT_NFS=y 59 - CONFIG_PARTITION_ADVANCED=y 60 - CONFIG_MAGIC_SYSRQ=y 61 - CONFIG_DEBUG_FS=y 62 - CONFIG_DEBUG_KERNEL=y 63 - CONFIG_DETECT_HUNG_TASK=y 64 - CONFIG_SCHEDSTATS=y 65 - CONFIG_FRAME_POINTER=y 66 - # CONFIG_CRYPTO_ANSI_CPRNG is not set
-1
arch/sh/drivers/pci/Makefile
··· 25 25 obj-$(CONFIG_SH_TITAN) += fixups-titan.o 26 26 obj-$(CONFIG_SH_LANDISK) += fixups-landisk.o 27 27 obj-$(CONFIG_SH_LBOX_RE2) += fixups-rts7751r2d.o 28 - obj-$(CONFIG_SH_CAYMAN) += fixups-cayman.o
-78
arch/sh/drivers/pci/fixups-cayman.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - #include <linux/kernel.h> 3 - #include <linux/init.h> 4 - #include <linux/pci.h> 5 - #include <linux/types.h> 6 - #include <cpu/irq.h> 7 - #include "pci-sh5.h" 8 - 9 - int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin) 10 - { 11 - int result = -1; 12 - 13 - /* The complication here is that the PCI IRQ lines from the Cayman's 2 14 - 5V slots get into the CPU via a different path from the IRQ lines 15 - from the 3 3.3V slots. Thus, we have to detect whether the card's 16 - interrupts go via the 5V or 3.3V path, i.e. the 'bridge swizzling' 17 - at the point where we cross from 5V to 3.3V is not the normal case. 18 - 19 - The added complication is that we don't know that the 5V slots are 20 - always bus 2, because a card containing a PCI-PCI bridge may be 21 - plugged into a 3.3V slot, and this changes the bus numbering. 22 - 23 - Also, the Cayman has an intermediate PCI bus that goes a custom 24 - expansion board header (and to the secondary bridge). This bus has 25 - never been used in practice. 26 - 27 - The 1ary onboard PCI-PCI bridge is device 3 on bus 0 28 - The 2ary onboard PCI-PCI bridge is device 0 on the 2ary bus of 29 - the 1ary bridge. 30 - */ 31 - 32 - struct slot_pin { 33 - int slot; 34 - int pin; 35 - } path[4]; 36 - int i=0; 37 - 38 - while (dev->bus->number > 0) { 39 - 40 - slot = path[i].slot = PCI_SLOT(dev->devfn); 41 - pin = path[i].pin = pci_swizzle_interrupt_pin(dev, pin); 42 - dev = dev->bus->self; 43 - i++; 44 - if (i > 3) panic("PCI path to root bus too long!\n"); 45 - } 46 - 47 - slot = PCI_SLOT(dev->devfn); 48 - /* This is the slot on bus 0 through which the device is eventually 49 - reachable. */ 50 - 51 - /* Now work back up. */ 52 - if ((slot < 3) || (i == 0)) { 53 - /* Bus 0 (incl. PCI-PCI bridge itself) : perform the final 54 - swizzle now. */ 55 - result = IRQ_INTA + pci_swizzle_interrupt_pin(dev, pin) - 1; 56 - } else { 57 - i--; 58 - slot = path[i].slot; 59 - pin = path[i].pin; 60 - if (slot > 0) { 61 - panic("PCI expansion bus device found - not handled!\n"); 62 - } else { 63 - if (i > 0) { 64 - /* 5V slots */ 65 - i--; 66 - slot = path[i].slot; 67 - pin = path[i].pin; 68 - /* 'pin' was swizzled earlier wrt slot, don't do it again. */ 69 - result = IRQ_P2INTA + (pin - 1); 70 - } else { 71 - /* IRQ for 2ary PCI-PCI bridge : unused */ 72 - result = -1; 73 - } 74 - } 75 - } 76 - 77 - return result; 78 - }
-1
arch/sh/tools/mach-types
··· 46 46 MAGICPANELR2 SH_MAGIC_PANEL_R2 47 47 R2D_PLUS RTS7751R2D_PLUS 48 48 R2D_1 RTS7751R2D_1 49 - CAYMAN SH_CAYMAN 50 49 SDK7780 SH_SDK7780 51 50 MIGOR SH_MIGOR 52 51 RSK7201 SH_RSK7201