MIPS: OCTEON: Move CAVIUM_OCTEON_CVMSEG_SIZE to CPU_CAVIUM_OCTEON

CVMSEG is related to the CPU core not the SoC system. So needs to be
configurable there.

Signed-off-by: David Daney <[e-mail]>
Signed-off-by: Andreas Herrmann <[e-mail]>
Cc: [e-mail]
Cc: James Hogan <[e-mail]>
Cc: [e-mail]
Patchwork: https://patchwork.linux-mips.org/patch/7013/
Signed-off-by: Ralf Baechle <[e-mail]>

arch/mips/cavium-octeon/Kconfig

···
 	  non-CN63XXP1 hardware, so it is recommended to select "n"
 	  unless it is known the workarounds are needed.
 
+config CAVIUM_OCTEON_CVMSEG_SIZE
+	int "Number of L1 cache lines reserved for CVMSEG memory"
+	range 0 54
+	default 1
+	help
+	  CVMSEG LM is a segment that accesses portions of the dcache as a
+	  local memory; the larger CVMSEG is, the smaller the cache is.
+	  This selects the size of CVMSEG LM, which is in cache blocks. The
+	  legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
+	  between zero and 6192 bytes).
+
 endif # CPU_CAVIUM_OCTEON
 
 if CAVIUM_OCTEON_SOC
···
 	  address and use the 2nd uart for output. This allows a kernel built
 	  with this option to be run at the same time as one built without this
 	  option.
-
-config CAVIUM_OCTEON_CVMSEG_SIZE
-	int "Number of L1 cache lines reserved for CVMSEG memory"
-	range 0 54
-	default 1
-	help
-	  CVMSEG LM is a segment that accesses portions of the dcache as a
-	  local memory; the larger CVMSEG is, the smaller the cache is.
-	  This selects the size of CVMSEG LM, which is in cache blocks. The
-	  legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
-	  between zero and 6192 bytes).
 
 config CAVIUM_OCTEON_LOCK_L2
 	bool "Lock often used kernel code in the L2"
···
 	def_bool y
 	select IOMMU_HELPER
 	select NEED_SG_DMA_LENGTH
-
 
 config OCTEON_ILM
 	tristate "Module to measure interrupt latency using Octeon CIU Timer"