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linux
powerpc/85xx: Change deprecated binding for 85xx-based boards
The "fsl,85..." style compatible binding was to be deprecated
some time ago. This patch corrects existing occurrences of
the incorrect binding. The memory-controller and
l2-cache-controller are the only affected nodes.
Signed-off-by: Bradley Hughes <bhughes@silicontkx.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
authored by
Bradley Hughes
and committed by
Kumar Gala
8a4ab218
e9502fbe
+14
-14
+2
-2
arch/powerpc/boot/dts/mpc8540ads.dts
+2
-2
arch/powerpc/boot/dts/mpc8540ads.dts
···
71
71
};
72
72
73
73
memory-controller@2000 {
74
-
compatible = "fsl,8540-memory-controller";
74
+
compatible = "fsl,mpc8540-memory-controller";
75
75
reg = <0x2000 0x1000>;
76
76
interrupt-parent = <&mpic>;
77
77
interrupts = <18 2>;
78
78
};
79
79
80
80
L2: l2-cache-controller@20000 {
81
-
compatible = "fsl,8540-l2-cache-controller";
81
+
compatible = "fsl,mpc8540-l2-cache-controller";
82
82
reg = <0x20000 0x1000>;
83
83
cache-line-size = <32>; // 32 bytes
84
84
cache-size = <0x40000>; // L2, 256K
+2
-2
arch/powerpc/boot/dts/mpc8541cds.dts
+2
-2
arch/powerpc/boot/dts/mpc8541cds.dts
···
71
71
};
72
72
73
73
memory-controller@2000 {
74
-
compatible = "fsl,8541-memory-controller";
74
+
compatible = "fsl,mpc8541-memory-controller";
75
75
reg = <0x2000 0x1000>;
76
76
interrupt-parent = <&mpic>;
77
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interrupts = <18 2>;
78
78
};
79
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80
80
L2: l2-cache-controller@20000 {
81
-
compatible = "fsl,8541-l2-cache-controller";
81
+
compatible = "fsl,mpc8541-l2-cache-controller";
82
82
reg = <0x20000 0x1000>;
83
83
cache-line-size = <32>; // 32 bytes
84
84
cache-size = <0x40000>; // L2, 256K
+2
-2
arch/powerpc/boot/dts/mpc8544ds.dts
+2
-2
arch/powerpc/boot/dts/mpc8544ds.dts
···
73
73
};
74
74
75
75
memory-controller@2000 {
76
-
compatible = "fsl,8544-memory-controller";
76
+
compatible = "fsl,mpc8544-memory-controller";
77
77
reg = <0x2000 0x1000>;
78
78
interrupt-parent = <&mpic>;
79
79
interrupts = <18 2>;
80
80
};
81
81
82
82
L2: l2-cache-controller@20000 {
83
-
compatible = "fsl,8544-l2-cache-controller";
83
+
compatible = "fsl,mpc8544-l2-cache-controller";
84
84
reg = <0x20000 0x1000>;
85
85
cache-line-size = <32>; // 32 bytes
86
86
cache-size = <0x40000>; // L2, 256K
+2
-2
arch/powerpc/boot/dts/mpc8548cds.dts
+2
-2
arch/powerpc/boot/dts/mpc8548cds.dts
···
74
74
};
75
75
76
76
memory-controller@2000 {
77
-
compatible = "fsl,8548-memory-controller";
77
+
compatible = "fsl,mpc8548-memory-controller";
78
78
reg = <0x2000 0x1000>;
79
79
interrupt-parent = <&mpic>;
80
80
interrupts = <18 2>;
81
81
};
82
82
83
83
L2: l2-cache-controller@20000 {
84
-
compatible = "fsl,8548-l2-cache-controller";
84
+
compatible = "fsl,mpc8548-l2-cache-controller";
85
85
reg = <0x20000 0x1000>;
86
86
cache-line-size = <32>; // 32 bytes
87
87
cache-size = <0x80000>; // L2, 512K
+2
-2
arch/powerpc/boot/dts/mpc8555cds.dts
+2
-2
arch/powerpc/boot/dts/mpc8555cds.dts
···
71
71
};
72
72
73
73
memory-controller@2000 {
74
-
compatible = "fsl,8555-memory-controller";
74
+
compatible = "fsl,mpc8555-memory-controller";
75
75
reg = <0x2000 0x1000>;
76
76
interrupt-parent = <&mpic>;
77
77
interrupts = <18 2>;
78
78
};
79
79
80
80
L2: l2-cache-controller@20000 {
81
-
compatible = "fsl,8555-l2-cache-controller";
81
+
compatible = "fsl,mpc8555-l2-cache-controller";
82
82
reg = <0x20000 0x1000>;
83
83
cache-line-size = <32>; // 32 bytes
84
84
cache-size = <0x40000>; // L2, 256K
+2
-2
arch/powerpc/boot/dts/mpc8560ads.dts
+2
-2
arch/powerpc/boot/dts/mpc8560ads.dts
···
71
71
};
72
72
73
73
memory-controller@2000 {
74
-
compatible = "fsl,8540-memory-controller";
74
+
compatible = "fsl,mpc8540-memory-controller";
75
75
reg = <0x2000 0x1000>;
76
76
interrupt-parent = <&mpic>;
77
77
interrupts = <18 2>;
78
78
};
79
79
80
80
L2: l2-cache-controller@20000 {
81
-
compatible = "fsl,8540-l2-cache-controller";
81
+
compatible = "fsl,mpc8540-l2-cache-controller";
82
82
reg = <0x20000 0x1000>;
83
83
cache-line-size = <32>; // 32 bytes
84
84
cache-size = <0x40000>; // L2, 256K
+2
-2
arch/powerpc/boot/dts/mpc8568mds.dts
+2
-2
arch/powerpc/boot/dts/mpc8568mds.dts
···
124
124
};
125
125
126
126
memory-controller@2000 {
127
-
compatible = "fsl,8568-memory-controller";
127
+
compatible = "fsl,mpc8568-memory-controller";
128
128
reg = <0x2000 0x1000>;
129
129
interrupt-parent = <&mpic>;
130
130
interrupts = <18 2>;
131
131
};
132
132
133
133
L2: l2-cache-controller@20000 {
134
-
compatible = "fsl,8568-l2-cache-controller";
134
+
compatible = "fsl,mpc8568-l2-cache-controller";
135
135
reg = <0x20000 0x1000>;
136
136
cache-line-size = <32>; // 32 bytes
137
137
cache-size = <0x80000>; // L2, 512K