Merge tag 'nand/for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next

+33

Documentation/devicetree/bindings/mtd/partitions/qcom,smem-part.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mtd/partitions/qcom,smem-part.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm SMEM NAND flash partition parser binding 8 + 9 + maintainers: 10 + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 11 + 12 + description: | 13 + The Qualcomm SoCs supporting the NAND controller interface features a Shared 14 + Memory (SMEM) based partition table scheme. The maximum partitions supported 15 + varies between partition table revisions. V3 supports maximum 16 partitions 16 + and V4 supports 48 partitions. 17 + 18 + properties: 19 + compatible: 20 + const: qcom,smem-part 21 + 22 + required: 23 + - compatible 24 + 25 + additionalProperties: false 26 + 27 + examples: 28 + - | 29 + flash { 30 + partitions { 31 + compatible = "qcom,smem-part"; 32 + }; 33 + };

-7

drivers/mtd/nand/raw/Kconfig

··· 102 102 when the is NAND chip selected or released, but will save 103 103 approximately 5mA of power when there is nothing happening. 104 104 105 - config MTD_NAND_TANGO 106 - tristate "Tango NAND controller" 107 - depends on ARCH_TANGO || COMPILE_TEST 108 - depends on HAS_IOMEM 109 - help 110 - Enables the NAND Flash controller on Tango chips. 111 - 112 105 config MTD_NAND_SHARPSL 113 106 tristate "Sharp SL Series (C7xx + others) NAND controller" 114 107 depends on ARCH_PXA || COMPILE_TEST

-1

drivers/mtd/nand/raw/Makefile

··· 10 10 obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o 11 11 obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o 12 12 obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o 13 - obj-$(CONFIG_MTD_NAND_TANGO) += tango_nand.o 14 13 obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o 15 14 obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o 16 15 obj-$(CONFIG_MTD_NAND_FSMC) += fsmc_nand.o

+4 -2

drivers/mtd/nand/raw/intel-nand-controller.c

··· 318 318 } 319 319 320 320 tx = dmaengine_prep_slave_single(chan, buf_dma, len, dir, flags); 321 - if (!tx) 322 - return -ENXIO; 321 + if (!tx) { 322 + ret = -ENXIO; 323 + goto err_unmap; 324 + } 323 325 324 326 tx->callback = callback; 325 327 tx->callback_param = ebu_host;

+1 -1

drivers/mtd/nand/raw/marvell_nand.c

··· 2396 2396 * be greater than that to be sure tCCS delay is respected. 2397 2397 */ 2398 2398 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), 2399 - period_ns) - 2, 2399 + period_ns) - 2; 2400 2400 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), 2401 2401 period_ns); 2402 2402

+1 -1

drivers/mtd/nand/raw/mxc_nand.c

··· 1731 1731 this->legacy.chip_delay = 5; 1732 1732 1733 1733 nand_set_controller_data(this, host); 1734 - nand_set_flash_node(this, pdev->dev.of_node), 1734 + nand_set_flash_node(this, pdev->dev.of_node); 1735 1735 this->legacy.dev_ready = mxc_nand_dev_ready; 1736 1736 this->legacy.cmdfunc = mxc_nand_command; 1737 1737 this->legacy.read_byte = mxc_nand_read_byte;

+3 -1

drivers/mtd/nand/raw/qcom_nandc.c

··· 2821 2821 return 0; 2822 2822 } 2823 2823 2824 + static const char * const probes[] = { "qcomsmem", NULL }; 2825 + 2824 2826 static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, 2825 2827 struct qcom_nand_host *host, 2826 2828 struct device_node *dn) ··· 2886 2884 } 2887 2885 } 2888 2886 2889 - ret = mtd_device_register(mtd, NULL, 0); 2887 + ret = mtd_device_parse_register(mtd, probes, NULL, NULL, 0); 2890 2888 if (ret) 2891 2889 nand_cleanup(chip); 2892 2890

-727

drivers/mtd/nand/raw/tango_nand.c

··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * Copyright (C) 2016 Sigma Designs 4 - */ 5 - 6 - #include <linux/io.h> 7 - #include <linux/of.h> 8 - #include <linux/clk.h> 9 - #include <linux/iopoll.h> 10 - #include <linux/module.h> 11 - #include <linux/mtd/rawnand.h> 12 - #include <linux/dmaengine.h> 13 - #include <linux/dma-mapping.h> 14 - #include <linux/platform_device.h> 15 - 16 - /* Offsets relative to chip->base */ 17 - #define PBUS_CMD 0 18 - #define PBUS_ADDR 4 19 - #define PBUS_DATA 8 20 - 21 - /* Offsets relative to reg_base */ 22 - #define NFC_STATUS 0x00 23 - #define NFC_FLASH_CMD 0x04 24 - #define NFC_DEVICE_CFG 0x08 25 - #define NFC_TIMING1 0x0c 26 - #define NFC_TIMING2 0x10 27 - #define NFC_XFER_CFG 0x14 28 - #define NFC_PKT_0_CFG 0x18 29 - #define NFC_PKT_N_CFG 0x1c 30 - #define NFC_BB_CFG 0x20 31 - #define NFC_ADDR_PAGE 0x24 32 - #define NFC_ADDR_OFFSET 0x28 33 - #define NFC_XFER_STATUS 0x2c 34 - 35 - /* NFC_STATUS values */ 36 - #define CMD_READY BIT(31) 37 - 38 - /* NFC_FLASH_CMD values */ 39 - #define NFC_READ 1 40 - #define NFC_WRITE 2 41 - 42 - /* NFC_XFER_STATUS values */ 43 - #define PAGE_IS_EMPTY BIT(16) 44 - 45 - /* Offsets relative to mem_base */ 46 - #define METADATA 0x000 47 - #define ERROR_REPORT 0x1c0 48 - 49 - /* 50 - * Error reports are split in two bytes: 51 - * byte 0 for the first packet in the page (PKT_0) 52 - * byte 1 for other packets in the page (PKT_N, for N > 0) 53 - * ERR_COUNT_PKT_N is the max error count over all but the first packet. 54 - */ 55 - #define ERR_COUNT_PKT_0(v) (((v) >> 0) & 0x3f) 56 - #define ERR_COUNT_PKT_N(v) (((v) >> 8) & 0x3f) 57 - #define DECODE_FAIL_PKT_0(v) (((v) & BIT(7)) == 0) 58 - #define DECODE_FAIL_PKT_N(v) (((v) & BIT(15)) == 0) 59 - 60 - /* Offsets relative to pbus_base */ 61 - #define PBUS_CS_CTRL 0x83c 62 - #define PBUS_PAD_MODE 0x8f0 63 - 64 - /* PBUS_CS_CTRL values */ 65 - #define PBUS_IORDY BIT(31) 66 - 67 - /* 68 - * PBUS_PAD_MODE values 69 - * In raw mode, the driver communicates directly with the NAND chips. 70 - * In NFC mode, the NAND Flash controller manages the communication. 71 - * We use NFC mode for read and write; raw mode for everything else. 72 - */ 73 - #define MODE_RAW 0 74 - #define MODE_NFC BIT(31) 75 - 76 - #define METADATA_SIZE 4 77 - #define BBM_SIZE 6 78 - #define FIELD_ORDER 15 79 - 80 - #define MAX_CS 4 81 - 82 - struct tango_nfc { 83 - struct nand_controller hw; 84 - void __iomem *reg_base; 85 - void __iomem *mem_base; 86 - void __iomem *pbus_base; 87 - struct tango_chip *chips[MAX_CS]; 88 - struct dma_chan *chan; 89 - int freq_kHz; 90 - }; 91 - 92 - #define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw) 93 - 94 - struct tango_chip { 95 - struct nand_chip nand_chip; 96 - void __iomem *base; 97 - u32 timing1; 98 - u32 timing2; 99 - u32 xfer_cfg; 100 - u32 pkt_0_cfg; 101 - u32 pkt_n_cfg; 102 - u32 bb_cfg; 103 - }; 104 - 105 - #define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip) 106 - 107 - #define XFER_CFG(cs, page_count, steps, metadata_size) \ 108 - ((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size)) 109 - 110 - #define PKT_CFG(size, strength) ((size) << 16 | (strength)) 111 - 112 - #define BB_CFG(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size)) 113 - 114 - #define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3)) 115 - 116 - static void tango_select_target(struct nand_chip *chip, unsigned int cs) 117 - { 118 - struct tango_nfc *nfc = to_tango_nfc(chip->controller); 119 - struct tango_chip *tchip = to_tango_chip(chip); 120 - 121 - writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1); 122 - writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2); 123 - writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG); 124 - writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG); 125 - writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG); 126 - writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG); 127 - } 128 - 129 - static int tango_waitrdy(struct nand_chip *chip, unsigned int timeout_ms) 130 - { 131 - struct tango_nfc *nfc = to_tango_nfc(chip->controller); 132 - u32 status; 133 - 134 - return readl_relaxed_poll_timeout(nfc->pbus_base + PBUS_CS_CTRL, 135 - status, status & PBUS_IORDY, 20, 136 - timeout_ms); 137 - } 138 - 139 - static int tango_exec_instr(struct nand_chip *chip, 140 - const struct nand_op_instr *instr) 141 - { 142 - struct tango_chip *tchip = to_tango_chip(chip); 143 - unsigned int i; 144 - 145 - switch (instr->type) { 146 - case NAND_OP_CMD_INSTR: 147 - writeb_relaxed(instr->ctx.cmd.opcode, tchip->base + PBUS_CMD); 148 - return 0; 149 - case NAND_OP_ADDR_INSTR: 150 - for (i = 0; i < instr->ctx.addr.naddrs; i++) 151 - writeb_relaxed(instr->ctx.addr.addrs[i], 152 - tchip->base + PBUS_ADDR); 153 - return 0; 154 - case NAND_OP_DATA_IN_INSTR: 155 - ioread8_rep(tchip->base + PBUS_DATA, instr->ctx.data.buf.in, 156 - instr->ctx.data.len); 157 - return 0; 158 - case NAND_OP_DATA_OUT_INSTR: 159 - iowrite8_rep(tchip->base + PBUS_DATA, instr->ctx.data.buf.out, 160 - instr->ctx.data.len); 161 - return 0; 162 - case NAND_OP_WAITRDY_INSTR: 163 - return tango_waitrdy(chip, 164 - instr->ctx.waitrdy.timeout_ms); 165 - default: 166 - break; 167 - } 168 - 169 - return -EINVAL; 170 - } 171 - 172 - static int tango_exec_op(struct nand_chip *chip, 173 - const struct nand_operation *op, 174 - bool check_only) 175 - { 176 - unsigned int i; 177 - int ret = 0; 178 - 179 - if (check_only) 180 - return 0; 181 - 182 - tango_select_target(chip, op->cs); 183 - for (i = 0; i < op->ninstrs; i++) { 184 - ret = tango_exec_instr(chip, &op->instrs[i]); 185 - if (ret) 186 - break; 187 - } 188 - 189 - return ret; 190 - } 191 - 192 - /* 193 - * The controller does not check for bitflips in erased pages, 194 - * therefore software must check instead. 195 - */ 196 - static int check_erased_page(struct nand_chip *chip, u8 *buf) 197 - { 198 - struct mtd_info *mtd = nand_to_mtd(chip); 199 - u8 *meta = chip->oob_poi + BBM_SIZE; 200 - u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE; 201 - const int ecc_size = chip->ecc.bytes; 202 - const int pkt_size = chip->ecc.size; 203 - int i, res, meta_len, bitflips = 0; 204 - 205 - for (i = 0; i < chip->ecc.steps; ++i) { 206 - meta_len = i ? 0 : METADATA_SIZE; 207 - res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, 208 - meta, meta_len, 209 - chip->ecc.strength); 210 - if (res < 0) 211 - mtd->ecc_stats.failed++; 212 - else 213 - mtd->ecc_stats.corrected += res; 214 - 215 - bitflips = max(res, bitflips); 216 - buf += pkt_size; 217 - ecc += ecc_size; 218 - } 219 - 220 - return bitflips; 221 - } 222 - 223 - static int decode_error_report(struct nand_chip *chip) 224 - { 225 - u32 status, res; 226 - struct mtd_info *mtd = nand_to_mtd(chip); 227 - struct tango_nfc *nfc = to_tango_nfc(chip->controller); 228 - 229 - status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS); 230 - if (status & PAGE_IS_EMPTY) 231 - return 0; 232 - 233 - res = readl_relaxed(nfc->mem_base + ERROR_REPORT); 234 - 235 - if (DECODE_FAIL_PKT_0(res) || DECODE_FAIL_PKT_N(res)) 236 - return -EBADMSG; 237 - 238 - /* ERR_COUNT_PKT_N is max, not sum, but that's all we have */ 239 - mtd->ecc_stats.corrected += 240 - ERR_COUNT_PKT_0(res) + ERR_COUNT_PKT_N(res); 241 - 242 - return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res)); 243 - } 244 - 245 - static void tango_dma_callback(void *arg) 246 - { 247 - complete(arg); 248 - } 249 - 250 - static int do_dma(struct tango_nfc *nfc, enum dma_data_direction dir, int cmd, 251 - const void *buf, int len, int page) 252 - { 253 - void __iomem *addr = nfc->reg_base + NFC_STATUS; 254 - struct dma_chan *chan = nfc->chan; 255 - struct dma_async_tx_descriptor *desc; 256 - enum dma_transfer_direction tdir; 257 - struct scatterlist sg; 258 - struct completion tx_done; 259 - int err = -EIO; 260 - u32 res, val; 261 - 262 - sg_init_one(&sg, buf, len); 263 - if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1) 264 - return -EIO; 265 - 266 - tdir = dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 267 - desc = dmaengine_prep_slave_sg(chan, &sg, 1, tdir, DMA_PREP_INTERRUPT); 268 - if (!desc) 269 - goto dma_unmap; 270 - 271 - desc->callback = tango_dma_callback; 272 - desc->callback_param = &tx_done; 273 - init_completion(&tx_done); 274 - 275 - writel_relaxed(MODE_NFC, nfc->pbus_base + PBUS_PAD_MODE); 276 - 277 - writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE); 278 - writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET); 279 - writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD); 280 - 281 - dmaengine_submit(desc); 282 - dma_async_issue_pending(chan); 283 - 284 - res = wait_for_completion_timeout(&tx_done, HZ); 285 - if (res > 0) 286 - err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000); 287 - 288 - writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); 289 - 290 - dma_unmap: 291 - dma_unmap_sg(chan->device->dev, &sg, 1, dir); 292 - 293 - return err; 294 - } 295 - 296 - static int tango_read_page(struct nand_chip *chip, u8 *buf, 297 - int oob_required, int page) 298 - { 299 - struct mtd_info *mtd = nand_to_mtd(chip); 300 - struct tango_nfc *nfc = to_tango_nfc(chip->controller); 301 - int err, res, len = mtd->writesize; 302 - 303 - tango_select_target(chip, chip->cur_cs); 304 - if (oob_required) 305 - chip->ecc.read_oob(chip, page); 306 - 307 - err = do_dma(nfc, DMA_FROM_DEVICE, NFC_READ, buf, len, page); 308 - if (err) 309 - return err; 310 - 311 - res = decode_error_report(chip); 312 - if (res < 0) { 313 - chip->ecc.read_oob_raw(chip, page); 314 - res = check_erased_page(chip, buf); 315 - } 316 - 317 - return res; 318 - } 319 - 320 - static int tango_write_page(struct nand_chip *chip, const u8 *buf, 321 - int oob_required, int page) 322 - { 323 - struct mtd_info *mtd = nand_to_mtd(chip); 324 - struct tango_nfc *nfc = to_tango_nfc(chip->controller); 325 - const struct nand_sdr_timings *timings; 326 - int err, len = mtd->writesize; 327 - u8 status; 328 - 329 - /* Calling tango_write_oob() would send PAGEPROG twice */ 330 - if (oob_required) 331 - return -ENOTSUPP; 332 - 333 - tango_select_target(chip, chip->cur_cs); 334 - writel_relaxed(0xffffffff, nfc->mem_base + METADATA); 335 - err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page); 336 - if (err) 337 - return err; 338 - 339 - timings = nand_get_sdr_timings(nand_get_interface_config(chip)); 340 - err = tango_waitrdy(chip, PSEC_TO_MSEC(timings->tR_max)); 341 - if (err) 342 - return err; 343 - 344 - err = nand_status_op(chip, &status); 345 - if (err) 346 - return err; 347 - 348 - return (status & NAND_STATUS_FAIL) ? -EIO : 0; 349 - } 350 - 351 - static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos) 352 - { 353 - *pos += len; 354 - 355 - if (!*buf) { 356 - /* skip over "len" bytes */ 357 - nand_change_read_column_op(chip, *pos, NULL, 0, false); 358 - } else { 359 - struct tango_chip *tchip = to_tango_chip(chip); 360 - 361 - ioread8_rep(tchip->base + PBUS_DATA, *buf, len); 362 - *buf += len; 363 - } 364 - } 365 - 366 - static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos) 367 - { 368 - *pos += len; 369 - 370 - if (!*buf) { 371 - /* skip over "len" bytes */ 372 - nand_change_write_column_op(chip, *pos, NULL, 0, false); 373 - } else { 374 - struct tango_chip *tchip = to_tango_chip(chip); 375 - 376 - iowrite8_rep(tchip->base + PBUS_DATA, *buf, len); 377 - *buf += len; 378 - } 379 - } 380 - 381 - /* 382 - * Physical page layout (not drawn to scale) 383 - * 384 - * NB: Bad Block Marker area splits PKT_N in two (N1, N2). 385 - * 386 - * +---+-----------------+-------+-----+-----------+-----+----+-------+ 387 - * | M | PKT_0 | ECC_0 | ... | N1 | BBM | N2 | ECC_N | 388 - * +---+-----------------+-------+-----+-----------+-----+----+-------+ 389 - * 390 - * Logical page layout: 391 - * 392 - * +-----+---+-------+-----+-------+ 393 - * oob = | BBM | M | ECC_0 | ... | ECC_N | 394 - * +-----+---+-------+-----+-------+ 395 - * 396 - * +-----------------+-----+-----------------+ 397 - * buf = | PKT_0 | ... | PKT_N | 398 - * +-----------------+-----+-----------------+ 399 - */ 400 - static void raw_read(struct nand_chip *chip, u8 *buf, u8 *oob) 401 - { 402 - struct mtd_info *mtd = nand_to_mtd(chip); 403 - u8 *oob_orig = oob; 404 - const int page_size = mtd->writesize; 405 - const int ecc_size = chip->ecc.bytes; 406 - const int pkt_size = chip->ecc.size; 407 - int pos = 0; /* position within physical page */ 408 - int rem = page_size; /* bytes remaining until BBM area */ 409 - 410 - if (oob) 411 - oob += BBM_SIZE; 412 - 413 - aux_read(chip, &oob, METADATA_SIZE, &pos); 414 - 415 - while (rem > pkt_size) { 416 - aux_read(chip, &buf, pkt_size, &pos); 417 - aux_read(chip, &oob, ecc_size, &pos); 418 - rem = page_size - pos; 419 - } 420 - 421 - aux_read(chip, &buf, rem, &pos); 422 - aux_read(chip, &oob_orig, BBM_SIZE, &pos); 423 - aux_read(chip, &buf, pkt_size - rem, &pos); 424 - aux_read(chip, &oob, ecc_size, &pos); 425 - } 426 - 427 - static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob) 428 - { 429 - struct mtd_info *mtd = nand_to_mtd(chip); 430 - const u8 *oob_orig = oob; 431 - const int page_size = mtd->writesize; 432 - const int ecc_size = chip->ecc.bytes; 433 - const int pkt_size = chip->ecc.size; 434 - int pos = 0; /* position within physical page */ 435 - int rem = page_size; /* bytes remaining until BBM area */ 436 - 437 - if (oob) 438 - oob += BBM_SIZE; 439 - 440 - aux_write(chip, &oob, METADATA_SIZE, &pos); 441 - 442 - while (rem > pkt_size) { 443 - aux_write(chip, &buf, pkt_size, &pos); 444 - aux_write(chip, &oob, ecc_size, &pos); 445 - rem = page_size - pos; 446 - } 447 - 448 - aux_write(chip, &buf, rem, &pos); 449 - aux_write(chip, &oob_orig, BBM_SIZE, &pos); 450 - aux_write(chip, &buf, pkt_size - rem, &pos); 451 - aux_write(chip, &oob, ecc_size, &pos); 452 - } 453 - 454 - static int tango_read_page_raw(struct nand_chip *chip, u8 *buf, 455 - int oob_required, int page) 456 - { 457 - tango_select_target(chip, chip->cur_cs); 458 - nand_read_page_op(chip, page, 0, NULL, 0); 459 - raw_read(chip, buf, chip->oob_poi); 460 - return 0; 461 - } 462 - 463 - static int tango_write_page_raw(struct nand_chip *chip, const u8 *buf, 464 - int oob_required, int page) 465 - { 466 - tango_select_target(chip, chip->cur_cs); 467 - nand_prog_page_begin_op(chip, page, 0, NULL, 0); 468 - raw_write(chip, buf, chip->oob_poi); 469 - return nand_prog_page_end_op(chip); 470 - } 471 - 472 - static int tango_read_oob(struct nand_chip *chip, int page) 473 - { 474 - tango_select_target(chip, chip->cur_cs); 475 - nand_read_page_op(chip, page, 0, NULL, 0); 476 - raw_read(chip, NULL, chip->oob_poi); 477 - return 0; 478 - } 479 - 480 - static int tango_write_oob(struct nand_chip *chip, int page) 481 - { 482 - tango_select_target(chip, chip->cur_cs); 483 - nand_prog_page_begin_op(chip, page, 0, NULL, 0); 484 - raw_write(chip, NULL, chip->oob_poi); 485 - return nand_prog_page_end_op(chip); 486 - } 487 - 488 - static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) 489 - { 490 - struct nand_chip *chip = mtd_to_nand(mtd); 491 - struct nand_ecc_ctrl *ecc = &chip->ecc; 492 - 493 - if (idx >= ecc->steps) 494 - return -ERANGE; 495 - 496 - res->offset = BBM_SIZE + METADATA_SIZE + ecc->bytes * idx; 497 - res->length = ecc->bytes; 498 - 499 - return 0; 500 - } 501 - 502 - static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) 503 - { 504 - return -ERANGE; /* no free space in spare area */ 505 - } 506 - 507 - static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = { 508 - .ecc = oob_ecc, 509 - .free = oob_free, 510 - }; 511 - 512 - static u32 to_ticks(int kHz, int ps) 513 - { 514 - return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC); 515 - } 516 - 517 - static int tango_set_timings(struct nand_chip *chip, int csline, 518 - const struct nand_interface_config *conf) 519 - { 520 - const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf); 521 - struct tango_nfc *nfc = to_tango_nfc(chip->controller); 522 - struct tango_chip *tchip = to_tango_chip(chip); 523 - u32 Trdy, Textw, Twc, Twpw, Tacc, Thold, Trpw, Textr; 524 - int kHz = nfc->freq_kHz; 525 - 526 - if (IS_ERR(sdr)) 527 - return PTR_ERR(sdr); 528 - 529 - if (csline == NAND_DATA_IFACE_CHECK_ONLY) 530 - return 0; 531 - 532 - Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max); 533 - Textw = to_ticks(kHz, sdr->tWB_max); 534 - Twc = to_ticks(kHz, sdr->tWC_min); 535 - Twpw = to_ticks(kHz, sdr->tWC_min - sdr->tWP_min); 536 - 537 - Tacc = to_ticks(kHz, sdr->tREA_max); 538 - Thold = to_ticks(kHz, sdr->tREH_min); 539 - Trpw = to_ticks(kHz, sdr->tRC_min - sdr->tREH_min); 540 - Textr = to_ticks(kHz, sdr->tRHZ_max); 541 - 542 - tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw); 543 - tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr); 544 - 545 - return 0; 546 - } 547 - 548 - static int tango_attach_chip(struct nand_chip *chip) 549 - { 550 - struct nand_ecc_ctrl *ecc = &chip->ecc; 551 - 552 - ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 553 - ecc->algo = NAND_ECC_ALGO_BCH; 554 - ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE); 555 - 556 - ecc->read_page_raw = tango_read_page_raw; 557 - ecc->write_page_raw = tango_write_page_raw; 558 - ecc->read_page = tango_read_page; 559 - ecc->write_page = tango_write_page; 560 - ecc->read_oob = tango_read_oob; 561 - ecc->write_oob = tango_write_oob; 562 - 563 - return 0; 564 - } 565 - 566 - static const struct nand_controller_ops tango_controller_ops = { 567 - .attach_chip = tango_attach_chip, 568 - .setup_interface = tango_set_timings, 569 - .exec_op = tango_exec_op, 570 - }; 571 - 572 - static int chip_init(struct device *dev, struct device_node *np) 573 - { 574 - u32 cs; 575 - int err, res; 576 - struct mtd_info *mtd; 577 - struct nand_chip *chip; 578 - struct tango_chip *tchip; 579 - struct nand_ecc_ctrl *ecc; 580 - struct tango_nfc *nfc = dev_get_drvdata(dev); 581 - 582 - tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL); 583 - if (!tchip) 584 - return -ENOMEM; 585 - 586 - res = of_property_count_u32_elems(np, "reg"); 587 - if (res < 0) 588 - return res; 589 - 590 - if (res != 1) 591 - return -ENOTSUPP; /* Multi-CS chips are not supported */ 592 - 593 - err = of_property_read_u32_index(np, "reg", 0, &cs); 594 - if (err) 595 - return err; 596 - 597 - if (cs >= MAX_CS) 598 - return -EINVAL; 599 - 600 - chip = &tchip->nand_chip; 601 - ecc = &chip->ecc; 602 - mtd = nand_to_mtd(chip); 603 - 604 - chip->options = NAND_USES_DMA | 605 - NAND_NO_SUBPAGE_WRITE | 606 - NAND_WAIT_TCCS; 607 - chip->controller = &nfc->hw; 608 - tchip->base = nfc->pbus_base + (cs * 256); 609 - 610 - nand_set_flash_node(chip, np); 611 - mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops); 612 - mtd->dev.parent = dev; 613 - 614 - err = nand_scan(chip, 1); 615 - if (err) 616 - return err; 617 - 618 - tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE); 619 - tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength); 620 - tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength); 621 - tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE); 622 - 623 - err = mtd_device_register(mtd, NULL, 0); 624 - if (err) { 625 - nand_cleanup(chip); 626 - return err; 627 - } 628 - 629 - nfc->chips[cs] = tchip; 630 - 631 - return 0; 632 - } 633 - 634 - static int tango_nand_remove(struct platform_device *pdev) 635 - { 636 - struct tango_nfc *nfc = platform_get_drvdata(pdev); 637 - struct nand_chip *chip; 638 - int cs, ret; 639 - 640 - dma_release_channel(nfc->chan); 641 - 642 - for (cs = 0; cs < MAX_CS; ++cs) { 643 - if (nfc->chips[cs]) { 644 - chip = &nfc->chips[cs]->nand_chip; 645 - ret = mtd_device_unregister(nand_to_mtd(chip)); 646 - WARN_ON(ret); 647 - nand_cleanup(chip); 648 - } 649 - } 650 - 651 - return 0; 652 - } 653 - 654 - static int tango_nand_probe(struct platform_device *pdev) 655 - { 656 - int err; 657 - struct clk *clk; 658 - struct resource *res; 659 - struct tango_nfc *nfc; 660 - struct device_node *np; 661 - 662 - nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); 663 - if (!nfc) 664 - return -ENOMEM; 665 - 666 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 667 - nfc->reg_base = devm_ioremap_resource(&pdev->dev, res); 668 - if (IS_ERR(nfc->reg_base)) 669 - return PTR_ERR(nfc->reg_base); 670 - 671 - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 672 - nfc->mem_base = devm_ioremap_resource(&pdev->dev, res); 673 - if (IS_ERR(nfc->mem_base)) 674 - return PTR_ERR(nfc->mem_base); 675 - 676 - res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 677 - nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res); 678 - if (IS_ERR(nfc->pbus_base)) 679 - return PTR_ERR(nfc->pbus_base); 680 - 681 - writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); 682 - 683 - clk = devm_clk_get(&pdev->dev, NULL); 684 - if (IS_ERR(clk)) 685 - return PTR_ERR(clk); 686 - 687 - nfc->chan = dma_request_chan(&pdev->dev, "rxtx"); 688 - if (IS_ERR(nfc->chan)) 689 - return PTR_ERR(nfc->chan); 690 - 691 - platform_set_drvdata(pdev, nfc); 692 - nand_controller_init(&nfc->hw); 693 - nfc->hw.ops = &tango_controller_ops; 694 - nfc->freq_kHz = clk_get_rate(clk) / 1000; 695 - 696 - for_each_child_of_node(pdev->dev.of_node, np) { 697 - err = chip_init(&pdev->dev, np); 698 - if (err) { 699 - tango_nand_remove(pdev); 700 - of_node_put(np); 701 - return err; 702 - } 703 - } 704 - 705 - return 0; 706 - } 707 - 708 - static const struct of_device_id tango_nand_ids[] = { 709 - { .compatible = "sigma,smp8758-nand" }, 710 - { /* sentinel */ } 711 - }; 712 - MODULE_DEVICE_TABLE(of, tango_nand_ids); 713 - 714 - static struct platform_driver tango_nand_driver = { 715 - .probe = tango_nand_probe, 716 - .remove = tango_nand_remove, 717 - .driver = { 718 - .name = "tango-nand", 719 - .of_match_table = tango_nand_ids, 720 - }, 721 - }; 722 - 723 - module_platform_driver(tango_nand_driver); 724 - 725 - MODULE_LICENSE("GPL"); 726 - MODULE_AUTHOR("Sigma Designs"); 727 - MODULE_DESCRIPTION("Tango4 NAND Flash controller driver");

+8

drivers/mtd/parsers/Kconfig

··· 160 160 'FIS directory' images, enable this option. 161 161 162 162 endif # MTD_REDBOOT_PARTS 163 + 164 + config MTD_QCOMSMEM_PARTS 165 + tristate "Qualcomm SMEM NAND flash partition parser" 166 + depends on MTD_NAND_QCOM || COMPILE_TEST 167 + depends on QCOM_SMEM 168 + help 169 + This provides support for parsing partitions from Shared Memory (SMEM) 170 + for NAND flash on Qualcomm platforms.

+1

drivers/mtd/parsers/Makefile

··· 9 9 obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o 10 10 obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o 11 11 obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o 12 + obj-$(CONFIG_MTD_QCOMSMEM_PARTS) += qcomsmempart.o

+170

drivers/mtd/parsers/qcomsmempart.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Qualcomm SMEM NAND flash partition parser 4 + * 5 + * Copyright (C) 2020, Linaro Ltd. 6 + */ 7 + 8 + #include <linux/ctype.h> 9 + #include <linux/module.h> 10 + #include <linux/mtd/mtd.h> 11 + #include <linux/mtd/partitions.h> 12 + #include <linux/slab.h> 13 + #include <linux/soc/qcom/smem.h> 14 + 15 + #define SMEM_AARM_PARTITION_TABLE 9 16 + #define SMEM_APPS 0 17 + 18 + #define SMEM_FLASH_PART_MAGIC1 0x55ee73aa 19 + #define SMEM_FLASH_PART_MAGIC2 0xe35ebddb 20 + #define SMEM_FLASH_PTABLE_V3 3 21 + #define SMEM_FLASH_PTABLE_V4 4 22 + #define SMEM_FLASH_PTABLE_MAX_PARTS_V3 16 23 + #define SMEM_FLASH_PTABLE_MAX_PARTS_V4 48 24 + #define SMEM_FLASH_PTABLE_HDR_LEN (4 * sizeof(u32)) 25 + #define SMEM_FLASH_PTABLE_NAME_SIZE 16 26 + 27 + /** 28 + * struct smem_flash_pentry - SMEM Flash partition entry 29 + * @name: Name of the partition 30 + * @offset: Offset in blocks 31 + * @length: Length of the partition in blocks 32 + * @attr: Flags for this partition 33 + */ 34 + struct smem_flash_pentry { 35 + char name[SMEM_FLASH_PTABLE_NAME_SIZE]; 36 + __le32 offset; 37 + __le32 length; 38 + u8 attr; 39 + } __packed __aligned(4); 40 + 41 + /** 42 + * struct smem_flash_ptable - SMEM Flash partition table 43 + * @magic1: Partition table Magic 1 44 + * @magic2: Partition table Magic 2 45 + * @version: Partition table version 46 + * @numparts: Number of partitions in this ptable 47 + * @pentry: Flash partition entries belonging to this ptable 48 + */ 49 + struct smem_flash_ptable { 50 + __le32 magic1; 51 + __le32 magic2; 52 + __le32 version; 53 + __le32 numparts; 54 + struct smem_flash_pentry pentry[SMEM_FLASH_PTABLE_MAX_PARTS_V4]; 55 + } __packed __aligned(4); 56 + 57 + static int parse_qcomsmem_part(struct mtd_info *mtd, 58 + const struct mtd_partition **pparts, 59 + struct mtd_part_parser_data *data) 60 + { 61 + struct smem_flash_pentry *pentry; 62 + struct smem_flash_ptable *ptable; 63 + size_t len = SMEM_FLASH_PTABLE_HDR_LEN; 64 + struct mtd_partition *parts; 65 + int ret, i, numparts; 66 + char *name, *c; 67 + 68 + pr_debug("Parsing partition table info from SMEM\n"); 69 + ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len); 70 + if (IS_ERR(ptable)) { 71 + pr_err("Error reading partition table header\n"); 72 + return PTR_ERR(ptable); 73 + } 74 + 75 + /* Verify ptable magic */ 76 + if (le32_to_cpu(ptable->magic1) != SMEM_FLASH_PART_MAGIC1 || 77 + le32_to_cpu(ptable->magic2) != SMEM_FLASH_PART_MAGIC2) { 78 + pr_err("Partition table magic verification failed\n"); 79 + return -EINVAL; 80 + } 81 + 82 + /* Ensure that # of partitions is less than the max we have allocated */ 83 + numparts = le32_to_cpu(ptable->numparts); 84 + if (numparts > SMEM_FLASH_PTABLE_MAX_PARTS_V4) { 85 + pr_err("Partition numbers exceed the max limit\n"); 86 + return -EINVAL; 87 + } 88 + 89 + /* Find out length of partition data based on table version */ 90 + if (le32_to_cpu(ptable->version) <= SMEM_FLASH_PTABLE_V3) { 91 + len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V3 * 92 + sizeof(struct smem_flash_pentry); 93 + } else if (le32_to_cpu(ptable->version) == SMEM_FLASH_PTABLE_V4) { 94 + len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V4 * 95 + sizeof(struct smem_flash_pentry); 96 + } else { 97 + pr_err("Unknown ptable version (%d)", le32_to_cpu(ptable->version)); 98 + return -EINVAL; 99 + } 100 + 101 + /* 102 + * Now that the partition table header has been parsed, verified 103 + * and the length of the partition table calculated, read the 104 + * complete partition table 105 + */ 106 + ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len); 107 + if (IS_ERR_OR_NULL(ptable)) { 108 + pr_err("Error reading partition table\n"); 109 + return PTR_ERR(ptable); 110 + } 111 + 112 + parts = kcalloc(numparts, sizeof(*parts), GFP_KERNEL); 113 + if (!parts) 114 + return -ENOMEM; 115 + 116 + for (i = 0; i < numparts; i++) { 117 + pentry = &ptable->pentry[i]; 118 + if (pentry->name[0] == '\0') 119 + continue; 120 + 121 + name = kstrdup(pentry->name, GFP_KERNEL); 122 + if (!name) { 123 + ret = -ENOMEM; 124 + goto out_free_parts; 125 + } 126 + 127 + /* Convert name to lower case */ 128 + for (c = name; *c != '\0'; c++) 129 + *c = tolower(*c); 130 + 131 + parts[i].name = name; 132 + parts[i].offset = le32_to_cpu(pentry->offset) * mtd->erasesize; 133 + parts[i].mask_flags = pentry->attr; 134 + parts[i].size = le32_to_cpu(pentry->length) * mtd->erasesize; 135 + pr_debug("%d: %s offs=0x%08x size=0x%08x attr:0x%08x\n", 136 + i, pentry->name, le32_to_cpu(pentry->offset), 137 + le32_to_cpu(pentry->length), pentry->attr); 138 + } 139 + 140 + pr_debug("SMEM partition table found: ver: %d len: %d\n", 141 + le32_to_cpu(ptable->version), numparts); 142 + *pparts = parts; 143 + 144 + return numparts; 145 + 146 + out_free_parts: 147 + while (--i >= 0) 148 + kfree(parts[i].name); 149 + kfree(parts); 150 + *pparts = NULL; 151 + 152 + return ret; 153 + } 154 + 155 + static const struct of_device_id qcomsmem_of_match_table[] = { 156 + { .compatible = "qcom,smem-part" }, 157 + {}, 158 + }; 159 + MODULE_DEVICE_TABLE(of, qcomsmem_of_match_table); 160 + 161 + static struct mtd_part_parser mtd_parser_qcomsmem = { 162 + .parse_fn = parse_qcomsmem_part, 163 + .name = "qcomsmem", 164 + .of_match_table = qcomsmem_of_match_table, 165 + }; 166 + module_mtd_part_parser(mtd_parser_qcomsmem); 167 + 168 + MODULE_LICENSE("GPL v2"); 169 + MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 170 + MODULE_DESCRIPTION("Qualcomm SMEM NAND flash partition parser");