dt-bindings: clk: vc5: Fix example

The example properties do not match the binding. Fix them, and prohibit
undocumented properties in clock nodes to prevent this from happening in
the future.

Fixes: 45c940184b50 ("dt-bindings: clk: versaclock5: convert to yaml")
Signed-off-by: Sean Anderson <[e-mail]>
Reviewed-by: Luca Ceresoli <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Rob Herring <[e-mail]>

Documentation/devicetree/bindings/clock/idt,versaclock5.yaml

···
         description: The Slew rate control for CMOS single-ended.
         $ref: /schemas/types.yaml#/definitions/uint32
         enum: [ 80, 85, 90, 100 ]
+    additionalProperties: false
 
 required:
   - compatible
···
             clock-names = "xin";
 
             OUT1 {
-                idt,drive-mode = <VC5_CMOSD>;
-                idt,voltage-microvolts = <1800000>;
+                idt,mode = <VC5_CMOSD>;
+                idt,voltage-microvolt = <1800000>;
                 idt,slew-percent = <80>;
             };
 
             OUT4 {
-                idt,drive-mode = <VC5_LVDS>;
+                idt,mode = <VC5_LVDS>;
             };
         };
     };