···151151first 18 GPIOs, at local offset 0 .. 17, are in use.152152153153If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an154154-additional bitmask is needed to specify which GPIOs are actually in use,155155-and which are dummies. The bindings for this case has not yet been156156-specified, but should be specified if/when such hardware appears.154154+additional set of tuples is needed to specify which GPIOs are unusable, with155155+the gpio-reserved-ranges binding. This property indicates the start and size156156+of the GPIOs that can't be used.157157158158Optionally, a GPIO controller may have a "gpio-line-names" property. This is159159an array of strings defining the names of the GPIO lines going out of the···178178 gpio-controller;179179 #gpio-cells = <2>;180180 ngpios = <18>;181181+ gpio-reserved-ranges = <0 4>, <12 2>;181182 gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",182183 "LED G", "LED B", "Col A", "Col B", "Col C", "Col D",183184 "Row A", "Row B", "Row C", "Row D", "NMI button",
+24
drivers/gpio/gpiolib-of.c
···511511}512512EXPORT_SYMBOL(of_mm_gpiochip_remove);513513514514+static void of_gpiochip_init_valid_mask(struct gpio_chip *chip)515515+{516516+ int len, i;517517+ u32 start, count;518518+ struct device_node *np = chip->of_node;519519+520520+ len = of_property_count_u32_elems(np, "gpio-reserved-ranges");521521+ if (len < 0 || len % 2 != 0)522522+ return;523523+524524+ for (i = 0; i < len; i += 2) {525525+ of_property_read_u32_index(np, "gpio-reserved-ranges",526526+ i, &start);527527+ of_property_read_u32_index(np, "gpio-reserved-ranges",528528+ i + 1, &count);529529+ if (start >= chip->ngpio || start + count >= chip->ngpio)530530+ continue;531531+532532+ bitmap_clear(chip->valid_mask, start, count);533533+ }534534+};535535+514536#ifdef CONFIG_PINCTRL515537static int of_gpiochip_add_pin_range(struct gpio_chip *chip)516538{···636614637615 if (chip->of_gpio_n_cells > MAX_PHANDLE_ARGS)638616 return -EINVAL;617617+618618+ of_gpiochip_init_valid_mask(chip);639619640620 status = of_gpiochip_add_pin_range(chip);641621 if (status)
+61-5
drivers/gpio/gpiolib.c
···337337 return 0;338338}339339340340+static unsigned long *gpiochip_allocate_mask(struct gpio_chip *chip)341341+{342342+ unsigned long *p;343343+344344+ p = kmalloc_array(BITS_TO_LONGS(chip->ngpio), sizeof(*p), GFP_KERNEL);345345+ if (!p)346346+ return NULL;347347+348348+ /* Assume by default all GPIOs are valid */349349+ bitmap_fill(p, chip->ngpio);350350+351351+ return p;352352+}353353+354354+static int gpiochip_init_valid_mask(struct gpio_chip *gpiochip)355355+{356356+#ifdef CONFIG_OF_GPIO357357+ int size;358358+ struct device_node *np = gpiochip->of_node;359359+360360+ size = of_property_count_u32_elems(np, "gpio-reserved-ranges");361361+ if (size > 0 && size % 2 == 0)362362+ gpiochip->need_valid_mask = true;363363+#endif364364+365365+ if (!gpiochip->need_valid_mask)366366+ return 0;367367+368368+ gpiochip->valid_mask = gpiochip_allocate_mask(gpiochip);369369+ if (!gpiochip->valid_mask)370370+ return -ENOMEM;371371+372372+ return 0;373373+}374374+375375+static void gpiochip_free_valid_mask(struct gpio_chip *gpiochip)376376+{377377+ kfree(gpiochip->valid_mask);378378+ gpiochip->valid_mask = NULL;379379+}380380+381381+bool gpiochip_line_is_valid(const struct gpio_chip *gpiochip,382382+ unsigned int offset)383383+{384384+ /* No mask means all valid */385385+ if (likely(!gpiochip->valid_mask))386386+ return true;387387+ return test_bit(offset, gpiochip->valid_mask);388388+}389389+EXPORT_SYMBOL_GPL(gpiochip_line_is_valid);390390+340391/*341392 * GPIO line handle management342393 */···13121261 if (status)13131262 goto err_remove_from_list;1314126312641264+ status = gpiochip_init_valid_mask(chip);12651265+ if (status)12661266+ goto err_remove_irqchip_mask;12671267+13151268 status = gpiochip_add_irqchip(chip, lock_key, request_key);13161269 if (status)13171270 goto err_remove_chip;···13451290 acpi_gpiochip_remove(chip);13461291 gpiochip_free_hogs(chip);13471292 of_gpiochip_remove(chip);12931293+ gpiochip_free_valid_mask(chip);12941294+err_remove_irqchip_mask:13481295 gpiochip_irqchip_free_valid_mask(chip);13491296err_remove_from_list:13501297 spin_lock_irqsave(&gpio_lock, flags);···14031346 acpi_gpiochip_remove(chip);14041347 gpiochip_remove_pin_ranges(chip);14051348 of_gpiochip_remove(chip);13491349+ gpiochip_free_valid_mask(chip);14061350 /*14071351 * We accept no more calls into the driver from this point, so14081352 * NULL the driver data pointer···15641506 if (!gpiochip->irq.need_valid_mask)15651507 return 0;1566150815671567- gpiochip->irq.valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio),15681568- sizeof(long), GFP_KERNEL);15091509+ gpiochip->irq.valid_mask = gpiochip_allocate_mask(gpiochip);15691510 if (!gpiochip->irq.valid_mask)15701511 return -ENOMEM;15711571-15721572- /* Assume by default all GPIOs are valid */15731573- bitmap_fill(gpiochip->irq.valid_mask, gpiochip->ngpio);1574151215751513 return 0;15761514}···15801526bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,15811527 unsigned int offset)15821528{15291529+ if (!gpiochip_line_is_valid(gpiochip, offset))15301530+ return false;15831531 /* No mask means all valid */15841532 if (likely(!gpiochip->irq.valid_mask))15851533 return true;
+62-3
drivers/pinctrl/qcom/pinctrl-msm.c
···105105 .dt_free_map = pinctrl_utils_free_map,106106};107107108108+static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)109109+{110110+ struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);111111+ struct gpio_chip *chip = &pctrl->chip;112112+113113+ return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;114114+}115115+108116static int msm_get_functions_count(struct pinctrl_dev *pctldev)109117{110118 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);···174166}175167176168static const struct pinmux_ops msm_pinmux_ops = {169169+ .request = msm_pinmux_request,177170 .get_functions_count = msm_get_functions_count,178171 .get_function_name = msm_get_function_name,179172 .get_function_groups = msm_get_function_groups,···515506 "pull up"516507 };517508509509+ if (!gpiochip_line_is_valid(chip, offset))510510+ return;511511+518512 g = &pctrl->soc->groups[offset];519513 ctl_reg = readl(pctrl->regs + g->ctl_reg);520514···529517 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);530518 seq_printf(s, " %dmA", msm_regval_to_drive(drive));531519 seq_printf(s, " %s", pulls[pull]);520520+ seq_puts(s, "\n");532521}533522534523static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)···537524 unsigned gpio = chip->base;538525 unsigned i;539526540540- for (i = 0; i < chip->ngpio; i++, gpio++) {527527+ for (i = 0; i < chip->ngpio; i++, gpio++)541528 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);542542- seq_puts(s, "\n");543543- }544529}545530546531#else···819808 chained_irq_exit(chip, desc);820809}821810811811+static int msm_gpio_init_valid_mask(struct gpio_chip *chip,812812+ struct msm_pinctrl *pctrl)813813+{814814+ int ret;815815+ unsigned int len, i;816816+ unsigned int max_gpios = pctrl->soc->ngpios;817817+ u16 *tmp;818818+819819+ /* The number of GPIOs in the ACPI tables */820820+ len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0);821821+ if (ret < 0)822822+ return 0;823823+824824+ if (ret > max_gpios)825825+ return -EINVAL;826826+827827+ tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);828828+ if (!tmp)829829+ return -ENOMEM;830830+831831+ ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);832832+ if (ret < 0) {833833+ dev_err(pctrl->dev, "could not read list of GPIOs\n");834834+ goto out;835835+ }836836+837837+ bitmap_zero(chip->valid_mask, max_gpios);838838+ for (i = 0; i < len; i++)839839+ set_bit(tmp[i], chip->valid_mask);840840+841841+out:842842+ kfree(tmp);843843+ return ret;844844+}845845+846846+static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)847847+{848848+ return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0;849849+}850850+822851static int msm_gpio_init(struct msm_pinctrl *pctrl)823852{824853 struct gpio_chip *chip;···875824 chip->parent = pctrl->dev;876825 chip->owner = THIS_MODULE;877826 chip->of_node = pctrl->dev->of_node;827827+ chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl);878828879829 ret = gpiochip_add_data(&pctrl->chip, pctrl);880830 if (ret) {881831 dev_err(pctrl->dev, "Failed register gpiochip\n");832832+ return ret;833833+ }834834+835835+ ret = msm_gpio_init_valid_mask(chip, pctrl);836836+ if (ret) {837837+ dev_err(pctrl->dev, "Failed to setup irq valid bits\n");838838+ gpiochip_remove(&pctrl->chip);882839 return ret;883840 }884841
+16
include/linux/gpio/driver.h
···288288 struct gpio_irq_chip irq;289289#endif290290291291+ /**292292+ * @need_valid_mask:293293+ *294294+ * If set core allocates @valid_mask with all bits set to one.295295+ */296296+ bool need_valid_mask;297297+298298+ /**299299+ * @valid_mask:300300+ *301301+ * If not %NULL holds bitmask of GPIOs which are valid to be used302302+ * from the chip.303303+ */304304+ unsigned long *valid_mask;305305+291306#if defined(CONFIG_OF_GPIO)292307 /*293308 * If CONFIG_OF is enabled, then all GPIO controllers described in the···399384400385/* Sleep persistence inquiry for drivers */401386bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);387387+bool gpiochip_line_is_valid(const struct gpio_chip *chip, unsigned int offset);402388403389/* get driver data */404390void *gpiochip_get_data(struct gpio_chip *chip);