Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

regulator: rtmv20: Update DT binding document and property name parsing

1. Add vendor suffix to all proprietary properties.
2. Fix typo.
3. Change lsw to normal property, not pattern property.
4. Due to item 1, modify source code for property parsing.

Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
Link: https://lore.kernel.org/r/1601460480-4259-1-git-send-email-u0084500@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

ChiYuan Huang and committed by
Mark Brown
89a5f77e 71d5f4dc

+42 -47
+22 -31
Documentation/devicetree/bindings/regulator/richtek,rtmv20-regulator.yaml
··· 26 26 27 27 wakeup-source: true 28 28 29 - interrupts-extend: 29 + interrupts: 30 30 maxItems: 1 31 31 32 32 enable-gpios: 33 33 description: A connection of the 'enable' gpio line. 34 34 maxItems: 1 35 35 36 - ld-pulse-delay-us: 36 + richtek,ld-pulse-delay-us: 37 37 description: | 38 38 load current pulse delay in microsecond after strobe pin pulse high. 39 - $ref: "/schemas/types.yaml#/definitions/uint32" 40 39 minimum: 0 41 40 maximum: 100000 42 41 default: 0 43 42 44 - ld-pulse-width-us: 43 + richtek,ld-pulse-width-us: 45 44 description: | 46 45 Load current pulse width in microsecond after strobe pin pulse high. 47 - $ref: "/schemas/types.yaml#/definitions/uint32" 48 46 minimum: 0 49 47 maximum: 10000 50 48 default: 1200 51 49 52 - fsin1-delay-us: 50 + richtek,fsin1-delay-us: 53 51 description: | 54 52 Fsin1 pulse high delay in microsecond after vsync signal pulse high. 55 - $ref: "/schemas/types.yaml#/definitions/uint32" 56 53 minimum: 0 57 54 maximum: 100000 58 55 default: 23000 59 56 60 - fsin1-width-us: 57 + richtek,fsin1-width-us: 61 58 description: | 62 59 Fsin1 pulse high width in microsecond after vsync signal pulse high. 63 - $ref: "/schemas/types.yaml#/definitions/uint32" 64 60 minimum: 40 65 61 maximum: 10000 66 62 default: 160 67 63 68 - fsin2-delay-us: 64 + richtek,fsin2-delay-us: 69 65 description: | 70 66 Fsin2 pulse high delay in microsecond after vsync signal pulse high. 71 - $ref: "/schemas/types.yaml#/definitions/uint32" 72 67 minimum: 0 73 68 maximum: 100000 74 69 default: 23000 75 70 76 - fsin2-width-us: 71 + richtek,fsin2-width-us: 77 72 description: | 78 73 Fsin2 pulse high width in microsecond after vsync signal pulse high. 79 - $ref: "/schemas/types.yaml#/definitions/uint32" 80 74 minimum: 40 81 75 maximum: 10000 82 76 default: 160 83 77 84 - es-pulse-width-us: 78 + richtek,es-pulse-width-us: 85 79 description: Eye safety function pulse width limit in microsecond. 86 - $ref: "/schemas/types.yaml#/definitions/uint32" 87 80 minimum: 0 88 81 maximum: 10000 89 82 default: 1200 90 83 91 - es-ld-current-microamp: 84 + richtek,es-ld-current-microamp: 92 85 description: Eye safety function load current limit in microamp. 93 - $ref: "/schemas/types.yaml#/definitions/uint32" 94 86 minimum: 0 95 87 maximum: 6000000 96 88 default: 3000000 97 89 98 - lbp-level-microvolt: 90 + richtek,lbp-level-microvolt: 99 91 description: Low battery protection level in microvolt. 100 - $ref: "/schemas/types.yaml#/definitions/uint32" 101 92 minimum: 2400000 102 93 maximum: 3700000 103 94 default: 2700000 104 95 105 - lbp-enable: 96 + richtek,lbp-enable: 106 97 description: Low battery protection function enable control. 107 98 type: boolean 108 99 109 - strobe-polarity-high: 100 + richtek,strobe-polarity-high: 110 101 description: Strobe pin active polarity control. 111 102 type: boolean 112 103 113 - vsync-polarity-high: 104 + richtek,vsync-polarity-high: 114 105 description: Vsync pin active polarity control. 115 106 type: boolean 116 107 117 - fsin-enable: 108 + richtek,fsin-enable: 118 109 description: Fsin function enable control. 119 110 type: boolean 120 111 121 - fsin-output: 112 + richtek,fsin-output: 122 113 description: Fsin function output control. 123 114 type: boolean 124 115 125 - es-enable: 116 + richtek,es-enable: 126 117 description: Eye safety function enable control. 127 118 type: boolean 128 119 129 - patternProperties: 130 - "lsw": 120 + lsw: 121 + description: load switch current regulator description. 131 122 type: object 132 123 $ref: "regulator.yaml#" 133 124 ··· 126 135 - compatible 127 136 - reg 128 137 - wakeup-source 129 - - interrupts-extend 138 + - interrupts 130 139 - enable-gpios 131 140 - lsw 132 141 ··· 143 152 compatible = "richtek,rtmv20"; 144 153 reg = <0x34>; 145 154 wakeup-source; 146 - interrupts-extend = <&gpio26 2 IRQ_TYPE_LEVEL_LOW>; 155 + interrupts-extended = <&gpio26 2 IRQ_TYPE_LEVEL_LOW>; 147 156 enable-gpios = <&gpio26 3 0>; 148 157 149 - strobe-polarity-high; 150 - vsync-polarity-high; 158 + richtek,strobe-polarity-high; 159 + richtek,vsync-polarity-high; 151 160 152 161 lsw { 153 162 regulator-name = "rtmv20,lsw";
+20 -16
drivers/regulator/rtmv20-regulator.c
··· 166 166 u32 addr; 167 167 u32 mask; 168 168 } props[] = { 169 - { "ld-pulse-delay-us", 0, 0, 100000, 100, RTMV20_REG_PULSEDELAY, 169 + { "richtek,ld-pulse-delay-us", 0, 0, 100000, 100, RTMV20_REG_PULSEDELAY, 170 170 RTMV20_DELAY_MASK }, 171 - { "ld-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_PULSEWIDTH, 171 + { "richtek,ld-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_PULSEWIDTH, 172 172 RTMV20_WIDTH_MASK }, 173 - { "fsin1-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN1CTRL1, 173 + { "richtek,fsin1-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN1CTRL1, 174 174 RTMV20_DELAY_MASK }, 175 - { "fsin1-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN1CTRL3, RTMV20_WIDTH2_MASK }, 176 - { "fsin2-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN2CTRL1, 175 + { "richtek,fsin1-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN1CTRL3, 176 + RTMV20_WIDTH2_MASK }, 177 + { "richtek,fsin2-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN2CTRL1, 177 178 RTMV20_DELAY_MASK }, 178 - { "fsin2-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN2CTRL3, RTMV20_WIDTH2_MASK }, 179 - { "es-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_ESPULSEWIDTH, 179 + { "richtek,fsin2-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN2CTRL3, 180 + RTMV20_WIDTH2_MASK }, 181 + { "richtek,es-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_ESPULSEWIDTH, 180 182 RTMV20_WIDTH_MASK }, 181 - { "es-ld-current-microamp", 3000000, 0, 6000000, 30000, RTMV20_REG_ESLDCTRL1, 182 - RTMV20_LDCURR_MASK }, 183 - { "lbp-level-microvolt", 2700000, 2400000, 3700000, 100000, RTMV20_REG_LBP, 183 + { "richtek,es-ld-current-microamp", 3000000, 0, 6000000, 30000, 184 + RTMV20_REG_ESLDCTRL1, RTMV20_LDCURR_MASK }, 185 + { "richtek,lbp-level-microvolt", 2700000, 2400000, 3700000, 100000, RTMV20_REG_LBP, 184 186 RTMV20_LBPLVL_MASK }, 185 - { "lbp-enable", 0, 0, 1, 1, RTMV20_REG_LBP, RTMV20_LBPEN_MASK }, 186 - { "strobe-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2, RTMV20_STROBEPOL_MASK }, 187 - { "vsync-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2, RTMV20_VSYNPOL_MASK }, 188 - { "fsin-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINEN_MASK }, 189 - { "fsin-output", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINOUT_MASK }, 190 - { "es-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_ESEN_MASK }, 187 + { "richtek,lbp-enable", 0, 0, 1, 1, RTMV20_REG_LBP, RTMV20_LBPEN_MASK }, 188 + { "richtek,strobe-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2, 189 + RTMV20_STROBEPOL_MASK }, 190 + { "richtek,vsync-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2, 191 + RTMV20_VSYNPOL_MASK }, 192 + { "richtek,fsin-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINEN_MASK }, 193 + { "richtek,fsin-output", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINOUT_MASK }, 194 + { "richtek,es-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_ESEN_MASK }, 191 195 }; 192 196 int i, ret; 193 197