Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Ocelot: remove remaining bits
[MIPS] TLB: Fix instruction bitmasks
[MIPS] R10000: Fix wrong test in dma-default.c
[MIPS] Provide empty irq_enable_hazard definition for legacy and R1 cores.
[MIPS] Sibyte: Remove broken dependency on EXPERIMENTAL from SIBYTE_SB1xxx_SOC.
[MIPS] Kconfig: whitespace cleanup.
[MIPS] PCI: Set need_domain_info if controller domain index is non-zero.
[MIPS] BCM1480: Fix computation of interrupt mask address register.
[MIPS] i8259: Add disable method.
[MIPS] tty: add the new ioctls and definitions.

+27 -60
+4 -18
arch/mips/Kconfig
··· 80 80 If you have one of the following DECstation Models you definitely 81 81 want to choose R4xx0 for the CPU Type: 82 82 83 - DECstation 5000/50 84 - DECstation 5000/150 85 - DECstation 5000/260 86 - DECsystem 5900/260 83 + DECstation 5000/50 84 + DECstation 5000/150 85 + DECstation 5000/260 86 + DECsystem 5900/260 87 87 88 88 otherwise choose R3000. 89 89 ··· 817 817 818 818 config SERIAL_RM9000 819 819 bool 820 - 821 - # 822 - # Unfortunately not all GT64120 systems run the chip at the same clock. 823 - # As the user for the clock rate and try to minimize the available options. 824 - # 825 - choice 826 - prompt "Galileo Chip Clock" 827 - depends on MOMENCO_OCELOT 828 - default SYSCLK_100 if MOMENCO_OCELOT 829 - 830 - config SYSCLK_100 831 - bool "100" if MOMENCO_OCELOT 832 - 833 - endchoice 834 820 835 821 config ARC32 836 822 bool
+1
arch/mips/kernel/i8259.c
··· 36 36 static struct irq_chip i8259A_chip = { 37 37 .name = "XT-PIC", 38 38 .mask = disable_8259A_irq, 39 + .disable = disable_8259A_irq, 39 40 .unmask = enable_8259A_irq, 40 41 .mask_ack = mask_and_ack_8259A, 41 42 };
+1 -1
arch/mips/mm/dma-default.c
··· 35 35 static inline int cpu_is_noncoherent_r10000(struct device *dev) 36 36 { 37 37 return !plat_device_is_coherent(dev) && 38 - (current_cpu_data.cputype == CPU_R10000 && 38 + (current_cpu_data.cputype == CPU_R10000 || 39 39 current_cpu_data.cputype == CPU_R12000); 40 40 } 41 41
+2 -2
arch/mips/mm/tlbex.c
··· 78 78 SET = 0x200 79 79 }; 80 80 81 - #define OP_MASK 0x2f 81 + #define OP_MASK 0x3f 82 82 #define OP_SH 26 83 83 #define RS_MASK 0x1f 84 84 #define RS_SH 21 ··· 92 92 #define IMM_SH 0 93 93 #define JIMM_MASK 0x3ffffff 94 94 #define JIMM_SH 0 95 - #define FUNC_MASK 0x2f 95 + #define FUNC_MASK 0x3f 96 96 #define FUNC_SH 0 97 97 #define SET_MASK 0x7 98 98 #define SET_SH 0
+1
arch/mips/pci/pci.c
··· 141 141 142 142 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 143 143 hose->bus = bus; 144 + need_domain_info = need_domain_info || hose->index; 144 145 hose->need_domain_info = need_domain_info; 145 146 if (bus) { 146 147 next_busno = bus->subordinate + 1;
-1
arch/mips/sibyte/Kconfig
··· 48 48 49 49 config SIBYTE_SB1xxx_SOC 50 50 bool 51 - depends on EXPERIMENTAL 52 51 select DMA_COHERENT 53 52 select SIBYTE_CFE 54 53 select SWAP_IO_SPACE
+4 -4
arch/mips/sibyte/bcm1480/irq.c
··· 100 100 101 101 void bcm1480_mask_irq(int cpu, int irq) 102 102 { 103 - unsigned long flags; 104 - u64 cur_ints,hl_spacing; 103 + unsigned long flags, hl_spacing; 104 + u64 cur_ints; 105 105 106 106 spin_lock_irqsave(&bcm1480_imr_lock, flags); 107 107 hl_spacing = 0; ··· 117 117 118 118 void bcm1480_unmask_irq(int cpu, int irq) 119 119 { 120 - unsigned long flags; 121 - u64 cur_ints,hl_spacing; 120 + unsigned long flags, hl_spacing; 121 + u64 cur_ints; 122 122 123 123 spin_lock_irqsave(&bcm1480_imr_lock, flags); 124 124 hl_spacing = 0;
+1
include/asm-mips/hazards.h
··· 172 172 nop; nop; nop 173 173 ) 174 174 ASMMACRO(irq_enable_hazard, 175 + _ssnop; _ssnop; _ssnop; 175 176 ) 176 177 ASMMACRO(irq_disable_hazard, 177 178 nop; nop; nop
+4
include/asm-mips/ioctls.h
··· 77 77 #define TIOCSBRK 0x5427 /* BSD compatibility */ 78 78 #define TIOCCBRK 0x5428 /* BSD compatibility */ 79 79 #define TIOCGSID 0x7416 /* Return the session ID of FD */ 80 + #define TCGETS2 _IOR('T',0x2A, struct termios2) 81 + #define TCSETS2 _IOW('T',0x2B, struct termios2) 82 + #define TCSETSW2 _IOW('T',0x2C, struct termios2) 83 + #define TCSETSF2 _IOW('T',0x2D, struct termios2) 80 84 #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ 81 85 #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ 82 86
-30
include/asm-mips/mach-ocelot/mach-gt64120.h
··· 1 - /* 2 - * Copyright 2001 MontaVista Software Inc. 3 - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 4 - * 5 - * This program is free software; you can redistribute it and/or modify it 6 - * under the terms of the GNU General Public License as published by the 7 - * Free Software Foundation; either version 2 of the License, or (at your 8 - * option) any later version. 9 - */ 10 - #ifndef _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H 11 - #define _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H 12 - 13 - /* 14 - * PCI address allocation 15 - */ 16 - #define GT_PCI_MEM_BASE (0x22000000UL) 17 - #define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE 18 - #define GT_PCI_IO_BASE (0x20000000UL) 19 - #define GT_PCI_IO_SIZE GT_DEF_PCI0_IO_SIZE 20 - 21 - extern unsigned long gt64120_base; 22 - 23 - #define GT64120_BASE (gt64120_base) 24 - 25 - /* 26 - * GT timer irq 27 - */ 28 - #define GT_TIMER 6 29 - 30 - #endif /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */
+5 -2
include/asm-mips/termbits.h
··· 164 164 #define HUPCL 0002000 /* Hang up on last close. */ 165 165 #define CLOCAL 0004000 /* Ignore modem status lines. */ 166 166 #define CBAUDEX 0010000 167 + #define BOTHER 0010000 167 168 #define B57600 0010001 168 169 #define B115200 0010002 169 170 #define B230400 0010003 ··· 180 179 #define B3000000 0010015 181 180 #define B3500000 0010016 182 181 #define B4000000 0010017 183 - #define CIBAUD 002003600000 /* input baud rate (not used) */ 182 + #define CIBAUD 002003600000 /* input baud rate */ 184 183 #define CMSPAR 010000000000 /* mark or space (stick) parity */ 185 - #define CRTSCTS 020000000000 /* flow control */ 184 + #define CRTSCTS 020000000000 /* flow control */ 185 + 186 + #define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ 186 187 187 188 /* c_lflag bits */ 188 189 #define ISIG 0000001 /* Enable signals. */
+4 -2
include/asm-mips/termios.h
··· 122 122 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ 123 123 }) 124 124 125 - #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) 126 - #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) 125 + #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) 126 + #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) 127 + #define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) 128 + #define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) 127 129 128 130 #endif /* defined(__KERNEL__) */ 129 131