mfd: stmpe: Rework registers access · tjh.dev/kernel@897ac66

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

mfd: stmpe: Rework registers access

this update allows to use registers map as following :
regs[reg_index + offset] instead of
regs[reg_index] + offset

This makes code clearer and will facilitate the addition of STMPE1600
on which LSB and MSB registers are respectively located at addr and addr + 1.
Despite for all others STMPE variant, LSB and MSB registers are respectively
located in reverse order at addr + 1 and addr.

For variant which have 3 registers's bank, we use LSB,CSB and MSB indexes
which contains respectively LSB (or LOW), CSB (or MID) and MSB (or HIGH)
register addresses (STMPE1801/STMPE24xx).
For variant which have 2 registers's bank, we use LSB and CSB indexes only.
In this case the CSB index contains the MSB regs address (STMPE 1601).

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

authored by

Patrice Chotard and committed by

Lee Jones 9 years ago 897ac667 c16bee78

+105 -10

3 changed files

expand all

drivers

mfd

stmpe.c

stmpe.h

include

linux

mfd

stmpe.h

+44 -4

drivers/mfd/stmpe.c

··· 483 483 [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF, 484 484 [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN, 485 485 [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA, 486 - [STMPE_IDX_GPEDR_MSB] = STMPE811_REG_GPIO_ED, 486 + [STMPE_IDX_GPEDR_LSB] = STMPE811_REG_GPIO_ED, 487 487 }; 488 488 489 489 static struct stmpe_variant_block stmpe811_blocks[] = { ··· 561 561 [STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL, 562 562 [STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2, 563 563 [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB, 564 + [STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB, 564 565 [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB, 565 566 [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB, 566 567 [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB, 568 + [STMPE_IDX_GPMR_CSB] = STMPE1601_REG_GPIO_MP_MSB, 567 569 [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB, 570 + [STMPE_IDX_GPSR_CSB] = STMPE1601_REG_GPIO_SET_MSB, 568 571 [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB, 572 + [STMPE_IDX_GPCR_CSB] = STMPE1601_REG_GPIO_CLR_MSB, 569 573 [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB, 574 + [STMPE_IDX_GPDR_CSB] = STMPE1601_REG_GPIO_SET_DIR_MSB, 575 + [STMPE_IDX_GPEDR_LSB] = STMPE1601_REG_GPIO_ED_LSB, 576 + [STMPE_IDX_GPEDR_CSB] = STMPE1601_REG_GPIO_ED_MSB, 570 577 [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB, 578 + [STMPE_IDX_GPRER_CSB] = STMPE1601_REG_GPIO_RE_MSB, 571 579 [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB, 580 + [STMPE_IDX_GPFER_CSB] = STMPE1601_REG_GPIO_FE_MSB, 572 581 [STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB, 573 582 [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB, 574 583 [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB, 584 + [STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB, 575 585 [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB, 576 - [STMPE_IDX_GPEDR_MSB] = STMPE1601_REG_GPIO_ED_MSB, 577 586 }; 578 587 579 588 static struct stmpe_variant_block stmpe1601_blocks[] = { ··· 728 719 [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW, 729 720 [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW, 730 721 [STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW, 722 + [STMPE_IDX_GPMR_CSB] = STMPE1801_REG_GPIO_MP_MID, 723 + [STMPE_IDX_GPMR_MSB] = STMPE1801_REG_GPIO_MP_HIGH, 731 724 [STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW, 725 + [STMPE_IDX_GPSR_CSB] = STMPE1801_REG_GPIO_SET_MID, 726 + [STMPE_IDX_GPSR_MSB] = STMPE1801_REG_GPIO_SET_HIGH, 732 727 [STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW, 728 + [STMPE_IDX_GPCR_CSB] = STMPE1801_REG_GPIO_CLR_MID, 729 + [STMPE_IDX_GPCR_MSB] = STMPE1801_REG_GPIO_CLR_HIGH, 733 730 [STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW, 731 + [STMPE_IDX_GPDR_CSB] = STMPE1801_REG_GPIO_SET_DIR_MID, 732 + [STMPE_IDX_GPDR_MSB] = STMPE1801_REG_GPIO_SET_DIR_HIGH, 734 733 [STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW, 734 + [STMPE_IDX_GPRER_CSB] = STMPE1801_REG_GPIO_RE_MID, 735 + [STMPE_IDX_GPRER_MSB] = STMPE1801_REG_GPIO_RE_HIGH, 735 736 [STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW, 737 + [STMPE_IDX_GPFER_CSB] = STMPE1801_REG_GPIO_FE_MID, 738 + [STMPE_IDX_GPFER_MSB] = STMPE1801_REG_GPIO_FE_HIGH, 736 739 [STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW, 737 740 [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW, 738 - [STMPE_IDX_ISGPIOR_LSB] = STMPE1801_REG_INT_STA_GPIO_LOW, 741 + [STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID, 742 + [STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH, 743 + [STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH, 739 744 }; 740 745 741 746 static struct stmpe_variant_block stmpe1801_blocks[] = { ··· 834 811 [STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL, 835 812 [STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2, 836 813 [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB, 814 + [STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB, 837 815 [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB, 838 816 [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB, 839 817 [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB, 818 + [STMPE_IDX_GPMR_CSB] = STMPE24XX_REG_GPMR_CSB, 819 + [STMPE_IDX_GPMR_MSB] = STMPE24XX_REG_GPMR_MSB, 840 820 [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB, 821 + [STMPE_IDX_GPSR_CSB] = STMPE24XX_REG_GPSR_CSB, 822 + [STMPE_IDX_GPSR_MSB] = STMPE24XX_REG_GPSR_MSB, 841 823 [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB, 824 + [STMPE_IDX_GPCR_CSB] = STMPE24XX_REG_GPCR_CSB, 825 + [STMPE_IDX_GPCR_MSB] = STMPE24XX_REG_GPCR_MSB, 842 826 [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB, 827 + [STMPE_IDX_GPDR_CSB] = STMPE24XX_REG_GPDR_CSB, 828 + [STMPE_IDX_GPDR_MSB] = STMPE24XX_REG_GPDR_MSB, 843 829 [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB, 830 + [STMPE_IDX_GPRER_CSB] = STMPE24XX_REG_GPRER_CSB, 831 + [STMPE_IDX_GPRER_MSB] = STMPE24XX_REG_GPRER_MSB, 844 832 [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB, 833 + [STMPE_IDX_GPFER_CSB] = STMPE24XX_REG_GPFER_CSB, 834 + [STMPE_IDX_GPFER_MSB] = STMPE24XX_REG_GPFER_MSB, 845 835 [STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB, 846 836 [STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB, 847 837 [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB, 848 838 [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB, 839 + [STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB, 840 + [STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB, 849 841 [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB, 842 + [STMPE_IDX_GPEDR_LSB] = STMPE24XX_REG_GPEDR_LSB, 843 + [STMPE_IDX_GPEDR_CSB] = STMPE24XX_REG_GPEDR_CSB, 850 844 [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB, 851 845 }; 852 846 ··· 1038 998 continue; 1039 999 1040 1000 stmpe->oldier[i] = new; 1041 - stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB] - i, new); 1001 + stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new); 1042 1002 } 1043 1003 1044 1004 mutex_unlock(&stmpe->irq_lock);

+43 -6

drivers/mfd/stmpe.h

··· 179 179 180 180 #define STMPE1601_REG_SYS_CTRL 0x02 181 181 #define STMPE1601_REG_SYS_CTRL2 0x03 182 + #define STMPE1601_REG_ICR_MSB 0x10 182 183 #define STMPE1601_REG_ICR_LSB 0x11 184 + #define STMPE1601_REG_IER_MSB 0x12 183 185 #define STMPE1601_REG_IER_LSB 0x13 184 186 #define STMPE1601_REG_ISR_MSB 0x14 185 - #define STMPE1601_REG_CHIP_ID 0x80 187 + #define STMPE1601_REG_ISR_LSB 0x15 188 + #define STMPE1601_REG_INT_EN_GPIO_MASK_MSB 0x16 186 189 #define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17 187 190 #define STMPE1601_REG_INT_STA_GPIO_MSB 0x18 188 - #define STMPE1601_REG_GPIO_MP_LSB 0x87 191 + #define STMPE1601_REG_INT_STA_GPIO_LSB 0x19 192 + #define STMPE1601_REG_CHIP_ID 0x80 193 + #define STMPE1601_REG_GPIO_SET_MSB 0x82 189 194 #define STMPE1601_REG_GPIO_SET_LSB 0x83 195 + #define STMPE1601_REG_GPIO_CLR_MSB 0x84 190 196 #define STMPE1601_REG_GPIO_CLR_LSB 0x85 197 + #define STMPE1601_REG_GPIO_MP_MSB 0x86 198 + #define STMPE1601_REG_GPIO_MP_LSB 0x87 199 + #define STMPE1601_REG_GPIO_SET_DIR_MSB 0x88 191 200 #define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89 192 201 #define STMPE1601_REG_GPIO_ED_MSB 0x8A 202 + #define STMPE1601_REG_GPIO_ED_LSB 0x8B 203 + #define STMPE1601_REG_GPIO_RE_MSB 0x8C 193 204 #define STMPE1601_REG_GPIO_RE_LSB 0x8D 205 + #define STMPE1601_REG_GPIO_FE_MSB 0x8E 194 206 #define STMPE1601_REG_GPIO_FE_LSB 0x8F 207 + #define STMPE1601_REG_GPIO_PU_MSB 0x90 195 208 #define STMPE1601_REG_GPIO_PU_LSB 0x91 196 209 #define STMPE1601_REG_GPIO_AF_U_MSB 0x92 197 210 ··· 280 267 281 268 #define STMPE24XX_REG_SYS_CTRL 0x02 282 269 #define STMPE24XX_REG_SYS_CTRL2 0x03 270 + #define STMPE24XX_REG_ICR_MSB 0x10 283 271 #define STMPE24XX_REG_ICR_LSB 0x11 272 + #define STMPE24XX_REG_IER_MSB 0x12 284 273 #define STMPE24XX_REG_IER_LSB 0x13 285 274 #define STMPE24XX_REG_ISR_MSB 0x14 286 - #define STMPE24XX_REG_CHIP_ID 0x80 275 + #define STMPE24XX_REG_ISR_LSB 0x15 276 + #define STMPE24XX_REG_IEGPIOR_MSB 0x16 277 + #define STMPE24XX_REG_IEGPIOR_CSB 0x17 287 278 #define STMPE24XX_REG_IEGPIOR_LSB 0x18 288 279 #define STMPE24XX_REG_ISGPIOR_MSB 0x19 289 - #define STMPE24XX_REG_GPMR_LSB 0xA4 280 + #define STMPE24XX_REG_ISGPIOR_CSB 0x1A 281 + #define STMPE24XX_REG_ISGPIOR_LSB 0x1B 282 + #define STMPE24XX_REG_CHIP_ID 0x80 283 + #define STMPE24XX_REG_GPSR_MSB 0x83 284 + #define STMPE24XX_REG_GPSR_CSB 0x84 290 285 #define STMPE24XX_REG_GPSR_LSB 0x85 286 + #define STMPE24XX_REG_GPCR_MSB 0x86 287 + #define STMPE24XX_REG_GPCR_CSB 0x87 291 288 #define STMPE24XX_REG_GPCR_LSB 0x88 289 + #define STMPE24XX_REG_GPDR_MSB 0x89 290 + #define STMPE24XX_REG_GPDR_CSB 0x8A 292 291 #define STMPE24XX_REG_GPDR_LSB 0x8B 293 292 #define STMPE24XX_REG_GPEDR_MSB 0x8C 293 + #define STMPE24XX_REG_GPEDR_CSB 0x8D 294 + #define STMPE24XX_REG_GPEDR_LSB 0x8E 295 + #define STMPE24XX_REG_GPRER_MSB 0x8F 296 + #define STMPE24XX_REG_GPRER_CSB 0x90 294 297 #define STMPE24XX_REG_GPRER_LSB 0x91 298 + #define STMPE24XX_REG_GPFER_MSB 0x92 299 + #define STMPE24XX_REG_GPFER_CSB 0x93 295 300 #define STMPE24XX_REG_GPFER_LSB 0x94 301 + #define STMPE24XX_REG_GPPUR_MSB 0x95 302 + #define STMPE24XX_REG_GPPUR_CSB 0x96 296 303 #define STMPE24XX_REG_GPPUR_LSB 0x97 297 - #define STMPE24XX_REG_GPPDR_LSB 0x9a 304 + #define STMPE24XX_REG_GPPDR_MSB 0x98 305 + #define STMPE24XX_REG_GPPDR_CSB 0x99 306 + #define STMPE24XX_REG_GPPDR_LSB 0x9A 298 307 #define STMPE24XX_REG_GPAFR_U_MSB 0x9B 299 - 308 + #define STMPE24XX_REG_GPMR_MSB 0xA2 309 + #define STMPE24XX_REG_GPMR_CSB 0xA3 310 + #define STMPE24XX_REG_GPMR_LSB 0xA4 300 311 #define STMPE24XX_SYS_CTRL_ENABLE_GPIO (1 << 3) 301 312 #define STMPE24XX_SYSCON_ENABLE_PWM (1 << 2) 302 313 #define STMPE24XX_SYS_CTRL_ENABLE_KPC (1 << 1)

+18

include/linux/mfd/stmpe.h

··· 43 43 STMPE_IDX_SYS_CTRL2, 44 44 STMPE_IDX_ICR_LSB, 45 45 STMPE_IDX_IER_LSB, 46 + STMPE_IDX_IER_MSB, 46 47 STMPE_IDX_ISR_LSB, 47 48 STMPE_IDX_ISR_MSB, 48 49 STMPE_IDX_GPMR_LSB, 50 + STMPE_IDX_GPMR_CSB, 51 + STMPE_IDX_GPMR_MSB, 49 52 STMPE_IDX_GPSR_LSB, 53 + STMPE_IDX_GPSR_CSB, 54 + STMPE_IDX_GPSR_MSB, 50 55 STMPE_IDX_GPCR_LSB, 56 + STMPE_IDX_GPCR_CSB, 57 + STMPE_IDX_GPCR_MSB, 51 58 STMPE_IDX_GPDR_LSB, 59 + STMPE_IDX_GPDR_CSB, 60 + STMPE_IDX_GPDR_MSB, 61 + STMPE_IDX_GPEDR_LSB, 62 + STMPE_IDX_GPEDR_CSB, 52 63 STMPE_IDX_GPEDR_MSB, 53 64 STMPE_IDX_GPRER_LSB, 65 + STMPE_IDX_GPRER_CSB, 66 + STMPE_IDX_GPRER_MSB, 54 67 STMPE_IDX_GPFER_LSB, 68 + STMPE_IDX_GPFER_CSB, 69 + STMPE_IDX_GPFER_MSB, 55 70 STMPE_IDX_GPPUR_LSB, 56 71 STMPE_IDX_GPPDR_LSB, 57 72 STMPE_IDX_GPAFR_U_MSB, 58 73 STMPE_IDX_IEGPIOR_LSB, 74 + STMPE_IDX_IEGPIOR_CSB, 75 + STMPE_IDX_IEGPIOR_MSB, 59 76 STMPE_IDX_ISGPIOR_LSB, 77 + STMPE_IDX_ISGPIOR_CSB, 60 78 STMPE_IDX_ISGPIOR_MSB, 61 79 STMPE_IDX_MAX, 62 80 };