tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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[media] coda: Add encoder/decoder support for CODA960

This patch adds support for the CODA960 VPU in Freescale i.MX6 SoCs.

It enables h.264 and MPEG4 encoding and decoding support. Besides the usual
register shifting, the CODA960 gains frame memory control and GDI registers
that are set up for linear mapping right now, needs ENC_PIC_SRC_INDEX to be
set beyond the number of internal buffers for some reason, and has subsampling
buffers that need to be set up. Also, the work buffer size is increased to
80 KiB.

The CODA960 firmware spins if there is not enough input data in the bitstream
buffer. To make it continue, buffers need to be copied into the bitstream as
soon as they are queued. As the bitstream fifo is written into from two places,
it must be protected with a mutex. For that, using a threaded interrupt handler
is necessary.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>

authored by

Philipp Zabel and committed by
Mauro Carvalho Chehab 89548441 06ce32cb

+466 -47
+354 -44
drivers/media/platform/coda.c
··· 44 44 #define CODA_FMO_BUF_SIZE 32 45 45 #define CODADX6_WORK_BUF_SIZE (288 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024) 46 46 #define CODA7_WORK_BUF_SIZE (128 * 1024) 47 + #define CODA9_WORK_BUF_SIZE (80 * 1024) 47 48 #define CODA7_TEMP_BUF_SIZE (304 * 1024) 49 + #define CODA9_TEMP_BUF_SIZE (204 * 1024) 48 50 #define CODA_PARA_BUF_SIZE (10 * 1024) 49 51 #define CODA_ISRAM_SIZE (2048 * 2) 50 52 #define CODADX6_IRAM_SIZE 0xb000 51 53 #define CODA7_IRAM_SIZE 0x14000 54 + #define CODA9_IRAM_SIZE 0x21000 52 55 53 56 #define CODA7_PS_BUF_SIZE 0x28000 57 + #define CODA9_PS_SAVE_SIZE (512 * 1024) 54 58 55 59 #define CODA_MAX_FRAMEBUFFERS 8 56 60 57 61 #define CODA_MAX_FRAME_SIZE 0x100000 58 62 #define FMO_SLICE_SAVE_BUF_SIZE (32) 59 63 #define CODA_DEFAULT_GAMMA 4096 64 + #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */ 60 65 61 66 #define MIN_W 176 62 67 #define MIN_H 144 ··· 89 84 enum coda_product { 90 85 CODA_DX6 = 0xf001, 91 86 CODA_7541 = 0xf012, 87 + CODA_960 = 0xf020, 92 88 }; 93 89 94 90 struct coda_fmt { ··· 183 177 phys_addr_t next_paddr; 184 178 }; 185 179 180 + struct gdi_tiled_map { 181 + int xy2ca_map[16]; 182 + int xy2ba_map[16]; 183 + int xy2ra_map[16]; 184 + int rbc2axi_map[32]; 185 + int xy2rbc_config; 186 + int map_type; 187 + #define GDI_LINEAR_FRAME_MAP 0 188 + }; 189 + 186 190 struct coda_ctx { 187 191 struct coda_dev *dev; 188 192 struct mutex buffer_mutex; ··· 231 215 int idx; 232 216 int reg_idx; 233 217 struct coda_iram_info iram_info; 218 + struct gdi_tiled_map tiled_map; 234 219 u32 bit_stream_param; 235 220 u32 frm_dis_flg; 221 + u32 frame_mem_ctrl; 236 222 int display_idx; 237 223 }; 238 224 ··· 283 265 { 284 266 struct coda_dev *dev = ctx->dev; 285 267 286 - if (dev->devtype->product == CODA_7541) { 268 + if (dev->devtype->product == CODA_960 || 269 + dev->devtype->product == CODA_7541) { 287 270 /* Restore context related registers to CODA */ 288 271 coda_write(dev, ctx->bit_stream_param, 289 272 CODA_REG_BIT_BIT_STREAM_PARAM); 290 273 coda_write(dev, ctx->frm_dis_flg, 291 274 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx)); 275 + coda_write(dev, ctx->frame_mem_ctrl, 276 + CODA_REG_BIT_FRAME_MEM_CTRL); 292 277 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR); 278 + } 279 + 280 + if (dev->devtype->product == CODA_960) { 281 + coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR); 282 + coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN); 293 283 } 294 284 295 285 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY); ··· 373 347 CODA_CODEC(CODA7_MODE_ENCODE_MP4, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_MPEG4, 1280, 720), 374 348 CODA_CODEC(CODA7_MODE_DECODE_H264, V4L2_PIX_FMT_H264, V4L2_PIX_FMT_YUV420, 1920, 1080), 375 349 CODA_CODEC(CODA7_MODE_DECODE_MP4, V4L2_PIX_FMT_MPEG4, V4L2_PIX_FMT_YUV420, 1920, 1080), 350 + }; 351 + 352 + static struct coda_codec coda9_codecs[] = { 353 + CODA_CODEC(CODA9_MODE_ENCODE_H264, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_H264, 1920, 1080), 354 + CODA_CODEC(CODA9_MODE_ENCODE_MP4, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_MPEG4, 1920, 1080), 355 + CODA_CODEC(CODA9_MODE_DECODE_H264, V4L2_PIX_FMT_H264, V4L2_PIX_FMT_YUV420, 1920, 1080), 356 + CODA_CODEC(CODA9_MODE_DECODE_MP4, V4L2_PIX_FMT_MPEG4, V4L2_PIX_FMT_YUV420, 1920, 1080), 376 357 }; 377 358 378 359 static bool coda_format_is_yuv(u32 fourcc) ··· 460 427 return "CodaDx6"; 461 428 case CODA_7541: 462 429 return "CODA7541"; 430 + case CODA_960: 431 + return "CODA960"; 463 432 default: 464 433 snprintf(buf, sizeof(buf), "(0x%04x)", product); 465 434 return buf; ··· 890 855 struct v4l2_decoder_cmd *dc) 891 856 { 892 857 struct coda_ctx *ctx = fh_to_ctx(fh); 858 + struct coda_dev *dev = ctx->dev; 893 859 int ret; 894 860 895 861 ret = coda_try_decoder_cmd(file, fh, dc); ··· 903 867 904 868 /* Set the strem-end flag on this context */ 905 869 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG; 870 + 871 + if ((dev->devtype->product == CODA_960) && 872 + coda_isbusy(dev) && 873 + (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) { 874 + /* If this context is currently running, update the hardware flag */ 875 + coda_write(dev, ctx->bit_stream_param, CODA_REG_BIT_BIT_STREAM_PARAM); 876 + } 906 877 907 878 return 0; 908 879 } ··· 1066 1023 } 1067 1024 } 1068 1025 1026 + static void coda_set_gdi_regs(struct coda_ctx *ctx) 1027 + { 1028 + struct gdi_tiled_map *tiled_map = &ctx->tiled_map; 1029 + struct coda_dev *dev = ctx->dev; 1030 + int i; 1031 + 1032 + for (i = 0; i < 16; i++) 1033 + coda_write(dev, tiled_map->xy2ca_map[i], 1034 + CODA9_GDI_XY2_CAS_0 + 4 * i); 1035 + for (i = 0; i < 4; i++) 1036 + coda_write(dev, tiled_map->xy2ba_map[i], 1037 + CODA9_GDI_XY2_BA_0 + 4 * i); 1038 + for (i = 0; i < 16; i++) 1039 + coda_write(dev, tiled_map->xy2ra_map[i], 1040 + CODA9_GDI_XY2_RAS_0 + 4 * i); 1041 + coda_write(dev, tiled_map->xy2rbc_config, CODA9_GDI_XY2_RBC_CONFIG); 1042 + for (i = 0; i < 32; i++) 1043 + coda_write(dev, tiled_map->rbc2axi_map[i], 1044 + CODA9_GDI_RBC2_AXI_0 + 4 * i); 1045 + } 1046 + 1069 1047 /* 1070 1048 * Mem-to-mem operations. 1071 1049 */ ··· 1135 1071 } 1136 1072 } 1137 1073 1074 + if (dev->devtype->product == CODA_960) 1075 + coda_set_gdi_regs(ctx); 1076 + 1138 1077 /* Set rotator output */ 1139 1078 picture_y = vb2_dma_contig_plane_dma_addr(dst_buf, 0); 1140 1079 if (q_data_dst->fourcc == V4L2_PIX_FMT_YVU420) { ··· 1148 1081 picture_cb = picture_y + stridey * height; 1149 1082 picture_cr = picture_cb + stridey / 2 * height / 2; 1150 1083 } 1151 - coda_write(dev, picture_y, CODA_CMD_DEC_PIC_ROT_ADDR_Y); 1152 - coda_write(dev, picture_cb, CODA_CMD_DEC_PIC_ROT_ADDR_CB); 1153 - coda_write(dev, picture_cr, CODA_CMD_DEC_PIC_ROT_ADDR_CR); 1154 - coda_write(dev, stridey, CODA_CMD_DEC_PIC_ROT_STRIDE); 1084 + 1085 + if (dev->devtype->product == CODA_960) { 1086 + /* 1087 + * The CODA960 seems to have an internal list of buffers with 1088 + * 64 entries that includes the registered frame buffers as 1089 + * well as the rotator buffer output. 1090 + * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames. 1091 + */ 1092 + coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->v4l2_buf.index, 1093 + CODA9_CMD_DEC_PIC_ROT_INDEX); 1094 + coda_write(dev, picture_y, CODA9_CMD_DEC_PIC_ROT_ADDR_Y); 1095 + coda_write(dev, picture_cb, CODA9_CMD_DEC_PIC_ROT_ADDR_CB); 1096 + coda_write(dev, picture_cr, CODA9_CMD_DEC_PIC_ROT_ADDR_CR); 1097 + coda_write(dev, stridey, CODA9_CMD_DEC_PIC_ROT_STRIDE); 1098 + } else { 1099 + coda_write(dev, picture_y, CODA_CMD_DEC_PIC_ROT_ADDR_Y); 1100 + coda_write(dev, picture_cb, CODA_CMD_DEC_PIC_ROT_ADDR_CB); 1101 + coda_write(dev, picture_cr, CODA_CMD_DEC_PIC_ROT_ADDR_CR); 1102 + coda_write(dev, stridey, CODA_CMD_DEC_PIC_ROT_STRIDE); 1103 + } 1155 1104 coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode, 1156 1105 CODA_CMD_DEC_PIC_ROT_MODE); 1157 1106 ··· 1176 1093 /* TBD */ 1177 1094 case CODA_7541: 1178 1095 coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION); 1096 + break; 1097 + case CODA_960: 1098 + coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION); /* 'hardcode to use interrupt disable mode'? */ 1179 1099 break; 1180 1100 } 1181 1101 ··· 1223 1137 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME; 1224 1138 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME; 1225 1139 } 1140 + 1141 + if (dev->devtype->product == CODA_960) 1142 + coda_set_gdi_regs(ctx); 1226 1143 1227 1144 /* 1228 1145 * Copy headers at the beginning of the first frame for H.264 only. ··· 1305 1216 break; 1306 1217 } 1307 1218 1308 - coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y); 1309 - coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB); 1310 - coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR); 1219 + if (dev->devtype->product == CODA_960) { 1220 + coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX); 1221 + coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE); 1222 + coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC); 1223 + 1224 + coda_write(dev, picture_y, CODA9_CMD_ENC_PIC_SRC_ADDR_Y); 1225 + coda_write(dev, picture_cb, CODA9_CMD_ENC_PIC_SRC_ADDR_CB); 1226 + coda_write(dev, picture_cr, CODA9_CMD_ENC_PIC_SRC_ADDR_CR); 1227 + } else { 1228 + coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y); 1229 + coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB); 1230 + coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR); 1231 + } 1311 1232 coda_write(dev, force_ipicture << 1 & 0x2, 1312 1233 CODA_CMD_ENC_PIC_OPTION); 1313 1234 1314 1235 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START); 1315 1236 coda_write(dev, pic_stream_buffer_size / 1024, 1316 1237 CODA_CMD_ENC_PIC_BB_SIZE); 1238 + 1239 + if (!ctx->streamon_out) { 1240 + /* After streamoff on the output side, set the stream end flag */ 1241 + ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG; 1242 + coda_write(dev, ctx->bit_stream_param, CODA_REG_BIT_BIT_STREAM_PARAM); 1243 + } 1317 1244 } 1318 1245 1319 1246 static void coda_device_run(void *m2m_priv) ··· 1455 1350 .unlock = coda_unlock, 1456 1351 }; 1457 1352 1353 + static void coda_set_tiled_map_type(struct coda_ctx *ctx, int tiled_map_type) 1354 + { 1355 + struct gdi_tiled_map *tiled_map = &ctx->tiled_map; 1356 + int luma_map, chro_map, i; 1357 + 1358 + memset(tiled_map, 0, sizeof(*tiled_map)); 1359 + 1360 + luma_map = 64; 1361 + chro_map = 64; 1362 + tiled_map->map_type = tiled_map_type; 1363 + for (i = 0; i < 16; i++) 1364 + tiled_map->xy2ca_map[i] = luma_map << 8 | chro_map; 1365 + for (i = 0; i < 4; i++) 1366 + tiled_map->xy2ba_map[i] = luma_map << 8 | chro_map; 1367 + for (i = 0; i < 16; i++) 1368 + tiled_map->xy2ra_map[i] = luma_map << 8 | chro_map; 1369 + 1370 + if (tiled_map_type == GDI_LINEAR_FRAME_MAP) { 1371 + tiled_map->xy2rbc_config = 0; 1372 + } else { 1373 + dev_err(&ctx->dev->plat_dev->dev, "invalid map type: %d\n", 1374 + tiled_map_type); 1375 + return; 1376 + } 1377 + } 1378 + 1458 1379 static void set_default_params(struct coda_ctx *ctx) 1459 1380 { 1460 1381 int max_w; ··· 1504 1373 ctx->q_data[V4L2_M2M_DST].width = max_w; 1505 1374 ctx->q_data[V4L2_M2M_DST].height = max_h; 1506 1375 ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE; 1376 + 1377 + if (ctx->dev->devtype->product == CODA_960) 1378 + coda_set_tiled_map_type(ctx, GDI_LINEAR_FRAME_MAP); 1507 1379 } 1508 1380 1509 1381 /* ··· 1556 1422 static void coda_buf_queue(struct vb2_buffer *vb) 1557 1423 { 1558 1424 struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 1425 + struct coda_dev *dev = ctx->dev; 1559 1426 struct coda_q_data *q_data; 1560 1427 1561 1428 q_data = get_q_data(ctx, vb->vb2_queue->type); ··· 1571 1436 * For backwards compatibility, queuing an empty buffer marks 1572 1437 * the stream end 1573 1438 */ 1574 - if (vb2_get_plane_payload(vb, 0) == 0) 1439 + if (vb2_get_plane_payload(vb, 0) == 0) { 1575 1440 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG; 1441 + if ((dev->devtype->product == CODA_960) && 1442 + coda_isbusy(dev) && 1443 + (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) { 1444 + /* if this decoder instance is running, set the stream end flag */ 1445 + coda_write(dev, ctx->bit_stream_param, CODA_REG_BIT_BIT_STREAM_PARAM); 1446 + } 1447 + } 1576 1448 mutex_lock(&ctx->bitstream_mutex); 1577 1449 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb); 1578 1450 coda_fill_bitstream(ctx); ··· 1754 1612 bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE; 1755 1613 ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE; 1756 1614 break; 1615 + case CODA_960: 1616 + dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE; 1617 + bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE; 1618 + ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE; 1619 + break; 1757 1620 default: /* CODA_DX6 */ 1758 1621 return; 1759 1622 } ··· 1868 1721 case CODA_7541: 1869 1722 size = CODA7_WORK_BUF_SIZE; 1870 1723 break; 1724 + case CODA_960: 1725 + size = CODA9_WORK_BUF_SIZE; 1726 + if (q_data->fourcc == V4L2_PIX_FMT_H264) 1727 + size += CODA9_PS_SAVE_SIZE; 1728 + break; 1871 1729 default: 1872 1730 return 0; 1873 1731 } ··· 1957 1805 coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START); 1958 1806 coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE); 1959 1807 val = 0; 1960 - if (dev->devtype->product == CODA_7541) 1808 + if ((dev->devtype->product == CODA_7541) || 1809 + (dev->devtype->product == CODA_960)) 1961 1810 val |= CODA_REORDER_ENABLE; 1962 1811 coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION); 1963 1812 1964 1813 ctx->params.codec_mode = ctx->codec->mode; 1965 - ctx->params.codec_mode_aux = 0; 1814 + if (dev->devtype->product == CODA_960 && 1815 + src_fourcc == V4L2_PIX_FMT_MPEG4) 1816 + ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4; 1817 + else 1818 + ctx->params.codec_mode_aux = 0; 1966 1819 if (src_fourcc == V4L2_PIX_FMT_H264) { 1967 1820 if (dev->devtype->product == CODA_7541) { 1968 1821 coda_write(dev, ctx->psbuf.paddr, ··· 1975 1818 coda_write(dev, (CODA7_PS_BUF_SIZE / 1024), 1976 1819 CODA_CMD_DEC_SEQ_PS_BB_SIZE); 1977 1820 } 1821 + if (dev->devtype->product == CODA_960) { 1822 + coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN); 1823 + coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE); 1824 + } 1825 + } 1826 + if (dev->devtype->product != CODA_960) { 1827 + coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE); 1978 1828 } 1979 1829 1980 1830 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) { ··· 2053 1889 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR); 2054 1890 coda_write(dev, ctx->iram_info.buf_ovl_use, 2055 1891 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR); 1892 + if (dev->devtype->product == CODA_960) 1893 + coda_write(dev, ctx->iram_info.buf_btp_use, 1894 + CODA9_CMD_SET_FRAME_AXI_BTP_ADDR); 1895 + } 1896 + 1897 + if (dev->devtype->product == CODA_960) { 1898 + coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY); 1899 + 1900 + coda_write(dev, 0x20262024, CODA9_CMD_SET_FRAME_CACHE_SIZE); 1901 + coda_write(dev, 2 << CODA9_CACHE_PAGEMERGE_OFFSET | 1902 + 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET | 1903 + 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET | 1904 + 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET, 1905 + CODA9_CMD_SET_FRAME_CACHE_CONFIG); 2056 1906 } 2057 1907 2058 1908 if (src_fourcc == V4L2_PIX_FMT_H264) { ··· 2080 1902 int max_mb_x = 1920 / 16; 2081 1903 int max_mb_y = 1088 / 16; 2082 1904 int max_mb_num = max_mb_x * max_mb_y; 1905 + 2083 1906 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y, 2084 1907 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE); 1908 + } else if (dev->devtype->product == CODA_960) { 1909 + int max_mb_x = 1920 / 16; 1910 + int max_mb_y = 1088 / 16; 1911 + int max_mb_num = max_mb_x * max_mb_y; 1912 + 1913 + coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y, 1914 + CODA9_CMD_SET_FRAME_MAX_DEC_SIZE); 2085 1915 } 2086 1916 2087 1917 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) { ··· 2105 1919 int header_code, u8 *header, int *size) 2106 1920 { 2107 1921 struct coda_dev *dev = ctx->dev; 1922 + size_t bufsize; 2108 1923 int ret; 1924 + int i; 1925 + 1926 + if (dev->devtype->product == CODA_960) 1927 + memset(vb2_plane_vaddr(buf, 0), 0, 64); 2109 1928 2110 1929 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), 2111 1930 CODA_CMD_ENC_HEADER_BB_START); 2112 - coda_write(dev, vb2_plane_size(buf, 0), CODA_CMD_ENC_HEADER_BB_SIZE); 1931 + bufsize = vb2_plane_size(buf, 0); 1932 + if (dev->devtype->product == CODA_960) 1933 + bufsize /= 1024; 1934 + coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE); 2113 1935 coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE); 2114 1936 ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER); 2115 1937 if (ret < 0) { 2116 1938 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n"); 2117 1939 return ret; 2118 1940 } 2119 - *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) - 2120 - coda_read(dev, CODA_CMD_ENC_HEADER_BB_START); 1941 + 1942 + if (dev->devtype->product == CODA_960) { 1943 + for (i = 63; i > 0; i--) 1944 + if (((char *)vb2_plane_vaddr(buf, 0))[i] != 0) 1945 + break; 1946 + *size = i + 1; 1947 + } else { 1948 + *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) - 1949 + coda_read(dev, CODA_CMD_ENC_HEADER_BB_START); 1950 + } 2121 1951 memcpy(header, vb2_plane_vaddr(buf, 0), *size); 2122 1952 2123 1953 return 0; 2124 1954 } 2125 1955 1956 + static int coda_start_encoding(struct coda_ctx *ctx); 1957 + 2126 1958 static int coda_start_streaming(struct vb2_queue *q, unsigned int count) 2127 1959 { 2128 1960 struct coda_ctx *ctx = vb2_get_drv_priv(q); 2129 1961 struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev; 2130 - u32 bitstream_buf, bitstream_size; 2131 1962 struct coda_dev *dev = ctx->dev; 2132 1963 struct coda_q_data *q_data_src, *q_data_dst; 2133 - struct vb2_buffer *buf; 2134 1964 u32 dst_fourcc; 2135 - u32 value; 2136 1965 int ret = 0; 2137 1966 2138 1967 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); ··· 2182 1981 v4l2_m2m_set_src_buffered(ctx->m2m_ctx, true); 2183 1982 2184 1983 ctx->gopcounter = ctx->params.gop_size - 1; 2185 - buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx); 2186 - bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0); 2187 1984 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); 2188 - bitstream_size = q_data_dst->sizeimage; 2189 1985 dst_fourcc = q_data_dst->fourcc; 2190 1986 2191 1987 ctx->codec = coda_find_codec(ctx->dev, q_data_src->fourcc, ··· 2201 2003 mutex_lock(&dev->coda_mutex); 2202 2004 ret = coda_start_decoding(ctx); 2203 2005 mutex_unlock(&dev->coda_mutex); 2204 - if (ret == -EAGAIN) { 2006 + if (ret == -EAGAIN) 2205 2007 return 0; 2206 - } else if (ret < 0) { 2008 + else if (ret < 0) 2207 2009 return ret; 2208 - } else { 2209 - ctx->initialized = 1; 2210 - return 0; 2211 - } 2010 + } else { 2011 + ret = coda_start_encoding(ctx); 2212 2012 } 2013 + 2014 + ctx->initialized = 1; 2015 + return ret; 2016 + } 2017 + 2018 + static int coda_start_encoding(struct coda_ctx *ctx) 2019 + { 2020 + struct coda_dev *dev = ctx->dev; 2021 + struct v4l2_device *v4l2_dev = &dev->v4l2_dev; 2022 + struct coda_q_data *q_data_src, *q_data_dst; 2023 + u32 bitstream_buf, bitstream_size; 2024 + struct vb2_buffer *buf; 2025 + int gamma, ret, value; 2026 + u32 dst_fourcc; 2027 + 2028 + q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); 2029 + q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); 2030 + dst_fourcc = q_data_dst->fourcc; 2031 + 2032 + buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx); 2033 + bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0); 2034 + bitstream_size = q_data_dst->sizeimage; 2213 2035 2214 2036 if (!coda_is_initialized(dev)) { 2215 2037 v4l2_err(v4l2_dev, "coda is not initialized.\n"); ··· 2246 2028 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN | 2247 2029 CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL); 2248 2030 break; 2249 - default: 2031 + case CODA_960: 2032 + coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN); 2033 + /* fallthrough */ 2034 + case CODA_7541: 2250 2035 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN | 2251 2036 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL); 2037 + break; 2252 2038 } 2039 + 2040 + value = coda_read(dev, CODA_REG_BIT_FRAME_MEM_CTRL); 2041 + value &= ~(1 << 2 | 0x7 << 9); 2042 + ctx->frame_mem_ctrl = value; 2043 + coda_write(dev, value, CODA_REG_BIT_FRAME_MEM_CTRL); 2253 2044 2254 2045 if (dev->devtype->product == CODA_DX6) { 2255 2046 /* Configure the coda */ ··· 2282 2055 ctx->params.codec_mode = ctx->codec->mode; 2283 2056 switch (dst_fourcc) { 2284 2057 case V4L2_PIX_FMT_MPEG4: 2285 - coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD); 2058 + if (dev->devtype->product == CODA_960) 2059 + coda_write(dev, CODA9_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD); 2060 + else 2061 + coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD); 2286 2062 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA); 2287 2063 break; 2288 2064 case V4L2_PIX_FMT_H264: 2289 - coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD); 2065 + if (dev->devtype->product == CODA_960) 2066 + coda_write(dev, CODA9_STD_H264, CODA_CMD_ENC_SEQ_COD_STD); 2067 + else 2068 + coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD); 2290 2069 coda_write(dev, 0, CODA_CMD_ENC_SEQ_264_PARA); 2291 2070 break; 2292 2071 default: ··· 2325 2092 /* Rate control enabled */ 2326 2093 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET; 2327 2094 value |= 1 & CODA_RATECONTROL_ENABLE_MASK; 2095 + if (dev->devtype->product == CODA_960) 2096 + value |= BIT(31); /* disable autoskip */ 2328 2097 } else { 2329 2098 value = 0; 2330 2099 } ··· 2338 2103 coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START); 2339 2104 coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE); 2340 2105 2341 - /* set default gamma */ 2342 - value = (CODA_DEFAULT_GAMMA & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET; 2343 - coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_GAMMA); 2344 2106 2345 - if (CODA_DEFAULT_GAMMA > 0) { 2346 - if (dev->devtype->product == CODA_DX6) 2347 - value = 1 << CODADX6_OPTION_GAMMA_OFFSET; 2348 - else 2349 - value = 1 << CODA7_OPTION_GAMMA_OFFSET; 2107 + value = 0; 2108 + if (dev->devtype->product == CODA_960) 2109 + gamma = CODA9_DEFAULT_GAMMA; 2110 + else 2111 + gamma = CODA_DEFAULT_GAMMA; 2112 + if (gamma > 0) { 2113 + coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET, 2114 + CODA_CMD_ENC_SEQ_RC_GAMMA); 2115 + } 2116 + if (dev->devtype->product == CODA_960) { 2117 + if (CODA_DEFAULT_GAMMA > 0) 2118 + value |= 1 << CODA9_OPTION_GAMMA_OFFSET; 2350 2119 } else { 2351 - value = 0; 2120 + if (CODA_DEFAULT_GAMMA > 0) { 2121 + if (dev->devtype->product == CODA_DX6) 2122 + value |= 1 << CODADX6_OPTION_GAMMA_OFFSET; 2123 + else 2124 + value |= 1 << CODA7_OPTION_GAMMA_OFFSET; 2125 + } 2352 2126 } 2353 2127 coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION); 2128 + 2129 + coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE); 2354 2130 2355 2131 coda_setup_iram(ctx); 2356 2132 2357 2133 if (dst_fourcc == V4L2_PIX_FMT_H264) { 2358 - if (dev->devtype->product == CODA_DX6) { 2134 + switch (dev->devtype->product) { 2135 + case CODA_DX6: 2359 2136 value = FMO_SLICE_SAVE_BUF_SIZE << 7; 2360 2137 coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO); 2361 - } else { 2138 + break; 2139 + case CODA_7541: 2362 2140 coda_write(dev, ctx->iram_info.search_ram_paddr, 2363 2141 CODA7_CMD_ENC_SEQ_SEARCH_BASE); 2364 2142 coda_write(dev, ctx->iram_info.search_ram_size, 2365 2143 CODA7_CMD_ENC_SEQ_SEARCH_SIZE); 2144 + break; 2145 + case CODA_960: 2146 + coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION); 2147 + coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT); 2366 2148 } 2367 2149 } 2368 2150 ··· 2395 2143 goto out; 2396 2144 } 2397 2145 2398 - ctx->num_internal_frames = 2; 2146 + if (dev->devtype->product == CODA_960) 2147 + ctx->num_internal_frames = 4; 2148 + else 2149 + ctx->num_internal_frames = 2; 2399 2150 ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc); 2400 2151 if (ret < 0) { 2401 2152 v4l2_err(v4l2_dev, "failed to allocate framebuffers\n"); ··· 2421 2166 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR); 2422 2167 coda_write(dev, ctx->iram_info.buf_ovl_use, 2423 2168 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR); 2169 + if (dev->devtype->product == CODA_960) { 2170 + coda_write(dev, ctx->iram_info.buf_btp_use, 2171 + CODA9_CMD_SET_FRAME_AXI_BTP_ADDR); 2172 + 2173 + /* FIXME */ 2174 + coda_write(dev, ctx->internal_frames[2].paddr, CODA9_CMD_SET_FRAME_SUBSAMP_A); 2175 + coda_write(dev, ctx->internal_frames[3].paddr, CODA9_CMD_SET_FRAME_SUBSAMP_B); 2176 + } 2424 2177 } 2178 + 2425 2179 ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF); 2426 2180 if (ret < 0) { 2427 2181 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n"); ··· 2514 2250 "%s: output\n", __func__); 2515 2251 ctx->streamon_out = 0; 2516 2252 2253 + if (ctx->inst_type == CODA_INST_DECODER && 2254 + coda_isbusy(dev) && ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX)) { 2255 + /* if this decoder instance is running, set the stream end flag */ 2256 + if (dev->devtype->product == CODA_960) { 2257 + u32 val = coda_read(dev, CODA_REG_BIT_BIT_STREAM_PARAM); 2258 + 2259 + val |= CODA_BIT_STREAM_END_FLAG; 2260 + coda_write(dev, val, CODA_REG_BIT_BIT_STREAM_PARAM); 2261 + ctx->bit_stream_param = val; 2262 + } 2263 + } 2517 2264 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG; 2518 2265 2519 2266 ctx->isequence = 0; ··· 2726 2451 ctx->idx = idx; 2727 2452 switch (dev->devtype->product) { 2728 2453 case CODA_7541: 2454 + case CODA_960: 2729 2455 ctx->reg_idx = 0; 2730 2456 break; 2731 2457 default: ··· 3047 2771 u32 wr_ptr, start_ptr; 3048 2772 3049 2773 src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx); 3050 - dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx); 2774 + dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx); 3051 2775 3052 2776 /* Get results from the coda */ 3053 2777 start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START); ··· 3084 2808 dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode; 3085 2809 3086 2810 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); 2811 + 2812 + dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx); 3087 2813 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); 3088 2814 3089 2815 ctx->gopcounter--; ··· 3184 2906 static u32 coda_supported_firmwares[] = { 3185 2907 CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5), 3186 2908 CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50), 2909 + CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5), 3187 2910 }; 3188 2911 3189 2912 static bool coda_firmware_supported(u32 vernum) ··· 3239 2960 coda_write(dev, 0, CODA_REG_BIT_CODE_BUF_ADDR + i * 4); 3240 2961 3241 2962 /* Tell the BIT where to find everything it needs */ 3242 - if (dev->devtype->product == CODA_7541) { 2963 + if (dev->devtype->product == CODA_960 || 2964 + dev->devtype->product == CODA_7541) { 3243 2965 coda_write(dev, dev->tempbuf.paddr, 3244 2966 CODA_REG_BIT_TEMP_BUF_ADDR); 3245 2967 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM); ··· 3260 2980 default: 3261 2981 coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL); 3262 2982 } 3263 - coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL); 2983 + if (dev->devtype->product == CODA_960) 2984 + coda_write(dev, 1 << 12, CODA_REG_BIT_FRAME_MEM_CTRL); 2985 + else 2986 + coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL); 3264 2987 3265 2988 if (dev->devtype->product != CODA_DX6) 3266 2989 coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE); ··· 3291 3008 clk_disable_unprepare(dev->clk_ahb); 3292 3009 v4l2_err(&dev->v4l2_dev, "firmware get command error\n"); 3293 3010 return -EIO; 3011 + } 3012 + 3013 + if (dev->devtype->product == CODA_960) { 3014 + data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV); 3015 + v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n", 3016 + data); 3294 3017 } 3295 3018 3296 3019 /* Check we are compatible with the loaded firmware */ ··· 3414 3125 enum coda_platform { 3415 3126 CODA_IMX27, 3416 3127 CODA_IMX53, 3128 + CODA_IMX6Q, 3129 + CODA_IMX6DL, 3417 3130 }; 3418 3131 3419 3132 static const struct coda_devtype coda_devdata[] = { ··· 3431 3140 .codecs = coda7_codecs, 3432 3141 .num_codecs = ARRAY_SIZE(coda7_codecs), 3433 3142 }, 3143 + [CODA_IMX6Q] = { 3144 + .firmware = "v4l-coda960-imx6q.bin", 3145 + .product = CODA_960, 3146 + .codecs = coda9_codecs, 3147 + .num_codecs = ARRAY_SIZE(coda9_codecs), 3148 + }, 3149 + [CODA_IMX6DL] = { 3150 + .firmware = "v4l-coda960-imx6dl.bin", 3151 + .product = CODA_960, 3152 + .codecs = coda9_codecs, 3153 + .num_codecs = ARRAY_SIZE(coda9_codecs), 3154 + }, 3434 3155 }; 3435 3156 3436 3157 static struct platform_device_id coda_platform_ids[] = { ··· 3456 3153 static const struct of_device_id coda_dt_ids[] = { 3457 3154 { .compatible = "fsl,imx27-vpu", .data = &coda_devdata[CODA_IMX27] }, 3458 3155 { .compatible = "fsl,imx53-vpu", .data = &coda_devdata[CODA_IMX53] }, 3156 + { .compatible = "fsl,imx6q-vpu", .data = &coda_devdata[CODA_IMX6Q] }, 3157 + { .compatible = "fsl,imx6dl-vpu", .data = &coda_devdata[CODA_IMX6DL] }, 3459 3158 { /* sentinel */ } 3460 3159 }; 3461 3160 MODULE_DEVICE_TABLE(of, coda_dt_ids); ··· 3560 3255 case CODA_7541: 3561 3256 dev->tempbuf.size = CODA7_TEMP_BUF_SIZE; 3562 3257 break; 3258 + case CODA_960: 3259 + dev->tempbuf.size = CODA9_TEMP_BUF_SIZE; 3260 + break; 3563 3261 } 3564 3262 if (dev->tempbuf.size) { 3565 3263 ret = coda_alloc_aux_buf(dev, &dev->tempbuf, ··· 3581 3273 case CODA_7541: 3582 3274 dev->iram.size = CODA7_IRAM_SIZE; 3583 3275 break; 3276 + case CODA_960: 3277 + dev->iram.size = CODA9_IRAM_SIZE; 3584 3278 } 3585 3279 dev->iram.vaddr = gen_pool_dma_alloc(dev->iram_pool, dev->iram.size, 3586 3280 &dev->iram.paddr);
+112 -3
drivers/media/platform/coda.h
··· 27 27 #define CODA_REG_BIT_CODE_RESET 0x014 28 28 #define CODA_REG_RESET_ENABLE (1 << 0) 29 29 #define CODA_REG_BIT_CUR_PC 0x018 30 + #define CODA9_REG_BIT_SW_RESET 0x024 31 + #define CODA9_SW_RESET_BPU_CORE 0x008 32 + #define CODA9_SW_RESET_BPU_BUS 0x010 33 + #define CODA9_SW_RESET_VCE_CORE 0x020 34 + #define CODA9_SW_RESET_VCE_BUS 0x040 35 + #define CODA9_SW_RESET_GDI_CORE 0x080 36 + #define CODA9_SW_RESET_GDI_BUS 0x100 37 + #define CODA9_REG_BIT_SW_RESET_STATUS 0x034 30 38 31 39 /* Static SW registers */ 32 40 #define CODA_REG_BIT_CODE_BUF_ADDR 0x100 ··· 47 39 #define CODADX6_STREAM_BUF_PIC_FLUSH (1 << 2) 48 40 #define CODA7_STREAM_BUF_DYNALLOC_EN (1 << 5) 49 41 #define CODADX6_STREAM_BUF_DYNALLOC_EN (1 << 4) 50 - #define CODA_STREAM_CHKDIS_OFFSET (1 << 1) 42 + #define CODADX6_STREAM_CHKDIS_OFFSET (1 << 1) 43 + #define CODA7_STREAM_SEL_64BITS_ENDIAN (1 << 1) 51 44 #define CODA_STREAM_ENDIAN_SELECT (1 << 0) 52 45 #define CODA_REG_BIT_FRAME_MEM_CTRL 0x110 46 + #define CODA_FRAME_CHROMA_INTERLEAVE (1 << 2) 53 47 #define CODA_IMAGE_ENDIAN_SELECT (1 << 0) 54 48 #define CODA_REG_BIT_BIT_STREAM_PARAM 0x114 55 49 #define CODA_BIT_STREAM_END_FLAG (1 << 2) ··· 62 52 #define CODA_REG_BIT_FRM_DIS_FLG(x) (0x150 + 4 * (x)) 63 53 #define CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR 0x140 64 54 #define CODA7_REG_BIT_AXI_SRAM_USE 0x140 55 + #define CODA9_USE_HOST_BTP_ENABLE (1 << 13) 56 + #define CODA9_USE_HOST_OVL_ENABLE (1 << 12) 65 57 #define CODA7_USE_HOST_ME_ENABLE (1 << 11) 58 + #define CODA9_USE_HOST_DBK_ENABLE (3 << 10) 66 59 #define CODA7_USE_HOST_OVL_ENABLE (1 << 10) 67 60 #define CODA7_USE_HOST_DBK_ENABLE (1 << 9) 61 + #define CODA9_USE_HOST_IP_ENABLE (1 << 9) 68 62 #define CODA7_USE_HOST_IP_ENABLE (1 << 8) 63 + #define CODA9_USE_HOST_BIT_ENABLE (1 << 8) 69 64 #define CODA7_USE_HOST_BIT_ENABLE (1 << 7) 65 + #define CODA9_USE_BTP_ENABLE (1 << 5) 70 66 #define CODA7_USE_ME_ENABLE (1 << 4) 67 + #define CODA9_USE_OVL_ENABLE (1 << 4) 71 68 #define CODA7_USE_OVL_ENABLE (1 << 3) 69 + #define CODA9_USE_DBK_ENABLE (3 << 2) 72 70 #define CODA7_USE_DBK_ENABLE (1 << 2) 73 71 #define CODA7_USE_IP_ENABLE (1 << 1) 74 72 #define CODA7_USE_BIT_ENABLE (1 << 0) ··· 111 93 #define CODA7_MODE_ENCODE_H264 8 112 94 #define CODA7_MODE_ENCODE_MP4 11 113 95 #define CODA7_MODE_ENCODE_MJPG 13 96 + #define CODA9_MODE_DECODE_H264 0 97 + #define CODA9_MODE_DECODE_VC1 1 98 + #define CODA9_MODE_DECODE_MP2 2 99 + #define CODA9_MODE_DECODE_MP4 3 100 + #define CODA9_MODE_DECODE_DV3 3 101 + #define CODA9_MODE_DECODE_RV 4 102 + #define CODA9_MODE_DECODE_AVS 5 103 + #define CODA9_MODE_DECODE_MJPG 6 104 + #define CODA9_MODE_DECODE_VPX 7 105 + #define CODA9_MODE_ENCODE_H264 8 106 + #define CODA9_MODE_ENCODE_MP4 11 107 + #define CODA9_MODE_ENCODE_MJPG 13 114 108 #define CODA_MODE_INVALID 0xffff 115 109 #define CODA_REG_BIT_INT_ENABLE 0x170 116 110 #define CODA_INT_INTERRUPT_ENABLE (1 << 3) ··· 159 129 #define CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE 0x1a0 160 130 161 131 #define CODA7_RET_DEC_SEQ_ASPECT 0x1b0 132 + #define CODA9_RET_DEC_SEQ_BITRATE 0x1b4 162 133 #define CODA_RET_DEC_SEQ_SUCCESS 0x1c0 163 134 #define CODA_RET_DEC_SEQ_SRC_FMT 0x1c4 /* SRC_SIZE on CODA7 */ 164 135 #define CODA_RET_DEC_SEQ_SRC_SIZE 0x1c4 ··· 176 145 #define CODA_RET_DEC_SEQ_FRATE_DR 0x1e8 177 146 #define CODA_RET_DEC_SEQ_JPG_PARA 0x1e4 178 147 #define CODA_RET_DEC_SEQ_JPG_THUMB_IND 0x1e8 148 + #define CODA9_RET_DEC_SEQ_HEADER_REPORT 0x1ec 179 149 180 150 /* Decoder Picture Run */ 181 151 #define CODA_CMD_DEC_PIC_ROT_MODE 0x180 182 152 #define CODA_CMD_DEC_PIC_ROT_ADDR_Y 0x184 153 + #define CODA9_CMD_DEC_PIC_ROT_INDEX 0x184 183 154 #define CODA_CMD_DEC_PIC_ROT_ADDR_CB 0x188 155 + #define CODA9_CMD_DEC_PIC_ROT_ADDR_Y 0x188 184 156 #define CODA_CMD_DEC_PIC_ROT_ADDR_CR 0x18c 157 + #define CODA9_CMD_DEC_PIC_ROT_ADDR_CB 0x18c 185 158 #define CODA_CMD_DEC_PIC_ROT_STRIDE 0x190 159 + #define CODA9_CMD_DEC_PIC_ROT_ADDR_CR 0x190 160 + #define CODA9_CMD_DEC_PIC_ROT_STRIDE 0x1b8 186 161 187 162 #define CODA_CMD_DEC_PIC_OPTION 0x194 188 163 #define CODA_PRE_SCAN_EN (1 << 0) ··· 220 183 #define CODA_RET_DEC_PIC_CROP_TOP_BOTTOM 0x1e4 221 184 #define CODA_RET_DEC_PIC_FRAME_NEED 0x1ec 222 185 186 + #define CODA9_RET_DEC_PIC_VP8_PIC_REPORT 0x1e8 187 + #define CODA9_RET_DEC_PIC_ASPECT 0x1f0 188 + #define CODA9_RET_DEC_PIC_VP8_SCALE_INFO 0x1f0 189 + #define CODA9_RET_DEC_PIC_FRATE_NR 0x1f4 190 + #define CODA9_RET_DEC_PIC_FRATE_DR 0x1f8 191 + 223 192 /* Encoder Sequence Initialization */ 224 193 #define CODA_CMD_ENC_SEQ_BB_START 0x180 225 194 #define CODA_CMD_ENC_SEQ_BB_SIZE 0x184 226 195 #define CODA_CMD_ENC_SEQ_OPTION 0x188 227 196 #define CODA7_OPTION_AVCINTRA16X16ONLY_OFFSET 9 197 + #define CODA9_OPTION_MVC_PREFIX_NAL_OFFSET 9 228 198 #define CODA7_OPTION_GAMMA_OFFSET 8 199 + #define CODA9_OPTION_MVC_PARASET_REFRESH_OFFSET 8 229 200 #define CODA7_OPTION_RCQPMAX_OFFSET 7 201 + #define CODA9_OPTION_GAMMA_OFFSET 7 230 202 #define CODADX6_OPTION_GAMMA_OFFSET 7 231 203 #define CODA7_OPTION_RCQPMIN_OFFSET 6 204 + #define CODA9_OPTION_RCQPMAX_OFFSET 6 232 205 #define CODA_OPTION_LIMITQP_OFFSET 6 233 206 #define CODA_OPTION_RCINTRAQP_OFFSET 5 234 207 #define CODA_OPTION_FMO_OFFSET 4 208 + #define CODA9_OPTION_MVC_INTERVIEW_OFFSET 4 235 209 #define CODA_OPTION_AVC_AUD_OFFSET 2 236 210 #define CODA_OPTION_SLICEREPORT_OFFSET 1 237 211 #define CODA_CMD_ENC_SEQ_COD_STD 0x18c 238 212 #define CODA_STD_MPEG4 0 213 + #define CODA9_STD_H264 0 239 214 #define CODA_STD_H263 1 240 215 #define CODA_STD_H264 2 241 216 #define CODA_STD_MJPG 3 217 + #define CODA9_STD_MPEG4 3 218 + 242 219 #define CODA_CMD_ENC_SEQ_SRC_SIZE 0x190 243 220 #define CODA7_PICWIDTH_OFFSET 16 244 221 #define CODA7_PICWIDTH_MASK 0xffff ··· 319 268 #define CODA7_CMD_ENC_SEQ_SEARCH_BASE 0x1b8 320 269 #define CODA7_CMD_ENC_SEQ_SEARCH_SIZE 0x1bc 321 270 #define CODA7_CMD_ENC_SEQ_INTRA_QP 0x1c4 322 - #define CODA_CMD_ENC_SEQ_RC_QP_MAX 0x1c8 271 + #define CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX 0x1c8 272 + #define CODA_QPMIN_OFFSET 8 273 + #define CODA_QPMIN_MASK 0x3f 323 274 #define CODA_QPMAX_OFFSET 0 324 275 #define CODA_QPMAX_MASK 0x3f 325 276 #define CODA_CMD_ENC_SEQ_RC_GAMMA 0x1cc 326 277 #define CODA_GAMMA_OFFSET 0 327 278 #define CODA_GAMMA_MASK 0xffff 279 + #define CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE 0x1d0 280 + #define CODA9_CMD_ENC_SEQ_INTRA_WEIGHT 0x1d4 281 + #define CODA9_CMD_ENC_SEQ_ME_OPTION 0x1d8 328 282 #define CODA_RET_ENC_SEQ_SUCCESS 0x1c0 329 283 330 284 /* Encoder Picture Run */ 285 + #define CODA9_CMD_ENC_PIC_SRC_INDEX 0x180 286 + #define CODA9_CMD_ENC_PIC_SRC_STRIDE 0x184 287 + #define CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC 0x1a4 288 + #define CODA9_CMD_ENC_PIC_SRC_ADDR_Y 0x1a8 289 + #define CODA9_CMD_ENC_PIC_SRC_ADDR_CB 0x1ac 290 + #define CODA9_CMD_ENC_PIC_SRC_ADDR_CR 0x1b0 331 291 #define CODA_CMD_ENC_PIC_SRC_ADDR_Y 0x180 332 292 #define CODA_CMD_ENC_PIC_SRC_ADDR_CB 0x184 333 293 #define CODA_CMD_ENC_PIC_SRC_ADDR_CR 0x188 ··· 353 291 #define CODA_MIR_VER (0x1 << 2) 354 292 #define CODA_MIR_HOR (0x2 << 2) 355 293 #define CODA_MIR_VER_HOR (0x3 << 2) 356 - #define CODA_CMD_ENC_PIC_OPTION 0x194 294 + #define CODA_CMD_ENC_PIC_OPTION 0x194 295 + #define CODA_FORCE_IPICTURE BIT(1) 296 + #define CODA_REPORT_MB_INFO BIT(3) 297 + #define CODA_REPORT_MV_INFO BIT(4) 298 + #define CODA_REPORT_SLICE_INFO BIT(5) 357 299 #define CODA_CMD_ENC_PIC_BB_START 0x198 358 300 #define CODA_CMD_ENC_PIC_BB_SIZE 0x19c 359 301 #define CODA_RET_ENC_FRAME_NUM 0x1c0 ··· 372 306 #define CODA_CMD_SET_FRAME_BUF_STRIDE 0x184 373 307 #define CODA_CMD_SET_FRAME_SLICE_BB_START 0x188 374 308 #define CODA_CMD_SET_FRAME_SLICE_BB_SIZE 0x18c 309 + #define CODA9_CMD_SET_FRAME_SUBSAMP_A 0x188 310 + #define CODA9_CMD_SET_FRAME_SUBSAMP_B 0x18c 375 311 #define CODA7_CMD_SET_FRAME_AXI_BIT_ADDR 0x190 376 312 #define CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR 0x194 377 313 #define CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR 0x198 378 314 #define CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR 0x19c 379 315 #define CODA7_CMD_SET_FRAME_AXI_OVL_ADDR 0x1a0 380 316 #define CODA7_CMD_SET_FRAME_MAX_DEC_SIZE 0x1a4 317 + #define CODA9_CMD_SET_FRAME_AXI_BTP_ADDR 0x1a4 381 318 #define CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE 0x1a8 319 + #define CODA9_CMD_SET_FRAME_CACHE_SIZE 0x1a8 320 + #define CODA9_CMD_SET_FRAME_CACHE_CONFIG 0x1ac 321 + #define CODA9_CACHE_BYPASS_OFFSET 28 322 + #define CODA9_CACHE_DUALCONF_OFFSET 26 323 + #define CODA9_CACHE_PAGEMERGE_OFFSET 24 324 + #define CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET 16 325 + #define CODA9_CACHE_CB_BUFFER_SIZE_OFFSET 8 326 + #define CODA9_CACHE_CR_BUFFER_SIZE_OFFSET 0 327 + #define CODA9_CMD_SET_FRAME_SUBSAMP_A_MVC 0x1b0 328 + #define CODA9_CMD_SET_FRAME_SUBSAMP_B_MVC 0x1b4 329 + #define CODA9_CMD_SET_FRAME_DP_BUF_BASE 0x1b0 330 + #define CODA9_CMD_SET_FRAME_DP_BUF_SIZE 0x1b4 331 + #define CODA9_CMD_SET_FRAME_MAX_DEC_SIZE 0x1b8 332 + #define CODA9_CMD_SET_FRAME_DELAY 0x1bc 382 333 383 334 /* Encoder Header */ 384 335 #define CODA_CMD_ENC_HEADER_CODE 0x180 ··· 405 322 #define CODA_HEADER_MP4V_VOL 0 406 323 #define CODA_HEADER_MP4V_VOS 1 407 324 #define CODA_HEADER_MP4V_VIS 2 325 + #define CODA9_HEADER_FRAME_CROP (1 << 3) 408 326 #define CODA_CMD_ENC_HEADER_BB_START 0x184 409 327 #define CODA_CMD_ENC_HEADER_BB_SIZE 0x188 328 + #define CODA9_CMD_ENC_HEADER_FRAME_CROP_H 0x18c 329 + #define CODA9_CMD_ENC_HEADER_FRAME_CROP_V 0x190 410 330 411 331 /* Get Version */ 412 332 #define CODA_CMD_FIRMWARE_VERNUM 0x1c0 ··· 420 334 #define CODA_FIRMWARE_VERNUM(product, major, minor, release) \ 421 335 ((product) << 16 | ((major) << 12) | \ 422 336 ((minor) << 8) | (release)) 337 + #define CODA9_CMD_FIRMWARE_CODE_REV 0x1c4 338 + 339 + #define CODA9_GDMA_BASE 0x1000 340 + #define CODA9_GDI_WPROT_ERR_CLR (CODA9_GDMA_BASE + 0x0a0) 341 + #define CODA9_GDI_WPROT_RGN_EN (CODA9_GDMA_BASE + 0x0ac) 342 + 343 + #define CODA9_GDI_BUS_CTRL (CODA9_GDMA_BASE + 0x0f0) 344 + #define CODA9_GDI_BUS_STATUS (CODA9_GDMA_BASE + 0x0f4) 345 + 346 + #define CODA9_GDI_XY2_CAS_0 (CODA9_GDMA_BASE + 0x800) 347 + #define CODA9_GDI_XY2_CAS_F (CODA9_GDMA_BASE + 0x83c) 348 + 349 + #define CODA9_GDI_XY2_BA_0 (CODA9_GDMA_BASE + 0x840) 350 + #define CODA9_GDI_XY2_BA_1 (CODA9_GDMA_BASE + 0x844) 351 + #define CODA9_GDI_XY2_BA_2 (CODA9_GDMA_BASE + 0x848) 352 + #define CODA9_GDI_XY2_BA_3 (CODA9_GDMA_BASE + 0x84c) 353 + 354 + #define CODA9_GDI_XY2_RAS_0 (CODA9_GDMA_BASE + 0x850) 355 + #define CODA9_GDI_XY2_RAS_F (CODA9_GDMA_BASE + 0x88c) 356 + 357 + #define CODA9_GDI_XY2_RBC_CONFIG (CODA9_GDMA_BASE + 0x890) 358 + #define CODA9_GDI_RBC2_AXI_0 (CODA9_GDMA_BASE + 0x8a0) 359 + #define CODA9_GDI_RBC2_AXI_1F (CODA9_GDMA_BASE + 0x91c) 423 360 424 361 #endif