tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
MIPS: BMIPS: Add DTS files for several platforms
Most of the supported chips use legacy (non-DT) bootloaders, so they will
need to select an appropriate builtin DTB at compile time until the
bootloader is updated. Provide suitable DTS files, and a means to compile
one of them into the kernel image.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Cc: f.fainelli@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8858/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
Kevin Cernekee
and committed by
Ralf Baechle
8945e37e
81a07b4a
+1992
-1
+1
arch/mips/Kconfig
+1
arch/mips/Kconfig
+58
arch/mips/bmips/Kconfig
+58
arch/mips/bmips/Kconfig
···
1
+
choice
2
+
prompt "Built-in device tree"
3
+
help
4
+
Legacy bootloaders do not pass a DTB pointer to the kernel, so
5
+
if a "wrapper" is not being used, the kernel will need to include
6
+
a device tree that matches the target board.
7
+
8
+
The builtin DTB will only be used if the firmware does not supply
9
+
a valid DTB.
10
+
11
+
config DT_NONE
12
+
bool "None"
13
+
14
+
config DT_BCM93384WVG
15
+
bool "BCM93384WVG Zephyr CPU"
16
+
select BUILTIN_DTB
17
+
18
+
config DT_BCM93384WVG_VIPER
19
+
bool "BCM93384WVG Viper CPU (EXPERIMENTAL)"
20
+
select BUILTIN_DTB
21
+
22
+
config DT_BCM96368MVWG
23
+
bool "BCM96368MVWG"
24
+
select BUILTIN_DTB
25
+
26
+
config DT_BCM9EJTAGPRB
27
+
bool "BCM9EJTAGPRB"
28
+
select BUILTIN_DTB
29
+
30
+
config DT_BCM97125CBMB
31
+
bool "BCM97125CBMB"
32
+
select BUILTIN_DTB
33
+
34
+
config DT_BCM97346DBSMB
35
+
bool "BCM97346DBSMB"
36
+
select BUILTIN_DTB
37
+
38
+
config DT_BCM97358SVMB
39
+
bool "BCM97358SVMB"
40
+
select BUILTIN_DTB
41
+
42
+
config DT_BCM97360SVMB
43
+
bool "BCM97360SVMB"
44
+
select BUILTIN_DTB
45
+
46
+
config DT_BCM97362SVMB
47
+
bool "BCM97362SVMB"
48
+
select BUILTIN_DTB
49
+
50
+
config DT_BCM97420C
51
+
bool "BCM97420C"
52
+
select BUILTIN_DTB
53
+
54
+
config DT_BCM97425SVMB
55
+
bool "BCM97425SVMB"
56
+
select BUILTIN_DTB
57
+
58
+
endchoice
+11
-1
arch/mips/boot/dts/brcm/Makefile
+11
-1
arch/mips/boot/dts/brcm/Makefile
···
1
-
dtb-$(CONFIG_BMIPS_GENERIC) += bcm93384wvg.dtb
1
+
dtb-$(CONFIG_DT_BCM93384WVG) += bcm93384wvg.dtb
2
+
dtb-$(CONFIG_DT_BCM93384WVG_VIPER) += bcm93384wvg_viper.dtb
3
+
dtb-$(CONFIG_DT_BCM96368MVWG) += bcm96368mvwg.dtb
4
+
dtb-$(CONFIG_DT_BCM9EJTAGPRB) += bcm9ejtagprb.dtb
5
+
dtb-$(CONFIG_DT_BCM97125CBMB) += bcm97125cbmb.dtb
6
+
dtb-$(CONFIG_DT_BCM97346DBSMB) += bcm97346dbsmb.dtb
7
+
dtb-$(CONFIG_DT_BCM97358SVMB) += bcm97358svmb.dtb
8
+
dtb-$(CONFIG_DT_BCM97360SVMB) += bcm97360svmb.dtb
9
+
dtb-$(CONFIG_DT_BCM97362SVMB) += bcm97362svmb.dtb
10
+
dtb-$(CONFIG_DT_BCM97420C) += bcm97420c.dtb
11
+
dtb-$(CONFIG_DT_BCM97425SVMB) += bcm97425svmb.dtb
2
12
3
13
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
4
14
+108
arch/mips/boot/dts/brcm/bcm3384_viper.dtsi
+108
arch/mips/boot/dts/brcm/bcm3384_viper.dtsi
···
1
+
/ {
2
+
#address-cells = <1>;
3
+
#size-cells = <1>;
4
+
compatible = "brcm,bcm3384-viper", "brcm,bcm33843-viper";
5
+
6
+
memory@0 {
7
+
device_type = "memory";
8
+
9
+
/* Typical ranges. The bootloader should fill these in. */
10
+
reg = <0x06000000 0x02000000>,
11
+
<0x0e000000 0x02000000>;
12
+
};
13
+
14
+
cpus {
15
+
#address-cells = <1>;
16
+
#size-cells = <0>;
17
+
18
+
/* 1/2 of the CPU core clock (standard MIPS behavior) */
19
+
mips-hpt-frequency = <300000000>;
20
+
21
+
cpu@0 {
22
+
compatible = "brcm,bmips4350";
23
+
device_type = "cpu";
24
+
reg = <0>;
25
+
};
26
+
};
27
+
28
+
cpu_intc: cpu_intc {
29
+
#address-cells = <0>;
30
+
compatible = "mti,cpu-interrupt-controller";
31
+
32
+
interrupt-controller;
33
+
#interrupt-cells = <1>;
34
+
};
35
+
36
+
clocks {
37
+
periph_clk: periph_clk {
38
+
compatible = "fixed-clock";
39
+
#clock-cells = <0>;
40
+
clock-frequency = <54000000>;
41
+
};
42
+
};
43
+
44
+
aliases {
45
+
uart0 = &uart0;
46
+
};
47
+
48
+
ubus {
49
+
#address-cells = <1>;
50
+
#size-cells = <1>;
51
+
52
+
compatible = "brcm,ubus", "simple-bus";
53
+
ranges;
54
+
/* No dma-ranges on Viper. */
55
+
56
+
periph_intc: periph_intc@14e00048 {
57
+
compatible = "brcm,bcm3380-l2-intc";
58
+
reg = <0x14e00048 0x4 0x14e0004c 0x4>,
59
+
<0x14e00350 0x4 0x14e00354 0x4>;
60
+
61
+
interrupt-controller;
62
+
#interrupt-cells = <1>;
63
+
64
+
interrupt-parent = <&cpu_intc>;
65
+
interrupts = <4>;
66
+
};
67
+
68
+
cmips_intc: cmips_intc@151f8048 {
69
+
compatible = "brcm,bcm3380-l2-intc";
70
+
reg = <0x151f8048 0x4 0x151f804c 0x4>;
71
+
72
+
interrupt-controller;
73
+
#interrupt-cells = <1>;
74
+
75
+
interrupt-parent = <&periph_intc>;
76
+
interrupts = <30>;
77
+
brcm,int-map-mask = <0xffffffff>;
78
+
};
79
+
80
+
uart0: serial@14e00520 {
81
+
compatible = "brcm,bcm6345-uart";
82
+
reg = <0x14e00520 0x18>;
83
+
interrupt-parent = <&periph_intc>;
84
+
interrupts = <2>;
85
+
clocks = <&periph_clk>;
86
+
status = "disabled";
87
+
};
88
+
89
+
ehci0: usb@15400300 {
90
+
compatible = "brcm,bcm3384-ehci", "generic-ehci";
91
+
reg = <0x15400300 0x100>;
92
+
big-endian;
93
+
interrupt-parent = <&periph_intc>;
94
+
interrupts = <41>;
95
+
status = "disabled";
96
+
};
97
+
98
+
ohci0: usb@15400400 {
99
+
compatible = "brcm,bcm3384-ohci", "generic-ohci";
100
+
reg = <0x15400400 0x100>;
101
+
big-endian;
102
+
no-big-frame-no;
103
+
interrupt-parent = <&periph_intc>;
104
+
interrupts = <40>;
105
+
status = "disabled";
106
+
};
107
+
};
108
+
};
+86
arch/mips/boot/dts/brcm/bcm6328.dtsi
+86
arch/mips/boot/dts/brcm/bcm6328.dtsi
···
1
+
/ {
2
+
#address-cells = <1>;
3
+
#size-cells = <1>;
4
+
compatible = "brcm,bcm6328";
5
+
6
+
cpus {
7
+
#address-cells = <1>;
8
+
#size-cells = <0>;
9
+
10
+
mips-hpt-frequency = <160000000>;
11
+
12
+
cpu@0 {
13
+
compatible = "brcm,bmips4350";
14
+
device_type = "cpu";
15
+
reg = <0>;
16
+
};
17
+
18
+
cpu@1 {
19
+
compatible = "brcm,bmips4350";
20
+
device_type = "cpu";
21
+
reg = <1>;
22
+
};
23
+
};
24
+
25
+
clocks {
26
+
periph_clk: periph_clk {
27
+
compatible = "fixed-clock";
28
+
#clock-cells = <0>;
29
+
clock-frequency = <50000000>;
30
+
};
31
+
};
32
+
33
+
aliases {
34
+
uart0 = &uart0;
35
+
};
36
+
37
+
cpu_intc: cpu_intc {
38
+
#address-cells = <0>;
39
+
compatible = "mti,cpu-interrupt-controller";
40
+
41
+
interrupt-controller;
42
+
#interrupt-cells = <1>;
43
+
};
44
+
45
+
ubus {
46
+
#address-cells = <1>;
47
+
#size-cells = <1>;
48
+
49
+
compatible = "simple-bus";
50
+
ranges;
51
+
52
+
periph_intc: periph_intc@10000020 {
53
+
compatible = "brcm,bcm3380-l2-intc";
54
+
reg = <0x10000024 0x4 0x1000002c 0x4>,
55
+
<0x10000020 0x4 0x10000028 0x4>;
56
+
57
+
interrupt-controller;
58
+
#interrupt-cells = <1>;
59
+
60
+
interrupt-parent = <&cpu_intc>;
61
+
interrupts = <2>;
62
+
};
63
+
64
+
uart0: serial@10000100 {
65
+
compatible = "brcm,bcm6345-uart";
66
+
reg = <0x10000100 0x18>;
67
+
interrupt-parent = <&periph_intc>;
68
+
interrupts = <28>;
69
+
clocks = <&periph_clk>;
70
+
status = "disabled";
71
+
};
72
+
73
+
timer: timer@10000040 {
74
+
compatible = "syscon";
75
+
reg = <0x10000040 0x2c>;
76
+
little-endian;
77
+
};
78
+
79
+
reboot {
80
+
compatible = "syscon-reboot";
81
+
regmap = <&timer>;
82
+
offset = <0x28>;
83
+
mask = <0x1>;
84
+
};
85
+
};
86
+
};
+93
arch/mips/boot/dts/brcm/bcm6368.dtsi
+93
arch/mips/boot/dts/brcm/bcm6368.dtsi
···
1
+
/ {
2
+
#address-cells = <1>;
3
+
#size-cells = <1>;
4
+
compatible = "brcm,bcm6368";
5
+
6
+
cpus {
7
+
#address-cells = <1>;
8
+
#size-cells = <0>;
9
+
10
+
mips-hpt-frequency = <200000000>;
11
+
12
+
cpu@0 {
13
+
compatible = "brcm,bmips4350";
14
+
device_type = "cpu";
15
+
reg = <0>;
16
+
};
17
+
18
+
cpu@1 {
19
+
compatible = "brcm,bmips4350";
20
+
device_type = "cpu";
21
+
reg = <1>;
22
+
};
23
+
24
+
};
25
+
26
+
clocks {
27
+
periph_clk: periph_clk {
28
+
compatible = "fixed-clock";
29
+
#clock-cells = <0>;
30
+
clock-frequency = <50000000>;
31
+
};
32
+
};
33
+
34
+
aliases {
35
+
uart0 = &uart0;
36
+
};
37
+
38
+
cpu_intc: cpu_intc {
39
+
#address-cells = <0>;
40
+
compatible = "mti,cpu-interrupt-controller";
41
+
42
+
interrupt-controller;
43
+
#interrupt-cells = <1>;
44
+
};
45
+
46
+
ubus {
47
+
#address-cells = <1>;
48
+
#size-cells = <1>;
49
+
50
+
compatible = "simple-bus";
51
+
ranges;
52
+
53
+
periph_intc: periph_intc@10000020 {
54
+
compatible = "brcm,bcm3380-l2-intc";
55
+
reg = <0x10000024 0x4 0x1000002c 0x4>,
56
+
<0x10000020 0x4 0x10000028 0x4>;
57
+
58
+
interrupt-controller;
59
+
#interrupt-cells = <1>;
60
+
61
+
interrupt-parent = <&cpu_intc>;
62
+
interrupts = <2>;
63
+
};
64
+
65
+
uart0: serial@10000100 {
66
+
compatible = "brcm,bcm6345-uart";
67
+
reg = <0x10000100 0x18>;
68
+
interrupt-parent = <&periph_intc>;
69
+
interrupts = <2>;
70
+
clocks = <&periph_clk>;
71
+
status = "disabled";
72
+
};
73
+
74
+
ehci0: usb@10001500 {
75
+
compatible = "brcm,bcm6368-ehci", "generic-ehci";
76
+
reg = <0x10001500 0x100>;
77
+
big-endian;
78
+
interrupt-parent = <&periph_intc>;
79
+
interrupts = <7>;
80
+
status = "disabled";
81
+
};
82
+
83
+
ohci0: usb@10001600 {
84
+
compatible = "brcm,bcm6368-ohci", "generic-ohci";
85
+
reg = <0x10001600 0x100>;
86
+
big-endian;
87
+
no-big-frame-no;
88
+
interrupt-parent = <&periph_intc>;
89
+
interrupts = <5>;
90
+
status = "disabled";
91
+
};
92
+
};
93
+
};
+139
arch/mips/boot/dts/brcm/bcm7125.dtsi
+139
arch/mips/boot/dts/brcm/bcm7125.dtsi
···
1
+
/ {
2
+
#address-cells = <1>;
3
+
#size-cells = <1>;
4
+
compatible = "brcm,bcm7125";
5
+
6
+
cpus {
7
+
#address-cells = <1>;
8
+
#size-cells = <0>;
9
+
10
+
mips-hpt-frequency = <202500000>;
11
+
12
+
cpu@0 {
13
+
compatible = "brcm,bmips4380";
14
+
device_type = "cpu";
15
+
reg = <0>;
16
+
};
17
+
18
+
cpu@1 {
19
+
compatible = "brcm,bmips4380";
20
+
device_type = "cpu";
21
+
reg = <1>;
22
+
};
23
+
};
24
+
25
+
aliases {
26
+
uart0 = &uart0;
27
+
};
28
+
29
+
cpu_intc: cpu_intc {
30
+
#address-cells = <0>;
31
+
compatible = "mti,cpu-interrupt-controller";
32
+
33
+
interrupt-controller;
34
+
#interrupt-cells = <1>;
35
+
};
36
+
37
+
clocks {
38
+
uart_clk: uart_clk {
39
+
compatible = "fixed-clock";
40
+
#clock-cells = <0>;
41
+
clock-frequency = <81000000>;
42
+
};
43
+
};
44
+
45
+
rdb {
46
+
#address-cells = <1>;
47
+
#size-cells = <1>;
48
+
49
+
compatible = "simple-bus";
50
+
ranges = <0 0x10000000 0x01000000>;
51
+
52
+
periph_intc: periph_intc@441400 {
53
+
compatible = "brcm,bcm7038-l1-intc";
54
+
reg = <0x441400 0x30>, <0x441600 0x30>;
55
+
56
+
interrupt-controller;
57
+
#interrupt-cells = <1>;
58
+
59
+
interrupt-parent = <&cpu_intc>;
60
+
interrupts = <2>, <3>;
61
+
};
62
+
63
+
sun_l2_intc: sun_l2_intc@401800 {
64
+
compatible = "brcm,l2-intc";
65
+
reg = <0x401800 0x30>;
66
+
interrupt-controller;
67
+
#interrupt-cells = <1>;
68
+
interrupt-parent = <&periph_intc>;
69
+
interrupts = <23>;
70
+
};
71
+
72
+
gisb-arb@400000 {
73
+
compatible = "brcm,bcm7400-gisb-arb";
74
+
reg = <0x400000 0xdc>;
75
+
native-endian;
76
+
interrupt-parent = <&sun_l2_intc>;
77
+
interrupts = <0>, <2>;
78
+
brcm,gisb-arb-master-mask = <0x2f7>;
79
+
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
80
+
"bsp_0", "rdc_0", "rptd_0",
81
+
"avd_0", "jtag_0";
82
+
};
83
+
84
+
upg_irq0_intc: upg_irq0_intc@406780 {
85
+
compatible = "brcm,bcm7120-l2-intc";
86
+
reg = <0x406780 0x8>;
87
+
88
+
brcm,int-map-mask = <0x44>;
89
+
brcm,int-fwd-mask = <0x70000>;
90
+
91
+
interrupt-controller;
92
+
#interrupt-cells = <1>;
93
+
94
+
interrupt-parent = <&periph_intc>;
95
+
interrupts = <18>;
96
+
};
97
+
98
+
sun_top_ctrl: syscon@404000 {
99
+
compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
100
+
reg = <0x404000 0x60c>;
101
+
little-endian;
102
+
};
103
+
104
+
reboot {
105
+
compatible = "brcm,bcm7038-reboot";
106
+
syscon = <&sun_top_ctrl 0x8 0x14>;
107
+
};
108
+
109
+
uart0: serial@406b00 {
110
+
compatible = "ns16550a";
111
+
reg = <0x406b00 0x20>;
112
+
reg-io-width = <0x4>;
113
+
reg-shift = <0x2>;
114
+
native-endian;
115
+
interrupt-parent = <&periph_intc>;
116
+
interrupts = <21>;
117
+
clocks = <&uart_clk>;
118
+
status = "disabled";
119
+
};
120
+
121
+
ehci0: usb@488300 {
122
+
compatible = "brcm,bcm7125-ehci", "generic-ehci";
123
+
reg = <0x488300 0x100>;
124
+
native-endian;
125
+
interrupt-parent = <&periph_intc>;
126
+
interrupts = <60>;
127
+
status = "disabled";
128
+
};
129
+
130
+
ohci0: usb@488400 {
131
+
compatible = "brcm,bcm7125-ohci", "generic-ohci";
132
+
reg = <0x488400 0x100>;
133
+
native-endian;
134
+
interrupt-parent = <&periph_intc>;
135
+
interrupts = <61>;
136
+
status = "disabled";
137
+
};
138
+
};
139
+
};
+224
arch/mips/boot/dts/brcm/bcm7346.dtsi
+224
arch/mips/boot/dts/brcm/bcm7346.dtsi
···
1
+
/ {
2
+
#address-cells = <1>;
3
+
#size-cells = <1>;
4
+
compatible = "brcm,bcm7346";
5
+
6
+
cpus {
7
+
#address-cells = <1>;
8
+
#size-cells = <0>;
9
+
10
+
mips-hpt-frequency = <163125000>;
11
+
12
+
cpu@0 {
13
+
compatible = "brcm,bmips5000";
14
+
device_type = "cpu";
15
+
reg = <0>;
16
+
};
17
+
18
+
cpu@1 {
19
+
compatible = "brcm,bmips5000";
20
+
device_type = "cpu";
21
+
reg = <1>;
22
+
};
23
+
};
24
+
25
+
aliases {
26
+
uart0 = &uart0;
27
+
};
28
+
29
+
cpu_intc: cpu_intc {
30
+
#address-cells = <0>;
31
+
compatible = "mti,cpu-interrupt-controller";
32
+
33
+
interrupt-controller;
34
+
#interrupt-cells = <1>;
35
+
};
36
+
37
+
clocks {
38
+
uart_clk: uart_clk {
39
+
compatible = "fixed-clock";
40
+
#clock-cells = <0>;
41
+
clock-frequency = <81000000>;
42
+
};
43
+
};
44
+
45
+
rdb {
46
+
#address-cells = <1>;
47
+
#size-cells = <1>;
48
+
49
+
compatible = "simple-bus";
50
+
ranges = <0 0x10000000 0x01000000>;
51
+
52
+
periph_intc: periph_intc@411400 {
53
+
compatible = "brcm,bcm7038-l1-intc";
54
+
reg = <0x411400 0x30>, <0x411600 0x30>;
55
+
56
+
interrupt-controller;
57
+
#interrupt-cells = <1>;
58
+
59
+
interrupt-parent = <&cpu_intc>;
60
+
interrupts = <2>, <3>;
61
+
};
62
+
63
+
sun_l2_intc: sun_l2_intc@403000 {
64
+
compatible = "brcm,l2-intc";
65
+
reg = <0x403000 0x30>;
66
+
interrupt-controller;
67
+
#interrupt-cells = <1>;
68
+
interrupt-parent = <&periph_intc>;
69
+
interrupts = <51>;
70
+
};
71
+
72
+
gisb-arb@400000 {
73
+
compatible = "brcm,bcm7400-gisb-arb";
74
+
reg = <0x400000 0xdc>;
75
+
native-endian;
76
+
interrupt-parent = <&sun_l2_intc>;
77
+
interrupts = <0>, <2>;
78
+
brcm,gisb-arb-master-mask = <0x673>;
79
+
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
80
+
"rdc_0", "raaga_0",
81
+
"jtag_0", "svd_0";
82
+
};
83
+
84
+
upg_irq0_intc: upg_irq0_intc@406780 {
85
+
compatible = "brcm,bcm7120-l2-intc";
86
+
reg = <0x406780 0x8>;
87
+
88
+
brcm,int-map-mask = <0x44>;
89
+
brcm,int-fwd-mask = <0x70000>;
90
+
91
+
interrupt-controller;
92
+
#interrupt-cells = <1>;
93
+
94
+
interrupt-parent = <&periph_intc>;
95
+
interrupts = <59>;
96
+
};
97
+
98
+
sun_top_ctrl: syscon@404000 {
99
+
compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
100
+
reg = <0x404000 0x51c>;
101
+
little-endian;
102
+
};
103
+
104
+
reboot {
105
+
compatible = "brcm,brcmstb-reboot";
106
+
syscon = <&sun_top_ctrl 0x304 0x308>;
107
+
};
108
+
109
+
uart0: serial@406900 {
110
+
compatible = "ns16550a";
111
+
reg = <0x406900 0x20>;
112
+
reg-io-width = <0x4>;
113
+
reg-shift = <0x2>;
114
+
native-endian;
115
+
interrupt-parent = <&periph_intc>;
116
+
interrupts = <64>;
117
+
clocks = <&uart_clk>;
118
+
status = "disabled";
119
+
};
120
+
121
+
enet0: ethernet@430000 {
122
+
phy-mode = "internal";
123
+
phy-handle = <&phy1>;
124
+
mac-address = [ 00 10 18 36 23 1a ];
125
+
compatible = "brcm,genet-v2";
126
+
#address-cells = <0x1>;
127
+
#size-cells = <0x1>;
128
+
reg = <0x430000 0x4c8c>;
129
+
interrupts = <24>, <25>;
130
+
interrupt-parent = <&periph_intc>;
131
+
status = "disabled";
132
+
133
+
mdio@e14 {
134
+
compatible = "brcm,genet-mdio-v2";
135
+
#address-cells = <0x1>;
136
+
#size-cells = <0x0>;
137
+
reg = <0xe14 0x8>;
138
+
139
+
phy1: ethernet-phy@1 {
140
+
max-speed = <100>;
141
+
reg = <0x1>;
142
+
compatible = "brcm,40nm-ephy",
143
+
"ethernet-phy-ieee802.3-c22";
144
+
};
145
+
};
146
+
};
147
+
148
+
ehci0: usb@480300 {
149
+
compatible = "brcm,bcm7346-ehci", "generic-ehci";
150
+
reg = <0x480300 0x100>;
151
+
native-endian;
152
+
interrupt-parent = <&periph_intc>;
153
+
interrupts = <68>;
154
+
status = "disabled";
155
+
};
156
+
157
+
ohci0: usb@480400 {
158
+
compatible = "brcm,bcm7346-ohci", "generic-ohci";
159
+
reg = <0x480400 0x100>;
160
+
native-endian;
161
+
no-big-frame-no;
162
+
interrupt-parent = <&periph_intc>;
163
+
interrupts = <70>;
164
+
status = "disabled";
165
+
};
166
+
167
+
ehci1: usb@480500 {
168
+
compatible = "brcm,bcm7346-ehci", "generic-ehci";
169
+
reg = <0x480500 0x100>;
170
+
native-endian;
171
+
interrupt-parent = <&periph_intc>;
172
+
interrupts = <69>;
173
+
status = "disabled";
174
+
};
175
+
176
+
ohci1: usb@480600 {
177
+
compatible = "brcm,bcm7346-ohci", "generic-ohci";
178
+
reg = <0x480600 0x100>;
179
+
native-endian;
180
+
no-big-frame-no;
181
+
interrupt-parent = <&periph_intc>;
182
+
interrupts = <71>;
183
+
status = "disabled";
184
+
};
185
+
186
+
ehci2: usb@490300 {
187
+
compatible = "brcm,bcm7346-ehci", "generic-ehci";
188
+
reg = <0x490300 0x100>;
189
+
native-endian;
190
+
interrupt-parent = <&periph_intc>;
191
+
interrupts = <73>;
192
+
status = "disabled";
193
+
};
194
+
195
+
ohci2: usb@490400 {
196
+
compatible = "brcm,bcm7346-ohci", "generic-ohci";
197
+
reg = <0x490400 0x100>;
198
+
native-endian;
199
+
no-big-frame-no;
200
+
interrupt-parent = <&periph_intc>;
201
+
interrupts = <75>;
202
+
status = "disabled";
203
+
};
204
+
205
+
ehci3: usb@490500 {
206
+
compatible = "brcm,bcm7346-ehci", "generic-ehci";
207
+
reg = <0x490500 0x100>;
208
+
native-endian;
209
+
interrupt-parent = <&periph_intc>;
210
+
interrupts = <74>;
211
+
status = "disabled";
212
+
};
213
+
214
+
ohci3: usb@490600 {
215
+
compatible = "brcm,bcm7346-ohci", "generic-ohci";
216
+
reg = <0x490600 0x100>;
217
+
native-endian;
218
+
no-big-frame-no;
219
+
interrupt-parent = <&periph_intc>;
220
+
interrupts = <76>;
221
+
status = "disabled";
222
+
};
223
+
};
224
+
};
+161
arch/mips/boot/dts/brcm/bcm7358.dtsi
+161
arch/mips/boot/dts/brcm/bcm7358.dtsi
···
1
+
/ {
2
+
#address-cells = <1>;
3
+
#size-cells = <1>;
4
+
compatible = "brcm,bcm7358";
5
+
6
+
cpus {
7
+
#address-cells = <1>;
8
+
#size-cells = <0>;
9
+
10
+
mips-hpt-frequency = <375000000>;
11
+
12
+
cpu@0 {
13
+
compatible = "brcm,bmips3300";
14
+
device_type = "cpu";
15
+
reg = <0>;
16
+
};
17
+
};
18
+
19
+
aliases {
20
+
uart0 = &uart0;
21
+
};
22
+
23
+
cpu_intc: cpu_intc {
24
+
#address-cells = <0>;
25
+
compatible = "mti,cpu-interrupt-controller";
26
+
27
+
interrupt-controller;
28
+
#interrupt-cells = <1>;
29
+
};
30
+
31
+
clocks {
32
+
uart_clk: uart_clk {
33
+
compatible = "fixed-clock";
34
+
#clock-cells = <0>;
35
+
clock-frequency = <81000000>;
36
+
};
37
+
};
38
+
39
+
rdb {
40
+
#address-cells = <1>;
41
+
#size-cells = <1>;
42
+
43
+
compatible = "simple-bus";
44
+
ranges = <0 0x10000000 0x01000000>;
45
+
46
+
periph_intc: periph_intc@411400 {
47
+
compatible = "brcm,bcm7038-l1-intc";
48
+
reg = <0x411400 0x30>;
49
+
50
+
interrupt-controller;
51
+
#interrupt-cells = <1>;
52
+
53
+
interrupt-parent = <&cpu_intc>;
54
+
interrupts = <2>;
55
+
};
56
+
57
+
sun_l2_intc: sun_l2_intc@403000 {
58
+
compatible = "brcm,l2-intc";
59
+
reg = <0x403000 0x30>;
60
+
interrupt-controller;
61
+
#interrupt-cells = <1>;
62
+
interrupt-parent = <&periph_intc>;
63
+
interrupts = <48>;
64
+
};
65
+
66
+
gisb-arb@400000 {
67
+
compatible = "brcm,bcm7400-gisb-arb";
68
+
reg = <0x400000 0xdc>;
69
+
native-endian;
70
+
interrupt-parent = <&sun_l2_intc>;
71
+
interrupts = <0>, <2>;
72
+
brcm,gisb-arb-master-mask = <0x2f3>;
73
+
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
74
+
"rdc_0", "raaga_0",
75
+
"avd_0", "jtag_0";
76
+
};
77
+
78
+
upg_irq0_intc: upg_irq0_intc@406600 {
79
+
compatible = "brcm,bcm7120-l2-intc";
80
+
reg = <0x406600 0x8>;
81
+
82
+
brcm,int-map-mask = <0x44>;
83
+
brcm,int-fwd-mask = <0x70000>;
84
+
85
+
interrupt-controller;
86
+
#interrupt-cells = <1>;
87
+
88
+
interrupt-parent = <&periph_intc>;
89
+
interrupts = <56>;
90
+
};
91
+
92
+
sun_top_ctrl: syscon@404000 {
93
+
compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
94
+
reg = <0x404000 0x51c>;
95
+
little-endian;
96
+
};
97
+
98
+
reboot {
99
+
compatible = "brcm,brcmstb-reboot";
100
+
syscon = <&sun_top_ctrl 0x304 0x308>;
101
+
};
102
+
103
+
uart0: serial@406800 {
104
+
compatible = "ns16550a";
105
+
reg = <0x406800 0x20>;
106
+
reg-io-width = <0x4>;
107
+
reg-shift = <0x2>;
108
+
native-endian;
109
+
interrupt-parent = <&periph_intc>;
110
+
interrupts = <61>;
111
+
clocks = <&uart_clk>;
112
+
status = "disabled";
113
+
};
114
+
115
+
enet0: ethernet@430000 {
116
+
phy-mode = "internal";
117
+
phy-handle = <&phy1>;
118
+
mac-address = [ 00 10 18 36 23 1a ];
119
+
compatible = "brcm,genet-v2";
120
+
#address-cells = <0x1>;
121
+
#size-cells = <0x1>;
122
+
reg = <0x430000 0x4c8c>;
123
+
interrupts = <24>, <25>;
124
+
interrupt-parent = <&periph_intc>;
125
+
status = "disabled";
126
+
127
+
mdio@e14 {
128
+
compatible = "brcm,genet-mdio-v2";
129
+
#address-cells = <0x1>;
130
+
#size-cells = <0x0>;
131
+
reg = <0xe14 0x8>;
132
+
133
+
phy1: ethernet-phy@1 {
134
+
max-speed = <100>;
135
+
reg = <0x1>;
136
+
compatible = "brcm,40nm-ephy",
137
+
"ethernet-phy-ieee802.3-c22";
138
+
};
139
+
};
140
+
};
141
+
142
+
ehci0: usb@480300 {
143
+
compatible = "brcm,bcm7358-ehci", "generic-ehci";
144
+
reg = <0x480300 0x100>;
145
+
native-endian;
146
+
interrupt-parent = <&periph_intc>;
147
+
interrupts = <65>;
148
+
status = "disabled";
149
+
};
150
+
151
+
ohci0: usb@480400 {
152
+
compatible = "brcm,bcm7358-ohci", "generic-ohci";
153
+
reg = <0x480400 0x100>;
154
+
native-endian;
155
+
no-big-frame-no;
156
+
interrupt-parent = <&periph_intc>;
157
+
interrupts = <66>;
158
+
status = "disabled";
159
+
};
160
+
};
161
+
};
+161
arch/mips/boot/dts/brcm/bcm7360.dtsi
+161
arch/mips/boot/dts/brcm/bcm7360.dtsi
···
1
+
/ {
2
+
#address-cells = <1>;
3
+
#size-cells = <1>;
4
+
compatible = "brcm,bcm7360";
5
+
6
+
cpus {
7
+
#address-cells = <1>;
8
+
#size-cells = <0>;
9
+
10
+
mips-hpt-frequency = <375000000>;
11
+
12
+
cpu@0 {
13
+
compatible = "brcm,bmips3300";
14
+
device_type = "cpu";
15
+
reg = <0>;
16
+
};
17
+
};
18
+
19
+
aliases {
20
+
uart0 = &uart0;
21
+
};
22
+
23
+
cpu_intc: cpu_intc {
24
+
#address-cells = <0>;
25
+
compatible = "mti,cpu-interrupt-controller";
26
+
27
+
interrupt-controller;
28
+
#interrupt-cells = <1>;
29
+
};
30
+
31
+
clocks {
32
+
uart_clk: uart_clk {
33
+
compatible = "fixed-clock";
34
+
#clock-cells = <0>;
35
+
clock-frequency = <81000000>;
36
+
};
37
+
};
38
+
39
+
rdb {
40
+
#address-cells = <1>;
41
+
#size-cells = <1>;
42
+
43
+
compatible = "simple-bus";
44
+
ranges = <0 0x10000000 0x01000000>;
45
+
46
+
periph_intc: periph_intc@411400 {
47
+
compatible = "brcm,bcm7038-l1-intc";
48
+
reg = <0x411400 0x30>;
49
+
50
+
interrupt-controller;
51
+
#interrupt-cells = <1>;
52
+
53
+
interrupt-parent = <&cpu_intc>;
54
+
interrupts = <2>;
55
+
};
56
+
57
+
sun_l2_intc: sun_l2_intc@403000 {
58
+
compatible = "brcm,l2-intc";
59
+
reg = <0x403000 0x30>;
60
+
interrupt-controller;
61
+
#interrupt-cells = <1>;
62
+
interrupt-parent = <&periph_intc>;
63
+
interrupts = <48>;
64
+
};
65
+
66
+
gisb-arb@400000 {
67
+
compatible = "brcm,bcm7400-gisb-arb";
68
+
reg = <0x400000 0xdc>;
69
+
native-endian;
70
+
interrupt-parent = <&sun_l2_intc>;
71
+
interrupts = <0>, <2>;
72
+
brcm,gisb-arb-master-mask = <0x2f3>;
73
+
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
74
+
"rdc_0", "raaga_0",
75
+
"avd_0", "jtag_0";
76
+
};
77
+
78
+
upg_irq0_intc: upg_irq0_intc@406600 {
79
+
compatible = "brcm,bcm7120-l2-intc";
80
+
reg = <0x406600 0x8>;
81
+
82
+
brcm,int-map-mask = <0x44>;
83
+
brcm,int-fwd-mask = <0x70000>;
84
+
85
+
interrupt-controller;
86
+
#interrupt-cells = <1>;
87
+
88
+
interrupt-parent = <&periph_intc>;
89
+
interrupts = <56>;
90
+
};
91
+
92
+
sun_top_ctrl: syscon@404000 {
93
+
compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
94
+
reg = <0x404000 0x51c>;
95
+
little-endian;
96
+
};
97
+
98
+
reboot {
99
+
compatible = "brcm,brcmstb-reboot";
100
+
syscon = <&sun_top_ctrl 0x304 0x308>;
101
+
};
102
+
103
+
uart0: serial@406800 {
104
+
compatible = "ns16550a";
105
+
reg = <0x406800 0x20>;
106
+
reg-io-width = <0x4>;
107
+
reg-shift = <0x2>;
108
+
native-endian;
109
+
interrupt-parent = <&periph_intc>;
110
+
interrupts = <61>;
111
+
clocks = <&uart_clk>;
112
+
status = "disabled";
113
+
};
114
+
115
+
enet0: ethernet@430000 {
116
+
phy-mode = "internal";
117
+
phy-handle = <&phy1>;
118
+
mac-address = [ 00 10 18 36 23 1a ];
119
+
compatible = "brcm,genet-v2";
120
+
#address-cells = <0x1>;
121
+
#size-cells = <0x1>;
122
+
reg = <0x430000 0x4c8c>;
123
+
interrupts = <24>, <25>;
124
+
interrupt-parent = <&periph_intc>;
125
+
status = "disabled";
126
+
127
+
mdio@e14 {
128
+
compatible = "brcm,genet-mdio-v2";
129
+
#address-cells = <0x1>;
130
+
#size-cells = <0x0>;
131
+
reg = <0xe14 0x8>;
132
+
133
+
phy1: ethernet-phy@1 {
134
+
max-speed = <100>;
135
+
reg = <0x1>;
136
+
compatible = "brcm,40nm-ephy",
137
+
"ethernet-phy-ieee802.3-c22";
138
+
};
139
+
};
140
+
};
141
+
142
+
ehci0: usb@480300 {
143
+
compatible = "brcm,bcm7360-ehci", "generic-ehci";
144
+
reg = <0x480300 0x100>;
145
+
native-endian;
146
+
interrupt-parent = <&periph_intc>;
147
+
interrupts = <65>;
148
+
status = "disabled";
149
+
};
150
+
151
+
ohci0: usb@480400 {
152
+
compatible = "brcm,bcm7360-ohci", "generic-ohci";
153
+
reg = <0x480400 0x100>;
154
+
native-endian;
155
+
no-big-frame-no;
156
+
interrupt-parent = <&periph_intc>;
157
+
interrupts = <66>;
158
+
status = "disabled";
159
+
};
160
+
};
161
+
};
+167
arch/mips/boot/dts/brcm/bcm7362.dtsi
+167
arch/mips/boot/dts/brcm/bcm7362.dtsi
···
1
+
/ {
2
+
#address-cells = <1>;
3
+
#size-cells = <1>;
4
+
compatible = "brcm,bcm7362";
5
+
6
+
cpus {
7
+
#address-cells = <1>;
8
+
#size-cells = <0>;
9
+
10
+
mips-hpt-frequency = <375000000>;
11
+
12
+
cpu@0 {
13
+
compatible = "brcm,bmips4380";
14
+
device_type = "cpu";
15
+
reg = <0>;
16
+
};
17
+
18
+
cpu@1 {
19
+
compatible = "brcm,bmips4380";
20
+
device_type = "cpu";
21
+
reg = <1>;
22
+
};
23
+
};
24
+
25
+
aliases {
26
+
uart0 = &uart0;
27
+
};
28
+
29
+
cpu_intc: cpu_intc {
30
+
#address-cells = <0>;
31
+
compatible = "mti,cpu-interrupt-controller";
32
+
33
+
interrupt-controller;
34
+
#interrupt-cells = <1>;
35
+
};
36
+
37
+
clocks {
38
+
uart_clk: uart_clk {
39
+
compatible = "fixed-clock";
40
+
#clock-cells = <0>;
41
+
clock-frequency = <81000000>;
42
+
};
43
+
};
44
+
45
+
rdb {
46
+
#address-cells = <1>;
47
+
#size-cells = <1>;
48
+
49
+
compatible = "simple-bus";
50
+
ranges = <0 0x10000000 0x01000000>;
51
+
52
+
periph_intc: periph_intc@411400 {
53
+
compatible = "brcm,bcm7038-l1-intc";
54
+
reg = <0x411400 0x30>, <0x411600 0x30>;
55
+
56
+
interrupt-controller;
57
+
#interrupt-cells = <1>;
58
+
59
+
interrupt-parent = <&cpu_intc>;
60
+
interrupts = <2>, <3>;
61
+
};
62
+
63
+
sun_l2_intc: sun_l2_intc@403000 {
64
+
compatible = "brcm,l2-intc";
65
+
reg = <0x403000 0x30>;
66
+
interrupt-controller;
67
+
#interrupt-cells = <1>;
68
+
interrupt-parent = <&periph_intc>;
69
+
interrupts = <48>;
70
+
};
71
+
72
+
gisb-arb@400000 {
73
+
compatible = "brcm,bcm7400-gisb-arb";
74
+
reg = <0x400000 0xdc>;
75
+
native-endian;
76
+
interrupt-parent = <&sun_l2_intc>;
77
+
interrupts = <0>, <2>;
78
+
brcm,gisb-arb-master-mask = <0x2f3>;
79
+
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
80
+
"rdc_0", "raaga_0",
81
+
"avd_0", "jtag_0";
82
+
};
83
+
84
+
upg_irq0_intc: upg_irq0_intc@406600 {
85
+
compatible = "brcm,bcm7120-l2-intc";
86
+
reg = <0x406600 0x8>;
87
+
88
+
brcm,int-map-mask = <0x44>;
89
+
brcm,int-fwd-mask = <0x70000>;
90
+
91
+
interrupt-controller;
92
+
#interrupt-cells = <1>;
93
+
94
+
interrupt-parent = <&periph_intc>;
95
+
interrupts = <56>;
96
+
};
97
+
98
+
sun_top_ctrl: syscon@404000 {
99
+
compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
100
+
reg = <0x404000 0x51c>;
101
+
little-endian;
102
+
};
103
+
104
+
reboot {
105
+
compatible = "brcm,brcmstb-reboot";
106
+
syscon = <&sun_top_ctrl 0x304 0x308>;
107
+
};
108
+
109
+
uart0: serial@406800 {
110
+
compatible = "ns16550a";
111
+
reg = <0x406800 0x20>;
112
+
reg-io-width = <0x4>;
113
+
reg-shift = <0x2>;
114
+
native-endian;
115
+
interrupt-parent = <&periph_intc>;
116
+
interrupts = <61>;
117
+
clocks = <&uart_clk>;
118
+
status = "disabled";
119
+
};
120
+
121
+
enet0: ethernet@430000 {
122
+
phy-mode = "internal";
123
+
phy-handle = <&phy1>;
124
+
mac-address = [ 00 10 18 36 23 1a ];
125
+
compatible = "brcm,genet-v2";
126
+
#address-cells = <0x1>;
127
+
#size-cells = <0x1>;
128
+
reg = <0x430000 0x4c8c>;
129
+
interrupts = <24>, <25>;
130
+
interrupt-parent = <&periph_intc>;
131
+
status = "disabled";
132
+
133
+
mdio@e14 {
134
+
compatible = "brcm,genet-mdio-v2";
135
+
#address-cells = <0x1>;
136
+
#size-cells = <0x0>;
137
+
reg = <0xe14 0x8>;
138
+
139
+
phy1: ethernet-phy@1 {
140
+
max-speed = <100>;
141
+
reg = <0x1>;
142
+
compatible = "brcm,40nm-ephy",
143
+
"ethernet-phy-ieee802.3-c22";
144
+
};
145
+
};
146
+
};
147
+
148
+
ehci0: usb@480300 {
149
+
compatible = "brcm,bcm7362-ehci", "generic-ehci";
150
+
reg = <0x480300 0x100>;
151
+
native-endian;
152
+
interrupt-parent = <&periph_intc>;
153
+
interrupts = <65>;
154
+
status = "disabled";
155
+
};
156
+
157
+
ohci0: usb@480400 {
158
+
compatible = "brcm,bcm7362-ohci", "generic-ohci";
159
+
reg = <0x480400 0x100>;
160
+
native-endian;
161
+
no-big-frame-no;
162
+
interrupt-parent = <&periph_intc>;
163
+
interrupts = <66>;
164
+
status = "disabled";
165
+
};
166
+
};
167
+
};
+184
arch/mips/boot/dts/brcm/bcm7420.dtsi
+184
arch/mips/boot/dts/brcm/bcm7420.dtsi
···
1
+
/ {
2
+
#address-cells = <1>;
3
+
#size-cells = <1>;
4
+
compatible = "brcm,bcm7420";
5
+
6
+
cpus {
7
+
#address-cells = <1>;
8
+
#size-cells = <0>;
9
+
10
+
mips-hpt-frequency = <93750000>;
11
+
12
+
cpu@0 {
13
+
compatible = "brcm,bmips5000";
14
+
device_type = "cpu";
15
+
reg = <0>;
16
+
};
17
+
18
+
cpu@1 {
19
+
compatible = "brcm,bmips5000";
20
+
device_type = "cpu";
21
+
reg = <1>;
22
+
};
23
+
};
24
+
25
+
aliases {
26
+
uart0 = &uart0;
27
+
};
28
+
29
+
cpu_intc: cpu_intc {
30
+
#address-cells = <0>;
31
+
compatible = "mti,cpu-interrupt-controller";
32
+
33
+
interrupt-controller;
34
+
#interrupt-cells = <1>;
35
+
};
36
+
37
+
clocks {
38
+
uart_clk: uart_clk {
39
+
compatible = "fixed-clock";
40
+
#clock-cells = <0>;
41
+
clock-frequency = <81000000>;
42
+
};
43
+
};
44
+
45
+
rdb {
46
+
#address-cells = <1>;
47
+
#size-cells = <1>;
48
+
49
+
compatible = "simple-bus";
50
+
ranges = <0 0x10000000 0x01000000>;
51
+
52
+
periph_intc: periph_intc@441400 {
53
+
compatible = "brcm,bcm7038-l1-intc";
54
+
reg = <0x441400 0x30>, <0x441600 0x30>;
55
+
56
+
interrupt-controller;
57
+
#interrupt-cells = <1>;
58
+
59
+
interrupt-parent = <&cpu_intc>;
60
+
interrupts = <2>, <3>;
61
+
};
62
+
63
+
sun_l2_intc: sun_l2_intc@401800 {
64
+
compatible = "brcm,l2-intc";
65
+
reg = <0x401800 0x30>;
66
+
interrupt-controller;
67
+
#interrupt-cells = <1>;
68
+
interrupt-parent = <&periph_intc>;
69
+
interrupts = <23>;
70
+
};
71
+
72
+
gisb-arb@400000 {
73
+
compatible = "brcm,bcm7400-gisb-arb";
74
+
reg = <0x400000 0xdc>;
75
+
native-endian;
76
+
interrupt-parent = <&sun_l2_intc>;
77
+
interrupts = <0>, <2>;
78
+
brcm,gisb-arb-master-mask = <0x3ff>;
79
+
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
80
+
"pcie_0", "bsp_0", "rdc_0",
81
+
"rptd_0", "avd_0", "avd_1",
82
+
"jtag_0";
83
+
};
84
+
85
+
upg_irq0_intc: upg_irq0_intc@406780 {
86
+
compatible = "brcm,bcm7120-l2-intc";
87
+
reg = <0x406780 0x8>;
88
+
89
+
brcm,int-map-mask = <0x44>;
90
+
brcm,int-fwd-mask = <0x70000>;
91
+
92
+
interrupt-controller;
93
+
#interrupt-cells = <1>;
94
+
95
+
interrupt-parent = <&periph_intc>;
96
+
interrupts = <18>;
97
+
};
98
+
99
+
sun_top_ctrl: syscon@404000 {
100
+
compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
101
+
reg = <0x404000 0x60c>;
102
+
little-endian;
103
+
};
104
+
105
+
reboot {
106
+
compatible = "brcm,bcm7038-reboot";
107
+
syscon = <&sun_top_ctrl 0x8 0x14>;
108
+
};
109
+
110
+
uart0: serial@406b00 {
111
+
compatible = "ns16550a";
112
+
reg = <0x406b00 0x20>;
113
+
reg-io-width = <0x4>;
114
+
reg-shift = <0x2>;
115
+
interrupt-parent = <&periph_intc>;
116
+
interrupts = <21>;
117
+
clocks = <&uart_clk>;
118
+
status = "disabled";
119
+
};
120
+
121
+
enet0: ethernet@468000 {
122
+
phy-mode = "internal";
123
+
phy-handle = <&phy1>;
124
+
mac-address = [ 00 10 18 36 23 1a ];
125
+
compatible = "brcm,genet-v1";
126
+
#address-cells = <0x1>;
127
+
#size-cells = <0x1>;
128
+
reg = <0x468000 0x3c8c>;
129
+
interrupts = <69>, <79>;
130
+
interrupt-parent = <&periph_intc>;
131
+
status = "disabled";
132
+
133
+
mdio@e14 {
134
+
compatible = "brcm,genet-mdio-v1";
135
+
#address-cells = <0x1>;
136
+
#size-cells = <0x0>;
137
+
reg = <0xe14 0x8>;
138
+
139
+
phy1: ethernet-phy@1 {
140
+
max-speed = <100>;
141
+
reg = <0x1>;
142
+
compatible = "brcm,65nm-ephy",
143
+
"ethernet-phy-ieee802.3-c22";
144
+
};
145
+
};
146
+
};
147
+
148
+
ehci0: usb@488300 {
149
+
compatible = "brcm,bcm7420-ehci", "generic-ehci";
150
+
reg = <0x488300 0x100>;
151
+
interrupt-parent = <&periph_intc>;
152
+
interrupts = <60>;
153
+
status = "disabled";
154
+
};
155
+
156
+
ohci0: usb@488400 {
157
+
compatible = "brcm,bcm7420-ohci", "generic-ohci";
158
+
reg = <0x488400 0x100>;
159
+
native-endian;
160
+
no-big-frame-no;
161
+
interrupt-parent = <&periph_intc>;
162
+
interrupts = <61>;
163
+
status = "disabled";
164
+
};
165
+
166
+
ehci1: usb@488500 {
167
+
compatible = "brcm,bcm7420-ehci", "generic-ehci";
168
+
reg = <0x488500 0x100>;
169
+
interrupt-parent = <&periph_intc>;
170
+
interrupts = <55>;
171
+
status = "disabled";
172
+
};
173
+
174
+
ohci1: usb@488600 {
175
+
compatible = "brcm,bcm7420-ohci", "generic-ohci";
176
+
reg = <0x488600 0x100>;
177
+
native-endian;
178
+
no-big-frame-no;
179
+
interrupt-parent = <&periph_intc>;
180
+
interrupts = <62>;
181
+
status = "disabled";
182
+
};
183
+
};
184
+
};
+225
arch/mips/boot/dts/brcm/bcm7425.dtsi
+225
arch/mips/boot/dts/brcm/bcm7425.dtsi
···
1
+
/ {
2
+
#address-cells = <1>;
3
+
#size-cells = <1>;
4
+
compatible = "brcm,bcm7425";
5
+
6
+
cpus {
7
+
#address-cells = <1>;
8
+
#size-cells = <0>;
9
+
10
+
mips-hpt-frequency = <163125000>;
11
+
12
+
cpu@0 {
13
+
compatible = "brcm,bmips5000";
14
+
device_type = "cpu";
15
+
reg = <0>;
16
+
};
17
+
18
+
cpu@1 {
19
+
compatible = "brcm,bmips5000";
20
+
device_type = "cpu";
21
+
reg = <1>;
22
+
};
23
+
};
24
+
25
+
aliases {
26
+
uart0 = &uart0;
27
+
};
28
+
29
+
cpu_intc: cpu_intc {
30
+
#address-cells = <0>;
31
+
compatible = "mti,cpu-interrupt-controller";
32
+
33
+
interrupt-controller;
34
+
#interrupt-cells = <1>;
35
+
};
36
+
37
+
clocks {
38
+
uart_clk: uart_clk {
39
+
compatible = "fixed-clock";
40
+
#clock-cells = <0>;
41
+
clock-frequency = <81000000>;
42
+
};
43
+
};
44
+
45
+
rdb {
46
+
#address-cells = <1>;
47
+
#size-cells = <1>;
48
+
49
+
compatible = "simple-bus";
50
+
ranges = <0 0x10000000 0x01000000>;
51
+
52
+
periph_intc: periph_intc@41a400 {
53
+
compatible = "brcm,bcm7038-l1-intc";
54
+
reg = <0x41a400 0x30>, <0x41a600 0x30>;
55
+
56
+
interrupt-controller;
57
+
#interrupt-cells = <1>;
58
+
59
+
interrupt-parent = <&cpu_intc>;
60
+
interrupts = <2>, <3>;
61
+
};
62
+
63
+
sun_l2_intc: sun_l2_intc@403000 {
64
+
compatible = "brcm,l2-intc";
65
+
reg = <0x403000 0x30>;
66
+
interrupt-controller;
67
+
#interrupt-cells = <1>;
68
+
interrupt-parent = <&periph_intc>;
69
+
interrupts = <47>;
70
+
};
71
+
72
+
gisb-arb@400000 {
73
+
compatible = "brcm,bcm7400-gisb-arb";
74
+
reg = <0x400000 0xdc>;
75
+
native-endian;
76
+
interrupt-parent = <&sun_l2_intc>;
77
+
interrupts = <0>, <2>;
78
+
brcm,gisb-arb-master-mask = <0x177b>;
79
+
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
80
+
"bsp_0", "rdc_0",
81
+
"raaga_0", "avd_1",
82
+
"jtag_0", "svd_0",
83
+
"vice_0";
84
+
};
85
+
86
+
upg_irq0_intc: upg_irq0_intc@406780 {
87
+
compatible = "brcm,bcm7120-l2-intc";
88
+
reg = <0x406780 0x8>;
89
+
90
+
brcm,int-map-mask = <0x44>;
91
+
brcm,int-fwd-mask = <0x70000>;
92
+
93
+
interrupt-controller;
94
+
#interrupt-cells = <1>;
95
+
96
+
interrupt-parent = <&periph_intc>;
97
+
interrupts = <55>;
98
+
};
99
+
100
+
sun_top_ctrl: syscon@404000 {
101
+
compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
102
+
reg = <0x404000 0x51c>;
103
+
little-endian;
104
+
};
105
+
106
+
reboot {
107
+
compatible = "brcm,brcmstb-reboot";
108
+
syscon = <&sun_top_ctrl 0x304 0x308>;
109
+
};
110
+
111
+
uart0: serial@406b00 {
112
+
compatible = "ns16550a";
113
+
reg = <0x406b00 0x20>;
114
+
reg-io-width = <0x4>;
115
+
reg-shift = <0x2>;
116
+
interrupt-parent = <&periph_intc>;
117
+
interrupts = <61>;
118
+
clocks = <&uart_clk>;
119
+
status = "disabled";
120
+
};
121
+
122
+
enet0: ethernet@b80000 {
123
+
phy-mode = "internal";
124
+
phy-handle = <&phy1>;
125
+
mac-address = [ 00 10 18 36 23 1a ];
126
+
compatible = "brcm,genet-v3";
127
+
#address-cells = <0x1>;
128
+
#size-cells = <0x1>;
129
+
reg = <0xb80000 0x11c88>;
130
+
interrupts = <17>, <18>;
131
+
interrupt-parent = <&periph_intc>;
132
+
status = "disabled";
133
+
134
+
mdio@e14 {
135
+
compatible = "brcm,genet-mdio-v3";
136
+
#address-cells = <0x1>;
137
+
#size-cells = <0x0>;
138
+
reg = <0xe14 0x8>;
139
+
140
+
phy1: ethernet-phy@1 {
141
+
max-speed = <100>;
142
+
reg = <0x1>;
143
+
compatible = "brcm,40nm-ephy",
144
+
"ethernet-phy-ieee802.3-c22";
145
+
};
146
+
};
147
+
};
148
+
149
+
ehci0: usb@480300 {
150
+
compatible = "brcm,bcm7425-ehci", "generic-ehci";
151
+
reg = <0x480300 0x100>;
152
+
native-endian;
153
+
interrupt-parent = <&periph_intc>;
154
+
interrupts = <65>;
155
+
status = "disabled";
156
+
};
157
+
158
+
ohci0: usb@480400 {
159
+
compatible = "brcm,bcm7425-ohci", "generic-ohci";
160
+
reg = <0x480400 0x100>;
161
+
native-endian;
162
+
no-big-frame-no;
163
+
interrupt-parent = <&periph_intc>;
164
+
interrupts = <67>;
165
+
status = "disabled";
166
+
};
167
+
168
+
ehci1: usb@480500 {
169
+
compatible = "brcm,bcm7425-ehci", "generic-ehci";
170
+
reg = <0x480500 0x100>;
171
+
native-endian;
172
+
interrupt-parent = <&periph_intc>;
173
+
interrupts = <66>;
174
+
status = "disabled";
175
+
};
176
+
177
+
ohci1: usb@480600 {
178
+
compatible = "brcm,bcm7425-ohci", "generic-ohci";
179
+
reg = <0x480600 0x100>;
180
+
native-endian;
181
+
no-big-frame-no;
182
+
interrupt-parent = <&periph_intc>;
183
+
interrupts = <68>;
184
+
status = "disabled";
185
+
};
186
+
187
+
ehci2: usb@490300 {
188
+
compatible = "brcm,bcm7425-ehci", "generic-ehci";
189
+
reg = <0x490300 0x100>;
190
+
native-endian;
191
+
interrupt-parent = <&periph_intc>;
192
+
interrupts = <70>;
193
+
status = "disabled";
194
+
};
195
+
196
+
ohci2: usb@490400 {
197
+
compatible = "brcm,bcm7425-ohci", "generic-ohci";
198
+
reg = <0x490400 0x100>;
199
+
native-endian;
200
+
no-big-frame-no;
201
+
interrupt-parent = <&periph_intc>;
202
+
interrupts = <72>;
203
+
status = "disabled";
204
+
};
205
+
206
+
ehci3: usb@490500 {
207
+
compatible = "brcm,bcm7425-ehci", "generic-ehci";
208
+
reg = <0x490500 0x100>;
209
+
native-endian;
210
+
interrupt-parent = <&periph_intc>;
211
+
interrupts = <71>;
212
+
status = "disabled";
213
+
};
214
+
215
+
ohci3: usb@490600 {
216
+
compatible = "brcm,bcm7425-ohci", "generic-ohci";
217
+
reg = <0x490600 0x100>;
218
+
native-endian;
219
+
no-big-frame-no;
220
+
interrupt-parent = <&periph_intc>;
221
+
interrupts = <73>;
222
+
status = "disabled";
223
+
};
224
+
};
225
+
};
+25
arch/mips/boot/dts/brcm/bcm93384wvg_viper.dts
+25
arch/mips/boot/dts/brcm/bcm93384wvg_viper.dts
···
1
+
/dts-v1/;
2
+
3
+
/include/ "bcm3384_viper.dtsi"
4
+
5
+
/ {
6
+
compatible = "brcm,bcm93384wvg-viper", "brcm,bcm3384-viper";
7
+
model = "Broadcom BCM93384WVG-viper";
8
+
9
+
chosen {
10
+
bootargs = "console=ttyS0,115200";
11
+
stdout-path = &uart0;
12
+
};
13
+
};
14
+
15
+
&uart0 {
16
+
status = "okay";
17
+
};
18
+
19
+
&ehci0 {
20
+
status = "okay";
21
+
};
22
+
23
+
&ohci0 {
24
+
status = "okay";
25
+
};
+31
arch/mips/boot/dts/brcm/bcm96368mvwg.dts
+31
arch/mips/boot/dts/brcm/bcm96368mvwg.dts
···
1
+
/dts-v1/;
2
+
3
+
/include/ "bcm6368.dtsi"
4
+
5
+
/ {
6
+
compatible = "brcm,bcm96368mvwg", "brcm,bcm6368";
7
+
model = "Broadcom BCM96368MVWG";
8
+
9
+
memory@0 {
10
+
device_type = "memory";
11
+
reg = <0x00000000 0x04000000>;
12
+
};
13
+
14
+
chosen {
15
+
bootargs = "console=ttyS0,115200";
16
+
stdout-path = &uart0;
17
+
};
18
+
};
19
+
20
+
&uart0 {
21
+
status = "okay";
22
+
};
23
+
24
+
/* FIXME: need to set up USB_CTRL registers first */
25
+
&ehci0 {
26
+
status = "disabled";
27
+
};
28
+
29
+
&ohci0 {
30
+
status = "disabled";
31
+
};
+31
arch/mips/boot/dts/brcm/bcm97125cbmb.dts
+31
arch/mips/boot/dts/brcm/bcm97125cbmb.dts
···
1
+
/dts-v1/;
2
+
3
+
/include/ "bcm7125.dtsi"
4
+
5
+
/ {
6
+
compatible = "brcm,bcm97125cbmb", "brcm,bcm7125";
7
+
model = "Broadcom BCM97125CBMB";
8
+
9
+
memory@0 {
10
+
device_type = "memory";
11
+
reg = <0x00000000 0x10000000>;
12
+
};
13
+
14
+
chosen {
15
+
bootargs = "console=ttyS0,115200";
16
+
stdout-path = &uart0;
17
+
};
18
+
};
19
+
20
+
&uart0 {
21
+
status = "okay";
22
+
};
23
+
24
+
/* FIXME: USB is wonky; disable it for now */
25
+
&ehci0 {
26
+
status = "disabled";
27
+
};
28
+
29
+
&ohci0 {
30
+
status = "disabled";
31
+
};
+58
arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
+58
arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
···
1
+
/dts-v1/;
2
+
3
+
/include/ "bcm7346.dtsi"
4
+
5
+
/ {
6
+
compatible = "brcm,bcm97346dbsmb", "brcm,bcm7346";
7
+
model = "Broadcom BCM97346DBSMB";
8
+
9
+
memory@0 {
10
+
device_type = "memory";
11
+
reg = <0x00000000 0x10000000>, <0x20000000 0x30000000>;
12
+
};
13
+
14
+
chosen {
15
+
bootargs = "console=ttyS0,115200";
16
+
stdout-path = &uart0;
17
+
};
18
+
};
19
+
20
+
&uart0 {
21
+
status = "okay";
22
+
};
23
+
24
+
&enet0 {
25
+
status = "okay";
26
+
};
27
+
28
+
&ehci0 {
29
+
status = "okay";
30
+
};
31
+
32
+
&ohci0 {
33
+
status = "okay";
34
+
};
35
+
36
+
&ehci1 {
37
+
status = "okay";
38
+
};
39
+
40
+
&ohci1 {
41
+
status = "okay";
42
+
};
43
+
44
+
&ehci2 {
45
+
status = "okay";
46
+
};
47
+
48
+
&ohci2 {
49
+
status = "okay";
50
+
};
51
+
52
+
&ehci3 {
53
+
status = "okay";
54
+
};
55
+
56
+
&ohci3 {
57
+
status = "okay";
58
+
};
+34
arch/mips/boot/dts/brcm/bcm97358svmb.dts
+34
arch/mips/boot/dts/brcm/bcm97358svmb.dts
···
1
+
/dts-v1/;
2
+
3
+
/include/ "bcm7358.dtsi"
4
+
5
+
/ {
6
+
compatible = "brcm,bcm97358svmb", "brcm,bcm7358";
7
+
model = "Broadcom BCM97358SVMB";
8
+
9
+
memory@0 {
10
+
device_type = "memory";
11
+
reg = <0x00000000 0x10000000>;
12
+
};
13
+
14
+
chosen {
15
+
bootargs = "console=ttyS0,115200";
16
+
stdout-path = &uart0;
17
+
};
18
+
};
19
+
20
+
&uart0 {
21
+
status = "okay";
22
+
};
23
+
24
+
&enet0 {
25
+
status = "okay";
26
+
};
27
+
28
+
&ehci0 {
29
+
status = "okay";
30
+
};
31
+
32
+
&ohci0 {
33
+
status = "okay";
34
+
};
+34
arch/mips/boot/dts/brcm/bcm97360svmb.dts
+34
arch/mips/boot/dts/brcm/bcm97360svmb.dts
···
1
+
/dts-v1/;
2
+
3
+
/include/ "bcm7360.dtsi"
4
+
5
+
/ {
6
+
compatible = "brcm,bcm97360svmb", "brcm,bcm7360";
7
+
model = "Broadcom BCM97360SVMB";
8
+
9
+
memory@0 {
10
+
device_type = "memory";
11
+
reg = <0x00000000 0x10000000>;
12
+
};
13
+
14
+
chosen {
15
+
bootargs = "console=ttyS0,115200";
16
+
stdout-path = &uart0;
17
+
};
18
+
};
19
+
20
+
&uart0 {
21
+
status = "okay";
22
+
};
23
+
24
+
&enet0 {
25
+
status = "okay";
26
+
};
27
+
28
+
&ehci0 {
29
+
status = "okay";
30
+
};
31
+
32
+
&ohci0 {
33
+
status = "okay";
34
+
};
+34
arch/mips/boot/dts/brcm/bcm97362svmb.dts
+34
arch/mips/boot/dts/brcm/bcm97362svmb.dts
···
1
+
/dts-v1/;
2
+
3
+
/include/ "bcm7362.dtsi"
4
+
5
+
/ {
6
+
compatible = "brcm,bcm97362svmb", "brcm,bcm7362";
7
+
model = "Broadcom BCM97362SVMB";
8
+
9
+
memory@0 {
10
+
device_type = "memory";
11
+
reg = <0x00000000 0x10000000>, <0x20000000 0x30000000>;
12
+
};
13
+
14
+
chosen {
15
+
bootargs = "console=ttyS0,115200";
16
+
stdout-path = &uart0;
17
+
};
18
+
};
19
+
20
+
&uart0 {
21
+
status = "okay";
22
+
};
23
+
24
+
&enet0 {
25
+
status = "okay";
26
+
};
27
+
28
+
&ehci0 {
29
+
status = "okay";
30
+
};
31
+
32
+
&ohci0 {
33
+
status = "okay";
34
+
};
+45
arch/mips/boot/dts/brcm/bcm97420c.dts
+45
arch/mips/boot/dts/brcm/bcm97420c.dts
···
1
+
/dts-v1/;
2
+
3
+
/include/ "bcm7420.dtsi"
4
+
5
+
/ {
6
+
compatible = "brcm,bcm97420c", "brcm,bcm7420";
7
+
model = "Broadcom BCM97420C";
8
+
9
+
memory@0 {
10
+
device_type = "memory";
11
+
reg = <0x00000000 0x10000000>,
12
+
<0x20000000 0x30000000>,
13
+
<0x60000000 0x10000000>;
14
+
};
15
+
16
+
chosen {
17
+
bootargs = "console=ttyS0,115200";
18
+
stdout-path = &uart0;
19
+
};
20
+
};
21
+
22
+
&uart0 {
23
+
status = "okay";
24
+
};
25
+
26
+
/* FIXME: MAC driver comes up but cannot attach to PHY */
27
+
&enet0 {
28
+
status = "disabled";
29
+
};
30
+
31
+
&ehci0 {
32
+
status = "okay";
33
+
};
34
+
35
+
&ohci0 {
36
+
status = "okay";
37
+
};
38
+
39
+
&ehci1 {
40
+
status = "okay";
41
+
};
42
+
43
+
&ohci1 {
44
+
status = "okay";
45
+
};
+60
arch/mips/boot/dts/brcm/bcm97425svmb.dts
+60
arch/mips/boot/dts/brcm/bcm97425svmb.dts
···
1
+
/dts-v1/;
2
+
3
+
/include/ "bcm7425.dtsi"
4
+
5
+
/ {
6
+
compatible = "brcm,bcm97425svmb", "brcm,bcm7425";
7
+
model = "Broadcom BCM97425SVMB";
8
+
9
+
memory@0 {
10
+
device_type = "memory";
11
+
reg = <0x00000000 0x10000000>,
12
+
<0x20000000 0x30000000>,
13
+
<0x90000000 0x40000000>;
14
+
};
15
+
16
+
chosen {
17
+
bootargs = "console=ttyS0,115200";
18
+
stdout-path = &uart0;
19
+
};
20
+
};
21
+
22
+
&uart0 {
23
+
status = "okay";
24
+
};
25
+
26
+
&enet0 {
27
+
status = "okay";
28
+
};
29
+
30
+
&ehci0 {
31
+
status = "okay";
32
+
};
33
+
34
+
&ohci0 {
35
+
status = "okay";
36
+
};
37
+
38
+
&ehci1 {
39
+
status = "okay";
40
+
};
41
+
42
+
&ohci1 {
43
+
status = "okay";
44
+
};
45
+
46
+
&ehci2 {
47
+
status = "okay";
48
+
};
49
+
50
+
&ohci2 {
51
+
status = "okay";
52
+
};
53
+
54
+
&ehci3 {
55
+
status = "okay";
56
+
};
57
+
58
+
&ohci3 {
59
+
status = "okay";
60
+
};
+22
arch/mips/boot/dts/brcm/bcm9ejtagprb.dts
+22
arch/mips/boot/dts/brcm/bcm9ejtagprb.dts
···
1
+
/dts-v1/;
2
+
3
+
/include/ "bcm6328.dtsi"
4
+
5
+
/ {
6
+
compatible = "brcm,bcm9ejtagprb", "brcm,bcm6328";
7
+
model = "Broadcom BCM9EJTAGPRB";
8
+
9
+
memory@0 {
10
+
device_type = "memory";
11
+
reg = <0x00000000 0x08000000>;
12
+
};
13
+
14
+
chosen {
15
+
bootargs = "console=ttyS0,115200";
16
+
stdout-path = &uart0;
17
+
};
18
+
};
19
+
20
+
&uart0 {
21
+
status = "okay";
22
+
};