tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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m68knommu: fix problems with SPI/GPIO on ColdFire 520x

The problem has its root in the calculation of the set-port offsets (macro
MCFGPIO_SETR() in arch/m68k/include/asm/gpio.h), this assumes that all ports
have the same offset from the base port address (MCFGPIO_SETR) which is
defined in mcf520xsim.h as an alias of MCFGIO_PSETR_BUSCTL. Because the BUSCTL
and BE port do not have a set-register (see MCF5208 Reference Manual Page
13-10, Table 13-3) the offset calculations went wrong.

Because the BE and BUSCTL port do not seem useful in these parts, as they
lack a set register, I removed them and adapted the gpio chip bases which
are also used for the offset-calculations. Now both setting and resetting
the chip selects works as expected from userland and from the kernelspace.

Signed-off-by: Peter Turczak <peter@turczak.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>

authored by

Peter Turczak and committed by
Greg Ungerer 89127ed3 f230e80b

+27 -63
+12 -14
arch/m68k/include/asm/m520xsim.h
··· 90 90 #define MCFGPIO_PDDR_FECH 0xFC0A4013 91 91 #define MCFGPIO_PDDR_FECL 0xFC0A4014 92 92 93 - #define MCFGPIO_PPDSDR_BUSCTL 0xFC0A401A 94 - #define MCFGPIO_PPDSDR_BE 0xFC0A401B 95 - #define MCFGPIO_PPDSDR_CS 0xFC0A401C 96 - #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401D 97 - #define MCFGPIO_PPDSDR_QSPI 0xFC0A401E 98 - #define MCFGPIO_PPDSDR_TIMER 0xFC0A401F 99 - #define MCFGPIO_PPDSDR_UART 0xFC0A4021 100 - #define MCFGPIO_PPDSDR_FECH 0xFC0A4021 101 - #define MCFGPIO_PPDSDR_FECL 0xFC0A4022 93 + #define MCFGPIO_PPDSDR_CS 0xFC0A401A 94 + #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B 95 + #define MCFGPIO_PPDSDR_QSPI 0xFC0A401C 96 + #define MCFGPIO_PPDSDR_TIMER 0xFC0A401D 97 + #define MCFGPIO_PPDSDR_UART 0xFC0A401E 98 + #define MCFGPIO_PPDSDR_FECH 0xFC0A401F 99 + #define MCFGPIO_PPDSDR_FECL 0xFC0A4020 102 100 103 101 #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 104 102 #define MCFGPIO_PCLRR_BE 0xFC0A4025 ··· 111 113 /* 112 114 * Generic GPIO support 113 115 */ 114 - #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 115 - #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 116 - #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 117 - #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 118 - #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 116 + #define MCFGPIO_PODR MCFGPIO_PODR_CS 117 + #define MCFGPIO_PDDR MCFGPIO_PDDR_CS 118 + #define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS 119 + #define MCFGPIO_SETR MCFGPIO_PPDSDR_CS 120 + #define MCFGPIO_CLRR MCFGPIO_PCLRR_CS 119 121 120 122 #define MCFGPIO_PIN_MAX 80 121 123 #define MCFGPIO_IRQ_MAX 8
+5 -3
arch/m68k/include/asm/mcfqspi.h
··· 24 24 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) 25 25 #define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) 26 26 #elif defined(CONFIG_M5249) 27 - #define MCFQSPI_IOBASE (MCF_MBAR + 0x300) 28 - #elif defined(CONFIG_M520x) || defined(CONFIG_M532x) 29 - #define MCFQSPI_IOBASE 0xFC058000 27 + #define MCFQSPI_IOBASE (MCF_MBAR + 0x300) 28 + #elif defined(CONFIG_M520x) 29 + #define MCFQSPI_IOBASE 0xFC05C000 30 + #elif defined(CONFIG_M532x) 31 + #define MCFQSPI_IOBASE 0xFC058000 30 32 #endif 31 33 #define MCFQSPI_IOSIZE 0x40 32 34
+3 -3
arch/m68k/platform/520x/config.c
··· 91 91 }, 92 92 }; 93 93 94 - #define MCFQSPI_CS0 62 95 - #define MCFQSPI_CS1 63 96 - #define MCFQSPI_CS2 44 94 + #define MCFQSPI_CS0 46 95 + #define MCFQSPI_CS1 47 96 + #define MCFQSPI_CS2 27 97 97 98 98 static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control) 99 99 {
+7 -43
arch/m68k/platform/520x/gpio.c
··· 38 38 }, 39 39 { 40 40 .gpio_chip = { 41 - .label = "BUSCTL", 42 - .request = mcf_gpio_request, 43 - .free = mcf_gpio_free, 44 - .direction_input = mcf_gpio_direction_input, 45 - .direction_output = mcf_gpio_direction_output, 46 - .get = mcf_gpio_get_value, 47 - .set = mcf_gpio_set_value_fast, 48 - .base = 8, 49 - .ngpio = 4, 50 - }, 51 - .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, 52 - .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, 53 - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, 54 - .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, 55 - .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, 56 - }, 57 - { 58 - .gpio_chip = { 59 - .label = "BE", 60 - .request = mcf_gpio_request, 61 - .free = mcf_gpio_free, 62 - .direction_input = mcf_gpio_direction_input, 63 - .direction_output = mcf_gpio_direction_output, 64 - .get = mcf_gpio_get_value, 65 - .set = mcf_gpio_set_value_fast, 66 - .base = 16, 67 - .ngpio = 4, 68 - }, 69 - .pddr = (void __iomem *) MCFGPIO_PDDR_BE, 70 - .podr = (void __iomem *) MCFGPIO_PODR_BE, 71 - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE, 72 - .setr = (void __iomem *) MCFGPIO_PPDSDR_BE, 73 - .clrr = (void __iomem *) MCFGPIO_PCLRR_BE, 74 - }, 75 - { 76 - .gpio_chip = { 77 41 .label = "CS", 78 42 .request = mcf_gpio_request, 79 43 .free = mcf_gpio_free, ··· 45 81 .direction_output = mcf_gpio_direction_output, 46 82 .get = mcf_gpio_get_value, 47 83 .set = mcf_gpio_set_value_fast, 48 - .base = 25, 84 + .base = 9, 49 85 .ngpio = 3, 50 86 }, 51 87 .pddr = (void __iomem *) MCFGPIO_PDDR_CS, ··· 63 99 .direction_output = mcf_gpio_direction_output, 64 100 .get = mcf_gpio_get_value, 65 101 .set = mcf_gpio_set_value_fast, 66 - .base = 32, 102 + .base = 16, 67 103 .ngpio = 4, 68 104 }, 69 105 .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, ··· 81 117 .direction_output = mcf_gpio_direction_output, 82 118 .get = mcf_gpio_get_value, 83 119 .set = mcf_gpio_set_value_fast, 84 - .base = 40, 120 + .base = 24, 85 121 .ngpio = 4, 86 122 }, 87 123 .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, ··· 99 135 .direction_output = mcf_gpio_direction_output, 100 136 .get = mcf_gpio_get_value, 101 137 .set = mcf_gpio_set_value_fast, 102 - .base = 48, 138 + .base = 32, 103 139 .ngpio = 4, 104 140 }, 105 141 .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, ··· 117 153 .direction_output = mcf_gpio_direction_output, 118 154 .get = mcf_gpio_get_value, 119 155 .set = mcf_gpio_set_value_fast, 120 - .base = 56, 156 + .base = 40, 121 157 .ngpio = 8, 122 158 }, 123 159 .pddr = (void __iomem *) MCFGPIO_PDDR_UART, ··· 135 171 .direction_output = mcf_gpio_direction_output, 136 172 .get = mcf_gpio_get_value, 137 173 .set = mcf_gpio_set_value_fast, 138 - .base = 64, 174 + .base = 48, 139 175 .ngpio = 8, 140 176 }, 141 177 .pddr = (void __iomem *) MCFGPIO_PDDR_FECH, ··· 153 189 .direction_output = mcf_gpio_direction_output, 154 190 .get = mcf_gpio_get_value, 155 191 .set = mcf_gpio_set_value_fast, 156 - .base = 72, 192 + .base = 56, 157 193 .ngpio = 8, 158 194 }, 159 195 .pddr = (void __iomem *) MCFGPIO_PDDR_FECL,