Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 3711/1: AT91 timer update
[ARM] 3709/1: pnx4008: convert to generic irq subsystem
[ARM] 3710/1: AT91 Serial: Use GPIO API
+45
arch/arm/mach-at91rm9200/at91rm9200.c
+45
arch/arm/mach-at91rm9200/at91rm9200.c
···
107
107
iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
108
108
}
109
109
110
+
/*
111
+
* The default interrupt priority levels (0 = lowest, 7 = highest).
112
+
*/
113
+
static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
114
+
7, /* Advanced Interrupt Controller (FIQ) */
115
+
7, /* System Peripherals */
116
+
0, /* Parallel IO Controller A */
117
+
0, /* Parallel IO Controller B */
118
+
0, /* Parallel IO Controller C */
119
+
0, /* Parallel IO Controller D */
120
+
6, /* USART 0 */
121
+
6, /* USART 1 */
122
+
6, /* USART 2 */
123
+
6, /* USART 3 */
124
+
0, /* Multimedia Card Interface */
125
+
4, /* USB Device Port */
126
+
0, /* Two-Wire Interface */
127
+
6, /* Serial Peripheral Interface */
128
+
5, /* Serial Synchronous Controller 0 */
129
+
5, /* Serial Synchronous Controller 1 */
130
+
5, /* Serial Synchronous Controller 2 */
131
+
0, /* Timer Counter 0 */
132
+
0, /* Timer Counter 1 */
133
+
0, /* Timer Counter 2 */
134
+
0, /* Timer Counter 3 */
135
+
0, /* Timer Counter 4 */
136
+
0, /* Timer Counter 5 */
137
+
3, /* USB Host port */
138
+
3, /* Ethernet MAC */
139
+
0, /* Advanced Interrupt Controller (IRQ0) */
140
+
0, /* Advanced Interrupt Controller (IRQ1) */
141
+
0, /* Advanced Interrupt Controller (IRQ2) */
142
+
0, /* Advanced Interrupt Controller (IRQ3) */
143
+
0, /* Advanced Interrupt Controller (IRQ4) */
144
+
0, /* Advanced Interrupt Controller (IRQ5) */
145
+
0 /* Advanced Interrupt Controller (IRQ6) */
146
+
};
147
+
148
+
void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS])
149
+
{
150
+
if (!priority)
151
+
priority = at91rm9200_default_irq_priority;
152
+
153
+
at91_aic_init(priority);
154
+
}
+7
-1
arch/arm/mach-at91rm9200/generic.h
+7
-1
arch/arm/mach-at91rm9200/generic.h
···
8
8
* published by the Free Software Foundation.
9
9
*/
10
10
11
-
void at91_gpio_irq_setup(unsigned banks);
11
+
/* Interrupts */
12
+
extern void __init at91rm9200_init_irq(unsigned int priority[]);
13
+
extern void __init at91_aic_init(unsigned int priority[]);
14
+
extern void __init at91_gpio_irq_setup(unsigned banks);
12
15
16
+
/* Timer */
13
17
struct sys_timer;
14
18
extern struct sys_timer at91rm9200_timer;
15
19
20
+
/* Memory Map */
16
21
extern void __init at91rm9200_map_io(void);
17
22
23
+
/* Clocks */
18
24
extern int __init at91_clock_init(unsigned long main_clock);
19
25
struct device;
20
26
extern void __init at91_clock_associate(const char *id, struct device *dev, const char *func);
+14
-56
arch/arm/mach-at91rm9200/irq.c
+14
-56
arch/arm/mach-at91rm9200/irq.c
···
36
36
37
37
#include "generic.h"
38
38
39
-
/*
40
-
* The default interrupt priority levels (0 = lowest, 7 = highest).
41
-
*/
42
-
static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
43
-
7, /* Advanced Interrupt Controller */
44
-
7, /* System Peripheral */
45
-
0, /* Parallel IO Controller A */
46
-
0, /* Parallel IO Controller B */
47
-
0, /* Parallel IO Controller C */
48
-
0, /* Parallel IO Controller D */
49
-
6, /* USART 0 */
50
-
6, /* USART 1 */
51
-
6, /* USART 2 */
52
-
6, /* USART 3 */
53
-
0, /* Multimedia Card Interface */
54
-
4, /* USB Device Port */
55
-
0, /* Two-Wire Interface */
56
-
6, /* Serial Peripheral Interface */
57
-
5, /* Serial Synchronous Controller */
58
-
5, /* Serial Synchronous Controller */
59
-
5, /* Serial Synchronous Controller */
60
-
0, /* Timer Counter 0 */
61
-
0, /* Timer Counter 1 */
62
-
0, /* Timer Counter 2 */
63
-
0, /* Timer Counter 3 */
64
-
0, /* Timer Counter 4 */
65
-
0, /* Timer Counter 5 */
66
-
3, /* USB Host port */
67
-
3, /* Ethernet MAC */
68
-
0, /* Advanced Interrupt Controller */
69
-
0, /* Advanced Interrupt Controller */
70
-
0, /* Advanced Interrupt Controller */
71
-
0, /* Advanced Interrupt Controller */
72
-
0, /* Advanced Interrupt Controller */
73
-
0, /* Advanced Interrupt Controller */
74
-
0 /* Advanced Interrupt Controller */
75
-
};
76
39
77
-
78
-
static void at91rm9200_mask_irq(unsigned int irq)
40
+
static void at91_aic_mask_irq(unsigned int irq)
79
41
{
80
42
/* Disable interrupt on AIC */
81
43
at91_sys_write(AT91_AIC_IDCR, 1 << irq);
82
44
}
83
45
84
-
static void at91rm9200_unmask_irq(unsigned int irq)
46
+
static void at91_aic_unmask_irq(unsigned int irq)
85
47
{
86
48
/* Enable interrupt on AIC */
87
49
at91_sys_write(AT91_AIC_IECR, 1 << irq);
88
50
}
89
51
90
-
static int at91rm9200_irq_type(unsigned irq, unsigned type)
52
+
static int at91_aic_set_type(unsigned irq, unsigned type)
91
53
{
92
54
unsigned int smr, srctype;
93
55
···
84
122
static u32 wakeups;
85
123
static u32 backups;
86
124
87
-
static int at91rm9200_irq_set_wake(unsigned irq, unsigned value)
125
+
static int at91_aic_set_wake(unsigned irq, unsigned value)
88
126
{
89
127
if (unlikely(irq >= 32))
90
128
return -EINVAL;
···
111
149
}
112
150
113
151
#else
114
-
#define at91rm9200_irq_set_wake NULL
152
+
#define at91_aic_set_wake NULL
115
153
#endif
116
154
117
-
static struct irqchip at91rm9200_irq_chip = {
118
-
.ack = at91rm9200_mask_irq,
119
-
.mask = at91rm9200_mask_irq,
120
-
.unmask = at91rm9200_unmask_irq,
121
-
.set_type = at91rm9200_irq_type,
122
-
.set_wake = at91rm9200_irq_set_wake,
155
+
static struct irqchip at91_aic_chip = {
156
+
.ack = at91_aic_mask_irq,
157
+
.mask = at91_aic_mask_irq,
158
+
.unmask = at91_aic_unmask_irq,
159
+
.set_type = at91_aic_set_type,
160
+
.set_wake = at91_aic_set_wake,
123
161
};
124
162
125
163
/*
126
164
* Initialize the AIC interrupt controller.
127
165
*/
128
-
void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS])
166
+
void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
129
167
{
130
168
unsigned int i;
131
-
132
-
/* No priority list specified for this board -> use defaults */
133
-
if (priority == NULL)
134
-
priority = at91rm9200_default_irq_priority;
135
169
136
170
/*
137
171
* The IVR is used by macro get_irqnr_and_base to read and verify.
···
136
178
for (i = 0; i < NR_AIC_IRQS; i++) {
137
179
/* Put irq number in Source Vector Register: */
138
180
at91_sys_write(AT91_AIC_SVR(i), i);
139
-
/* Store the Source Mode Register as defined in table above */
181
+
/* Active Low interrupt, with the specified priority */
140
182
at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
141
183
142
-
set_irq_chip(i, &at91rm9200_irq_chip);
184
+
set_irq_chip(i, &at91_aic_chip);
143
185
set_irq_handler(i, do_level_IRQ);
144
186
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
145
187
-2
arch/arm/mach-pnx4008/core.c
-2
arch/arm/mach-pnx4008/core.c
···
27
27
#include <linux/spi/spi.h>
28
28
29
29
#include <asm/hardware.h>
30
-
#include <asm/irq.h>
31
30
#include <asm/io.h>
32
31
#include <asm/setup.h>
33
32
#include <asm/mach-types.h>
···
35
36
#include <asm/system.h>
36
37
37
38
#include <asm/mach/arch.h>
38
-
#include <asm/mach/irq.h>
39
39
#include <asm/mach/map.h>
40
40
#include <asm/mach/time.h>
41
41
-1
arch/arm/mach-pnx4008/dma.c
-1
arch/arm/mach-pnx4008/dma.c
+10
-12
arch/arm/mach-pnx4008/irq.c
+10
-12
arch/arm/mach-pnx4008/irq.c
···
22
22
#include <linux/init.h>
23
23
#include <linux/ioport.h>
24
24
#include <linux/device.h>
25
+
#include <linux/irq.h>
25
26
#include <asm/hardware.h>
26
-
#include <asm/irq.h>
27
27
#include <asm/io.h>
28
28
#include <asm/setup.h>
29
29
#include <asm/mach-types.h>
···
96
96
{
97
97
unsigned int i;
98
98
99
-
/* configure and enable IRQ 0,1,30,31 (cascade interrupts) mask all others */
99
+
/* configure IRQ's */
100
+
for (i = 0; i < NR_IRQS; i++) {
101
+
set_irq_flags(i, IRQF_VALID);
102
+
set_irq_chip(i, &pnx4008_irq_chip);
103
+
pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
104
+
}
105
+
106
+
/* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
100
107
pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
101
108
pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
102
109
pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
103
110
pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
104
111
112
+
/* mask all others */
105
113
__raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
106
114
(1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
107
115
INTC_ER(MAIN_BASE_INT));
108
116
__raw_writel(0, INTC_ER(SIC1_BASE_INT));
109
117
__raw_writel(0, INTC_ER(SIC2_BASE_INT));
110
-
111
-
/* configure all other IRQ's */
112
-
for (i = 0; i < NR_IRQS; i++) {
113
-
if (i == SUB2_FIQ_N || i == SUB1_FIQ_N ||
114
-
i == SUB2_IRQ_N || i == SUB1_IRQ_N)
115
-
continue;
116
-
set_irq_flags(i, IRQF_VALID);
117
-
set_irq_chip(i, &pnx4008_irq_chip);
118
-
pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
119
-
}
120
118
}
121
119
+3
-5
arch/arm/mach-pnx4008/time.c
+3
-5
arch/arm/mach-pnx4008/time.c
···
20
20
#include <linux/spinlock.h>
21
21
#include <linux/module.h>
22
22
#include <linux/kallsyms.h>
23
+
#include <linux/time.h>
24
+
#include <linux/timex.h>
25
+
#include <linux/irq.h>
23
26
24
27
#include <asm/system.h>
25
28
#include <asm/hardware.h>
26
29
#include <asm/io.h>
27
30
#include <asm/leds.h>
28
-
#include <asm/irq.h>
29
-
#include <asm/mach/irq.h>
30
31
#include <asm/mach/time.h>
31
-
32
-
#include <linux/time.h>
33
-
#include <linux/timex.h>
34
32
#include <asm/errno.h>
35
33
36
34
/*! Note: all timers are UPCOUNTING */
+3
-2
drivers/serial/at91_serial.c
+3
-2
drivers/serial/at91_serial.c
···
41
41
#include <asm/mach/serial_at91.h>
42
42
#include <asm/arch/board.h>
43
43
#include <asm/arch/system.h>
44
+
#include <asm/arch/gpio.h>
44
45
45
46
#if defined(CONFIG_SERIAL_AT91_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
46
47
#define SUPPORT_SYSRQ
···
141
140
*/
142
141
if (port->mapbase == AT91_BASE_US0) {
143
142
if (mctrl & TIOCM_RTS)
144
-
at91_sys_write(AT91_PIOA + PIO_CODR, AT91_PA21_RTS0);
143
+
at91_set_gpio_value(AT91_PIN_PA21, 0);
145
144
else
146
-
at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0);
145
+
at91_set_gpio_value(AT91_PIN_PA21, 1);
147
146
}
148
147
}
149
148