tjh.dev
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arch/parisc/include/asm/ldcw.h
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arch/parisc/include/asm/ldcw.h
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for the semaphore. */
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#define __PA_LDCW_ALIGNMENT 16
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#define __PA_LDCW_ALIGN_ORDER 4
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#define __ldcw_align(a) ({ \
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unsigned long __ret = (unsigned long) &(a)->lock[0]; \
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__ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
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ldcd). */
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#define __PA_LDCW_ALIGNMENT 4
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#define __PA_LDCW_ALIGN_ORDER 2
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#define __ldcw_align(a) (&(a)->slock)
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#define __LDCW "ldcw,co"
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arch/parisc/kernel/entry.S
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arch/parisc/kernel/entry.S
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#include <asm/pgtable.h>
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#include <asm/signal.h>
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#include <asm/unistd.h>
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#include <asm/ldcw.h>
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#include <asm/thread_info.h>
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#include <linux/linkage.h>
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#endif
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.import pa_tlb_lock,data
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.macro load_pa_tlb_lock reg
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#if __PA_LDCW_ALIGNMENT > 4
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load32 PA(pa_tlb_lock) + __PA_LDCW_ALIGNMENT-1, \reg
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depi 0,31,__PA_LDCW_ALIGN_ORDER, \reg
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#else
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load32 PA(pa_tlb_lock), \reg
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#endif
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.endm
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/* space_to_prot macro creates a prot id from a space id */
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.macro tlb_lock spc,ptp,pte,tmp,tmp1,fault
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#ifdef CONFIG_SMP
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cmpib,COND(=),n 0,\spc,2f
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load32 PA(pa_tlb_lock),\tmp
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load_pa_tlb_lock \tmp
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1: LDCW 0(\tmp),\tmp1
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cmpib,COND(=) 0,\tmp1,1b
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nop
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/* Release pa_tlb_lock lock. */
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.macro tlb_unlock1 spc,tmp
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#ifdef CONFIG_SMP
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load32 PA(pa_tlb_lock),\tmp
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load_pa_tlb_lock \tmp
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tlb_unlock0 \spc,\tmp
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#endif
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.endm
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arch/parisc/kernel/pacache.S
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arch/parisc/kernel/pacache.S
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#include <asm/assembly.h>
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#include <asm/pgtable.h>
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#include <asm/cache.h>
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#include <asm/ldcw.h>
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#include <linux/linkage.h>
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.text
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.macro tlb_lock la,flags,tmp
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#ifdef CONFIG_SMP
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ldil L%pa_tlb_lock,%r1
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ldo R%pa_tlb_lock(%r1),\la
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#if __PA_LDCW_ALIGNMENT > 4
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load32 pa_tlb_lock + __PA_LDCW_ALIGNMENT-1, \la
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depi 0,31,__PA_LDCW_ALIGN_ORDER, \la
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#else
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load32 pa_tlb_lock, \la
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#endif
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rsm PSW_SM_I,\flags
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1: LDCW 0(\la),\tmp
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cmpib,<>,n 0,\tmp,3f