Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

PCI: designware: Move calculation of bus addresses to DRA7xx

Commit f4c55c5a3f7f ("PCI: designware: Program ATU with untranslated
address") added the calculation of PCI bus addresses in pcie-designware.c,
storing them in new fields added in struct pcie_port. This calculation is
done for every DesignWare user even though it only applies to DRA7xx.

Move the calculation of the bus addresses to the DRA7xx driver to allow the
rework of DesignWare to use the new DT parsing API.

Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>

authored by

Gabriele Paoloni and committed by
Bjorn Helgaas
883cc17c 907fce09

+11 -11
+7
drivers/pci/host/pci-dra7xx.c
··· 62 62 63 63 #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C 64 64 #define LINK_UP BIT(16) 65 + #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF 65 66 66 67 struct dra7xx_pcie { 67 68 void __iomem *base; ··· 152 151 static void dra7xx_pcie_host_init(struct pcie_port *pp) 153 152 { 154 153 dw_pcie_setup_rc(pp); 154 + 155 + pp->io_mod_base &= DRA7XX_CPU_TO_BUS_ADDR; 156 + pp->mem_mod_base &= DRA7XX_CPU_TO_BUS_ADDR; 157 + pp->cfg0_mod_base &= DRA7XX_CPU_TO_BUS_ADDR; 158 + pp->cfg1_mod_base &= DRA7XX_CPU_TO_BUS_ADDR; 159 + 155 160 dra7xx_pcie_establish_link(pp); 156 161 if (IS_ENABLED(CONFIG_PCI_MSI)) 157 162 dw_pcie_msi_init(pp);
+4 -11
drivers/pci/host/pcie-designware.c
··· 417 417 struct of_pci_range range; 418 418 struct of_pci_range_parser parser; 419 419 struct resource *cfg_res; 420 - u32 val, na, ns; 420 + u32 val, ns; 421 421 const __be32 *addrp; 422 422 int i, index, ret; 423 423 424 - /* Find the address cell size and the number of cells in order to get 425 - * the untranslated address. 426 - */ 427 - of_property_read_u32(np, "#address-cells", &na); 428 424 ns = of_n_size_cells(np); 429 425 430 426 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); ··· 463 467 pp->io_base = range.cpu_addr; 464 468 465 469 /* Find the untranslated IO space address */ 466 - pp->io_mod_base = of_read_number(parser.range - 467 - parser.np + na, ns); 470 + pp->io_mod_base = range.cpu_addr; 468 471 } 469 472 if (restype == IORESOURCE_MEM) { 470 473 of_pci_range_to_resource(&range, np, &pp->mem); ··· 472 477 pp->mem_bus_addr = range.pci_addr; 473 478 474 479 /* Find the untranslated MEM space address */ 475 - pp->mem_mod_base = of_read_number(parser.range - 476 - parser.np + na, ns); 480 + pp->mem_mod_base = range.cpu_addr; 477 481 } 478 482 if (restype == 0) { 479 483 of_pci_range_to_resource(&range, np, &pp->cfg); ··· 482 488 pp->cfg1_base = pp->cfg.start + pp->cfg0_size; 483 489 484 490 /* Find the untranslated configuration space address */ 485 - pp->cfg0_mod_base = of_read_number(parser.range - 486 - parser.np + na, ns); 491 + pp->cfg0_mod_base = range.cpu_addr; 487 492 pp->cfg1_mod_base = pp->cfg0_mod_base + 488 493 pp->cfg0_size; 489 494 }