tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
perf list: Update event description for IBM zEC12/zBC12 to latest level
Update IBM zEC12/zBC12 event counter description to the latest level
as described in the documents
1. SA23-2260-07:
"The Load-Program-Parameter and the CPU-Measurement Facilities."
released on May, 2022
for the following counter sets:
* Basic counter set
* Problem counter set
* Crypto counter set
2. SA23-2261-07:
"The CPU-Measurement Facility Extended Counters Definition
for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15 and z16"
released on April 29, 2022
for the following counter sets:
* Extended counter set
* MT-Diagnostic counter set
Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
Acked-by: Ian Rogers <irogers@google.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Link: https://lore.kernel.org/r/20220531092706.1931503-7-tmricht@linux.ibm.com
Cc: acme@kernel.org
Cc: gor@linux.ibm.com
Cc: hca@linux.ibm.com
Cc: svens@linux.ibm.com
Cc: linux-kernel@vger.kernel.org
Cc: linux-perf-users@vger.kernel.org
authored by
Thomas Richter
and committed by
Arnaldo Carvalho de Melo
882f5424
dfeab63a
+89
-89
+24
-24
tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
+24
-24
tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
···
3
3
"Unit": "CPU-M-CF",
4
4
"EventCode": "0",
5
5
"EventName": "CPU_CYCLES",
6
-
"BriefDescription": "CPU Cycles",
7
-
"PublicDescription": "Cycle Count"
6
+
"BriefDescription": "Cycle Count",
7
+
"PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state."
8
8
},
9
9
{
10
10
"Unit": "CPU-M-CF",
11
11
"EventCode": "1",
12
12
"EventName": "INSTRUCTIONS",
13
-
"BriefDescription": "Instructions",
14
-
"PublicDescription": "Instruction Count"
13
+
"BriefDescription": "Instruction Count",
14
+
"PublicDescription": "This counter counts the total number of instructions executed by the CPU."
15
15
},
16
16
{
17
17
"Unit": "CPU-M-CF",
18
18
"EventCode": "2",
19
19
"EventName": "L1I_DIR_WRITES",
20
-
"BriefDescription": "L1I Directory Writes",
21
-
"PublicDescription": "Level-1 I-Cache Directory Write Count"
20
+
"BriefDescription": "Level-1 I-Cache Directory Write Count",
21
+
"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes."
22
22
},
23
23
{
24
24
"Unit": "CPU-M-CF",
25
25
"EventCode": "3",
26
26
"EventName": "L1I_PENALTY_CYCLES",
27
-
"BriefDescription": "L1I Penalty Cycles",
28
-
"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
27
+
"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28
+
"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
29
29
},
30
30
{
31
31
"Unit": "CPU-M-CF",
32
32
"EventCode": "4",
33
33
"EventName": "L1D_DIR_WRITES",
34
-
"BriefDescription": "L1D Directory Writes",
35
-
"PublicDescription": "Level-1 D-Cache Directory Write Count"
34
+
"BriefDescription": "Level-1 D-Cache Directory Write Count",
35
+
"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes."
36
36
},
37
37
{
38
38
"Unit": "CPU-M-CF",
39
39
"EventCode": "5",
40
40
"EventName": "L1D_PENALTY_CYCLES",
41
-
"BriefDescription": "L1D Penalty Cycles",
42
-
"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
41
+
"BriefDescription": "Level-1 D-Cache Penalty Cycle Count",
42
+
"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache."
43
43
},
44
44
{
45
45
"Unit": "CPU-M-CF",
46
46
"EventCode": "32",
47
47
"EventName": "PROBLEM_STATE_CPU_CYCLES",
48
-
"BriefDescription": "Problem-State CPU Cycles",
49
-
"PublicDescription": "Problem-State Cycle Count"
48
+
"BriefDescription": "Problem-State Cycle Count",
49
+
"PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state."
50
50
},
51
51
{
52
52
"Unit": "CPU-M-CF",
53
53
"EventCode": "33",
54
54
"EventName": "PROBLEM_STATE_INSTRUCTIONS",
55
-
"BriefDescription": "Problem-State Instructions",
56
-
"PublicDescription": "Problem-State Instruction Count"
55
+
"BriefDescription": "Problem-State Instruction Count",
56
+
"PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state."
57
57
},
58
58
{
59
59
"Unit": "CPU-M-CF",
60
60
"EventCode": "34",
61
61
"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
62
-
"BriefDescription": "Problem-State L1I Directory Writes",
63
-
"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
62
+
"BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count",
63
+
"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state."
64
64
},
65
65
{
66
66
"Unit": "CPU-M-CF",
67
67
"EventCode": "35",
68
68
"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
69
-
"BriefDescription": "Problem-State L1I Penalty Cycles",
70
-
"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
69
+
"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
70
+
"PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state."
71
71
},
72
72
{
73
73
"Unit": "CPU-M-CF",
74
74
"EventCode": "36",
75
75
"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
76
-
"BriefDescription": "Problem-State L1D Directory Writes",
77
-
"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
76
+
"BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count",
77
+
"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state."
78
78
},
79
79
{
80
80
"Unit": "CPU-M-CF",
81
81
"EventCode": "37",
82
82
"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
83
-
"BriefDescription": "Problem-State L1D Penalty Cycles",
84
-
"PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
83
+
"BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count",
84
+
"PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state."
85
85
}
86
86
]
+32
-32
tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
+32
-32
tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
···
3
3
"Unit": "CPU-M-CF",
4
4
"EventCode": "64",
5
5
"EventName": "PRNG_FUNCTIONS",
6
-
"BriefDescription": "PRNG Functions",
7
-
"PublicDescription": "Total number of the PRNG functions issued by the CPU"
6
+
"BriefDescription": "PRNG Function Count",
7
+
"PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
8
8
},
9
9
{
10
10
"Unit": "CPU-M-CF",
11
11
"EventCode": "65",
12
12
"EventName": "PRNG_CYCLES",
13
-
"BriefDescription": "PRNG Cycles",
14
-
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
13
+
"BriefDescription": "PRNG Cycle Count",
14
+
"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
15
15
},
16
16
{
17
17
"Unit": "CPU-M-CF",
18
18
"EventCode": "66",
19
19
"EventName": "PRNG_BLOCKED_FUNCTIONS",
20
-
"BriefDescription": "PRNG Blocked Functions",
21
-
"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
20
+
"BriefDescription": "PRNG Blocked Function Count",
21
+
"PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
22
22
},
23
23
{
24
24
"Unit": "CPU-M-CF",
25
25
"EventCode": "67",
26
26
"EventName": "PRNG_BLOCKED_CYCLES",
27
-
"BriefDescription": "PRNG Blocked Cycles",
28
-
"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
27
+
"BriefDescription": "PRNG Blocked Cycle Count",
28
+
"PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
29
29
},
30
30
{
31
31
"Unit": "CPU-M-CF",
32
32
"EventCode": "68",
33
33
"EventName": "SHA_FUNCTIONS",
34
-
"BriefDescription": "SHA Functions",
35
-
"PublicDescription": "Total number of SHA functions issued by the CPU"
34
+
"BriefDescription": "SHA Function Count",
35
+
"PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
36
36
},
37
37
{
38
38
"Unit": "CPU-M-CF",
39
39
"EventCode": "69",
40
40
"EventName": "SHA_CYCLES",
41
-
"BriefDescription": "SHA Cycles",
42
-
"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
41
+
"BriefDescription": "SHA Cycle Count",
42
+
"PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
43
43
},
44
44
{
45
45
"Unit": "CPU-M-CF",
46
46
"EventCode": "70",
47
47
"EventName": "SHA_BLOCKED_FUNCTIONS",
48
-
"BriefDescription": "SHA Blocked Functions",
49
-
"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
48
+
"BriefDescription": "SHA Blocked Function Count",
49
+
"PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU."
50
50
},
51
51
{
52
52
"Unit": "CPU-M-CF",
53
53
"EventCode": "71",
54
54
"EventName": "SHA_BLOCKED_CYCLES",
55
-
"BriefDescription": "SHA Bloced Cycles",
56
-
"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
55
+
"BriefDescription": "SHA Blocked Cycle Count",
56
+
"PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU."
57
57
},
58
58
{
59
59
"Unit": "CPU-M-CF",
60
60
"EventCode": "72",
61
61
"EventName": "DEA_FUNCTIONS",
62
-
"BriefDescription": "DEA Functions",
63
-
"PublicDescription": "Total number of the DEA functions issued by the CPU"
62
+
"BriefDescription": "DEA Function Count",
63
+
"PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU."
64
64
},
65
65
{
66
66
"Unit": "CPU-M-CF",
67
67
"EventCode": "73",
68
68
"EventName": "DEA_CYCLES",
69
-
"BriefDescription": "DEA Cycles",
70
-
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
69
+
"BriefDescription": "DEA Cycle Count",
70
+
"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU."
71
71
},
72
72
{
73
73
"Unit": "CPU-M-CF",
74
74
"EventCode": "74",
75
75
"EventName": "DEA_BLOCKED_FUNCTIONS",
76
-
"BriefDescription": "DEA Blocked Functions",
77
-
"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
76
+
"BriefDescription": "DEA Blocked Function Count",
77
+
"PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."
78
78
},
79
79
{
80
80
"Unit": "CPU-M-CF",
81
81
"EventCode": "75",
82
82
"EventName": "DEA_BLOCKED_CYCLES",
83
-
"BriefDescription": "DEA Blocked Cycles",
84
-
"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
83
+
"BriefDescription": "DEA Blocked Cycle Count",
84
+
"PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."
85
85
},
86
86
{
87
87
"Unit": "CPU-M-CF",
88
88
"EventCode": "76",
89
89
"EventName": "AES_FUNCTIONS",
90
-
"BriefDescription": "AES Functions",
91
-
"PublicDescription": "Total number of AES functions issued by the CPU"
90
+
"BriefDescription": "AES Function Count",
91
+
"PublicDescription": "This counter counts the total number of the AES functions issued by the CPU."
92
92
},
93
93
{
94
94
"Unit": "CPU-M-CF",
95
95
"EventCode": "77",
96
96
"EventName": "AES_CYCLES",
97
-
"BriefDescription": "AES Cycles",
98
-
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
97
+
"BriefDescription": "AES Cycle Count",
98
+
"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU."
99
99
},
100
100
{
101
101
"Unit": "CPU-M-CF",
102
102
"EventCode": "78",
103
103
"EventName": "AES_BLOCKED_FUNCTIONS",
104
-
"BriefDescription": "AES Blocked Functions",
105
-
"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
104
+
"BriefDescription": "AES Blocked Function Count",
105
+
"PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."
106
106
},
107
107
{
108
108
"Unit": "CPU-M-CF",
109
109
"EventCode": "79",
110
110
"EventName": "AES_BLOCKED_CYCLES",
111
-
"BriefDescription": "AES Blocked Cycles",
112
-
"PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
111
+
"BriefDescription": "AES Blocked Cycle Count",
112
+
"PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."
113
113
}
114
114
]
+33
-33
tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
+33
-33
tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
···
18
18
"EventCode": "130",
19
19
"EventName": "L1D_L2I_SOURCED_WRITES",
20
20
"BriefDescription": "L1D L2I Sourced Writes",
21
-
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
21
+
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache."
22
22
},
23
23
{
24
24
"Unit": "CPU-M-CF",
25
25
"EventCode": "131",
26
26
"EventName": "L1I_L2I_SOURCED_WRITES",
27
27
"BriefDescription": "L1I L2I Sourced Writes",
28
-
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
28
+
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache."
29
29
},
30
30
{
31
31
"Unit": "CPU-M-CF",
32
32
"EventCode": "132",
33
33
"EventName": "L1D_L2D_SOURCED_WRITES",
34
34
"BriefDescription": "L1D L2D Sourced Writes",
35
-
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
35
+
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache."
36
36
},
37
37
{
38
38
"Unit": "CPU-M-CF",
39
39
"EventCode": "133",
40
40
"EventName": "DTLB1_WRITES",
41
41
"BriefDescription": "DTLB1 Writes",
42
-
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
42
+
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)."
43
43
},
44
44
{
45
45
"Unit": "CPU-M-CF",
46
46
"EventCode": "135",
47
47
"EventName": "L1D_LMEM_SOURCED_WRITES",
48
48
"BriefDescription": "L1D Local Memory Sourced Writes",
49
-
"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
49
+
"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)."
50
50
},
51
51
{
52
52
"Unit": "CPU-M-CF",
53
53
"EventCode": "137",
54
54
"EventName": "L1I_LMEM_SOURCED_WRITES",
55
55
"BriefDescription": "L1I Local Memory Sourced Writes",
56
-
"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
56
+
"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)."
57
57
},
58
58
{
59
59
"Unit": "CPU-M-CF",
60
60
"EventCode": "138",
61
61
"EventName": "L1D_RO_EXCL_WRITES",
62
62
"BriefDescription": "L1D Read-only Exclusive Writes",
63
-
"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
63
+
"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
64
64
},
65
65
{
66
66
"Unit": "CPU-M-CF",
67
67
"EventCode": "139",
68
68
"EventName": "DTLB1_HPAGE_WRITES",
69
69
"BriefDescription": "DTLB1 One-Megabyte Page Writes",
70
-
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
70
+
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page."
71
71
},
72
72
{
73
73
"Unit": "CPU-M-CF",
74
74
"EventCode": "140",
75
75
"EventName": "ITLB1_WRITES",
76
76
"BriefDescription": "ITLB1 Writes",
77
-
"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
77
+
"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)."
78
78
},
79
79
{
80
80
"Unit": "CPU-M-CF",
81
81
"EventCode": "141",
82
82
"EventName": "TLB2_PTE_WRITES",
83
83
"BriefDescription": "TLB2 PTE Writes",
84
-
"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
84
+
"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays."
85
85
},
86
86
{
87
87
"Unit": "CPU-M-CF",
88
88
"EventCode": "142",
89
89
"EventName": "TLB2_CRSTE_HPAGE_WRITES",
90
90
"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
91
-
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
91
+
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation."
92
92
},
93
93
{
94
94
"Unit": "CPU-M-CF",
95
95
"EventCode": "143",
96
96
"EventName": "TLB2_CRSTE_WRITES",
97
97
"BriefDescription": "TLB2 CRSTE Writes",
98
-
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
98
+
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays."
99
99
},
100
100
{
101
101
"Unit": "CPU-M-CF",
102
102
"EventCode": "144",
103
103
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
104
104
"BriefDescription": "L1D On-Chip L3 Sourced Writes",
105
-
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
105
+
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention."
106
106
},
107
107
{
108
108
"Unit": "CPU-M-CF",
109
109
"EventCode": "145",
110
110
"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
111
111
"BriefDescription": "L1D Off-Chip L3 Sourced Writes",
112
-
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
112
+
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention."
113
113
},
114
114
{
115
115
"Unit": "CPU-M-CF",
116
116
"EventCode": "146",
117
117
"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
118
118
"BriefDescription": "L1D Off-Book L3 Sourced Writes",
119
-
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
119
+
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention."
120
120
},
121
121
{
122
122
"Unit": "CPU-M-CF",
123
123
"EventCode": "147",
124
124
"EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
125
125
"BriefDescription": "L1D On-Book L4 Sourced Writes",
126
-
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache"
126
+
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache."
127
127
},
128
128
{
129
129
"Unit": "CPU-M-CF",
130
130
"EventCode": "148",
131
131
"EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
132
132
"BriefDescription": "L1D Off-Book L4 Sourced Writes",
133
-
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
133
+
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache."
134
134
},
135
135
{
136
136
"Unit": "CPU-M-CF",
137
137
"EventCode": "149",
138
138
"EventName": "TX_NC_TEND",
139
139
"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
140
-
"PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode"
140
+
"PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode."
141
141
},
142
142
{
143
143
"Unit": "CPU-M-CF",
144
144
"EventCode": "150",
145
145
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
146
146
"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
147
-
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention"
147
+
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention."
148
148
},
149
149
{
150
150
"Unit": "CPU-M-CF",
151
151
"EventCode": "151",
152
152
"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV",
153
153
"BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention",
154
-
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
154
+
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention."
155
155
},
156
156
{
157
157
"Unit": "CPU-M-CF",
158
158
"EventCode": "152",
159
159
"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV",
160
160
"BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention",
161
-
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
161
+
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention."
162
162
},
163
163
{
164
164
"Unit": "CPU-M-CF",
165
165
"EventCode": "153",
166
166
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
167
167
"BriefDescription": "L1I On-Chip L3 Sourced Writes",
168
-
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
168
+
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention."
169
169
},
170
170
{
171
171
"Unit": "CPU-M-CF",
172
172
"EventCode": "154",
173
173
"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
174
174
"BriefDescription": "L1I Off-Chip L3 Sourced Writes",
175
-
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
175
+
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention."
176
176
},
177
177
{
178
178
"Unit": "CPU-M-CF",
179
179
"EventCode": "155",
180
180
"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
181
181
"BriefDescription": "L1I Off-Book L3 Sourced Writes",
182
-
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
182
+
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention."
183
183
},
184
184
{
185
185
"Unit": "CPU-M-CF",
186
186
"EventCode": "156",
187
187
"EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
188
188
"BriefDescription": "L1I On-Book L4 Sourced Writes",
189
-
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache"
189
+
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache."
190
190
},
191
191
{
192
192
"Unit": "CPU-M-CF",
193
193
"EventCode": "157",
194
194
"EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
195
195
"BriefDescription": "L1I Off-Book L4 Sourced Writes",
196
-
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
196
+
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache."
197
197
},
198
198
{
199
199
"Unit": "CPU-M-CF",
200
200
"EventCode": "158",
201
201
"EventName": "TX_C_TEND",
202
202
"BriefDescription": "Completed TEND instructions in constrained TX mode",
203
-
"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
203
+
"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode."
204
204
},
205
205
{
206
206
"Unit": "CPU-M-CF",
207
207
"EventCode": "159",
208
208
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
209
209
"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
210
-
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
210
+
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention."
211
211
},
212
212
{
213
213
"Unit": "CPU-M-CF",
214
214
"EventCode": "160",
215
215
"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV",
216
216
"BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention",
217
-
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
217
+
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention."
218
218
},
219
219
{
220
220
"Unit": "CPU-M-CF",
221
221
"EventCode": "161",
222
222
"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV",
223
223
"BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention",
224
-
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
224
+
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention."
225
225
},
226
226
{
227
227
"Unit": "CPU-M-CF",
228
228
"EventCode": "177",
229
229
"EventName": "TX_NC_TABORT",
230
230
"BriefDescription": "Aborted transactions in non-constrained TX mode",
231
-
"PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode"
231
+
"PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode."
232
232
},
233
233
{
234
234
"Unit": "CPU-M-CF",
235
235
"EventCode": "178",
236
236
"EventName": "TX_C_TABORT_NO_SPECIAL",
237
237
"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
238
-
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
238
+
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete."
239
239
},
240
240
{
241
241
"Unit": "CPU-M-CF",
242
242
"EventCode": "179",
243
243
"EventName": "TX_C_TABORT_SPECIAL",
244
244
"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
245
-
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
245
+
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete."
246
246
}
247
247
]