watchdog: s3c2410_wdt: Add max and min timeout values

The watchdog maximum timeout value is determined by the number of bits
for the interval timer counter, its source clock frequency, the number
of bits of the prescaler and maximum divider value.

This can be calculated with the following equation:

max_timeout = counter / (freq / (max_prescale + 1) / max_divider)

Setting a maximum timeout value will allow the watchdog core to refuse
user-space calls to the WDIOC_SETTIMEOUT ioctl that sets not supported
timeout values.

For example, systemd tries to set a timeout of 10 minutes on reboot to
ensure that the machine will be rebooted even if a reboot failed. This
leads to the following error message on an Exynos5422 Odroid XU4 board:

[ 147.986045] s3c2410-wdt 101d0000.watchdog: timeout 600 too big

Reported-by: Krzysztof Kozlowski <[e-mail]>
Signed-off-by: Javier Martinez Canillas <[e-mail]>
Reviewed-by: Krzysztof Kozlowski <[e-mail]>
Signed-off-by: Guenter Roeck <[e-mail]>
Signed-off-by: Wim Van Sebroeck <[e-mail]>

drivers/watchdog/s3c2410_wdt.c

···
 #define S3C2410_WTDAT		0x04
 #define S3C2410_WTCNT		0x08
 
+#define S3C2410_WTCNT_MAXCNT	0xffff
+
 #define S3C2410_WTCON_RSTEN	(1 << 0)
 #define S3C2410_WTCON_INTEN	(1 << 2)
 #define S3C2410_WTCON_ENABLE	(1 << 5)
···
 #define S3C2410_WTCON_DIV64	(2 << 3)
 #define S3C2410_WTCON_DIV128	(3 << 3)
 
+#define S3C2410_WTCON_MAXDIV	0x80
+
 #define S3C2410_WTCON_PRESCALE(x)	((x) << 8)
 #define S3C2410_WTCON_PRESCALE_MASK	(0xff << 8)
+#define S3C2410_WTCON_PRESCALE_MAX	0xff
 
 #define CONFIG_S3C2410_WATCHDOG_ATBOOT		(0)
 #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME	(15)
···
 } while (0)
 
 /* functions */
+
+static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock)
+{
+	unsigned long freq = clk_get_rate(clock);
+
+	return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1)
+				       / S3C2410_WTCON_MAXDIV);
+}
 
 static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
 {
···
 		dev_err(dev, "failed to enable clock\n");
 		return ret;
 	}
+
+	wdt->wdt_device.min_timeout = 1;
+	wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock);
 
 	ret = s3c2410wdt_cpufreq_register(wdt);
 	if (ret < 0) {