tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/vrr: fix register file style
Fix indents, use of spaces vs. tabs, grouping, remove superfluous
comments, remove some line continuations, wrap macro arguments in
parens, rename dev_priv to display. This is the way.
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://lore.kernel.org/r/20250618155137.1651865-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+57
-64
+57
-64
drivers/gpu/drm/i915/display/intel_vrr_regs.h
+57
-64
drivers/gpu/drm/i915/display/intel_vrr_regs.h
···
8
8
9
9
#include "intel_display_reg_defs.h"
10
10
11
-
/* VRR registers */
12
11
#define _TRANS_VRR_CTL_A 0x60420
13
12
#define _TRANS_VRR_CTL_B 0x61420
14
13
#define _TRANS_VRR_CTL_C 0x62420
15
14
#define _TRANS_VRR_CTL_D 0x63420
16
-
#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
17
-
#define VRR_CTL_VRR_ENABLE REG_BIT(31)
18
-
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
19
-
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
20
-
#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
21
-
#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
22
-
#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
23
-
#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
24
-
#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
15
+
#define TRANS_VRR_CTL(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_CTL_A)
16
+
#define VRR_CTL_VRR_ENABLE REG_BIT(31)
17
+
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
18
+
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
19
+
#define VRR_CTL_CMRR_ENABLE REG_BIT(27)
20
+
#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
21
+
#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
22
+
#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
23
+
#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
24
+
#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
25
25
26
26
#define _TRANS_VRR_VMAX_A 0x60424
27
27
#define _TRANS_VRR_VMAX_B 0x61424
28
28
#define _TRANS_VRR_VMAX_C 0x62424
29
29
#define _TRANS_VRR_VMAX_D 0x63424
30
-
#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
31
-
#define VRR_VMAX_MASK REG_GENMASK(19, 0)
30
+
#define TRANS_VRR_VMAX(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAX_A)
31
+
#define VRR_VMAX_MASK REG_GENMASK(19, 0)
32
32
33
33
#define _TRANS_VRR_VMIN_A 0x60434
34
34
#define _TRANS_VRR_VMIN_B 0x61434
35
35
#define _TRANS_VRR_VMIN_C 0x62434
36
36
#define _TRANS_VRR_VMIN_D 0x63434
37
-
#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
38
-
#define VRR_VMIN_MASK REG_GENMASK(15, 0)
37
+
#define TRANS_VRR_VMIN(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMIN_A)
38
+
#define VRR_VMIN_MASK REG_GENMASK(15, 0)
39
39
40
40
#define _TRANS_VRR_VMAXSHIFT_A 0x60428
41
41
#define _TRANS_VRR_VMAXSHIFT_B 0x61428
42
42
#define _TRANS_VRR_VMAXSHIFT_C 0x62428
43
43
#define _TRANS_VRR_VMAXSHIFT_D 0x63428
44
-
#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
45
-
_TRANS_VRR_VMAXSHIFT_A)
46
-
#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
47
-
#define VRR_VMAXSHIFT_DEC REG_BIT(16)
48
-
#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
44
+
#define TRANS_VRR_VMAXSHIFT(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAXSHIFT_A)
45
+
#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
46
+
#define VRR_VMAXSHIFT_DEC REG_BIT(16)
47
+
#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
49
48
50
49
#define _TRANS_VRR_STATUS_A 0x6042c
51
50
#define _TRANS_VRR_STATUS_B 0x6142c
52
51
#define _TRANS_VRR_STATUS_C 0x6242c
53
52
#define _TRANS_VRR_STATUS_D 0x6342c
54
-
#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
55
-
#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
56
-
#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
57
-
#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
58
-
#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
59
-
#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
60
-
#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
61
-
#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
62
-
#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
63
-
#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
64
-
#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
65
-
#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
66
-
#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
67
-
#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
68
-
#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
53
+
#define TRANS_VRR_STATUS(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS_A)
54
+
#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
55
+
#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
56
+
#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
57
+
#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
58
+
#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
59
+
#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
60
+
#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
61
+
#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
62
+
#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
63
+
#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
64
+
#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
65
+
#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
66
+
#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
67
+
#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
69
68
70
69
#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
71
70
#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
72
71
#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
73
72
#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
74
-
#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
75
-
_TRANS_VRR_VTOTAL_PREV_A)
76
-
#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
77
-
#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
78
-
#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
79
-
#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
73
+
#define TRANS_VRR_VTOTAL_PREV(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VTOTAL_PREV_A)
74
+
#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
75
+
#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
76
+
#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
77
+
#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
80
78
81
79
#define _TRANS_VRR_FLIPLINE_A 0x60438
82
80
#define _TRANS_VRR_FLIPLINE_B 0x61438
83
81
#define _TRANS_VRR_FLIPLINE_C 0x62438
84
82
#define _TRANS_VRR_FLIPLINE_D 0x63438
85
-
#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
86
-
_TRANS_VRR_FLIPLINE_A)
87
-
#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
83
+
#define TRANS_VRR_FLIPLINE(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_FLIPLINE_A)
84
+
#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
88
85
89
86
#define _TRANS_VRR_STATUS2_A 0x6043c
90
87
#define _TRANS_VRR_STATUS2_B 0x6143c
91
88
#define _TRANS_VRR_STATUS2_C 0x6243c
92
89
#define _TRANS_VRR_STATUS2_D 0x6343c
93
-
#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
94
-
#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
90
+
#define TRANS_VRR_STATUS2(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS2_A)
91
+
#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
95
92
96
93
#define _TRANS_PUSH_A 0x60a70
97
94
#define _TRANS_PUSH_B 0x61a70
98
95
#define _TRANS_PUSH_C 0x62a70
99
96
#define _TRANS_PUSH_D 0x63a70
100
-
#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)
101
-
#define TRANS_PUSH_EN REG_BIT(31)
102
-
#define TRANS_PUSH_SEND REG_BIT(30)
97
+
#define TRANS_PUSH(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_PUSH_A)
98
+
#define TRANS_PUSH_EN REG_BIT(31)
99
+
#define TRANS_PUSH_SEND REG_BIT(30)
103
100
104
101
#define _TRANS_VRR_VSYNC_A 0x60078
105
-
#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
106
-
#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
107
-
#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
108
-
#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
109
-
#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
102
+
#define TRANS_VRR_VSYNC(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VSYNC_A)
103
+
#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
104
+
#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
105
+
#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
106
+
#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
110
107
111
108
/* Common register for HDMI EMP and DP AS SDP */
112
109
#define _EMP_AS_SDP_TL_A 0x60204
113
-
#define EMP_AS_SDP_DB_TL_MASK REG_GENMASK(12, 0)
114
-
#define EMP_AS_SDP_TL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _EMP_AS_SDP_TL_A)
115
-
#define EMP_AS_SDP_DB_TL(db_transmit_line) REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line))
116
-
117
-
/*CMRR Registers*/
110
+
#define EMP_AS_SDP_TL(display, trans) _MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A)
111
+
#define EMP_AS_SDP_DB_TL_MASK REG_GENMASK(12, 0)
112
+
#define EMP_AS_SDP_DB_TL(db_transmit_line) REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line))
118
113
119
114
#define _TRANS_CMRR_M_LO_A 0x604F0
120
-
#define TRANS_CMRR_M_LO(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A)
115
+
#define TRANS_CMRR_M_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_LO_A)
121
116
122
117
#define _TRANS_CMRR_M_HI_A 0x604F4
123
-
#define TRANS_CMRR_M_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A)
118
+
#define TRANS_CMRR_M_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_HI_A)
124
119
125
120
#define _TRANS_CMRR_N_LO_A 0x604F8
126
-
#define TRANS_CMRR_N_LO(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A)
121
+
#define TRANS_CMRR_N_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_LO_A)
127
122
128
123
#define _TRANS_CMRR_N_HI_A 0x604FC
129
-
#define TRANS_CMRR_N_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)
130
-
131
-
#define VRR_CTL_CMRR_ENABLE REG_BIT(27)
124
+
#define TRANS_CMRR_N_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_HI_A)
132
125
133
126
#endif /* __INTEL_VRR_REGS__ */