tjh.dev / kernel
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drm/amdgpu: Prefer pcie_capability_read_word()

Commit 8c0d3a02c130 ("PCI: Add accessors for PCI Express Capability")
added accessors for the PCI Express Capability so that drivers didn't
need to be aware of differences between v1 and v2 of the PCI
Express Capability.

Replace pci_read_config_word() and pci_write_config_word() calls with
pcie_capability_read_word() and pcie_capability_write_word().

[bhelgaas: fix a couple remaining instances in cik.c]
Link: https://lore.kernel.org/r/20191118003513.10852-1-fred@fredlawl.com
Signed-off-by: Frederick Lawler <fred@fredlawl.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Frederick Lawler and committed by
Bjorn Helgaas 88027c89 35e768e2

+90 -52
+45 -26
drivers/gpu/drm/amd/amdgpu/cik.c
··· 1384 1384 static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 1385 1385 { 1386 1386 struct pci_dev *root = adev->pdev->bus->self; 1387 - int bridge_pos, gpu_pos; 1388 1387 u32 speed_cntl, current_data_rate; 1389 1388 int i; 1390 1389 u16 tmp16; ··· 1418 1419 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1419 1420 } 1420 1421 1421 - bridge_pos = pci_pcie_cap(root); 1422 - if (!bridge_pos) 1423 - return; 1424 - 1425 - gpu_pos = pci_pcie_cap(adev->pdev); 1426 - if (!gpu_pos) 1422 + if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) 1427 1423 return; 1428 1424 1429 1425 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { ··· 1428 1434 u16 bridge_cfg2, gpu_cfg2; 1429 1435 u32 max_lw, current_lw, tmp; 1430 1436 1431 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1432 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1437 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1438 + &bridge_cfg); 1439 + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL, 1440 + &gpu_cfg); 1433 1441 1434 1442 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 1435 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1443 + pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); 1436 1444 1437 1445 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 1438 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1446 + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL, 1447 + tmp16); 1439 1448 1440 1449 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); 1441 1450 max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> ··· 1462 1465 1463 1466 for (i = 0; i < 10; i++) { 1464 1467 /* check status */ 1465 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); 1468 + pcie_capability_read_word(adev->pdev, 1469 + PCI_EXP_DEVSTA, 1470 + &tmp16); 1466 1471 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 1467 1472 break; 1468 1473 1469 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1470 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1474 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1475 + &bridge_cfg); 1476 + pcie_capability_read_word(adev->pdev, 1477 + PCI_EXP_LNKCTL, 1478 + &gpu_cfg); 1471 1479 1472 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); 1473 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); 1480 + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1481 + &bridge_cfg2); 1482 + pcie_capability_read_word(adev->pdev, 1483 + PCI_EXP_LNKCTL2, 1484 + &gpu_cfg2); 1474 1485 1475 1486 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1476 1487 tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; ··· 1491 1486 msleep(100); 1492 1487 1493 1488 /* linkctl */ 1494 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); 1489 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1490 + &tmp16); 1495 1491 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1496 1492 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 1497 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1493 + pcie_capability_write_word(root, PCI_EXP_LNKCTL, 1494 + tmp16); 1498 1495 1499 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); 1496 + pcie_capability_read_word(adev->pdev, 1497 + PCI_EXP_LNKCTL, 1498 + &tmp16); 1500 1499 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1501 1500 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 1502 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1501 + pcie_capability_write_word(adev->pdev, 1502 + PCI_EXP_LNKCTL, 1503 + tmp16); 1503 1504 1504 1505 /* linkctl2 */ 1505 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); 1506 + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1507 + &tmp16); 1506 1508 tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1507 1509 PCI_EXP_LNKCTL2_TX_MARGIN); 1508 1510 tmp16 |= (bridge_cfg2 & 1509 1511 (PCI_EXP_LNKCTL2_ENTER_COMP | 1510 1512 PCI_EXP_LNKCTL2_TX_MARGIN)); 1511 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); 1513 + pcie_capability_write_word(root, 1514 + PCI_EXP_LNKCTL2, 1515 + tmp16); 1512 1516 1513 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1517 + pcie_capability_read_word(adev->pdev, 1518 + PCI_EXP_LNKCTL2, 1519 + &tmp16); 1514 1520 tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1515 1521 PCI_EXP_LNKCTL2_TX_MARGIN); 1516 1522 tmp16 |= (gpu_cfg2 & 1517 1523 (PCI_EXP_LNKCTL2_ENTER_COMP | 1518 1524 PCI_EXP_LNKCTL2_TX_MARGIN)); 1519 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1525 + pcie_capability_write_word(adev->pdev, 1526 + PCI_EXP_LNKCTL2, 1527 + tmp16); 1520 1528 1521 1529 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1522 1530 tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; ··· 1544 1526 speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; 1545 1527 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); 1546 1528 1547 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1529 + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16); 1548 1530 tmp16 &= ~PCI_EXP_LNKCTL2_TLS; 1531 + 1549 1532 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1550 1533 tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 1551 1534 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1552 1535 tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 1553 1536 else 1554 1537 tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 1555 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1538 + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16); 1556 1539 1557 1540 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1558 1541 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;
+45 -26
drivers/gpu/drm/amd/amdgpu/si.c
··· 1633 1633 static void si_pcie_gen3_enable(struct amdgpu_device *adev) 1634 1634 { 1635 1635 struct pci_dev *root = adev->pdev->bus->self; 1636 - int bridge_pos, gpu_pos; 1637 1636 u32 speed_cntl, current_data_rate; 1638 1637 int i; 1639 1638 u16 tmp16; ··· 1667 1668 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1668 1669 } 1669 1670 1670 - bridge_pos = pci_pcie_cap(root); 1671 - if (!bridge_pos) 1672 - return; 1673 - 1674 - gpu_pos = pci_pcie_cap(adev->pdev); 1675 - if (!gpu_pos) 1671 + if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) 1676 1672 return; 1677 1673 1678 1674 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { ··· 1676 1682 u16 bridge_cfg2, gpu_cfg2; 1677 1683 u32 max_lw, current_lw, tmp; 1678 1684 1679 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1680 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1685 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1686 + &bridge_cfg); 1687 + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL, 1688 + &gpu_cfg); 1681 1689 1682 1690 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 1683 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1691 + pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); 1684 1692 1685 1693 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 1686 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1694 + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL, 1695 + tmp16); 1687 1696 1688 1697 tmp = RREG32_PCIE(PCIE_LC_STATUS1); 1689 1698 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; ··· 1703 1706 } 1704 1707 1705 1708 for (i = 0; i < 10; i++) { 1706 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); 1709 + pcie_capability_read_word(adev->pdev, 1710 + PCI_EXP_DEVSTA, 1711 + &tmp16); 1707 1712 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 1708 1713 break; 1709 1714 1710 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1711 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1715 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1716 + &bridge_cfg); 1717 + pcie_capability_read_word(adev->pdev, 1718 + PCI_EXP_LNKCTL, 1719 + &gpu_cfg); 1712 1720 1713 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); 1714 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); 1721 + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1722 + &bridge_cfg2); 1723 + pcie_capability_read_word(adev->pdev, 1724 + PCI_EXP_LNKCTL2, 1725 + &gpu_cfg2); 1715 1726 1716 1727 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 1717 1728 tmp |= LC_SET_QUIESCE; ··· 1731 1726 1732 1727 mdelay(100); 1733 1728 1734 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); 1729 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1730 + &tmp16); 1735 1731 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1736 1732 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 1737 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1733 + pcie_capability_write_word(root, PCI_EXP_LNKCTL, 1734 + tmp16); 1738 1735 1739 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); 1736 + pcie_capability_read_word(adev->pdev, 1737 + PCI_EXP_LNKCTL, 1738 + &tmp16); 1740 1739 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1741 1740 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 1742 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1741 + pcie_capability_write_word(adev->pdev, 1742 + PCI_EXP_LNKCTL, 1743 + tmp16); 1743 1744 1744 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); 1745 + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1746 + &tmp16); 1745 1747 tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1746 1748 PCI_EXP_LNKCTL2_TX_MARGIN); 1747 1749 tmp16 |= (bridge_cfg2 & 1748 1750 (PCI_EXP_LNKCTL2_ENTER_COMP | 1749 1751 PCI_EXP_LNKCTL2_TX_MARGIN)); 1750 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); 1752 + pcie_capability_write_word(root, 1753 + PCI_EXP_LNKCTL2, 1754 + tmp16); 1751 1755 1752 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1756 + pcie_capability_read_word(adev->pdev, 1757 + PCI_EXP_LNKCTL2, 1758 + &tmp16); 1753 1759 tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1754 1760 PCI_EXP_LNKCTL2_TX_MARGIN); 1755 1761 tmp16 |= (gpu_cfg2 & 1756 1762 (PCI_EXP_LNKCTL2_ENTER_COMP | 1757 1763 PCI_EXP_LNKCTL2_TX_MARGIN)); 1758 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1764 + pcie_capability_write_word(adev->pdev, 1765 + PCI_EXP_LNKCTL2, 1766 + tmp16); 1759 1767 1760 1768 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 1761 1769 tmp &= ~LC_SET_QUIESCE; ··· 1781 1763 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; 1782 1764 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 1783 1765 1784 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1766 + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16); 1785 1767 tmp16 &= ~PCI_EXP_LNKCTL2_TLS; 1768 + 1786 1769 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1787 1770 tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 1788 1771 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1789 1772 tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 1790 1773 else 1791 1774 tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 1792 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1775 + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16); 1793 1776 1794 1777 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1795 1778 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;