drm/amd/display: add set dp lane settings to link_hwss

+29 -11

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

··· 295 295 const struct link_training_settings *link_settings, 296 296 uint32_t offset) 297 297 { 298 - struct link_encoder *encoder = link->link_enc; 298 + const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 299 299 300 300 if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && !is_immediate_downstream(link, offset)) 301 301 return; 302 302 303 - /* call Encoder to set lane settings */ 304 - if (dp_get_link_encoding_format(&link_settings->link_settings) == 305 - DP_128b_132b_ENCODING) { 306 - link_res->hpo_dp_link_enc->funcs->set_ffe( 307 - link_res->hpo_dp_link_enc, 303 + if (link_hwss->ext.set_dp_lane_settings) 304 + link_hwss->ext.set_dp_lane_settings(link, link_res, 308 305 &link_settings->link_settings, 309 - link_settings->lane_settings[0].FFE_PRESET.raw); 310 - } else if (dp_get_link_encoding_format(&link_settings->link_settings) 311 - == DP_8b_10b_ENCODING) { 312 - encoder->funcs->dp_set_lane_settings(encoder, link_settings); 313 - } 306 + link_settings->hw_lane_settings); 307 + 314 308 memmove(link->cur_lane_setting, 315 309 link_settings->lane_settings, 316 310 sizeof(link->cur_lane_setting)); ··· 742 748 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN); 743 749 } 744 750 751 + static void set_dio_dp_lane_settings(struct dc_link *link, 752 + const struct link_resource *link_res, 753 + const struct dc_link_settings *link_settings, 754 + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) 755 + { 756 + struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link); 757 + 758 + link_enc->funcs->dp_set_lane_settings(link_enc, link_settings, lane_settings); 759 + } 760 + 745 761 static const struct link_hwss dio_link_hwss = { 746 762 .setup_stream_encoder = setup_dio_stream_encoder, 747 763 .reset_stream_encoder = reset_dio_stream_encoder, ··· 760 756 .enable_dp_link_output = enable_dio_dp_link_output, 761 757 .disable_dp_link_output = disable_dio_dp_link_output, 762 758 .set_dp_link_test_pattern = set_dio_dp_link_test_pattern, 759 + .set_dp_lane_settings = set_dio_dp_lane_settings, 763 760 }, 764 761 }; 765 762 ··· 936 931 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN); 937 932 } 938 933 934 + static void set_hpo_dp_lane_settings(struct dc_link *link, 935 + const struct link_resource *link_res, 936 + const struct dc_link_settings *link_settings, 937 + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) 938 + { 939 + link_res->hpo_dp_link_enc->funcs->set_ffe( 940 + link_res->hpo_dp_link_enc, 941 + link_settings, 942 + lane_settings[0].FFE_PRESET.raw); 943 + } 944 + 939 945 static const struct link_hwss hpo_dp_link_hwss = { 940 946 .setup_stream_encoder = setup_hpo_dp_stream_encoder, 941 947 .reset_stream_encoder = reset_hpo_dp_stream_encoder, ··· 956 940 .enable_dp_link_output = enable_hpo_dp_link_output, 957 941 .disable_dp_link_output = disable_hpo_dp_link_output, 958 942 .set_dp_link_test_pattern = set_hpo_dp_link_test_pattern, 943 + .set_dp_lane_settings = set_hpo_dp_lane_settings, 959 944 }, 960 945 }; 961 946 /*********************** below goes to dpia_link_hwss *************************/ ··· 975 958 .enable_dp_link_output = enable_dio_dp_link_output, 976 959 .disable_dp_link_output = disable_dio_dp_link_output, 977 960 .set_dp_link_test_pattern = set_dio_dp_link_test_pattern, 961 + .set_dp_lane_settings = set_dio_dp_lane_settings, 978 962 }, 979 963 }; 980 964

+9 -8

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

··· 1325 1325 1326 1326 void dce110_link_encoder_dp_set_lane_settings( 1327 1327 struct link_encoder *enc, 1328 - const struct link_training_settings *link_settings) 1328 + const struct dc_link_settings *link_settings, 1329 + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) 1329 1330 { 1330 1331 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1331 1332 union dpcd_training_lane_set training_lane_set = { { 0 } }; ··· 1341 1340 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS; 1342 1341 cntl.transmitter = enc110->base.transmitter; 1343 1342 cntl.connector_obj_id = enc110->base.connector; 1344 - cntl.lanes_number = link_settings->link_settings.lane_count; 1343 + cntl.lanes_number = link_settings->lane_count; 1345 1344 cntl.hpd_sel = enc110->base.hpd_source; 1346 - cntl.pixel_clock = link_settings->link_settings.link_rate * 1345 + cntl.pixel_clock = link_settings->link_rate * 1347 1346 LINK_RATE_REF_FREQ_IN_KHZ; 1348 1347 1349 - for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { 1348 + for (lane = 0; lane < link_settings->lane_count; lane++) { 1350 1349 /* translate lane settings */ 1351 1350 1352 1351 training_lane_set.bits.VOLTAGE_SWING_SET = 1353 - link_settings->lane_settings[lane].VOLTAGE_SWING; 1352 + lane_settings[lane].VOLTAGE_SWING; 1354 1353 training_lane_set.bits.PRE_EMPHASIS_SET = 1355 - link_settings->lane_settings[lane].PRE_EMPHASIS; 1354 + lane_settings[lane].PRE_EMPHASIS; 1356 1355 1357 1356 /* post cursor 2 setting only applies to HBR2 link rate */ 1358 - if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) { 1357 + if (link_settings->link_rate == LINK_RATE_HIGH2) { 1359 1358 /* this is passed to VBIOS 1360 1359 * to program post cursor 2 level */ 1361 1360 1362 1361 training_lane_set.bits.POST_CURSOR2_SET = 1363 - link_settings->lane_settings[lane].POST_CURSOR2; 1362 + lane_settings[lane].POST_CURSOR2; 1364 1363 } 1365 1364 1366 1365 cntl.lane_select = lane;

+2 -1

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

··· 279 279 /* set DP lane settings */ 280 280 void dce110_link_encoder_dp_set_lane_settings( 281 281 struct link_encoder *enc, 282 - const struct link_training_settings *link_settings); 282 + const struct dc_link_settings *link_settings, 283 + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]); 283 284 284 285 void dce110_link_encoder_dp_set_phy_pattern( 285 286 struct link_encoder *enc,

+9 -9

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

··· 1101 1101 1102 1102 void dcn10_link_encoder_dp_set_lane_settings( 1103 1103 struct link_encoder *enc, 1104 - const struct link_training_settings *link_settings) 1104 + const struct dc_link_settings *link_settings, 1105 + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) 1105 1106 { 1106 1107 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 1107 1108 union dpcd_training_lane_set training_lane_set = { { 0 } }; ··· 1117 1116 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS; 1118 1117 cntl.transmitter = enc10->base.transmitter; 1119 1118 cntl.connector_obj_id = enc10->base.connector; 1120 - cntl.lanes_number = link_settings->link_settings.lane_count; 1119 + cntl.lanes_number = link_settings->lane_count; 1121 1120 cntl.hpd_sel = enc10->base.hpd_source; 1122 - cntl.pixel_clock = link_settings->link_settings.link_rate * 1123 - LINK_RATE_REF_FREQ_IN_KHZ; 1121 + cntl.pixel_clock = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 1124 1122 1125 - for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { 1123 + for (lane = 0; lane < link_settings->lane_count; lane++) { 1126 1124 /* translate lane settings */ 1127 1125 1128 1126 training_lane_set.bits.VOLTAGE_SWING_SET = 1129 - link_settings->lane_settings[lane].VOLTAGE_SWING; 1127 + lane_settings[lane].VOLTAGE_SWING; 1130 1128 training_lane_set.bits.PRE_EMPHASIS_SET = 1131 - link_settings->lane_settings[lane].PRE_EMPHASIS; 1129 + lane_settings[lane].PRE_EMPHASIS; 1132 1130 1133 1131 /* post cursor 2 setting only applies to HBR2 link rate */ 1134 - if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) { 1132 + if (link_settings->link_rate == LINK_RATE_HIGH2) { 1135 1133 /* this is passed to VBIOS 1136 1134 * to program post cursor 2 level 1137 1135 */ 1138 1136 training_lane_set.bits.POST_CURSOR2_SET = 1139 - link_settings->lane_settings[lane].POST_CURSOR2; 1137 + lane_settings[lane].POST_CURSOR2; 1140 1138 } 1141 1139 1142 1140 cntl.lane_select = lane;

+2 -1

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

··· 581 581 /* set DP lane settings */ 582 582 void dcn10_link_encoder_dp_set_lane_settings( 583 583 struct link_encoder *enc, 584 - const struct link_training_settings *link_settings); 584 + const struct dc_link_settings *link_settings, 585 + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]); 585 586 586 587 void dcn10_link_encoder_dp_set_phy_pattern( 587 588 struct link_encoder *enc,

+2 -1

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

··· 162 162 void (*disable_output)(struct link_encoder *link_enc, 163 163 enum signal_type signal); 164 164 void (*dp_set_lane_settings)(struct link_encoder *enc, 165 - const struct link_training_settings *link_settings); 165 + const struct dc_link_settings *link_settings, 166 + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]); 166 167 void (*dp_set_phy_pattern)(struct link_encoder *enc, 167 168 const struct encoder_set_dp_phy_pattern_param *para); 168 169 void (*update_mst_stream_allocation_table)(

+4

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

··· 97 97 void (*set_dp_link_test_pattern)(struct dc_link *link, 98 98 const struct link_resource *link_res, 99 99 struct encoder_set_dp_phy_pattern_param *tp_params); 100 + void (*set_dp_lane_settings)(struct dc_link *link, 101 + const struct link_resource *link_res, 102 + const struct dc_link_settings *link_settings, 103 + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]); 100 104 }; 101 105 102 106 struct link_hwss {

+2 -1

drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c

··· 63 63 64 64 static void virtual_link_encoder_dp_set_lane_settings( 65 65 struct link_encoder *enc, 66 - const struct link_training_settings *link_settings) {} 66 + const struct dc_link_settings *link_settings, 67 + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) {} 67 68 68 69 static void virtual_link_encoder_dp_set_phy_pattern( 69 70 struct link_encoder *enc,