drm/amdgpu: refine query function of mmhub EDC counter in vg20

+178 -50

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

··· 27 27 #include "mmhub/mmhub_1_0_offset.h" 28 28 #include "mmhub/mmhub_1_0_sh_mask.h" 29 29 #include "mmhub/mmhub_1_0_default.h" 30 - #include "mmhub/mmhub_9_4_0_offset.h" 31 30 #include "vega10_enum.h" 32 - 31 + #include "soc15.h" 33 32 #include "soc15_common.h" 34 33 35 34 #define mmDAGB0_CNTL_MISC2_RV 0x008f 36 35 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0 37 - 38 - #define EA_EDC_CNT_MASK 0x3 39 - #define EA_EDC_CNT_SHIFT 0x2 40 36 41 37 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) 42 38 { ··· 558 562 *flags |= AMD_CG_SUPPORT_MC_LS; 559 563 } 560 564 565 + static const struct soc15_ras_field_entry mmhub_v1_0_ras_fields[] = { 566 + { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 567 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT), 568 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT), 569 + }, 570 + { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 571 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT), 572 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT), 573 + }, 574 + { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 575 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT), 576 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT), 577 + }, 578 + { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 579 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT), 580 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT), 581 + }, 582 + { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 583 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT), 584 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT), 585 + }, 586 + { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 587 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT), 588 + 0, 0, 589 + }, 590 + { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 591 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT), 592 + 0, 0, 593 + }, 594 + { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 595 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT), 596 + 0, 0, 597 + }, 598 + { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 599 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT), 600 + 0, 0, 601 + }, 602 + { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 603 + SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT), 604 + 0, 0, 605 + }, 606 + { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 607 + SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT), 608 + SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT), 609 + }, 610 + { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 611 + SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT), 612 + SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT), 613 + }, 614 + { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 615 + SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT), 616 + SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT), 617 + }, 618 + { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 619 + SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT), 620 + 0, 0, 621 + }, 622 + { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 623 + SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT), 624 + 0, 0, 625 + }, 626 + { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 627 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT), 628 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT), 629 + }, 630 + { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 631 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT), 632 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT), 633 + }, 634 + { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 635 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT), 636 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT), 637 + }, 638 + { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 639 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT), 640 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT), 641 + }, 642 + { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 643 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT), 644 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT), 645 + }, 646 + { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 647 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT), 648 + 0, 0, 649 + }, 650 + { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 651 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT), 652 + 0, 0, 653 + }, 654 + { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 655 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT), 656 + 0, 0, 657 + }, 658 + { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 659 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT), 660 + 0, 0, 661 + }, 662 + { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 663 + SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT), 664 + 0, 0, 665 + }, 666 + { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 667 + SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT), 668 + SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT), 669 + }, 670 + { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 671 + SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT), 672 + SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT), 673 + }, 674 + { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 675 + SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT), 676 + SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT), 677 + }, 678 + { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 679 + SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT), 680 + 0, 0, 681 + }, 682 + { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 683 + SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT), 684 + 0, 0, 685 + } 686 + }; 687 + 688 + static const struct soc15_reg_entry mmhub_v1_0_edc_cnt_regs[] = { 689 + { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 0, 0, 0}, 690 + { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 0, 0, 0}, 691 + { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 0, 0, 0}, 692 + { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 0, 0, 0}, 693 + }; 694 + 695 + static int mmhub_v1_0_get_ras_error_count(const struct soc15_reg_entry *reg, 696 + uint32_t value, uint32_t *sec_count, uint32_t *ded_count) 697 + { 698 + uint32_t i; 699 + uint32_t sec_cnt, ded_cnt; 700 + 701 + for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_ras_fields); i++) { 702 + if(mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset) 703 + continue; 704 + 705 + sec_cnt = (value & 706 + mmhub_v1_0_ras_fields[i].sec_count_mask) >> 707 + mmhub_v1_0_ras_fields[i].sec_count_shift; 708 + if (sec_cnt) { 709 + DRM_INFO("MMHUB SubBlock %s, SEC %d\n", 710 + mmhub_v1_0_ras_fields[i].name, 711 + sec_cnt); 712 + *sec_count += sec_cnt; 713 + } 714 + 715 + ded_cnt = (value & 716 + mmhub_v1_0_ras_fields[i].ded_count_mask) >> 717 + mmhub_v1_0_ras_fields[i].ded_count_shift; 718 + if (ded_cnt) { 719 + DRM_INFO("MMHUB SubBlock %s, DED %d\n", 720 + mmhub_v1_0_ras_fields[i].name, 721 + ded_cnt); 722 + *ded_count += ded_cnt; 723 + } 724 + } 725 + 726 + return 0; 727 + } 728 + 561 729 static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev, 562 730 void *ras_error_status) 563 731 { 564 - int i; 565 - uint32_t ea0_edc_cnt, ea0_edc_cnt2; 566 - uint32_t ea1_edc_cnt, ea1_edc_cnt2; 567 732 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 733 + uint32_t sec_count = 0, ded_count = 0; 734 + uint32_t i; 735 + uint32_t reg_value; 568 736 569 - /* EDC CNT will be cleared automatically after read */ 570 - ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20); 571 - ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20); 572 - ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20); 573 - ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20); 737 + err_data->ue_count = 0; 738 + err_data->ce_count = 0; 574 739 575 - /* error count of each error type is recorded by 2 bits, 576 - * ce and ue count in EDC_CNT 577 - */ 578 - for (i = 0; i < 5; i++) { 579 - err_data->ce_count += (ea0_edc_cnt & EA_EDC_CNT_MASK); 580 - err_data->ce_count += (ea1_edc_cnt & EA_EDC_CNT_MASK); 581 - ea0_edc_cnt >>= EA_EDC_CNT_SHIFT; 582 - ea1_edc_cnt >>= EA_EDC_CNT_SHIFT; 583 - err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK); 584 - err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK); 585 - ea0_edc_cnt >>= EA_EDC_CNT_SHIFT; 586 - ea1_edc_cnt >>= EA_EDC_CNT_SHIFT; 587 - } 588 - /* successive ue count in EDC_CNT */ 589 - for (i = 0; i < 5; i++) { 590 - err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK); 591 - err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK); 592 - ea0_edc_cnt >>= EA_EDC_CNT_SHIFT; 593 - ea1_edc_cnt >>= EA_EDC_CNT_SHIFT; 740 + for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++) { 741 + reg_value = 742 + RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); 743 + if (reg_value) 744 + mmhub_v1_0_get_ras_error_count(&mmhub_v1_0_edc_cnt_regs[i], 745 + reg_value, &sec_count, &ded_count); 594 746 } 595 747 596 - /* ce and ue count in EDC_CNT2 */ 597 - for (i = 0; i < 3; i++) { 598 - err_data->ce_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK); 599 - err_data->ce_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK); 600 - ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT; 601 - ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT; 602 - err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK); 603 - err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK); 604 - ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT; 605 - ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT; 606 - } 607 - /* successive ue count in EDC_CNT2 */ 608 - for (i = 0; i < 6; i++) { 609 - err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK); 610 - err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK); 611 - ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT; 612 - ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT; 613 - } 748 + err_data->ce_count += sec_count; 749 + err_data->ue_count += ded_count; 614 750 } 615 751 616 752 const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {

+2 -2

drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c

··· 63 63 #include "soc15_hw_ip.h" 64 64 #include "vega10_ip_offset.h" 65 65 #include "nbio/nbio_6_1_offset.h" 66 - #include "mmhub/mmhub_9_4_0_offset.h" 67 - #include "mmhub/mmhub_9_4_0_sh_mask.h" 66 + #include "mmhub/mmhub_1_0_offset.h" 67 + #include "mmhub/mmhub_1_0_sh_mask.h" 68 68 #include "reg_helper.h" 69 69 70 70 #include "dce100/dce100_resource.h"

+16

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h

··· 1964 1964 #define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x084a 1965 1965 #define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1966 1966 1967 + /* MMEA */ 1968 + #define mmMMEA0_EDC_CNT_VG20 0x0206 1969 + #define mmMMEA0_EDC_CNT_VG20_BASE_IDX 0 1970 + #define mmMMEA0_EDC_CNT2_VG20 0x0207 1971 + #define mmMMEA0_EDC_CNT2_VG20_BASE_IDX 0 1972 + #define mmMMEA1_EDC_CNT_VG20 0x0346 1973 + #define mmMMEA1_EDC_CNT_VG20_BASE_IDX 0 1974 + #define mmMMEA1_EDC_CNT2_VG20 0x0347 1975 + #define mmMMEA1_EDC_CNT2_VG20_BASE_IDX 0 1976 + 1977 + // addressBlock: mmhub_utcl2_vmsharedpfdec 1978 + // base address: 0x6a040 1979 + #define mmMC_VM_XGMI_LFB_CNTL 0x0823 1980 + #define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 1981 + #define mmMC_VM_XGMI_LFB_SIZE 0x0824 1982 + #define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 1967 1983 #endif

+122

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h

··· 10124 10124 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 10125 10125 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 10126 10126 10127 + //MMEA0_EDC_CNT 10128 + #define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 10129 + #define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 10130 + #define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 10131 + #define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 10132 + #define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 10133 + #define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 10134 + #define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 10135 + #define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 10136 + #define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 10137 + #define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 10138 + #define MMEA0_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 10139 + #define MMEA0_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 10140 + #define MMEA0_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 10141 + #define MMEA0_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 10142 + #define MMEA0_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 10143 + #define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 10144 + #define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 10145 + #define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 10146 + #define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 10147 + #define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 10148 + #define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 10149 + #define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 10150 + #define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 10151 + #define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 10152 + #define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 10153 + #define MMEA0_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 10154 + #define MMEA0_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 10155 + #define MMEA0_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 10156 + #define MMEA0_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 10157 + #define MMEA0_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 10158 + //MMEA0_EDC_CNT2 10159 + #define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 10160 + #define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 10161 + #define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 10162 + #define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 10163 + #define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 10164 + #define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 10165 + #define MMEA0_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 10166 + #define MMEA0_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 10167 + #define MMEA0_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT__SHIFT 0x10 10168 + #define MMEA0_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT__SHIFT 0x12 10169 + #define MMEA0_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT__SHIFT 0x14 10170 + #define MMEA0_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT__SHIFT 0x16 10171 + #define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 10172 + #define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 10173 + #define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 10174 + #define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 10175 + #define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 10176 + #define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 10177 + #define MMEA0_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 10178 + #define MMEA0_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 10179 + #define MMEA0_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 10180 + #define MMEA0_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 10181 + #define MMEA0_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 10182 + #define MMEA0_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 10183 + //MMEA1_EDC_CNT 10184 + #define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 10185 + #define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 10186 + #define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 10187 + #define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 10188 + #define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 10189 + #define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 10190 + #define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 10191 + #define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 10192 + #define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 10193 + #define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 10194 + #define MMEA1_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 10195 + #define MMEA1_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 10196 + #define MMEA1_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 10197 + #define MMEA1_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 10198 + #define MMEA1_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 10199 + #define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 10200 + #define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 10201 + #define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 10202 + #define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 10203 + #define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 10204 + #define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 10205 + #define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 10206 + #define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 10207 + #define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 10208 + #define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 10209 + #define MMEA1_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 10210 + #define MMEA1_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 10211 + #define MMEA1_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 10212 + #define MMEA1_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 10213 + #define MMEA1_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 10214 + //MMEA1_EDC_CNT2 10215 + #define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 10216 + #define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 10217 + #define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 10218 + #define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 10219 + #define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 10220 + #define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 10221 + #define MMEA1_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 10222 + #define MMEA1_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 10223 + #define MMEA1_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT__SHIFT 0x10 10224 + #define MMEA1_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT__SHIFT 0x12 10225 + #define MMEA1_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT__SHIFT 0x14 10226 + #define MMEA1_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT__SHIFT 0x16 10227 + #define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 10228 + #define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 10229 + #define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 10230 + #define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 10231 + #define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 10232 + #define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 10233 + #define MMEA1_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 10234 + #define MMEA1_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 10235 + #define MMEA1_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 10236 + #define MMEA1_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 10237 + #define MMEA1_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 10238 + #define MMEA1_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 10239 + 10240 + // addressBlock: mmhub_utcl2_vmsharedpfdec 10241 + //MC_VM_XGMI_LFB_CNTL 10242 + #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 10243 + #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 10244 + #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L 10245 + #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000070L 10246 + //MC_VM_XGMI_LFB_SIZE 10247 + #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 10248 + #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL 10127 10249 #endif

-53

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h

··· 1 - /* 2 - * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 - * 4 - * Permission is hereby granted, free of charge, to any person obtaining a 5 - * copy of this software and associated documentation files (the "Software"), 6 - * to deal in the Software without restriction, including without limitation 7 - * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 - * and/or sell copies of the Software, and to permit persons to whom the 9 - * Software is furnished to do so, subject to the following conditions: 10 - * 11 - * The above copyright notice and this permission notice shall be included 12 - * in all copies or substantial portions of the Software. 13 - * 14 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 - */ 21 - #ifndef _mmhub_9_4_0_OFFSET_HEADER 22 - #define _mmhub_9_4_0_OFFSET_HEADER 23 - 24 - /* MMEA */ 25 - #define mmMMEA0_SDP_ARB_FINAL_VG20 0x01ee 26 - #define mmMMEA0_SDP_ARB_FINAL_VG20_BASE_IDX 0 27 - #define mmMMEA0_EDC_CNT_VG20 0x0206 28 - #define mmMMEA0_EDC_CNT_VG20_BASE_IDX 0 29 - #define mmMMEA0_EDC_CNT2_VG20 0x0207 30 - #define mmMMEA0_EDC_CNT2_VG20_BASE_IDX 0 31 - #define mmMMEA0_EDC_MODE_VG20 0x0210 32 - #define mmMMEA0_EDC_MODE_VG20_BASE_IDX 0 33 - #define mmMMEA0_ERR_STATUS_VG20 0x0211 34 - #define mmMMEA0_ERR_STATUS_VG20_BASE_IDX 0 35 - #define mmMMEA1_SDP_ARB_FINAL_VG20 0x032e 36 - #define mmMMEA1_SDP_ARB_FINAL_VG20_BASE_IDX 0 37 - #define mmMMEA1_EDC_CNT_VG20 0x0346 38 - #define mmMMEA1_EDC_CNT_VG20_BASE_IDX 0 39 - #define mmMMEA1_EDC_CNT2_VG20 0x0347 40 - #define mmMMEA1_EDC_CNT2_VG20_BASE_IDX 0 41 - #define mmMMEA1_EDC_MODE_VG20 0x0350 42 - #define mmMMEA1_EDC_MODE_VG20_BASE_IDX 0 43 - #define mmMMEA1_ERR_STATUS_VG20 0x0351 44 - #define mmMMEA1_ERR_STATUS_VG20_BASE_IDX 0 45 - 46 - // addressBlock: mmhub_utcl2_vmsharedpfdec 47 - // base address: 0x6a040 48 - #define mmMC_VM_XGMI_LFB_CNTL 0x0823 49 - #define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 50 - #define mmMC_VM_XGMI_LFB_SIZE 0x0824 51 - #define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 52 - 53 - #endif

-257

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h

··· 1 - /* 2 - * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 - * 4 - * Permission is hereby granted, free of charge, to any person obtaining a 5 - * copy of this software and associated documentation files (the "Software"), 6 - * to deal in the Software without restriction, including without limitation 7 - * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 - * and/or sell copies of the Software, and to permit persons to whom the 9 - * Software is furnished to do so, subject to the following conditions: 10 - * 11 - * The above copyright notice and this permission notice shall be included 12 - * in all copies or substantial portions of the Software. 13 - * 14 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 - */ 21 - #ifndef _mmhub_9_4_0_SH_MASK_HEADER 22 - #define _mmhub_9_4_0_SH_MASK_HEADER 23 - 24 - //MMEA0_SDP_ARB_FINAL 25 - #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 26 - #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 27 - #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 28 - #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 29 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 30 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 31 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 32 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 33 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 34 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 35 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 36 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 37 - #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 38 - #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 39 - #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 40 - #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 41 - #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 42 - #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 43 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 44 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 45 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 46 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 47 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 48 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 49 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 50 - #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 51 - #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 52 - #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 53 - //MMEA0_EDC_CNT 54 - #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 55 - #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 56 - #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 57 - #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 58 - #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 59 - #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 60 - #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 61 - #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 62 - #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 63 - #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 64 - #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 65 - #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 66 - #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 67 - #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 68 - #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 69 - #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 70 - #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 71 - #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 72 - #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 73 - #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 74 - #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 75 - #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 76 - #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 77 - #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 78 - #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 79 - #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 80 - #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 81 - #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 82 - #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 83 - #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 84 - //MMEA0_EDC_CNT2 85 - #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 86 - #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 87 - #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 88 - #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 89 - #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 90 - #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 91 - #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 92 - #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 93 - #define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 94 - #define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 95 - #define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 96 - #define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 97 - #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 98 - #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 99 - #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 100 - #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 101 - #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 102 - #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 103 - #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 104 - #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 105 - #define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 106 - #define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 107 - #define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 108 - #define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 109 - //MMEA0_EDC_MODE 110 - #define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 111 - #define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 112 - #define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 113 - #define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d 114 - #define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f 115 - #define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 116 - #define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L 117 - #define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L 118 - #define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L 119 - #define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L 120 - //MMEA0_ERR_STATUS 121 - #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 122 - #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 123 - #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 124 - #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 125 - #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 126 - #define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 127 - #define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd 128 - #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 129 - #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 130 - #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 131 - #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 132 - #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 133 - #define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 134 - #define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 135 - //MMEA1_SDP_ARB_FINAL 136 - #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 137 - #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 138 - #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 139 - #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 140 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 141 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 142 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 143 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 144 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 145 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 146 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 147 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 148 - #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 149 - #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 150 - #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 151 - #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 152 - #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 153 - #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 154 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 155 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 156 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 157 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 158 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 159 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 160 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 161 - #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 162 - #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 163 - #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 164 - //MMEA1_EDC_CNT 165 - #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 166 - #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 167 - #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 168 - #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 169 - #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 170 - #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 171 - #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 172 - #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 173 - #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 174 - #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 175 - #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 176 - #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 177 - #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 178 - #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 179 - #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 180 - #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 181 - #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 182 - #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 183 - #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 184 - #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 185 - #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 186 - #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 187 - #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 188 - #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 189 - #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 190 - #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 191 - #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 192 - #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 193 - #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 194 - #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 195 - //MMEA1_EDC_CNT2 196 - #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 197 - #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 198 - #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 199 - #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 200 - #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 201 - #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 202 - #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 203 - #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 204 - #define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 205 - #define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 206 - #define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 207 - #define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 208 - #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 209 - #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 210 - #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 211 - #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 212 - #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 213 - #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 214 - #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 215 - #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 216 - #define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 217 - #define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 218 - #define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 219 - #define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 220 - //MMEA1_EDC_MODE 221 - #define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 222 - #define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 223 - #define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 224 - #define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d 225 - #define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f 226 - #define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 227 - #define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L 228 - #define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L 229 - #define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L 230 - #define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L 231 - //MMEA1_ERR_STATUS 232 - #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 233 - #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 234 - #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 235 - #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 236 - #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 237 - #define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 238 - #define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd 239 - #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 240 - #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 241 - #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 242 - #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 243 - #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 244 - #define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 245 - #define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 246 - 247 - // addressBlock: mmhub_utcl2_vmsharedpfdec 248 - //MC_VM_XGMI_LFB_CNTL 249 - #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 250 - #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 251 - #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L 252 - #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000070L 253 - //MC_VM_XGMI_LFB_SIZE 254 - #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 255 - #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL 256 - 257 - #endif