tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/nouveau/sw: rename from software (no binary change)
Shorter device name, make consistent with our engine enums.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+351
-351
+1
-1
drivers/gpu/drm/nouveau/include/nvif/device.h
+1
-1
drivers/gpu/drm/nouveau/include/nvif/device.h
-51
drivers/gpu/drm/nouveau/include/nvkm/engine/software.h
-51
drivers/gpu/drm/nouveau/include/nvkm/engine/software.h
···
1
-
#ifndef __NOUVEAU_SOFTWARE_H__
2
-
#define __NOUVEAU_SOFTWARE_H__
3
-
4
-
#include <core/engine.h>
5
-
#include <core/engctx.h>
6
-
7
-
struct nouveau_software_chan {
8
-
struct nouveau_engctx base;
9
-
10
-
int (*flip)(void *);
11
-
void *flip_data;
12
-
};
13
-
14
-
#define nouveau_software_context_create(p,e,c,d) \
15
-
nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d))
16
-
#define nouveau_software_context_destroy(d) \
17
-
nouveau_engctx_destroy(&(d)->base)
18
-
#define nouveau_software_context_init(d) \
19
-
nouveau_engctx_init(&(d)->base)
20
-
#define nouveau_software_context_fini(d,s) \
21
-
nouveau_engctx_fini(&(d)->base, (s))
22
-
23
-
#define _nouveau_software_context_dtor _nouveau_engctx_dtor
24
-
#define _nouveau_software_context_init _nouveau_engctx_init
25
-
#define _nouveau_software_context_fini _nouveau_engctx_fini
26
-
27
-
struct nouveau_software {
28
-
struct nouveau_engine base;
29
-
};
30
-
31
-
#define nouveau_software_create(p,e,c,d) \
32
-
nouveau_engine_create((p), (e), (c), true, "SW", "software", (d))
33
-
#define nouveau_software_destroy(d) \
34
-
nouveau_engine_destroy(&(d)->base)
35
-
#define nouveau_software_init(d) \
36
-
nouveau_engine_init(&(d)->base)
37
-
#define nouveau_software_fini(d,s) \
38
-
nouveau_engine_fini(&(d)->base, (s))
39
-
40
-
#define _nouveau_software_dtor _nouveau_engine_dtor
41
-
#define _nouveau_software_init _nouveau_engine_init
42
-
#define _nouveau_software_fini _nouveau_engine_fini
43
-
44
-
extern struct nouveau_oclass *nv04_software_oclass;
45
-
extern struct nouveau_oclass *nv10_software_oclass;
46
-
extern struct nouveau_oclass *nv50_software_oclass;
47
-
extern struct nouveau_oclass *nvc0_software_oclass;
48
-
49
-
void nv04_software_intr(struct nouveau_subdev *);
50
-
51
-
#endif
+51
drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
+51
drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
···
1
+
#ifndef __NOUVEAU_SW_H__
2
+
#define __NOUVEAU_SW_H__
3
+
4
+
#include <core/engine.h>
5
+
#include <core/engctx.h>
6
+
7
+
struct nouveau_sw_chan {
8
+
struct nouveau_engctx base;
9
+
10
+
int (*flip)(void *);
11
+
void *flip_data;
12
+
};
13
+
14
+
#define nouveau_sw_context_create(p,e,c,d) \
15
+
nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d))
16
+
#define nouveau_sw_context_destroy(d) \
17
+
nouveau_engctx_destroy(&(d)->base)
18
+
#define nouveau_sw_context_init(d) \
19
+
nouveau_engctx_init(&(d)->base)
20
+
#define nouveau_sw_context_fini(d,s) \
21
+
nouveau_engctx_fini(&(d)->base, (s))
22
+
23
+
#define _nouveau_sw_context_dtor _nouveau_engctx_dtor
24
+
#define _nouveau_sw_context_init _nouveau_engctx_init
25
+
#define _nouveau_sw_context_fini _nouveau_engctx_fini
26
+
27
+
struct nouveau_sw {
28
+
struct nouveau_engine base;
29
+
};
30
+
31
+
#define nouveau_sw_create(p,e,c,d) \
32
+
nouveau_engine_create((p), (e), (c), true, "SW", "software", (d))
33
+
#define nouveau_sw_destroy(d) \
34
+
nouveau_engine_destroy(&(d)->base)
35
+
#define nouveau_sw_init(d) \
36
+
nouveau_engine_init(&(d)->base)
37
+
#define nouveau_sw_fini(d,s) \
38
+
nouveau_engine_fini(&(d)->base, (s))
39
+
40
+
#define _nouveau_sw_dtor _nouveau_engine_dtor
41
+
#define _nouveau_sw_init _nouveau_engine_init
42
+
#define _nouveau_sw_fini _nouveau_engine_fini
43
+
44
+
extern struct nouveau_oclass *nv04_sw_oclass;
45
+
extern struct nouveau_oclass *nv10_sw_oclass;
46
+
extern struct nouveau_oclass *nv50_sw_oclass;
47
+
extern struct nouveau_oclass *nvc0_sw_oclass;
48
+
49
+
void nv04_sw_intr(struct nouveau_subdev *);
50
+
51
+
#endif
+1
-1
drivers/gpu/drm/nouveau/nouveau_chan.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_chan.c
···
282
282
struct nvif_device *device = chan->device;
283
283
struct nouveau_cli *cli = (void *)nvif_client(&device->base);
284
284
struct nouveau_mmu *mmu = nvkm_mmu(device);
285
-
struct nouveau_software_chan *swch;
285
+
struct nouveau_sw_chan *swch;
286
286
struct nv_dma_v0 args = {};
287
287
int ret, i;
288
288
+1
-1
drivers/gpu/drm/nouveau/nouveau_drm.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_drm.c
···
231
231
ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW,
232
232
nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw);
233
233
if (ret == 0) {
234
-
struct nouveau_software_chan *swch;
234
+
struct nouveau_sw_chan *swch;
235
235
ret = RING_SPACE(drm->channel, 2);
236
236
if (ret == 0) {
237
237
if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
+1
-1
drivers/gpu/drm/nouveau/nouveau_reg.h
+1
-1
drivers/gpu/drm/nouveau/nouveau_reg.h
···
72
72
# define NV_RAMHT_CONTEXT_VALID (1<<31)
73
73
# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24
74
74
# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16
75
-
# define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0
75
+
# define NV_RAMHT_CONTEXT_ENGINE_SW 0
76
76
# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1
77
77
# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0
78
78
# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+3
-3
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+3
-3
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
···
45
45
#include <engine/device.h>
46
46
#include <engine/dmaobj.h>
47
47
#include <engine/fifo.h>
48
-
#include <engine/software.h>
48
+
#include <engine/sw.h>
49
49
#include <engine/gr.h>
50
50
#include <engine/disp.h>
51
51
#include <engine/ce.h>
···
85
85
#endif
86
86
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
87
87
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
88
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
88
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
89
89
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
90
90
device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
91
91
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
···
129
129
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
130
130
#if 0
131
131
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
132
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
132
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
133
133
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
134
134
#endif
135
135
device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
+3
-3
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+3
-3
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
···
36
36
#include <engine/device.h>
37
37
#include <engine/dmaobj.h>
38
38
#include <engine/fifo.h>
39
-
#include <engine/software.h>
39
+
#include <engine/sw.h>
40
40
#include <engine/gr.h>
41
41
#include <engine/disp.h>
42
42
···
58
58
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
59
59
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
60
60
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
61
-
device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
61
+
device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
62
62
device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
63
63
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
64
64
break;
···
76
76
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
77
77
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
78
78
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
79
-
device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
79
+
device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
80
80
device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
81
81
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
82
82
break;
+8
-8
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+8
-8
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
···
37
37
#include <engine/device.h>
38
38
#include <engine/dmaobj.h>
39
39
#include <engine/fifo.h>
40
-
#include <engine/software.h>
40
+
#include <engine/sw.h>
41
41
#include <engine/gr.h>
42
42
#include <engine/disp.h>
43
43
···
77
77
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
78
78
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
79
79
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
80
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
80
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
81
81
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
82
82
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
83
83
break;
···
96
96
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
97
97
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
98
98
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
99
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
99
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
100
100
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
101
101
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
102
102
break;
···
115
115
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
116
116
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
117
117
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
118
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
118
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
119
119
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
120
120
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
121
121
break;
···
134
134
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
135
135
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
136
136
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
137
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
137
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
138
138
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
139
139
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
140
140
break;
···
153
153
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
154
154
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
155
155
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
156
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
156
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
157
157
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
158
158
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
159
159
break;
···
172
172
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
173
173
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
174
174
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
175
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
175
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
176
176
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
177
177
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
178
178
break;
···
191
191
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
192
192
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
193
193
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
194
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
194
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
195
195
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
196
196
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
197
197
break;
+5
-5
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+5
-5
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
···
38
38
#include <engine/device.h>
39
39
#include <engine/dmaobj.h>
40
40
#include <engine/fifo.h>
41
-
#include <engine/software.h>
41
+
#include <engine/sw.h>
42
42
#include <engine/gr.h>
43
43
#include <engine/disp.h>
44
44
···
61
61
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
62
62
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
63
63
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
64
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
64
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
65
65
device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass;
66
66
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
67
67
break;
···
80
80
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
81
81
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
82
82
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
83
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
83
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
84
84
device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
85
85
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
86
86
break;
···
99
99
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
100
100
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
101
101
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
102
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
102
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
103
103
device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
104
104
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
105
105
break;
···
118
118
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
119
119
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
120
120
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
121
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
121
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
122
122
device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass;
123
123
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
124
124
break;
+6
-6
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+6
-6
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
···
37
37
#include <engine/device.h>
38
38
#include <engine/dmaobj.h>
39
39
#include <engine/fifo.h>
40
-
#include <engine/software.h>
40
+
#include <engine/sw.h>
41
41
#include <engine/gr.h>
42
42
#include <engine/mpeg.h>
43
43
#include <engine/disp.h>
···
61
61
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
62
62
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
63
63
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
64
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
64
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
65
65
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
66
66
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
67
67
break;
···
80
80
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
81
81
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
82
82
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
83
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
83
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
84
84
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
85
85
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
86
86
break;
···
99
99
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
100
100
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
101
101
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
102
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
102
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
103
103
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
104
104
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
105
105
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
119
119
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
120
120
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
121
121
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
122
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
122
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
123
123
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
124
124
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
125
125
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
139
139
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
140
140
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
141
141
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
142
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
142
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
143
143
device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass;
144
144
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
145
145
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
+17
-17
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+17
-17
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
···
40
40
#include <engine/device.h>
41
41
#include <engine/dmaobj.h>
42
42
#include <engine/fifo.h>
43
-
#include <engine/software.h>
43
+
#include <engine/sw.h>
44
44
#include <engine/gr.h>
45
45
#include <engine/mpeg.h>
46
46
#include <engine/disp.h>
···
67
67
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
68
68
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
69
69
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
70
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
70
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
71
71
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
72
72
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
73
73
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
90
90
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
91
91
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
92
92
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
93
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
93
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
94
94
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
95
95
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
96
96
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
113
113
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
114
114
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
115
115
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
116
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
116
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
117
117
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
118
118
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
119
119
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
136
136
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
137
137
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
138
138
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
139
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
139
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
140
140
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
141
141
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
142
142
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
159
159
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
160
160
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
161
161
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
162
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
162
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
163
163
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
164
164
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
165
165
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
182
182
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
183
183
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
184
184
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
185
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
185
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
186
186
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
187
187
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
188
188
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
205
205
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
206
206
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
207
207
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
208
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
208
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
209
209
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
210
210
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
211
211
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
228
228
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
229
229
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
230
230
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
231
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
231
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
232
232
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
233
233
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
234
234
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
251
251
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
252
252
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
253
253
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
254
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
254
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
255
255
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
256
256
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
257
257
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
274
274
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
275
275
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
276
276
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
277
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
277
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
278
278
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
279
279
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
280
280
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
297
297
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
298
298
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
299
299
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
300
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
300
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
301
301
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
302
302
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
303
303
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
320
320
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
321
321
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
322
322
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
323
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
323
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
324
324
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
325
325
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
326
326
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
343
343
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
344
344
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
345
345
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
346
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
346
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
347
347
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
348
348
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
349
349
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
366
366
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
367
367
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
368
368
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
369
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
369
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
370
370
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
371
371
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
372
372
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
389
389
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
390
390
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
391
391
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
392
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
392
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
393
393
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
394
394
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
395
395
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
···
412
412
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
413
413
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
414
414
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
415
-
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
415
+
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
416
416
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
417
417
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
418
418
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
+15
-15
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+15
-15
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
···
43
43
#include <engine/device.h>
44
44
#include <engine/dmaobj.h>
45
45
#include <engine/fifo.h>
46
-
#include <engine/software.h>
46
+
#include <engine/sw.h>
47
47
#include <engine/gr.h>
48
48
#include <engine/mpeg.h>
49
49
#include <engine/vp.h>
···
80
80
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
81
81
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
82
82
device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
83
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
83
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
84
84
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
85
85
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
86
86
device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
···
106
106
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
107
107
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
108
108
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
109
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
109
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
110
110
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
111
111
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
112
112
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
···
135
135
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
136
136
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
137
137
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
138
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
138
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
139
139
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
140
140
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
141
141
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
···
164
164
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
165
165
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
166
166
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
167
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
167
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
168
168
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
169
169
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
170
170
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
···
193
193
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
194
194
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
195
195
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
196
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
196
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
197
197
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
198
198
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
199
199
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
···
222
222
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
223
223
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
224
224
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
225
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
225
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
226
226
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
227
227
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
228
228
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
···
251
251
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
252
252
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
253
253
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
254
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
254
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
255
255
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
256
256
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
257
257
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
···
280
280
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
281
281
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
282
282
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
283
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
283
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
284
284
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
285
285
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
286
286
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
···
309
309
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
310
310
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
311
311
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
312
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
312
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
313
313
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
314
314
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
315
315
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
···
338
338
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
339
339
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
340
340
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
341
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
341
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
342
342
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
343
343
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
344
344
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
···
368
368
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
369
369
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
370
370
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
371
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
371
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
372
372
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
373
373
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
374
374
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
···
399
399
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
400
400
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
401
401
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
402
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
402
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
403
403
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
404
404
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
405
405
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
···
429
429
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
430
430
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
431
431
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
432
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
432
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
433
433
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
434
434
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
435
435
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
···
459
459
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
460
460
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
461
461
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
462
-
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
462
+
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
463
463
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
464
464
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
465
465
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
+10
-10
drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+10
-10
drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
···
45
45
#include <engine/device.h>
46
46
#include <engine/dmaobj.h>
47
47
#include <engine/fifo.h>
48
-
#include <engine/software.h>
48
+
#include <engine/sw.h>
49
49
#include <engine/gr.h>
50
50
#include <engine/vp.h>
51
51
#include <engine/bsp.h>
···
82
82
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
83
83
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
84
84
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
85
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
85
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
86
86
device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
87
87
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
88
88
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
···
115
115
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
116
116
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
117
117
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
118
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
118
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
119
119
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
120
120
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
121
121
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
···
148
148
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
149
149
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
150
150
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
151
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
151
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
152
152
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
153
153
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
154
154
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
···
180
180
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
181
181
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
182
182
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
183
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
183
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
184
184
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
185
185
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
186
186
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
···
213
213
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
214
214
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
215
215
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
216
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
216
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
217
217
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
218
218
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
219
219
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
···
245
245
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
246
246
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
247
247
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
248
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
248
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
249
249
device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
250
250
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
251
251
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
···
277
277
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
278
278
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
279
279
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
280
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
280
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
281
281
device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
282
282
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
283
283
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
···
310
310
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
311
311
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
312
312
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
313
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
313
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
314
314
device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
315
315
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
316
316
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
···
340
340
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
341
341
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
342
342
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
343
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
343
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
344
344
device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
345
345
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
346
346
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
+9
-9
drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+9
-9
drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
···
45
45
#include <engine/device.h>
46
46
#include <engine/dmaobj.h>
47
47
#include <engine/fifo.h>
48
-
#include <engine/software.h>
48
+
#include <engine/sw.h>
49
49
#include <engine/gr.h>
50
50
#include <engine/disp.h>
51
51
#include <engine/ce.h>
···
82
82
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
83
83
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
84
84
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
85
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
85
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
86
86
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
87
87
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
88
88
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
···
116
116
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
117
117
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
118
118
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
119
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
119
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
120
120
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
121
121
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
122
122
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
···
150
150
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
151
151
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
152
152
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
153
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
153
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
154
154
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
155
155
device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
156
156
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
···
176
176
device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
177
177
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
178
178
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
179
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
179
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
180
180
device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
181
181
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
182
182
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
···
206
206
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
207
207
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
208
208
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
209
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
209
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
210
210
device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass;
211
211
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
212
212
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
···
240
240
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
241
241
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
242
242
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
243
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
243
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
244
244
device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
245
245
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
246
246
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
···
274
274
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
275
275
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
276
276
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
277
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
277
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
278
278
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
279
279
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
280
280
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
···
307
307
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
308
308
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
309
309
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
310
-
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
310
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
311
311
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
312
312
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
313
313
device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c
-4
drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild
-4
drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild
+31
-49
drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
+31
-49
drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
···
25
25
#include <core/os.h>
26
26
#include <core/engctx.h>
27
27
28
-
#include <engine/software.h>
29
-
#include <engine/fifo.h>
28
+
#include <engine/sw.h>
30
29
31
-
struct nv04_software_priv {
32
-
struct nouveau_software base;
30
+
struct nv10_sw_priv {
31
+
struct nouveau_sw base;
33
32
};
34
33
35
-
struct nv04_software_chan {
36
-
struct nouveau_software_chan base;
34
+
struct nv10_sw_chan {
35
+
struct nouveau_sw_chan base;
37
36
};
38
37
39
38
/*******************************************************************************
···
40
41
******************************************************************************/
41
42
42
43
static int
43
-
nv04_software_set_ref(struct nouveau_object *object, u32 mthd,
44
-
void *data, u32 size)
45
-
{
46
-
struct nouveau_object *channel = (void *)nv_engctx(object->parent);
47
-
struct nouveau_fifo_chan *fifo = (void *)channel->parent;
48
-
atomic_set(&fifo->refcnt, *(u32*)data);
49
-
return 0;
50
-
}
51
-
52
-
static int
53
-
nv04_software_flip(struct nouveau_object *object, u32 mthd,
44
+
nv10_sw_flip(struct nouveau_object *object, u32 mthd,
54
45
void *args, u32 size)
55
46
{
56
-
struct nv04_software_chan *chan = (void *)nv_engctx(object->parent);
47
+
struct nv10_sw_chan *chan = (void *)nv_engctx(object->parent);
57
48
if (chan->base.flip)
58
49
return chan->base.flip(chan->base.flip_data);
59
50
return -EINVAL;
60
51
}
61
52
62
53
static struct nouveau_omthds
63
-
nv04_software_omthds[] = {
64
-
{ 0x0150, 0x0150, nv04_software_set_ref },
65
-
{ 0x0500, 0x0500, nv04_software_flip },
54
+
nv10_sw_omthds[] = {
55
+
{ 0x0500, 0x0500, nv10_sw_flip },
66
56
{}
67
57
};
68
58
69
59
static struct nouveau_oclass
70
-
nv04_software_sclass[] = {
71
-
{ 0x006e, &nouveau_object_ofuncs, nv04_software_omthds },
60
+
nv10_sw_sclass[] = {
61
+
{ 0x016e, &nouveau_object_ofuncs, nv10_sw_omthds },
72
62
{}
73
63
};
74
64
···
66
78
******************************************************************************/
67
79
68
80
static int
69
-
nv04_software_context_ctor(struct nouveau_object *parent,
81
+
nv10_sw_context_ctor(struct nouveau_object *parent,
70
82
struct nouveau_object *engine,
71
83
struct nouveau_oclass *oclass, void *data, u32 size,
72
84
struct nouveau_object **pobject)
73
85
{
74
-
struct nv04_software_chan *chan;
86
+
struct nv10_sw_chan *chan;
75
87
int ret;
76
88
77
-
ret = nouveau_software_context_create(parent, engine, oclass, &chan);
89
+
ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
78
90
*pobject = nv_object(chan);
79
91
if (ret)
80
92
return ret;
···
83
95
}
84
96
85
97
static struct nouveau_oclass
86
-
nv04_software_cclass = {
98
+
nv10_sw_cclass = {
87
99
.handle = NV_ENGCTX(SW, 0x04),
88
100
.ofuncs = &(struct nouveau_ofuncs) {
89
-
.ctor = nv04_software_context_ctor,
90
-
.dtor = _nouveau_software_context_dtor,
91
-
.init = _nouveau_software_context_init,
92
-
.fini = _nouveau_software_context_fini,
101
+
.ctor = nv10_sw_context_ctor,
102
+
.dtor = _nouveau_sw_context_dtor,
103
+
.init = _nouveau_sw_context_init,
104
+
.fini = _nouveau_sw_context_fini,
93
105
},
94
106
};
95
107
···
97
109
* software engine/subdev functions
98
110
******************************************************************************/
99
111
100
-
void
101
-
nv04_software_intr(struct nouveau_subdev *subdev)
102
-
{
103
-
nv_mask(subdev, 0x000100, 0x80000000, 0x00000000);
104
-
}
105
-
106
112
static int
107
-
nv04_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
113
+
nv10_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
108
114
struct nouveau_oclass *oclass, void *data, u32 size,
109
115
struct nouveau_object **pobject)
110
116
{
111
-
struct nv04_software_priv *priv;
117
+
struct nv10_sw_priv *priv;
112
118
int ret;
113
119
114
-
ret = nouveau_software_create(parent, engine, oclass, &priv);
120
+
ret = nouveau_sw_create(parent, engine, oclass, &priv);
115
121
*pobject = nv_object(priv);
116
122
if (ret)
117
123
return ret;
118
124
119
-
nv_engine(priv)->cclass = &nv04_software_cclass;
120
-
nv_engine(priv)->sclass = nv04_software_sclass;
121
-
nv_subdev(priv)->intr = nv04_software_intr;
125
+
nv_engine(priv)->cclass = &nv10_sw_cclass;
126
+
nv_engine(priv)->sclass = nv10_sw_sclass;
127
+
nv_subdev(priv)->intr = nv04_sw_intr;
122
128
return 0;
123
129
}
124
130
125
131
struct nouveau_oclass *
126
-
nv04_software_oclass = &(struct nouveau_oclass) {
127
-
.handle = NV_ENGINE(SW, 0x04),
132
+
nv10_sw_oclass = &(struct nouveau_oclass) {
133
+
.handle = NV_ENGINE(SW, 0x10),
128
134
.ofuncs = &(struct nouveau_ofuncs) {
129
-
.ctor = nv04_software_ctor,
130
-
.dtor = _nouveau_software_dtor,
131
-
.init = _nouveau_software_init,
132
-
.fini = _nouveau_software_fini,
135
+
.ctor = nv10_sw_ctor,
136
+
.dtor = _nouveau_sw_dtor,
137
+
.init = _nouveau_sw_init,
138
+
.fini = _nouveau_sw_fini,
133
139
},
134
140
};
+49
-31
drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
+49
-31
drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
···
25
25
#include <core/os.h>
26
26
#include <core/engctx.h>
27
27
28
-
#include <engine/software.h>
28
+
#include <engine/sw.h>
29
+
#include <engine/fifo.h>
29
30
30
-
struct nv10_software_priv {
31
-
struct nouveau_software base;
31
+
struct nv04_sw_priv {
32
+
struct nouveau_sw base;
32
33
};
33
34
34
-
struct nv10_software_chan {
35
-
struct nouveau_software_chan base;
35
+
struct nv04_sw_chan {
36
+
struct nouveau_sw_chan base;
36
37
};
37
38
38
39
/*******************************************************************************
···
41
40
******************************************************************************/
42
41
43
42
static int
44
-
nv10_software_flip(struct nouveau_object *object, u32 mthd,
43
+
nv04_sw_set_ref(struct nouveau_object *object, u32 mthd,
44
+
void *data, u32 size)
45
+
{
46
+
struct nouveau_object *channel = (void *)nv_engctx(object->parent);
47
+
struct nouveau_fifo_chan *fifo = (void *)channel->parent;
48
+
atomic_set(&fifo->refcnt, *(u32*)data);
49
+
return 0;
50
+
}
51
+
52
+
static int
53
+
nv04_sw_flip(struct nouveau_object *object, u32 mthd,
45
54
void *args, u32 size)
46
55
{
47
-
struct nv10_software_chan *chan = (void *)nv_engctx(object->parent);
56
+
struct nv04_sw_chan *chan = (void *)nv_engctx(object->parent);
48
57
if (chan->base.flip)
49
58
return chan->base.flip(chan->base.flip_data);
50
59
return -EINVAL;
51
60
}
52
61
53
62
static struct nouveau_omthds
54
-
nv10_software_omthds[] = {
55
-
{ 0x0500, 0x0500, nv10_software_flip },
63
+
nv04_sw_omthds[] = {
64
+
{ 0x0150, 0x0150, nv04_sw_set_ref },
65
+
{ 0x0500, 0x0500, nv04_sw_flip },
56
66
{}
57
67
};
58
68
59
69
static struct nouveau_oclass
60
-
nv10_software_sclass[] = {
61
-
{ 0x016e, &nouveau_object_ofuncs, nv10_software_omthds },
70
+
nv04_sw_sclass[] = {
71
+
{ 0x006e, &nouveau_object_ofuncs, nv04_sw_omthds },
62
72
{}
63
73
};
64
74
···
78
66
******************************************************************************/
79
67
80
68
static int
81
-
nv10_software_context_ctor(struct nouveau_object *parent,
69
+
nv04_sw_context_ctor(struct nouveau_object *parent,
82
70
struct nouveau_object *engine,
83
71
struct nouveau_oclass *oclass, void *data, u32 size,
84
72
struct nouveau_object **pobject)
85
73
{
86
-
struct nv10_software_chan *chan;
74
+
struct nv04_sw_chan *chan;
87
75
int ret;
88
76
89
-
ret = nouveau_software_context_create(parent, engine, oclass, &chan);
77
+
ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
90
78
*pobject = nv_object(chan);
91
79
if (ret)
92
80
return ret;
···
95
83
}
96
84
97
85
static struct nouveau_oclass
98
-
nv10_software_cclass = {
86
+
nv04_sw_cclass = {
99
87
.handle = NV_ENGCTX(SW, 0x04),
100
88
.ofuncs = &(struct nouveau_ofuncs) {
101
-
.ctor = nv10_software_context_ctor,
102
-
.dtor = _nouveau_software_context_dtor,
103
-
.init = _nouveau_software_context_init,
104
-
.fini = _nouveau_software_context_fini,
89
+
.ctor = nv04_sw_context_ctor,
90
+
.dtor = _nouveau_sw_context_dtor,
91
+
.init = _nouveau_sw_context_init,
92
+
.fini = _nouveau_sw_context_fini,
105
93
},
106
94
};
107
95
···
109
97
* software engine/subdev functions
110
98
******************************************************************************/
111
99
100
+
void
101
+
nv04_sw_intr(struct nouveau_subdev *subdev)
102
+
{
103
+
nv_mask(subdev, 0x000100, 0x80000000, 0x00000000);
104
+
}
105
+
112
106
static int
113
-
nv10_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
107
+
nv04_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
114
108
struct nouveau_oclass *oclass, void *data, u32 size,
115
109
struct nouveau_object **pobject)
116
110
{
117
-
struct nv10_software_priv *priv;
111
+
struct nv04_sw_priv *priv;
118
112
int ret;
119
113
120
-
ret = nouveau_software_create(parent, engine, oclass, &priv);
114
+
ret = nouveau_sw_create(parent, engine, oclass, &priv);
121
115
*pobject = nv_object(priv);
122
116
if (ret)
123
117
return ret;
124
118
125
-
nv_engine(priv)->cclass = &nv10_software_cclass;
126
-
nv_engine(priv)->sclass = nv10_software_sclass;
127
-
nv_subdev(priv)->intr = nv04_software_intr;
119
+
nv_engine(priv)->cclass = &nv04_sw_cclass;
120
+
nv_engine(priv)->sclass = nv04_sw_sclass;
121
+
nv_subdev(priv)->intr = nv04_sw_intr;
128
122
return 0;
129
123
}
130
124
131
125
struct nouveau_oclass *
132
-
nv10_software_oclass = &(struct nouveau_oclass) {
133
-
.handle = NV_ENGINE(SW, 0x10),
126
+
nv04_sw_oclass = &(struct nouveau_oclass) {
127
+
.handle = NV_ENGINE(SW, 0x04),
134
128
.ofuncs = &(struct nouveau_ofuncs) {
135
-
.ctor = nv10_software_ctor,
136
-
.dtor = _nouveau_software_dtor,
137
-
.init = _nouveau_software_init,
138
-
.fini = _nouveau_software_fini,
129
+
.ctor = nv04_sw_ctor,
130
+
.dtor = _nouveau_sw_dtor,
131
+
.init = _nouveau_sw_init,
132
+
.fini = _nouveau_sw_fini,
139
133
},
140
134
};
+47
-47
drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
+47
-47
drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
···
41
41
******************************************************************************/
42
42
43
43
static int
44
-
nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
44
+
nv50_sw_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
45
45
void *args, u32 size)
46
46
{
47
-
struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
47
+
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
48
48
struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent;
49
49
struct nouveau_handle *handle;
50
50
int ret = -EINVAL;
···
63
63
}
64
64
65
65
static int
66
-
nv50_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
66
+
nv50_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
67
67
void *args, u32 size)
68
68
{
69
-
struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
69
+
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
70
70
chan->vblank.offset = *(u32 *)args;
71
71
return 0;
72
72
}
73
73
74
74
int
75
-
nv50_software_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
75
+
nv50_sw_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
76
76
void *args, u32 size)
77
77
{
78
-
struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
78
+
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
79
79
chan->vblank.value = *(u32 *)args;
80
80
return 0;
81
81
}
82
82
83
83
int
84
-
nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
84
+
nv50_sw_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
85
85
void *args, u32 size)
86
86
{
87
-
struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
87
+
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
88
88
u32 head = *(u32 *)args;
89
89
if (head >= nouveau_disp(chan)->vblank.index_nr)
90
90
return -EINVAL;
···
94
94
}
95
95
96
96
int
97
-
nv50_software_mthd_flip(struct nouveau_object *object, u32 mthd,
97
+
nv50_sw_mthd_flip(struct nouveau_object *object, u32 mthd,
98
98
void *args, u32 size)
99
99
{
100
-
struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
100
+
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
101
101
if (chan->base.flip)
102
102
return chan->base.flip(chan->base.flip_data);
103
103
return -EINVAL;
104
104
}
105
105
106
106
static struct nouveau_omthds
107
-
nv50_software_omthds[] = {
108
-
{ 0x018c, 0x018c, nv50_software_mthd_dma_vblsem },
109
-
{ 0x0400, 0x0400, nv50_software_mthd_vblsem_offset },
110
-
{ 0x0404, 0x0404, nv50_software_mthd_vblsem_value },
111
-
{ 0x0408, 0x0408, nv50_software_mthd_vblsem_release },
112
-
{ 0x0500, 0x0500, nv50_software_mthd_flip },
107
+
nv50_sw_omthds[] = {
108
+
{ 0x018c, 0x018c, nv50_sw_mthd_dma_vblsem },
109
+
{ 0x0400, 0x0400, nv50_sw_mthd_vblsem_offset },
110
+
{ 0x0404, 0x0404, nv50_sw_mthd_vblsem_value },
111
+
{ 0x0408, 0x0408, nv50_sw_mthd_vblsem_release },
112
+
{ 0x0500, 0x0500, nv50_sw_mthd_flip },
113
113
{}
114
114
};
115
115
116
116
static struct nouveau_oclass
117
-
nv50_software_sclass[] = {
118
-
{ 0x506e, &nouveau_object_ofuncs, nv50_software_omthds },
117
+
nv50_sw_sclass[] = {
118
+
{ 0x506e, &nouveau_object_ofuncs, nv50_sw_omthds },
119
119
{}
120
120
};
121
121
···
124
124
******************************************************************************/
125
125
126
126
static int
127
-
nv50_software_vblsem_release(struct nvkm_notify *notify)
127
+
nv50_sw_vblsem_release(struct nvkm_notify *notify)
128
128
{
129
-
struct nv50_software_chan *chan =
129
+
struct nv50_sw_chan *chan =
130
130
container_of(notify, typeof(*chan), vblank.notify[notify->index]);
131
-
struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
131
+
struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
132
132
struct nouveau_bar *bar = nouveau_bar(priv);
133
133
134
134
nv_wr32(priv, 0x001704, chan->vblank.channel);
···
147
147
}
148
148
149
149
void
150
-
nv50_software_context_dtor(struct nouveau_object *object)
150
+
nv50_sw_context_dtor(struct nouveau_object *object)
151
151
{
152
-
struct nv50_software_chan *chan = (void *)object;
152
+
struct nv50_sw_chan *chan = (void *)object;
153
153
int i;
154
154
155
155
for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++)
156
156
nvkm_notify_fini(&chan->vblank.notify[i]);
157
157
158
-
nouveau_software_context_destroy(&chan->base);
158
+
nouveau_sw_context_destroy(&chan->base);
159
159
}
160
160
161
161
int
162
-
nv50_software_context_ctor(struct nouveau_object *parent,
162
+
nv50_sw_context_ctor(struct nouveau_object *parent,
163
163
struct nouveau_object *engine,
164
164
struct nouveau_oclass *oclass, void *data, u32 size,
165
165
struct nouveau_object **pobject)
166
166
{
167
167
struct nouveau_disp *pdisp = nouveau_disp(parent);
168
-
struct nv50_software_cclass *pclass = (void *)oclass;
169
-
struct nv50_software_chan *chan;
168
+
struct nv50_sw_cclass *pclass = (void *)oclass;
169
+
struct nv50_sw_chan *chan;
170
170
int ret, i;
171
171
172
-
ret = nouveau_software_context_create(parent, engine, oclass, &chan);
172
+
ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
173
173
*pobject = nv_object(chan);
174
174
if (ret)
175
175
return ret;
···
191
191
return 0;
192
192
}
193
193
194
-
static struct nv50_software_cclass
195
-
nv50_software_cclass = {
194
+
static struct nv50_sw_cclass
195
+
nv50_sw_cclass = {
196
196
.base.handle = NV_ENGCTX(SW, 0x50),
197
197
.base.ofuncs = &(struct nouveau_ofuncs) {
198
-
.ctor = nv50_software_context_ctor,
199
-
.dtor = nv50_software_context_dtor,
200
-
.init = _nouveau_software_context_init,
201
-
.fini = _nouveau_software_context_fini,
198
+
.ctor = nv50_sw_context_ctor,
199
+
.dtor = nv50_sw_context_dtor,
200
+
.init = _nouveau_sw_context_init,
201
+
.fini = _nouveau_sw_context_fini,
202
202
},
203
-
.vblank = nv50_software_vblsem_release,
203
+
.vblank = nv50_sw_vblsem_release,
204
204
};
205
205
206
206
/*******************************************************************************
···
208
208
******************************************************************************/
209
209
210
210
int
211
-
nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
211
+
nv50_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
212
212
struct nouveau_oclass *oclass, void *data, u32 size,
213
213
struct nouveau_object **pobject)
214
214
{
215
-
struct nv50_software_oclass *pclass = (void *)oclass;
216
-
struct nv50_software_priv *priv;
215
+
struct nv50_sw_oclass *pclass = (void *)oclass;
216
+
struct nv50_sw_priv *priv;
217
217
int ret;
218
218
219
-
ret = nouveau_software_create(parent, engine, oclass, &priv);
219
+
ret = nouveau_sw_create(parent, engine, oclass, &priv);
220
220
*pobject = nv_object(priv);
221
221
if (ret)
222
222
return ret;
223
223
224
224
nv_engine(priv)->cclass = pclass->cclass;
225
225
nv_engine(priv)->sclass = pclass->sclass;
226
-
nv_subdev(priv)->intr = nv04_software_intr;
226
+
nv_subdev(priv)->intr = nv04_sw_intr;
227
227
return 0;
228
228
}
229
229
230
230
struct nouveau_oclass *
231
-
nv50_software_oclass = &(struct nv50_software_oclass) {
231
+
nv50_sw_oclass = &(struct nv50_sw_oclass) {
232
232
.base.handle = NV_ENGINE(SW, 0x50),
233
233
.base.ofuncs = &(struct nouveau_ofuncs) {
234
-
.ctor = nv50_software_ctor,
235
-
.dtor = _nouveau_software_dtor,
236
-
.init = _nouveau_software_init,
237
-
.fini = _nouveau_software_fini,
234
+
.ctor = nv50_sw_ctor,
235
+
.dtor = _nouveau_sw_dtor,
236
+
.init = _nouveau_sw_init,
237
+
.fini = _nouveau_sw_fini,
238
238
},
239
-
.cclass = &nv50_software_cclass.base,
240
-
.sclass = nv50_software_sclass,
239
+
.cclass = &nv50_sw_cclass.base,
240
+
.sclass = nv50_sw_sclass,
241
241
}.base;
-46
drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h
-46
drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h
···
1
-
#ifndef __NVKM_SW_NV50_H__
2
-
#define __NVKM_SW_NV50_H__
3
-
4
-
#include <engine/software.h>
5
-
6
-
struct nv50_software_oclass {
7
-
struct nouveau_oclass base;
8
-
struct nouveau_oclass *cclass;
9
-
struct nouveau_oclass *sclass;
10
-
};
11
-
12
-
struct nv50_software_priv {
13
-
struct nouveau_software base;
14
-
};
15
-
16
-
int nv50_software_ctor(struct nouveau_object *, struct nouveau_object *,
17
-
struct nouveau_oclass *, void *, u32,
18
-
struct nouveau_object **);
19
-
20
-
struct nv50_software_cclass {
21
-
struct nouveau_oclass base;
22
-
int (*vblank)(struct nvkm_notify *);
23
-
};
24
-
25
-
struct nv50_software_chan {
26
-
struct nouveau_software_chan base;
27
-
struct {
28
-
struct nvkm_notify notify[4];
29
-
u32 channel;
30
-
u32 ctxdma;
31
-
u64 offset;
32
-
u32 value;
33
-
} vblank;
34
-
};
35
-
36
-
int nv50_software_context_ctor(struct nouveau_object *,
37
-
struct nouveau_object *,
38
-
struct nouveau_oclass *, void *, u32,
39
-
struct nouveau_object **);
40
-
void nv50_software_context_dtor(struct nouveau_object *);
41
-
42
-
int nv50_software_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32);
43
-
int nv50_software_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32);
44
-
int nv50_software_mthd_flip(struct nouveau_object *, u32, void *, u32);
45
-
46
-
#endif
+34
-34
drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c
drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c
+34
-34
drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c
drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c
···
28
28
29
29
#include <subdev/bar.h>
30
30
31
-
#include <engine/software.h>
31
+
#include <engine/sw.h>
32
32
#include <engine/disp.h>
33
33
34
34
#include "nv50.h"
···
38
38
******************************************************************************/
39
39
40
40
static int
41
-
nvc0_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
41
+
nvc0_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
42
42
void *args, u32 size)
43
43
{
44
-
struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
44
+
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
45
45
u64 data = *(u32 *)args;
46
46
if (mthd == 0x0400) {
47
47
chan->vblank.offset &= 0x00ffffffffULL;
···
54
54
}
55
55
56
56
static int
57
-
nvc0_software_mthd_mp_control(struct nouveau_object *object, u32 mthd,
57
+
nvc0_sw_mthd_mp_control(struct nouveau_object *object, u32 mthd,
58
58
void *args, u32 size)
59
59
{
60
-
struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
61
-
struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
60
+
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
61
+
struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
62
62
u32 data = *(u32 *)args;
63
63
64
64
switch (mthd) {
···
80
80
}
81
81
82
82
static struct nouveau_omthds
83
-
nvc0_software_omthds[] = {
84
-
{ 0x0400, 0x0400, nvc0_software_mthd_vblsem_offset },
85
-
{ 0x0404, 0x0404, nvc0_software_mthd_vblsem_offset },
86
-
{ 0x0408, 0x0408, nv50_software_mthd_vblsem_value },
87
-
{ 0x040c, 0x040c, nv50_software_mthd_vblsem_release },
88
-
{ 0x0500, 0x0500, nv50_software_mthd_flip },
89
-
{ 0x0600, 0x0600, nvc0_software_mthd_mp_control },
90
-
{ 0x0644, 0x0644, nvc0_software_mthd_mp_control },
91
-
{ 0x06ac, 0x06ac, nvc0_software_mthd_mp_control },
83
+
nvc0_sw_omthds[] = {
84
+
{ 0x0400, 0x0400, nvc0_sw_mthd_vblsem_offset },
85
+
{ 0x0404, 0x0404, nvc0_sw_mthd_vblsem_offset },
86
+
{ 0x0408, 0x0408, nv50_sw_mthd_vblsem_value },
87
+
{ 0x040c, 0x040c, nv50_sw_mthd_vblsem_release },
88
+
{ 0x0500, 0x0500, nv50_sw_mthd_flip },
89
+
{ 0x0600, 0x0600, nvc0_sw_mthd_mp_control },
90
+
{ 0x0644, 0x0644, nvc0_sw_mthd_mp_control },
91
+
{ 0x06ac, 0x06ac, nvc0_sw_mthd_mp_control },
92
92
{}
93
93
};
94
94
95
95
static struct nouveau_oclass
96
-
nvc0_software_sclass[] = {
97
-
{ 0x906e, &nouveau_object_ofuncs, nvc0_software_omthds },
96
+
nvc0_sw_sclass[] = {
97
+
{ 0x906e, &nouveau_object_ofuncs, nvc0_sw_omthds },
98
98
{}
99
99
};
100
100
···
103
103
******************************************************************************/
104
104
105
105
static int
106
-
nvc0_software_vblsem_release(struct nvkm_notify *notify)
106
+
nvc0_sw_vblsem_release(struct nvkm_notify *notify)
107
107
{
108
-
struct nv50_software_chan *chan =
108
+
struct nv50_sw_chan *chan =
109
109
container_of(notify, typeof(*chan), vblank.notify[notify->index]);
110
-
struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
110
+
struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
111
111
struct nouveau_bar *bar = nouveau_bar(priv);
112
112
113
113
nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
···
119
119
return NVKM_NOTIFY_DROP;
120
120
}
121
121
122
-
static struct nv50_software_cclass
123
-
nvc0_software_cclass = {
122
+
static struct nv50_sw_cclass
123
+
nvc0_sw_cclass = {
124
124
.base.handle = NV_ENGCTX(SW, 0xc0),
125
125
.base.ofuncs = &(struct nouveau_ofuncs) {
126
-
.ctor = nv50_software_context_ctor,
127
-
.dtor = nv50_software_context_dtor,
128
-
.init = _nouveau_software_context_init,
129
-
.fini = _nouveau_software_context_fini,
126
+
.ctor = nv50_sw_context_ctor,
127
+
.dtor = nv50_sw_context_dtor,
128
+
.init = _nouveau_sw_context_init,
129
+
.fini = _nouveau_sw_context_fini,
130
130
},
131
-
.vblank = nvc0_software_vblsem_release,
131
+
.vblank = nvc0_sw_vblsem_release,
132
132
};
133
133
134
134
/*******************************************************************************
···
136
136
******************************************************************************/
137
137
138
138
struct nouveau_oclass *
139
-
nvc0_software_oclass = &(struct nv50_software_oclass) {
139
+
nvc0_sw_oclass = &(struct nv50_sw_oclass) {
140
140
.base.handle = NV_ENGINE(SW, 0xc0),
141
141
.base.ofuncs = &(struct nouveau_ofuncs) {
142
-
.ctor = nv50_software_ctor,
143
-
.dtor = _nouveau_software_dtor,
144
-
.init = _nouveau_software_init,
145
-
.fini = _nouveau_software_fini,
142
+
.ctor = nv50_sw_ctor,
143
+
.dtor = _nouveau_sw_dtor,
144
+
.init = _nouveau_sw_init,
145
+
.fini = _nouveau_sw_fini,
146
146
},
147
-
.cclass = &nvc0_software_cclass.base,
148
-
.sclass = nvc0_software_sclass,
147
+
.cclass = &nvc0_sw_cclass.base,
148
+
.sclass = nvc0_sw_sclass,
149
149
}.base;
+4
drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
+4
drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
+46
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
+46
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
···
1
+
#ifndef __NVKM_SW_NV50_H__
2
+
#define __NVKM_SW_NV50_H__
3
+
4
+
#include <engine/sw.h>
5
+
6
+
struct nv50_sw_oclass {
7
+
struct nouveau_oclass base;
8
+
struct nouveau_oclass *cclass;
9
+
struct nouveau_oclass *sclass;
10
+
};
11
+
12
+
struct nv50_sw_priv {
13
+
struct nouveau_sw base;
14
+
};
15
+
16
+
int nv50_sw_ctor(struct nouveau_object *, struct nouveau_object *,
17
+
struct nouveau_oclass *, void *, u32,
18
+
struct nouveau_object **);
19
+
20
+
struct nv50_sw_cclass {
21
+
struct nouveau_oclass base;
22
+
int (*vblank)(struct nvkm_notify *);
23
+
};
24
+
25
+
struct nv50_sw_chan {
26
+
struct nouveau_sw_chan base;
27
+
struct {
28
+
struct nvkm_notify notify[4];
29
+
u32 channel;
30
+
u32 ctxdma;
31
+
u64 offset;
32
+
u32 value;
33
+
} vblank;
34
+
};
35
+
36
+
int nv50_sw_context_ctor(struct nouveau_object *,
37
+
struct nouveau_object *,
38
+
struct nouveau_oclass *, void *, u32,
39
+
struct nouveau_object **);
40
+
void nv50_sw_context_dtor(struct nouveau_object *);
41
+
42
+
int nv50_sw_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32);
43
+
int nv50_sw_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32);
44
+
int nv50_sw_mthd_flip(struct nouveau_object *, u32, void *, u32);
45
+
46
+
#endif