Merge branches 'sh/serial-rework' and 'sh/oprofile'

+2 -4

arch/sh/oprofile/op_model_sh7750.c

··· 255 255 return -ENODEV; 256 256 257 257 ops = &sh7750_perf_counter_ops; 258 - ops->cpu_type = (char *)get_cpu_subtype(&current_cpu_data); 258 + ops->cpu_type = "sh/sh7750"; 259 259 260 - printk(KERN_INFO "oprofile: using SH-4 (%s) performance monitoring.\n", 261 - sh7750_perf_counter_ops.cpu_type); 260 + printk(KERN_INFO "oprofile: using SH-4 performance monitoring.\n"); 262 261 263 262 /* Clear the counters */ 264 263 ctrl_outw(ctrl_inw(PMCR1) | PMCR_PMCLR, PMCR1); ··· 269 270 void oprofile_arch_exit(void) 270 271 { 271 272 } 272 -

+1 -16

drivers/serial/sh-sci.c

··· 250 250 } 251 251 #endif 252 252 253 - #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \ 254 - defined(__H8300H__) || defined(__H8300S__) 253 + #if defined(__H8300H__) || defined(__H8300S__) 255 254 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag) 256 255 { 257 256 int ch = (port->mapbase - SMR0) >> 3; ··· 284 285 #define sci_init_pins_irda NULL 285 286 #endif 286 287 287 - #ifdef SCI_ONLY 288 - #define sci_init_pins_scif NULL 289 - #endif 290 - 291 - #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) 292 288 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 293 289 static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag) 294 290 { ··· 443 449 return sci_in(port, SCFDR) & SCIF_RFDC_MASK; 444 450 } 445 451 #endif 446 - #endif /* SCIF_ONLY || SCI_AND_SCIF */ 447 452 448 453 static inline int sci_txroom(struct uart_port *port) 449 454 { ··· 478 485 return; 479 486 } 480 487 481 - #ifndef SCI_ONLY 482 488 if (port->type == PORT_SCIF) 483 489 count = scif_txroom(port); 484 490 else 485 - #endif 486 491 count = sci_txroom(port); 487 492 488 493 do { ··· 510 519 } else { 511 520 ctrl = sci_in(port, SCSCR); 512 521 513 - #if !defined(SCI_ONLY) 514 522 if (port->type == PORT_SCIF) { 515 523 sci_in(port, SCxSR); /* Dummy read */ 516 524 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 517 525 } 518 - #endif 519 526 520 527 ctrl |= SCI_CTRL_FLAGS_TIE; 521 528 sci_out(port, SCSCR, ctrl); ··· 536 547 return; 537 548 538 549 while (1) { 539 - #if !defined(SCI_ONLY) 540 550 if (port->type == PORT_SCIF) 541 551 count = scif_rxroom(port); 542 552 else 543 - #endif 544 553 count = sci_rxroom(port); 545 554 546 555 /* Don't copy more bytes than there is room for in the buffer */ ··· 1041 1054 1042 1055 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1043 1056 1044 - #if !defined(SCI_ONLY) 1045 1057 if (port->type == PORT_SCIF) 1046 1058 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1047 - #endif 1048 1059 1049 1060 smr_val = sci_in(port, SCSMR) & 3; 1050 1061 if ((termios->c_cflag & CSIZE) == CS7)

+15 -67

drivers/serial/sh-sci.h

··· 16 16 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 17 17 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 18 18 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 19 - # define SCI_AND_SCIF 20 19 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) 21 20 # define SCIF0 0xA4400000 22 21 # define SCIF2 0xA4410000 ··· 29 30 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output 30 31 */ 31 32 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 32 - # define SCIF_ONLY 33 33 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 34 34 defined(CONFIG_CPU_SUBTYPE_SH7721) 35 35 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 36 - # define SCIF_ONLY 37 36 #define SCIF_ORER 0x0200 /* overrun error bit */ 38 37 #elif defined(CONFIG_SH_RTS7751R2D) 39 38 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 40 39 # define SCIF_ORER 0x0001 /* overrun error bit */ 41 40 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 42 - # define SCIF_ONLY 43 41 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 44 42 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 45 43 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ ··· 49 53 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ 50 54 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 51 55 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) 52 - # define SCI_AND_SCIF 53 56 #elif defined(CONFIG_CPU_SUBTYPE_SH7760) 54 57 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 55 58 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 56 59 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 57 60 # define SCIF_ORER 0x0001 /* overrun error bit */ 58 61 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 59 - # define SCIF_ONLY 60 62 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 61 63 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 62 64 # define SCIF_ORER 0x0001 /* overrun error bit */ 63 65 # define PACR 0xa4050100 64 66 # define PBCR 0xa4050102 65 67 # define SCSCR_INIT(port) 0x3B 66 - # define SCIF_ONLY 67 68 #elif defined(CONFIG_CPU_SUBTYPE_SH7343) 68 69 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 69 70 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 70 71 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 71 72 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 72 73 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 73 - # define SCIF_ONLY 74 74 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) 75 75 # define PADR 0xA4050120 76 76 # define PSDR 0xA405013e ··· 74 82 # define PSCR 0xA405011E 75 83 # define SCIF_ORER 0x0001 /* overrun error bit */ 76 84 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 77 - # define SCIF_ONLY 78 85 #elif defined(CONFIG_CPU_SUBTYPE_SH7366) 79 86 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 80 87 # define SCSPTR0 SCPDR0 ··· 89 98 # define SCSPTR5 0xa4050128 90 99 # define SCIF_ORER 0x0001 /* overrun error bit */ 91 100 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 92 - # define SCIF_ONLY 93 101 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 94 102 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 95 103 # define SCIF_ORER 0x0001 /* overrun error bit */ 96 104 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 97 - # define SCIF_ONLY 98 105 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 99 106 # define SCIF_BASE_ADDR 0x01030000 100 107 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR ··· 101 112 # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 102 113 # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 103 114 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ 104 - # define SCIF_ONLY 105 115 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 106 116 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 107 - # define SCI_ONLY 108 117 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 109 118 #elif defined(CONFIG_H8S2678) 110 119 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 111 - # define SCI_ONLY 112 120 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 113 121 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) 114 122 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ ··· 113 127 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 114 128 # define SCIF_ORER 0x0001 /* overrun error bit */ 115 129 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 116 - # define SCIF_ONLY 117 130 #elif defined(CONFIG_CPU_SUBTYPE_SH7770) 118 131 # define SCSPTR0 0xff923020 /* 16 bit SCIF */ 119 132 # define SCSPTR1 0xff924020 /* 16 bit SCIF */ 120 133 # define SCSPTR2 0xff925020 /* 16 bit SCIF */ 121 134 # define SCIF_ORER 0x0001 /* overrun error bit */ 122 135 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ 123 - # define SCIF_ONLY 124 136 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) 125 137 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 126 138 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 127 139 # define SCIF_ORER 0x0001 /* Overrun error bit */ 128 140 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 129 - # define SCIF_ONLY 130 141 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) 131 142 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 132 143 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ ··· 133 150 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 134 151 # define SCIF_OPER 0x0001 /* Overrun error bit */ 135 152 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 136 - # define SCIF_ONLY 137 153 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ 138 154 defined(CONFIG_CPU_SUBTYPE_SH7206) || \ 139 155 defined(CONFIG_CPU_SUBTYPE_SH7263) ··· 141 159 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 142 160 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 143 161 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 144 - # define SCIF_ONLY 145 162 #elif defined(CONFIG_CPU_SUBTYPE_SH7619) 146 163 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 147 164 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 148 165 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 149 166 # define SCIF_ORER 0x0001 /* overrun error bit */ 150 167 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 151 - # define SCIF_ONLY 152 168 #elif defined(CONFIG_CPU_SUBTYPE_SHX3) 153 169 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 154 170 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ ··· 154 174 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 155 175 # define SCIF_ORER 0x0001 /* Overrun error bit */ 156 176 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 157 - # define SCIF_ONLY 158 177 #else 159 178 # error CPU subtype not defined 160 179 #endif ··· 224 245 # define SCIF_TXROOM_MAX 16 225 246 #endif 226 247 227 - #if defined(SCI_ONLY) 228 - # define SCxSR_TEND(port) SCI_TEND 229 - # define SCxSR_ERRORS(port) SCI_ERRORS 230 - # define SCxSR_RDxF(port) SCI_RDRF 231 - # define SCxSR_TDxE(port) SCI_TDRE 232 - # define SCxSR_ORER(port) SCI_ORER 233 - # define SCxSR_FER(port) SCI_FER 234 - # define SCxSR_PER(port) SCI_PER 235 - # define SCxSR_BRK(port) 0x00 236 - # define SCxSR_RDxF_CLEAR(port) 0xbc 237 - # define SCxSR_ERROR_CLEAR(port) 0xc4 238 - # define SCxSR_TDxE_CLEAR(port) 0x78 239 - # define SCxSR_BREAK_CLEAR(port) 0xc4 240 - #elif defined(SCIF_ONLY) 241 - # define SCxSR_TEND(port) SCIF_TEND 242 - # define SCxSR_ERRORS(port) SCIF_ERRORS 243 - # define SCxSR_RDxF(port) SCIF_RDF 244 - # define SCxSR_TDxE(port) SCIF_TDFE 248 + #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 249 + #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) 250 + #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 251 + #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 252 + #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 253 + #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 254 + #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 255 + 245 256 #if defined(CONFIG_CPU_SUBTYPE_SH7705) 246 - # define SCxSR_ORER(port) SCIF_ORER 257 + # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) 247 258 #else 248 - # define SCxSR_ORER(port) 0x0000 259 + # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) 249 260 #endif 250 - # define SCxSR_FER(port) SCIF_FER 251 - # define SCxSR_PER(port) SCIF_PER 252 - # define SCxSR_BRK(port) SCIF_BRK 261 + 253 262 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 254 263 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 255 264 defined(CONFIG_CPU_SUBTYPE_SH7721) 256 - # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) 257 - # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) 258 - # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) 259 - # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3) 265 + # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 266 + # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 267 + # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 268 + # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) 260 269 #else 261 - /* SH7705 can also use this, clearing is same between 7705 and 7709 */ 262 - # define SCxSR_RDxF_CLEAR(port) 0x00fc 263 - # define SCxSR_ERROR_CLEAR(port) 0x0073 264 - # define SCxSR_TDxE_CLEAR(port) 0x00df 265 - # define SCxSR_BREAK_CLEAR(port) 0x00e3 266 - #endif 267 - #else 268 - # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 269 - # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) 270 - # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 271 - # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 272 - # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) 273 - # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 274 - # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 275 - # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 276 270 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) 277 271 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) 278 272 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) ··· 531 579 defined(CONFIG_CPU_SUBTYPE_SH4_202) 532 580 static inline int sci_rxd_in(struct uart_port *port) 533 581 { 534 - #ifndef SCIF_ONLY 535 582 if (port->mapbase == 0xffe00000) 536 583 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 537 - #endif 538 - #ifndef SCI_ONLY 539 584 if (port->mapbase == 0xffe80000) 540 585 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 541 - #endif 542 586 return 1; 543 587 } 544 588 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)