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kernel
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linux
[ARM] 3991/1: i.MX/MX1 high resolution time source
Enhanced resolution for time measurement functions.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
authored by
Pavel Pisa
and committed by
Russell King
86987d5b
5c894cd1
+51
-38
+50
-36
arch/arm/mach-imx/time.c
+50
-36
arch/arm/mach-imx/time.c
···
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/time.h>
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#include <linux/clocksource.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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/* Use timer 1 as system timer */
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#define TIMER_BASE IMX_TIM1_BASE
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/*
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* Returns number of us since last clock interrupt. Note that interrupts
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* will have been disabled by do_gettimeoffset()
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*/
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static unsigned long imx_gettimeoffset(void)
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{
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unsigned long ticks;
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/*
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* Get the current number of ticks. Note that there is a race
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* condition between us reading the timer and checking for
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* an interrupt. We get around this by ensuring that the
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* counter has not reloaded between our two reads.
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*/
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ticks = IMX_TCN(TIMER_BASE);
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/*
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* Interrupt pending? If so, we've reloaded once already.
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*/
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if (IMX_TSTAT(TIMER_BASE) & TSTAT_COMP)
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ticks += LATCH;
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/*
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* Convert the ticks to usecs
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*/
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return (1000000 / CLK32) * ticks;
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}
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static unsigned long evt_diff;
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/*
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* IRQ handler for the timer
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static irqreturn_t
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imx_timer_interrupt(int irq, void *dev_id)
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{
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write_seqlock(&xtime_lock);
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uint32_t tstat;
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/* clear the interrupt */
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if (IMX_TSTAT(TIMER_BASE))
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IMX_TSTAT(TIMER_BASE) = 0;
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tstat = IMX_TSTAT(TIMER_BASE);
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IMX_TSTAT(TIMER_BASE) = 0;
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timer_tick();
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write_sequnlock(&xtime_lock);
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if (tstat & TSTAT_COMP) {
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do {
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write_seqlock(&xtime_lock);
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timer_tick();
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write_sequnlock(&xtime_lock);
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IMX_TCMP(TIMER_BASE) += evt_diff;
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} while (unlikely((int32_t)(IMX_TCMP(TIMER_BASE)
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- IMX_TCN(TIMER_BASE)) < 0));
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}
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return IRQ_HANDLED;
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}
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};
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/*
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* Set up timer interrupt, and return the current time in seconds.
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* Set up timer hardware into expected mode and state.
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*/
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static void __init imx_timer_init(void)
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static void __init imx_timer_hardware_init(void)
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{
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/*
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* Initialise to a known state (all timers off, and timing reset)
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IMX_TCTL(TIMER_BASE) = 0;
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IMX_TPRER(TIMER_BASE) = 0;
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IMX_TCMP(TIMER_BASE) = LATCH - 1;
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IMX_TCTL(TIMER_BASE) = TCTL_CLK_32 | TCTL_IRQEN | TCTL_TEN;
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IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_IRQEN | TCTL_TEN;
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evt_diff = LATCH;
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}
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cycle_t imx_get_cycles(void)
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{
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return IMX_TCN(TIMER_BASE);
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}
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static struct clocksource clocksource_imx = {
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.name = "imx_timer1",
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.rating = 200,
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.read = imx_get_cycles,
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.mask = 0xFFFFFFFF,
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.shift = 20,
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.is_continuous = 1,
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};
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static int __init imx_clocksource_init(void)
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{
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clocksource_imx.mult =
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clocksource_hz2mult(imx_get_perclk1(), clocksource_imx.shift);
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clocksource_register(&clocksource_imx);
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return 0;
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}
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static void __init imx_timer_init(void)
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{
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imx_timer_hardware_init();
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imx_clocksource_init();
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/*
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* Make irqs happen for the system timer
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struct sys_timer imx_timer = {
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.init = imx_timer_init,
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.offset = imx_gettimeoffset,
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};