Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

ARM: EXYNOS: apply S5P_CENTRAL_SEQ_OPTION fix only when necessary

Commit c2dd114d2486 ("ARM: EXYNOS: fix register setup for AFTR mode
code") added S5P_CENTRAL_SEQ_OPTION register setup fix for all
Exynos SoCs to AFTR mode code-path. It turned out that for coupled
cpuidle AFTR mode on Exynos4210 (added by the next patch) applying
this fix causes lockup so enable it in the AFTR mode code-path only
on SoCs that require it (in the suspend code-path it can be always
applied like it was before commit c2dd114d2486 ("ARM: EXYNOS: fix
register setup for AFTR mode code")

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Colin Cross <ccross@google.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>

authored by

Bartlomiej Zolnierkiewicz and committed by
Kukjin Kim
865e8b76 97bf6af1

+11 -4
+7 -4
arch/arm/mach-exynos/pm.c
··· 97 97 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 98 98 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 99 99 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 100 - 101 - /* Setting SEQ_OPTION register */ 102 - pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, 103 - S5P_CENTRAL_SEQ_OPTION); 104 100 } 105 101 106 102 int exynos_pm_central_resume(void) ··· 159 163 cpu_pm_enter(); 160 164 161 165 exynos_pm_central_suspend(); 166 + 167 + if (of_machine_is_compatible("samsung,exynos4212") || 168 + of_machine_is_compatible("samsung,exynos4412")) { 169 + /* Setting SEQ_OPTION register */ 170 + pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, 171 + S5P_CENTRAL_SEQ_OPTION); 172 + } 162 173 163 174 cpu_suspend(0, exynos_aftr_finisher); 164 175
+4
arch/arm/mach-exynos/suspend.c
··· 282 282 { 283 283 exynos_pm_central_suspend(); 284 284 285 + /* Setting SEQ_OPTION register */ 286 + pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, 287 + S5P_CENTRAL_SEQ_OPTION); 288 + 285 289 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 286 290 exynos_cpu_save_register(); 287 291