tjh.dev
+6
-1
arch/arm/mach-shmobile/clock-r8a7740.c
+6
-1
arch/arm/mach-shmobile/clock-r8a7740.c
···
455
455
MSTP128, MSTP127, MSTP125,
456
456
MSTP116, MSTP111, MSTP100, MSTP117,
457
457
458
-
MSTP230,
458
+
MSTP230, MSTP229,
459
459
MSTP222,
460
460
MSTP218, MSTP217, MSTP216, MSTP214,
461
461
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
···
479
479
[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
480
480
481
481
[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
482
+
[MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 29, 0), /* INTCA */
482
483
[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
483
484
[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
484
485
[MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
···
576
575
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
577
576
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
578
577
CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]),
578
+
CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP229]),
579
+
CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP229]),
580
+
CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP229]),
581
+
CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP229]),
579
582
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
580
583
CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]),
581
584