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dt-bindings: rtc: add schema for NXP S32G2/S32G3 SoCs

RTC tracks clock time during system suspend and it is used as a wakeup
source on S32G2/S32G3 architecture.

RTC from S32G2/S32G3 is not battery-powered and it is not kept alive
during system reset.

Co-developed-by: Bogdan-Gabriel Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Bogdan-Gabriel Roman <bogdan-gabriel.roman@nxp.com>
Co-developed-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250403103346.3064895-2-ciprianmarian.costea@oss.nxp.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

authored by

Ciprian Marian Costea and committed by
Alexandre Belloni
8568d8b4 bf1c27c6

+72
+72
Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rtc/nxp,s32g-rtc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: NXP S32G2/S32G3 Real Time Clock (RTC) 8 + 9 + maintainers: 10 + - Bogdan Hamciuc <bogdan.hamciuc@nxp.com> 11 + - Ciprian Marian Costea <ciprianmarian.costea@nxp.com> 12 + 13 + description: 14 + RTC hardware module present on S32G2/S32G3 SoCs is used as a wakeup source. 15 + It is not kept alive during system reset and it is not battery-powered. 16 + 17 + allOf: 18 + - $ref: rtc.yaml# 19 + 20 + properties: 21 + compatible: 22 + oneOf: 23 + - enum: 24 + - nxp,s32g2-rtc 25 + - items: 26 + - const: nxp,s32g3-rtc 27 + - const: nxp,s32g2-rtc 28 + 29 + reg: 30 + maxItems: 1 31 + 32 + interrupts: 33 + maxItems: 1 34 + 35 + clocks: 36 + items: 37 + - description: ipg clock drives the access to the RTC iomapped registers 38 + - description: Clock source for the RTC module. Can be selected between 39 + 4 different clock sources using an integrated hardware mux. 40 + On S32G2/S32G3 SoCs, 'source0' is the SIRC clock (~32KHz) and it is 41 + available during standby and runtime. 'source1' is reserved and cannot 42 + be used. 'source2' is the FIRC clock and it is only available during 43 + runtime providing a better resolution (~48MHz). 'source3' is an external 44 + RTC clock source which can be additionally added in hardware. 45 + 46 + clock-names: 47 + items: 48 + - const: ipg 49 + - enum: [ source0, source1, source2, source3 ] 50 + 51 + required: 52 + - compatible 53 + - reg 54 + - interrupts 55 + - clocks 56 + - clock-names 57 + 58 + additionalProperties: false 59 + 60 + examples: 61 + - | 62 + #include <dt-bindings/interrupt-controller/arm-gic.h> 63 + #include <dt-bindings/interrupt-controller/irq.h> 64 + 65 + rtc@40060000 { 66 + compatible = "nxp,s32g3-rtc", 67 + "nxp,s32g2-rtc"; 68 + reg = <0x40060000 0x1000>; 69 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 70 + clocks = <&clks 54>, <&clks 55>; 71 + clock-names = "ipg", "source0"; 72 + };