tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/i915/vrr: convert to struct intel_display

Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_vrr.[ch] to struct intel_display.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1d25a08c62a320133fbb0a89dac3dd1081139487.1724342644.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Jani Nikula 85279198 aa451ae7

+61 -66
+61 -66
drivers/gpu/drm/i915/display/intel_vrr.c
··· 17 17 18 18 bool intel_vrr_is_capable(struct intel_connector *connector) 19 19 { 20 + struct intel_display *display = to_intel_display(connector); 20 21 const struct drm_display_info *info = &connector->base.display_info; 21 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 22 22 struct intel_dp *intel_dp; 23 23 24 24 /* ··· 43 43 return false; 44 44 } 45 45 46 - return HAS_VRR(i915) && 46 + return HAS_VRR(display) && 47 47 info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; 48 48 } 49 49 ··· 89 89 */ 90 90 static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state) 91 91 { 92 - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 93 - struct drm_i915_private *i915 = to_i915(crtc->base.dev); 92 + struct intel_display *display = to_intel_display(crtc_state); 94 93 95 - if (DISPLAY_VER(i915) >= 13) 94 + if (DISPLAY_VER(display) >= 13) 96 95 return crtc_state->vrr.guardband; 97 96 else 98 97 /* The hw imposes the extra scanline before frame start */ ··· 112 113 static bool 113 114 is_cmrr_frac_required(struct intel_crtc_state *crtc_state) 114 115 { 116 + struct intel_display *display = to_intel_display(crtc_state); 115 117 int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line; 116 118 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 117 - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 118 119 119 - if (!HAS_CMRR(i915)) 120 + if (!HAS_CMRR(display)) 120 121 return false; 121 122 122 123 actual_refresh_k = ··· 160 161 intel_vrr_compute_config(struct intel_crtc_state *crtc_state, 161 162 struct drm_connector_state *conn_state) 162 163 { 163 - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 164 - struct drm_i915_private *i915 = to_i915(crtc->base.dev); 164 + struct intel_display *display = to_intel_display(crtc_state); 165 165 struct intel_connector *connector = 166 166 to_intel_connector(conn_state->connector); 167 167 struct intel_dp *intel_dp = intel_attached_dp(connector); ··· 184 186 if (!crtc_state->vrr.in_range) 185 187 return; 186 188 187 - if (HAS_LRR(i915)) 189 + if (HAS_LRR(display)) 188 190 crtc_state->update_lrr = true; 189 191 190 192 vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, ··· 244 246 * For XE_LPD+, we use guardband and pipeline override 245 247 * is deprecated. 246 248 */ 247 - if (DISPLAY_VER(i915) >= 13) { 249 + if (DISPLAY_VER(display) >= 13) { 248 250 crtc_state->vrr.guardband = 249 251 crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start; 250 252 } else { ··· 256 258 257 259 static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state) 258 260 { 259 - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 261 + struct intel_display *display = to_intel_display(crtc_state); 260 262 261 - if (DISPLAY_VER(i915) >= 13) 263 + if (DISPLAY_VER(display) >= 13) 262 264 return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN | 263 265 XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband); 264 266 else ··· 269 271 270 272 void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 271 273 { 272 - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 274 + struct intel_display *display = to_intel_display(crtc_state); 273 275 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 274 276 275 277 /* ··· 277 279 * TGL: generate VRR "safe window" for DSB vblank waits 278 280 * ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR 279 281 */ 280 - if (IS_DISPLAY_VER(dev_priv, 12, 13)) 281 - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 282 + if (IS_DISPLAY_VER(display, 12, 13)) 283 + intel_de_rmw(display, CHICKEN_TRANS(cpu_transcoder), 282 284 0, PIPE_VBLANK_WITH_DELAY); 283 285 284 286 if (!crtc_state->vrr.flipline) { 285 - intel_de_write(dev_priv, 286 - TRANS_VRR_CTL(dev_priv, cpu_transcoder), 0); 287 + intel_de_write(display, 288 + TRANS_VRR_CTL(display, cpu_transcoder), 0); 287 289 return; 288 290 } 289 291 290 292 if (crtc_state->cmrr.enable) { 291 - intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv, cpu_transcoder), 293 + intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 292 294 upper_32_bits(crtc_state->cmrr.cmrr_m)); 293 - intel_de_write(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder), 295 + intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 294 296 lower_32_bits(crtc_state->cmrr.cmrr_m)); 295 - intel_de_write(dev_priv, TRANS_CMRR_N_HI(dev_priv, cpu_transcoder), 297 + intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 296 298 upper_32_bits(crtc_state->cmrr.cmrr_n)); 297 - intel_de_write(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder), 299 + intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 298 300 lower_32_bits(crtc_state->cmrr.cmrr_n)); 299 301 } 300 302 301 - intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder), 303 + intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), 302 304 crtc_state->vrr.vmin - 1); 303 - intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder), 305 + intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), 304 306 crtc_state->vrr.vmax - 1); 305 - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), 307 + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 306 308 trans_vrr_ctl(crtc_state)); 307 - intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder), 309 + intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), 308 310 crtc_state->vrr.flipline - 1); 309 311 } 310 312 311 313 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) 312 314 { 313 - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 314 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 315 + struct intel_display *display = to_intel_display(crtc_state); 315 316 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 316 317 317 318 if (!crtc_state->vrr.enable) 318 319 return; 319 320 320 - intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 321 + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 321 322 TRANS_PUSH_EN | TRANS_PUSH_SEND); 322 323 } 323 324 324 325 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) 325 326 { 326 - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 327 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 327 + struct intel_display *display = to_intel_display(crtc_state); 328 328 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 329 329 330 330 if (!crtc_state->vrr.enable) 331 331 return false; 332 332 333 - return intel_de_read(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder)) & TRANS_PUSH_SEND; 333 + return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; 334 334 } 335 335 336 336 void intel_vrr_enable(const struct intel_crtc_state *crtc_state) 337 337 { 338 - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 338 + struct intel_display *display = to_intel_display(crtc_state); 339 339 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 340 340 341 341 if (!crtc_state->vrr.enable) 342 342 return; 343 343 344 - intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 344 + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 345 345 TRANS_PUSH_EN); 346 346 347 - if (HAS_AS_SDP(dev_priv)) 348 - intel_de_write(dev_priv, 349 - TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), 347 + if (HAS_AS_SDP(display)) 348 + intel_de_write(display, 349 + TRANS_VRR_VSYNC(display, cpu_transcoder), 350 350 VRR_VSYNC_END(crtc_state->vrr.vsync_end) | 351 351 VRR_VSYNC_START(crtc_state->vrr.vsync_start)); 352 352 353 353 if (crtc_state->cmrr.enable) { 354 - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), 354 + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 355 355 VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | 356 356 trans_vrr_ctl(crtc_state)); 357 357 } else { 358 - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), 358 + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 359 359 VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); 360 360 } 361 361 } 362 362 363 363 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) 364 364 { 365 - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 366 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 365 + struct intel_display *display = to_intel_display(old_crtc_state); 367 366 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 368 367 369 368 if (!old_crtc_state->vrr.enable) 370 369 return; 371 370 372 - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), 371 + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 373 372 trans_vrr_ctl(old_crtc_state)); 374 - intel_de_wait_for_clear(dev_priv, 375 - TRANS_VRR_STATUS(dev_priv, cpu_transcoder), 373 + intel_de_wait_for_clear(display, 374 + TRANS_VRR_STATUS(display, cpu_transcoder), 376 375 VRR_STATUS_VRR_EN_LIVE, 1000); 377 - intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 0); 376 + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); 378 377 379 - if (HAS_AS_SDP(dev_priv)) 380 - intel_de_write(dev_priv, 381 - TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), 0); 378 + if (HAS_AS_SDP(display)) 379 + intel_de_write(display, 380 + TRANS_VRR_VSYNC(display, cpu_transcoder), 0); 382 381 } 383 382 384 383 void intel_vrr_get_config(struct intel_crtc_state *crtc_state) 385 384 { 386 - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 385 + struct intel_display *display = to_intel_display(crtc_state); 387 386 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 388 387 u32 trans_vrr_ctl, trans_vrr_vsync; 389 388 390 - trans_vrr_ctl = intel_de_read(dev_priv, 391 - TRANS_VRR_CTL(dev_priv, cpu_transcoder)); 389 + trans_vrr_ctl = intel_de_read(display, 390 + TRANS_VRR_CTL(display, cpu_transcoder)); 392 391 393 392 crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; 394 - if (HAS_CMRR(dev_priv)) 393 + if (HAS_CMRR(display)) 395 394 crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); 396 395 397 396 if (crtc_state->cmrr.enable) { 398 397 crtc_state->cmrr.cmrr_n = 399 - intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder), 400 - TRANS_CMRR_N_HI(dev_priv, cpu_transcoder)); 398 + intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 399 + TRANS_CMRR_N_HI(display, cpu_transcoder)); 401 400 crtc_state->cmrr.cmrr_m = 402 - intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder), 403 - TRANS_CMRR_M_HI(dev_priv, cpu_transcoder)); 401 + intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 402 + TRANS_CMRR_M_HI(display, cpu_transcoder)); 404 403 } 405 404 406 - if (DISPLAY_VER(dev_priv) >= 13) 405 + if (DISPLAY_VER(display) >= 13) 407 406 crtc_state->vrr.guardband = 408 407 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); 409 408 else ··· 409 414 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); 410 415 411 416 if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) { 412 - crtc_state->vrr.flipline = intel_de_read(dev_priv, 413 - TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder)) + 1; 414 - crtc_state->vrr.vmax = intel_de_read(dev_priv, 415 - TRANS_VRR_VMAX(dev_priv, cpu_transcoder)) + 1; 416 - crtc_state->vrr.vmin = intel_de_read(dev_priv, 417 - TRANS_VRR_VMIN(dev_priv, cpu_transcoder)) + 1; 417 + crtc_state->vrr.flipline = intel_de_read(display, 418 + TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1; 419 + crtc_state->vrr.vmax = intel_de_read(display, 420 + TRANS_VRR_VMAX(display, cpu_transcoder)) + 1; 421 + crtc_state->vrr.vmin = intel_de_read(display, 422 + TRANS_VRR_VMIN(display, cpu_transcoder)) + 1; 418 423 } 419 424 420 425 if (crtc_state->vrr.enable) { 421 426 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 422 427 423 - if (HAS_AS_SDP(dev_priv)) { 428 + if (HAS_AS_SDP(display)) { 424 429 trans_vrr_vsync = 425 - intel_de_read(dev_priv, 426 - TRANS_VRR_VSYNC(dev_priv, cpu_transcoder)); 430 + intel_de_read(display, 431 + TRANS_VRR_VSYNC(display, cpu_transcoder)); 427 432 crtc_state->vrr.vsync_start = 428 433 REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync); 429 434 crtc_state->vrr.vsync_end =