+10
-6
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+10
-6
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
···
4743
4743
4744
4744
for (i=0; i < dep_table->count; i++) {
4745
4745
if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
4746
-
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
4747
-
break;
4746
+
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
4747
+
return;
4748
4748
}
4749
4749
}
4750
-
if (i == dep_table->count)
4750
+
if (i == dep_table->count && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
4751
4751
data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
4752
+
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4753
+
}
4752
4754
4753
4755
dep_table = table_info->vdd_dep_on_sclk;
4754
4756
odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
4755
4757
for (i=0; i < dep_table->count; i++) {
4756
4758
if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
4757
-
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
4758
-
break;
4759
+
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
4760
+
return;
4759
4761
}
4760
4762
}
4761
-
if (i == dep_table->count)
4763
+
if (i == dep_table->count && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
4762
4764
data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
4765
+
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4766
+
}
4763
4767
}
4764
4768
4765
4769
static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,