tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'sh-pfc-for-v4.21-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.21
- Fix VIN (Video IN) versioned groups on R-Car V2H, H3, and M3-W,
- Add I2C[0-3], DU1, VIN, QSPI1, and SDHI pin groups on RZ/G1C,
- Add audio, SDHI, VIN, HSCIF, and CAN(FD) support on R-Car E3,
- Add QSPI pin groups on R-Car V3M and V3H,
- Add VIN and CAN(FD) pin groups on R-Car M3-N,
- Add I2C[035] pin groups on R-Car H3 and M3-W,
- Add pinctrl and GPIO support for the new RZ/A2M (R7S9210) SoC,
- Small cleanups,
- Maintainership updates.
+3594
-125
+87
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
+87
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
···
1
+
Renesas RZ/A2 combined Pin and GPIO controller
2
+
3
+
The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller.
4
+
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
5
+
Each port features up to 8 pins, each of them configurable for GPIO
6
+
function (port mode) or in alternate function mode.
7
+
Up to 8 different alternate function modes exist for each single pin.
8
+
9
+
Pin controller node
10
+
-------------------
11
+
12
+
Required properties:
13
+
- compatible: shall be:
14
+
- "renesas,r7s9210-pinctrl": for RZ/A2M
15
+
- reg
16
+
Address base and length of the memory area where the pin controller
17
+
hardware is mapped to.
18
+
- gpio-controller
19
+
This pin controller also controls pins as GPIO
20
+
- #gpio-cells
21
+
Must be 2
22
+
- gpio-ranges
23
+
Expresses the total number of GPIO ports/pins in this SoC
24
+
25
+
Example: Pin controller node for RZ/A2M SoC (r7s9210)
26
+
27
+
pinctrl: pin-controller@fcffe000 {
28
+
compatible = "renesas,r7s9210-pinctrl";
29
+
reg = <0xfcffe000 0x1000>;
30
+
31
+
gpio-controller;
32
+
#gpio-cells = <2>;
33
+
gpio-ranges = <&pinctrl 0 0 176>;
34
+
};
35
+
36
+
Sub-nodes
37
+
---------
38
+
39
+
The child nodes of the pin controller designate pins to be used for
40
+
specific peripheral functions or as GPIO.
41
+
42
+
- Pin multiplexing sub-nodes:
43
+
A pin multiplexing sub-node describes how to configure a set of
44
+
(or a single) pin in some desired alternate function mode.
45
+
The values for the pinmux properties are a combination of port name, pin
46
+
number and the desired function index. Use the RZA2_PINMUX macro located
47
+
in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these.
48
+
For assigning GPIO pins, use the macro RZA2_PIN also in r7s9210-pinctrl.h
49
+
to express the desired port pin.
50
+
51
+
Required properties:
52
+
- pinmux:
53
+
integer array representing pin number and pin multiplexing configuration.
54
+
When a pin has to be configured in alternate function mode, use this
55
+
property to identify the pin by its global index, and provide its
56
+
alternate function configuration number along with it.
57
+
When multiple pins are required to be configured as part of the same
58
+
alternate function they shall be specified as members of the same
59
+
argument list of a single "pinmux" property.
60
+
Helper macros to ease assembling the pin index from its position
61
+
(port where it sits on and pin number) and alternate function identifier
62
+
are provided by the pin controller header file at:
63
+
<dt-bindings/pinctrl/r7s9210-pinctrl.h>
64
+
Integers values in "pinmux" argument list are assembled as:
65
+
((PORT * 8 + PIN) | MUX_FUNC << 16)
66
+
67
+
Example: Board specific pins configuration
68
+
69
+
&pinctrl {
70
+
/* Serial Console */
71
+
scif4_pins: serial4 {
72
+
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
73
+
<RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
74
+
};
75
+
};
76
+
77
+
Example: Assigning a GPIO:
78
+
79
+
leds {
80
+
status = "okay";
81
+
compatible = "gpio-leds";
82
+
83
+
led0 {
84
+
/* P6_0 */
85
+
gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
86
+
};
87
+
};
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
11749
11749
F: drivers/pinctrl/qcom/
11750
11750
11751
11751
PIN CONTROLLER - RENESAS
11752
-
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11753
11752
M: Geert Uytterhoeven <geert+renesas@glider.be>
11754
11753
L: linux-renesas-soc@vger.kernel.org
11755
11754
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc
11756
11755
S: Maintained
11756
+
F: drivers/pinctrl/pinctrl-rz*
11757
11757
F: drivers/pinctrl/sh-pfc/
11758
11758
11759
11759
PIN CONTROLLER - SAMSUNG
+11
drivers/pinctrl/Kconfig
+11
drivers/pinctrl/Kconfig
···
195
195
help
196
196
This selects pinctrl driver for Renesas RZ/A1 platforms.
197
197
198
+
config PINCTRL_RZA2
199
+
bool "Renesas RZ/A2 gpio and pinctrl driver"
200
+
depends on OF
201
+
depends on ARCH_R7S9210 || COMPILE_TEST
202
+
select GPIOLIB
203
+
select GENERIC_PINCTRL_GROUPS
204
+
select GENERIC_PINMUX_FUNCTIONS
205
+
select GENERIC_PINCONF
206
+
help
207
+
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
208
+
198
209
config PINCTRL_RZN1
199
210
bool "Renesas RZ/N1 pinctrl driver"
200
211
depends on OF
+1
drivers/pinctrl/Makefile
+1
drivers/pinctrl/Makefile
···
27
27
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
28
28
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
29
29
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
30
+
obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
30
31
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
31
32
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
32
33
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
+519
drivers/pinctrl/pinctrl-rza2.c
+519
drivers/pinctrl/pinctrl-rza2.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
4
+
*
5
+
* Copyright (C) 2018 Chris Brandt
6
+
*/
7
+
8
+
/*
9
+
* This pin controller/gpio combined driver supports Renesas devices of RZ/A2
10
+
* family.
11
+
*/
12
+
13
+
#include <linux/bitops.h>
14
+
#include <linux/gpio.h>
15
+
#include <linux/module.h>
16
+
#include <linux/of_device.h>
17
+
#include <linux/pinctrl/pinmux.h>
18
+
19
+
#include "core.h"
20
+
#include "pinmux.h"
21
+
22
+
#define DRIVER_NAME "pinctrl-rza2"
23
+
24
+
#define RZA2_PINS_PER_PORT 8
25
+
#define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT)
26
+
#define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT)
27
+
28
+
/*
29
+
* Use 16 lower bits [15:0] for pin identifier
30
+
* Use 16 higher bits [31:16] for pin mux function
31
+
*/
32
+
#define MUX_PIN_ID_MASK GENMASK(15, 0)
33
+
#define MUX_FUNC_MASK GENMASK(31, 16)
34
+
#define MUX_FUNC_OFFS 16
35
+
#define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
36
+
37
+
static const char port_names[] = "0123456789ABCDEFGHJKLM";
38
+
39
+
struct rza2_pinctrl_priv {
40
+
struct device *dev;
41
+
void __iomem *base;
42
+
43
+
struct pinctrl_pin_desc *pins;
44
+
struct pinctrl_desc desc;
45
+
struct pinctrl_dev *pctl;
46
+
struct pinctrl_gpio_range gpio_range;
47
+
int npins;
48
+
};
49
+
50
+
#define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
51
+
#define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
52
+
#define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
53
+
#define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
54
+
#define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
55
+
#define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
56
+
57
+
#define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
58
+
#define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */
59
+
#define RZA2_PPOC 0x0900 /* Dedicated Pins 32-bit */
60
+
#define RZA2_PHMOMO 0x0980 /* Peripheral Pins 32-bit */
61
+
#define RZA2_PCKIO 0x09d0 /* CKIO Drive 8-bit */
62
+
63
+
#define RZA2_PDR_INPUT 0x02
64
+
#define RZA2_PDR_OUTPUT 0x03
65
+
#define RZA2_PDR_MASK 0x03
66
+
67
+
#define PWPR_B0WI BIT(7) /* Bit Write Disable */
68
+
#define PWPR_PFSWE BIT(6) /* PFS Register Write Enable */
69
+
#define PFS_ISEL BIT(6) /* Interrupt Select */
70
+
71
+
static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin,
72
+
u8 func)
73
+
{
74
+
u16 mask16;
75
+
u16 reg16;
76
+
u8 reg8;
77
+
78
+
/* Set pin to 'Non-use (Hi-z input protection)' */
79
+
reg16 = readw(pfc_base + RZA2_PDR(port));
80
+
mask16 = RZA2_PDR_MASK << (pin * 2);
81
+
reg16 &= ~mask16;
82
+
writew(reg16, pfc_base + RZA2_PDR(port));
83
+
84
+
/* Temporarily switch to GPIO */
85
+
reg8 = readb(pfc_base + RZA2_PMR(port));
86
+
reg8 &= ~BIT(pin);
87
+
writeb(reg8, pfc_base + RZA2_PMR(port));
88
+
89
+
/* PFS Register Write Protect : OFF */
90
+
writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
91
+
writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=1 */
92
+
93
+
/* Set Pin function (interrupt disabled, ISEL=0) */
94
+
writeb(func, pfc_base + RZA2_PFS(port, pin));
95
+
96
+
/* PFS Register Write Protect : ON */
97
+
writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
98
+
writeb(0x80, pfc_base + RZA2_PWPR); /* B0WI=1, PFSWE=0 */
99
+
100
+
/* Port Mode : Peripheral module pin functions */
101
+
reg8 = readb(pfc_base + RZA2_PMR(port));
102
+
reg8 |= BIT(pin);
103
+
writeb(reg8, pfc_base + RZA2_PMR(port));
104
+
}
105
+
106
+
static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
107
+
u8 dir)
108
+
{
109
+
u8 port = RZA2_PIN_ID_TO_PORT(offset);
110
+
u8 pin = RZA2_PIN_ID_TO_PIN(offset);
111
+
u16 mask16;
112
+
u16 reg16;
113
+
114
+
reg16 = readw(pfc_base + RZA2_PDR(port));
115
+
mask16 = RZA2_PDR_MASK << (pin * 2);
116
+
reg16 &= ~mask16;
117
+
118
+
if (dir == GPIOF_DIR_IN)
119
+
reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */
120
+
else
121
+
reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */
122
+
123
+
writew(reg16, pfc_base + RZA2_PDR(port));
124
+
}
125
+
126
+
static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
127
+
{
128
+
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
129
+
u8 port = RZA2_PIN_ID_TO_PORT(offset);
130
+
u8 pin = RZA2_PIN_ID_TO_PIN(offset);
131
+
u16 reg16;
132
+
133
+
reg16 = readw(priv->base + RZA2_PDR(port));
134
+
reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
135
+
136
+
if (reg16 == RZA2_PDR_OUTPUT)
137
+
return GPIOF_DIR_OUT;
138
+
139
+
if (reg16 == RZA2_PDR_INPUT)
140
+
return GPIOF_DIR_IN;
141
+
142
+
/*
143
+
* This GPIO controller has a default Hi-Z state that is not input or
144
+
* output, so force the pin to input now.
145
+
*/
146
+
rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
147
+
148
+
return GPIOF_DIR_IN;
149
+
}
150
+
151
+
static int rza2_chip_direction_input(struct gpio_chip *chip,
152
+
unsigned int offset)
153
+
{
154
+
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
155
+
156
+
rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
157
+
158
+
return 0;
159
+
}
160
+
161
+
static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
162
+
{
163
+
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
164
+
u8 port = RZA2_PIN_ID_TO_PORT(offset);
165
+
u8 pin = RZA2_PIN_ID_TO_PIN(offset);
166
+
167
+
return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
168
+
}
169
+
170
+
static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
171
+
int value)
172
+
{
173
+
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
174
+
u8 port = RZA2_PIN_ID_TO_PORT(offset);
175
+
u8 pin = RZA2_PIN_ID_TO_PIN(offset);
176
+
u8 new_value;
177
+
178
+
new_value = readb(priv->base + RZA2_PODR(port));
179
+
180
+
if (value)
181
+
new_value |= BIT(pin);
182
+
else
183
+
new_value &= ~BIT(pin);
184
+
185
+
writeb(new_value, priv->base + RZA2_PODR(port));
186
+
}
187
+
188
+
static int rza2_chip_direction_output(struct gpio_chip *chip,
189
+
unsigned int offset, int val)
190
+
{
191
+
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
192
+
193
+
rza2_chip_set(chip, offset, val);
194
+
rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_OUT);
195
+
196
+
return 0;
197
+
}
198
+
199
+
static const char * const rza2_gpio_names[] = {
200
+
"P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
201
+
"P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
202
+
"P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
203
+
"P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
204
+
"P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
205
+
"P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
206
+
"P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
207
+
"P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
208
+
"P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
209
+
"P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
210
+
"PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7",
211
+
"PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7",
212
+
"PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
213
+
"PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
214
+
"PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
215
+
"PF_0", "PF_1", "PF_2", "PF_3", "P0_4", "PF_5", "PF_6", "PF_7",
216
+
"PG_0", "PG_1", "PG_2", "P0_3", "PG_4", "PG_5", "PG_6", "PG_7",
217
+
"PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
218
+
/* port I does not exist */
219
+
"PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
220
+
"PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7",
221
+
"PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7",
222
+
"PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7",
223
+
};
224
+
225
+
static struct gpio_chip chip = {
226
+
.names = rza2_gpio_names,
227
+
.base = -1,
228
+
.get_direction = rza2_chip_get_direction,
229
+
.direction_input = rza2_chip_direction_input,
230
+
.direction_output = rza2_chip_direction_output,
231
+
.get = rza2_chip_get,
232
+
.set = rza2_chip_set,
233
+
};
234
+
235
+
static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
236
+
{
237
+
struct device_node *np = priv->dev->of_node;
238
+
struct of_phandle_args of_args;
239
+
int ret;
240
+
241
+
chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
242
+
chip.of_node = np;
243
+
chip.parent = priv->dev;
244
+
chip.ngpio = priv->npins;
245
+
246
+
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
247
+
&of_args);
248
+
if (ret) {
249
+
dev_err(priv->dev, "Unable to parse gpio-ranges\n");
250
+
return ret;
251
+
}
252
+
253
+
if ((of_args.args[0] != 0) ||
254
+
(of_args.args[1] != 0) ||
255
+
(of_args.args[2] != priv->npins)) {
256
+
dev_err(priv->dev, "gpio-ranges does not match selected SOC\n");
257
+
return -EINVAL;
258
+
}
259
+
priv->gpio_range.id = 0;
260
+
priv->gpio_range.pin_base = priv->gpio_range.base = 0;
261
+
priv->gpio_range.npins = priv->npins;
262
+
priv->gpio_range.name = chip.label;
263
+
priv->gpio_range.gc = &chip;
264
+
265
+
/* Register our gpio chip with gpiolib */
266
+
ret = devm_gpiochip_add_data(priv->dev, &chip, priv);
267
+
if (ret)
268
+
return ret;
269
+
270
+
/* Register pin range with pinctrl core */
271
+
pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range);
272
+
273
+
dev_dbg(priv->dev, "Registered gpio controller\n");
274
+
275
+
return 0;
276
+
}
277
+
278
+
static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv)
279
+
{
280
+
struct pinctrl_pin_desc *pins;
281
+
unsigned int i;
282
+
int ret;
283
+
284
+
pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL);
285
+
if (!pins)
286
+
return -ENOMEM;
287
+
288
+
priv->pins = pins;
289
+
priv->desc.pins = pins;
290
+
priv->desc.npins = priv->npins;
291
+
292
+
for (i = 0; i < priv->npins; i++) {
293
+
pins[i].number = i;
294
+
pins[i].name = rza2_gpio_names[i];
295
+
}
296
+
297
+
ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv,
298
+
&priv->pctl);
299
+
if (ret) {
300
+
dev_err(priv->dev, "pinctrl registration failed\n");
301
+
return ret;
302
+
}
303
+
304
+
ret = pinctrl_enable(priv->pctl);
305
+
if (ret) {
306
+
dev_err(priv->dev, "pinctrl enable failed\n");
307
+
return ret;
308
+
}
309
+
310
+
ret = rza2_gpio_register(priv);
311
+
if (ret) {
312
+
dev_err(priv->dev, "GPIO registration failed\n");
313
+
return ret;
314
+
}
315
+
316
+
return 0;
317
+
}
318
+
319
+
/*
320
+
* For each DT node, create a single pin mapping. That pin mapping will only
321
+
* contain a single group of pins, and that group of pins will only have a
322
+
* single function that can be selected.
323
+
*/
324
+
static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev,
325
+
struct device_node *np,
326
+
struct pinctrl_map **map,
327
+
unsigned int *num_maps)
328
+
{
329
+
struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
330
+
unsigned int *pins, *psel_val;
331
+
int i, ret, npins, gsel, fsel;
332
+
struct property *of_pins;
333
+
const char **pin_fn;
334
+
335
+
/* Find out how many pins to map */
336
+
of_pins = of_find_property(np, "pinmux", NULL);
337
+
if (!of_pins) {
338
+
dev_info(priv->dev, "Missing pinmux property\n");
339
+
return -ENOENT;
340
+
}
341
+
npins = of_pins->length / sizeof(u32);
342
+
343
+
pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL);
344
+
psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val),
345
+
GFP_KERNEL);
346
+
pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL);
347
+
if (!pins || !psel_val || !pin_fn)
348
+
return -ENOMEM;
349
+
350
+
/* Collect pin locations and mux settings from DT properties */
351
+
for (i = 0; i < npins; ++i) {
352
+
u32 value;
353
+
354
+
ret = of_property_read_u32_index(np, "pinmux", i, &value);
355
+
if (ret)
356
+
return ret;
357
+
pins[i] = value & MUX_PIN_ID_MASK;
358
+
psel_val[i] = MUX_FUNC(value);
359
+
}
360
+
361
+
/* Register a single pin group listing all the pins we read from DT */
362
+
gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
363
+
if (gsel < 0)
364
+
return gsel;
365
+
366
+
/*
367
+
* Register a single group function where the 'data' is an array PSEL
368
+
* register values read from DT.
369
+
*/
370
+
pin_fn[0] = np->name;
371
+
fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
372
+
psel_val);
373
+
if (fsel < 0) {
374
+
ret = fsel;
375
+
goto remove_group;
376
+
}
377
+
378
+
dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins);
379
+
380
+
/* Create map where to retrieve function and mux settings from */
381
+
*num_maps = 0;
382
+
*map = kzalloc(sizeof(**map), GFP_KERNEL);
383
+
if (!*map) {
384
+
ret = -ENOMEM;
385
+
goto remove_function;
386
+
}
387
+
388
+
(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
389
+
(*map)->data.mux.group = np->name;
390
+
(*map)->data.mux.function = np->name;
391
+
*num_maps = 1;
392
+
393
+
return 0;
394
+
395
+
remove_function:
396
+
pinmux_generic_remove_function(pctldev, fsel);
397
+
398
+
remove_group:
399
+
pinctrl_generic_remove_group(pctldev, gsel);
400
+
401
+
dev_err(priv->dev, "Unable to parse DT node %s\n", np->name);
402
+
403
+
return ret;
404
+
}
405
+
406
+
static void rza2_dt_free_map(struct pinctrl_dev *pctldev,
407
+
struct pinctrl_map *map, unsigned int num_maps)
408
+
{
409
+
kfree(map);
410
+
}
411
+
412
+
static const struct pinctrl_ops rza2_pinctrl_ops = {
413
+
.get_groups_count = pinctrl_generic_get_group_count,
414
+
.get_group_name = pinctrl_generic_get_group_name,
415
+
.get_group_pins = pinctrl_generic_get_group_pins,
416
+
.dt_node_to_map = rza2_dt_node_to_map,
417
+
.dt_free_map = rza2_dt_free_map,
418
+
};
419
+
420
+
static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
421
+
unsigned int group)
422
+
{
423
+
struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
424
+
struct function_desc *func;
425
+
unsigned int i, *psel_val;
426
+
struct group_desc *grp;
427
+
428
+
grp = pinctrl_generic_get_group(pctldev, group);
429
+
if (!grp)
430
+
return -EINVAL;
431
+
432
+
func = pinmux_generic_get_function(pctldev, selector);
433
+
if (!func)
434
+
return -EINVAL;
435
+
436
+
psel_val = func->data;
437
+
438
+
for (i = 0; i < grp->num_pins; ++i) {
439
+
dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
440
+
port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])],
441
+
RZA2_PIN_ID_TO_PIN(grp->pins[i]),
442
+
psel_val[i]);
443
+
rza2_set_pin_function(
444
+
priv->base,
445
+
RZA2_PIN_ID_TO_PORT(grp->pins[i]),
446
+
RZA2_PIN_ID_TO_PIN(grp->pins[i]),
447
+
psel_val[i]);
448
+
}
449
+
450
+
return 0;
451
+
}
452
+
453
+
static const struct pinmux_ops rza2_pinmux_ops = {
454
+
.get_functions_count = pinmux_generic_get_function_count,
455
+
.get_function_name = pinmux_generic_get_function_name,
456
+
.get_function_groups = pinmux_generic_get_function_groups,
457
+
.set_mux = rza2_set_mux,
458
+
.strict = true,
459
+
};
460
+
461
+
static int rza2_pinctrl_probe(struct platform_device *pdev)
462
+
{
463
+
struct rza2_pinctrl_priv *priv;
464
+
struct resource *res;
465
+
int ret;
466
+
467
+
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
468
+
if (!priv)
469
+
return -ENOMEM;
470
+
471
+
priv->dev = &pdev->dev;
472
+
473
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474
+
priv->base = devm_ioremap_resource(&pdev->dev, res);
475
+
if (IS_ERR(priv->base))
476
+
return PTR_ERR(priv->base);
477
+
478
+
platform_set_drvdata(pdev, priv);
479
+
480
+
priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) *
481
+
RZA2_PINS_PER_PORT;
482
+
483
+
priv->desc.name = DRIVER_NAME;
484
+
priv->desc.pctlops = &rza2_pinctrl_ops;
485
+
priv->desc.pmxops = &rza2_pinmux_ops;
486
+
priv->desc.owner = THIS_MODULE;
487
+
488
+
ret = rza2_pinctrl_register(priv);
489
+
if (ret)
490
+
return ret;
491
+
492
+
dev_info(&pdev->dev, "Registered ports P0 - P%c\n",
493
+
port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]);
494
+
495
+
return 0;
496
+
}
497
+
498
+
static const struct of_device_id rza2_pinctrl_of_match[] = {
499
+
{ .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
500
+
{ /* sentinel */ }
501
+
};
502
+
503
+
static struct platform_driver rza2_pinctrl_driver = {
504
+
.driver = {
505
+
.name = DRIVER_NAME,
506
+
.of_match_table = rza2_pinctrl_of_match,
507
+
},
508
+
.probe = rza2_pinctrl_probe,
509
+
};
510
+
511
+
static int __init rza2_pinctrl_init(void)
512
+
{
513
+
return platform_driver_register(&rza2_pinctrl_driver);
514
+
}
515
+
core_initcall(rza2_pinctrl_init);
516
+
517
+
MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
518
+
MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
519
+
MODULE_LICENSE("GPL v2");
+676
-2
drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+676
-2
drivers/pinctrl/sh-pfc/pfc-r8a77470.c
···
10
10
#include "sh_pfc.h"
11
11
12
12
#define CPU_ALL_PORT(fn, sfx) \
13
-
PORT_GP_23(0, fn, sfx), \
13
+
PORT_GP_4(0, fn, sfx), \
14
+
PORT_GP_1(0, 4, fn, sfx), \
15
+
PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
16
+
PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
17
+
PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
18
+
PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
19
+
PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
20
+
PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
21
+
PORT_GP_1(0, 11, fn, sfx), \
22
+
PORT_GP_1(0, 12, fn, sfx), \
23
+
PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
24
+
PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
25
+
PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
26
+
PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27
+
PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28
+
PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
29
+
PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
30
+
PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
31
+
PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
32
+
PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
14
33
PORT_GP_23(1, fn, sfx), \
15
34
PORT_GP_32(2, fn, sfx), \
16
35
PORT_GP_17(3, fn, sfx), \
17
36
PORT_GP_1(3, 27, fn, sfx), \
18
37
PORT_GP_1(3, 28, fn, sfx), \
19
38
PORT_GP_1(3, 29, fn, sfx), \
20
-
PORT_GP_26(4, fn, sfx), \
39
+
PORT_GP_14(4, fn, sfx), \
40
+
PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
41
+
PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
42
+
PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
43
+
PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
44
+
PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
45
+
PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
46
+
PORT_GP_1(4, 20, fn, sfx), \
47
+
PORT_GP_1(4, 21, fn, sfx), \
48
+
PORT_GP_1(4, 22, fn, sfx), \
49
+
PORT_GP_1(4, 23, fn, sfx), \
50
+
PORT_GP_1(4, 24, fn, sfx), \
51
+
PORT_GP_1(4, 25, fn, sfx), \
21
52
PORT_GP_32(5, fn, sfx)
22
53
23
54
enum {
···
1315
1284
static const unsigned int du0_disp_mux[] = {
1316
1285
DU0_DISP_MARK
1317
1286
};
1287
+
static const unsigned int du1_rgb666_pins[] = {
1288
+
/* R[7:2], G[7:2], B[7:2] */
1289
+
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
1290
+
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1291
+
RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
1292
+
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
1293
+
RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1294
+
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1295
+
};
1296
+
static const unsigned int du1_rgb666_mux[] = {
1297
+
DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1298
+
DU1_DR3_MARK, DU1_DR2_MARK,
1299
+
DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1300
+
DU1_DG3_MARK, DU1_DG2_MARK,
1301
+
DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1302
+
DU1_DB3_MARK, DU1_DB2_MARK,
1303
+
};
1304
+
static const unsigned int du1_rgb888_pins[] = {
1305
+
/* R[7:0], G[7:0], B[7:0] */
1306
+
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
1307
+
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1308
+
RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1309
+
RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
1310
+
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
1311
+
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1312
+
RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1313
+
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1314
+
RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1315
+
};
1316
+
static const unsigned int du1_rgb888_mux[] = {
1317
+
DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1318
+
DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1319
+
DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1320
+
DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1321
+
DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1322
+
DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1323
+
};
1324
+
static const unsigned int du1_clk0_out_pins[] = {
1325
+
/* DOTCLKOUT0 */
1326
+
RCAR_GP_PIN(5, 2),
1327
+
};
1328
+
static const unsigned int du1_clk0_out_mux[] = {
1329
+
DU1_DOTCLKOUT0_MARK
1330
+
};
1331
+
static const unsigned int du1_clk1_out_pins[] = {
1332
+
/* DOTCLKOUT1 */
1333
+
RCAR_GP_PIN(5, 0),
1334
+
};
1335
+
static const unsigned int du1_clk1_out_mux[] = {
1336
+
DU1_DOTCLKOUT1_MARK
1337
+
};
1338
+
static const unsigned int du1_clk_in_pins[] = {
1339
+
/* DOTCLKIN */
1340
+
RCAR_GP_PIN(5, 1),
1341
+
};
1342
+
static const unsigned int du1_clk_in_mux[] = {
1343
+
DU1_DOTCLKIN_MARK
1344
+
};
1345
+
static const unsigned int du1_sync_pins[] = {
1346
+
/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1347
+
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4),
1348
+
};
1349
+
static const unsigned int du1_sync_mux[] = {
1350
+
DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1351
+
};
1352
+
static const unsigned int du1_oddf_pins[] = {
1353
+
/* EXODDF/ODDF/DISP/CDE */
1354
+
RCAR_GP_PIN(5, 3),
1355
+
};
1356
+
static const unsigned int du1_oddf_mux[] = {
1357
+
DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1358
+
};
1359
+
static const unsigned int du1_cde_pins[] = {
1360
+
/* CDE */
1361
+
RCAR_GP_PIN(5, 7),
1362
+
};
1363
+
static const unsigned int du1_cde_mux[] = {
1364
+
DU1_CDE_MARK
1365
+
};
1366
+
static const unsigned int du1_disp_pins[] = {
1367
+
/* DISP */
1368
+
RCAR_GP_PIN(5, 6),
1369
+
};
1370
+
static const unsigned int du1_disp_mux[] = {
1371
+
DU1_DISP_MARK
1372
+
};
1373
+
/* - I2C0 ------------------------------------------------------------------- */
1374
+
static const unsigned int i2c0_a_pins[] = {
1375
+
/* SCL, SDA */
1376
+
RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1377
+
};
1378
+
static const unsigned int i2c0_a_mux[] = {
1379
+
SCL0_A_MARK, SDA0_A_MARK,
1380
+
};
1381
+
static const unsigned int i2c0_b_pins[] = {
1382
+
/* SCL, SDA */
1383
+
RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1384
+
};
1385
+
static const unsigned int i2c0_b_mux[] = {
1386
+
SCL0_B_MARK, SDA0_B_MARK,
1387
+
};
1388
+
static const unsigned int i2c0_c_pins[] = {
1389
+
/* SCL, SDA */
1390
+
RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1391
+
};
1392
+
static const unsigned int i2c0_c_mux[] = {
1393
+
SCL0_C_MARK, SDA0_C_MARK,
1394
+
};
1395
+
static const unsigned int i2c0_d_pins[] = {
1396
+
/* SCL, SDA */
1397
+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
1398
+
};
1399
+
static const unsigned int i2c0_d_mux[] = {
1400
+
SCL0_D_MARK, SDA0_D_MARK,
1401
+
};
1402
+
static const unsigned int i2c0_e_pins[] = {
1403
+
/* SCL, SDA */
1404
+
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1405
+
};
1406
+
static const unsigned int i2c0_e_mux[] = {
1407
+
SCL0_E_MARK, SDA0_E_MARK,
1408
+
};
1409
+
/* - I2C1 ------------------------------------------------------------------- */
1410
+
static const unsigned int i2c1_a_pins[] = {
1411
+
/* SCL, SDA */
1412
+
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1413
+
};
1414
+
static const unsigned int i2c1_a_mux[] = {
1415
+
SCL1_A_MARK, SDA1_A_MARK,
1416
+
};
1417
+
static const unsigned int i2c1_b_pins[] = {
1418
+
/* SCL, SDA */
1419
+
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
1420
+
};
1421
+
static const unsigned int i2c1_b_mux[] = {
1422
+
SCL1_B_MARK, SDA1_B_MARK,
1423
+
};
1424
+
static const unsigned int i2c1_c_pins[] = {
1425
+
/* SCL, SDA */
1426
+
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1427
+
};
1428
+
static const unsigned int i2c1_c_mux[] = {
1429
+
SCL1_C_MARK, SDA1_C_MARK,
1430
+
};
1431
+
static const unsigned int i2c1_d_pins[] = {
1432
+
/* SCL, SDA */
1433
+
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1434
+
};
1435
+
static const unsigned int i2c1_d_mux[] = {
1436
+
SCL1_D_MARK, SDA1_D_MARK,
1437
+
};
1438
+
static const unsigned int i2c1_e_pins[] = {
1439
+
/* SCL, SDA */
1440
+
RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1441
+
};
1442
+
static const unsigned int i2c1_e_mux[] = {
1443
+
SCL1_E_MARK, SDA1_E_MARK,
1444
+
};
1445
+
/* - I2C2 ------------------------------------------------------------------- */
1446
+
static const unsigned int i2c2_a_pins[] = {
1447
+
/* SCL, SDA */
1448
+
RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
1449
+
};
1450
+
static const unsigned int i2c2_a_mux[] = {
1451
+
SCL2_A_MARK, SDA2_A_MARK,
1452
+
};
1453
+
static const unsigned int i2c2_b_pins[] = {
1454
+
/* SCL, SDA */
1455
+
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1456
+
};
1457
+
static const unsigned int i2c2_b_mux[] = {
1458
+
SCL2_B_MARK, SDA2_B_MARK,
1459
+
};
1460
+
static const unsigned int i2c2_c_pins[] = {
1461
+
/* SCL, SDA */
1462
+
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1463
+
};
1464
+
static const unsigned int i2c2_c_mux[] = {
1465
+
SCL2_C_MARK, SDA2_C_MARK,
1466
+
};
1467
+
static const unsigned int i2c2_d_pins[] = {
1468
+
/* SCL, SDA */
1469
+
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1470
+
};
1471
+
static const unsigned int i2c2_d_mux[] = {
1472
+
SCL2_D_MARK, SDA2_D_MARK,
1473
+
};
1474
+
/* - I2C3 ------------------------------------------------------------------- */
1475
+
static const unsigned int i2c3_a_pins[] = {
1476
+
/* SCL, SDA */
1477
+
RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1478
+
};
1479
+
static const unsigned int i2c3_a_mux[] = {
1480
+
SCL3_A_MARK, SDA3_A_MARK,
1481
+
};
1482
+
static const unsigned int i2c3_b_pins[] = {
1483
+
/* SCL, SDA */
1484
+
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
1485
+
};
1486
+
static const unsigned int i2c3_b_mux[] = {
1487
+
SCL3_B_MARK, SDA3_B_MARK,
1488
+
};
1489
+
static const unsigned int i2c3_c_pins[] = {
1490
+
/* SCL, SDA */
1491
+
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1492
+
};
1493
+
static const unsigned int i2c3_c_mux[] = {
1494
+
SCL3_C_MARK, SDA3_C_MARK,
1495
+
};
1496
+
static const unsigned int i2c3_d_pins[] = {
1497
+
/* SCL, SDA */
1498
+
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1499
+
};
1500
+
static const unsigned int i2c3_d_mux[] = {
1501
+
SCL3_D_MARK, SDA3_D_MARK,
1502
+
};
1503
+
static const unsigned int i2c3_e_pins[] = {
1504
+
/* SCL, SDA */
1505
+
RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
1506
+
};
1507
+
static const unsigned int i2c3_e_mux[] = {
1508
+
SCL3_E_MARK, SDA3_E_MARK,
1509
+
};
1318
1510
/* - I2C4 ------------------------------------------------------------------- */
1319
1511
static const unsigned int i2c4_a_pins[] = {
1320
1512
/* SCL, SDA */
···
1634
1380
static const unsigned int qspi0_data4_mux[] = {
1635
1381
QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
1636
1382
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1383
+
};
1384
+
static const unsigned int qspi1_ctrl_pins[] = {
1385
+
/* SPCLK, SSL */
1386
+
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9),
1387
+
};
1388
+
static const unsigned int qspi1_ctrl_mux[] = {
1389
+
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1390
+
};
1391
+
static const unsigned int qspi1_data2_pins[] = {
1392
+
/* MOSI_IO0, MISO_IO1 */
1393
+
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1394
+
};
1395
+
static const unsigned int qspi1_data2_mux[] = {
1396
+
QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
1397
+
};
1398
+
static const unsigned int qspi1_data4_pins[] = {
1399
+
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
1400
+
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1401
+
RCAR_GP_PIN(4, 8),
1402
+
};
1403
+
static const unsigned int qspi1_data4_mux[] = {
1404
+
QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
1405
+
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1637
1406
};
1638
1407
/* - SCIF0 ------------------------------------------------------------------ */
1639
1408
static const unsigned int scif0_data_a_pins[] = {
···
1896
1619
static const unsigned int scif_clk_b_mux[] = {
1897
1620
SCIF_CLK_B_MARK,
1898
1621
};
1622
+
/* - SDHI0 ------------------------------------------------------------------ */
1623
+
static const unsigned int sdhi0_data1_pins[] = {
1624
+
/* D0 */
1625
+
RCAR_GP_PIN(0, 7),
1626
+
};
1627
+
static const unsigned int sdhi0_data1_mux[] = {
1628
+
SD0_DAT0_MARK,
1629
+
};
1630
+
static const unsigned int sdhi0_data4_pins[] = {
1631
+
/* D[0:3] */
1632
+
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1633
+
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1634
+
};
1635
+
static const unsigned int sdhi0_data4_mux[] = {
1636
+
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1637
+
};
1638
+
static const unsigned int sdhi0_ctrl_pins[] = {
1639
+
/* CLK, CMD */
1640
+
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1641
+
};
1642
+
static const unsigned int sdhi0_ctrl_mux[] = {
1643
+
SD0_CLK_MARK, SD0_CMD_MARK,
1644
+
};
1645
+
static const unsigned int sdhi0_cd_pins[] = {
1646
+
/* CD */
1647
+
RCAR_GP_PIN(0, 11),
1648
+
};
1649
+
static const unsigned int sdhi0_cd_mux[] = {
1650
+
SD0_CD_MARK,
1651
+
};
1652
+
static const unsigned int sdhi0_wp_pins[] = {
1653
+
/* WP */
1654
+
RCAR_GP_PIN(0, 12),
1655
+
};
1656
+
static const unsigned int sdhi0_wp_mux[] = {
1657
+
SD0_WP_MARK,
1658
+
};
1659
+
/* - SDHI1 ------------------------------------------------------------------ */
1660
+
static const unsigned int sdhi1_data1_pins[] = {
1661
+
/* D0 */
1662
+
RCAR_GP_PIN(0, 15),
1663
+
};
1664
+
static const unsigned int sdhi1_data1_mux[] = {
1665
+
MMC0_D0_SDHI1_D0_MARK,
1666
+
};
1667
+
static const unsigned int sdhi1_data4_pins[] = {
1668
+
/* D[0:3] */
1669
+
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1670
+
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1671
+
};
1672
+
static const unsigned int sdhi1_data4_mux[] = {
1673
+
MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
1674
+
MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
1675
+
};
1676
+
static const unsigned int sdhi1_ctrl_pins[] = {
1677
+
/* CLK, CMD */
1678
+
RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1679
+
};
1680
+
static const unsigned int sdhi1_ctrl_mux[] = {
1681
+
MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
1682
+
};
1683
+
static const unsigned int sdhi1_cd_pins[] = {
1684
+
/* CD */
1685
+
RCAR_GP_PIN(0, 19),
1686
+
};
1687
+
static const unsigned int sdhi1_cd_mux[] = {
1688
+
SD1_CD_MARK,
1689
+
};
1690
+
static const unsigned int sdhi1_wp_pins[] = {
1691
+
/* WP */
1692
+
RCAR_GP_PIN(0, 20),
1693
+
};
1694
+
static const unsigned int sdhi1_wp_mux[] = {
1695
+
SD1_WP_MARK,
1696
+
};
1899
1697
/* - SDHI2 ------------------------------------------------------------------ */
1900
1698
static const unsigned int sdhi2_data1_pins[] = {
1901
1699
/* D0 */
···
2026
1674
USB1_PWEN_MARK,
2027
1675
USB1_OVC_MARK,
2028
1676
};
1677
+
/* - VIN0 ------------------------------------------------------------------- */
1678
+
static const union vin_data vin0_data_pins = {
1679
+
.data24 = {
1680
+
/* B */
1681
+
RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
1682
+
RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1683
+
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1684
+
RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1685
+
/* G */
1686
+
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1687
+
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1688
+
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
1689
+
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1690
+
/* R */
1691
+
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
1692
+
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1693
+
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1694
+
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
1695
+
},
1696
+
};
1697
+
static const union vin_data vin0_data_mux = {
1698
+
.data24 = {
1699
+
/* B */
1700
+
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
1701
+
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
1702
+
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
1703
+
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
1704
+
/* G */
1705
+
VI0_G0_MARK, VI0_G1_MARK,
1706
+
VI0_G2_MARK, VI0_G3_MARK,
1707
+
VI0_G4_MARK, VI0_G5_MARK,
1708
+
VI0_G6_MARK, VI0_G7_MARK,
1709
+
/* R */
1710
+
VI0_R0_MARK, VI0_R1_MARK,
1711
+
VI0_R2_MARK, VI0_R3_MARK,
1712
+
VI0_R4_MARK, VI0_R5_MARK,
1713
+
VI0_R6_MARK, VI0_R7_MARK,
1714
+
},
1715
+
};
1716
+
static const unsigned int vin0_data18_pins[] = {
1717
+
/* B */
1718
+
RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1719
+
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1720
+
RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1721
+
/* G */
1722
+
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1723
+
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
1724
+
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1725
+
/* R */
1726
+
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1727
+
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1728
+
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
1729
+
};
1730
+
static const unsigned int vin0_data18_mux[] = {
1731
+
/* B */
1732
+
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
1733
+
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
1734
+
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
1735
+
/* G */
1736
+
VI0_G2_MARK, VI0_G3_MARK,
1737
+
VI0_G4_MARK, VI0_G5_MARK,
1738
+
VI0_G6_MARK, VI0_G7_MARK,
1739
+
/* R */
1740
+
VI0_R2_MARK, VI0_R3_MARK,
1741
+
VI0_R4_MARK, VI0_R5_MARK,
1742
+
VI0_R6_MARK, VI0_R7_MARK,
1743
+
};
1744
+
static const unsigned int vin0_sync_pins[] = {
1745
+
RCAR_GP_PIN(5, 30), /* HSYNC */
1746
+
RCAR_GP_PIN(5, 31), /* VSYNC */
1747
+
};
1748
+
static const unsigned int vin0_sync_mux[] = {
1749
+
VI0_HSYNC_N_MARK,
1750
+
VI0_VSYNC_N_MARK,
1751
+
};
1752
+
static const unsigned int vin0_field_pins[] = {
1753
+
RCAR_GP_PIN(5, 29),
1754
+
};
1755
+
static const unsigned int vin0_field_mux[] = {
1756
+
VI0_FIELD_MARK,
1757
+
};
1758
+
static const unsigned int vin0_clkenb_pins[] = {
1759
+
RCAR_GP_PIN(5, 28),
1760
+
};
1761
+
static const unsigned int vin0_clkenb_mux[] = {
1762
+
VI0_CLKENB_MARK,
1763
+
};
1764
+
static const unsigned int vin0_clk_pins[] = {
1765
+
RCAR_GP_PIN(5, 18),
1766
+
};
1767
+
static const unsigned int vin0_clk_mux[] = {
1768
+
VI0_CLK_MARK,
1769
+
};
1770
+
/* - VIN1 ------------------------------------------------------------------- */
1771
+
static const union vin_data vin1_data_pins = {
1772
+
.data12 = {
1773
+
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1774
+
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1775
+
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
1776
+
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
1777
+
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1778
+
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1779
+
},
1780
+
};
1781
+
static const union vin_data vin1_data_mux = {
1782
+
.data12 = {
1783
+
VI1_DATA0_MARK, VI1_DATA1_MARK,
1784
+
VI1_DATA2_MARK, VI1_DATA3_MARK,
1785
+
VI1_DATA4_MARK, VI1_DATA5_MARK,
1786
+
VI1_DATA6_MARK, VI1_DATA7_MARK,
1787
+
VI1_DATA8_MARK, VI1_DATA9_MARK,
1788
+
VI1_DATA10_MARK, VI1_DATA11_MARK,
1789
+
},
1790
+
};
1791
+
static const unsigned int vin1_sync_pins[] = {
1792
+
RCAR_GP_PIN(3, 11), /* HSYNC */
1793
+
RCAR_GP_PIN(3, 12), /* VSYNC */
1794
+
};
1795
+
static const unsigned int vin1_sync_mux[] = {
1796
+
VI1_HSYNC_N_MARK,
1797
+
VI1_VSYNC_N_MARK,
1798
+
};
1799
+
static const unsigned int vin1_field_pins[] = {
1800
+
RCAR_GP_PIN(3, 10),
1801
+
};
1802
+
static const unsigned int vin1_field_mux[] = {
1803
+
VI1_FIELD_MARK,
1804
+
};
1805
+
static const unsigned int vin1_clkenb_pins[] = {
1806
+
RCAR_GP_PIN(3, 9),
1807
+
};
1808
+
static const unsigned int vin1_clkenb_mux[] = {
1809
+
VI1_CLKENB_MARK,
1810
+
};
1811
+
static const unsigned int vin1_clk_pins[] = {
1812
+
RCAR_GP_PIN(3, 0),
1813
+
};
1814
+
static const unsigned int vin1_clk_mux[] = {
1815
+
VI1_CLK_MARK,
1816
+
};
2029
1817
2030
1818
static const struct sh_pfc_pin_group pinmux_groups[] = {
2031
1819
SH_PFC_PIN_GROUP(avb_col),
···
2190
1698
SH_PFC_PIN_GROUP(du0_oddf),
2191
1699
SH_PFC_PIN_GROUP(du0_cde),
2192
1700
SH_PFC_PIN_GROUP(du0_disp),
1701
+
SH_PFC_PIN_GROUP(du1_rgb666),
1702
+
SH_PFC_PIN_GROUP(du1_rgb888),
1703
+
SH_PFC_PIN_GROUP(du1_clk0_out),
1704
+
SH_PFC_PIN_GROUP(du1_clk1_out),
1705
+
SH_PFC_PIN_GROUP(du1_clk_in),
1706
+
SH_PFC_PIN_GROUP(du1_sync),
1707
+
SH_PFC_PIN_GROUP(du1_oddf),
1708
+
SH_PFC_PIN_GROUP(du1_cde),
1709
+
SH_PFC_PIN_GROUP(du1_disp),
1710
+
SH_PFC_PIN_GROUP(i2c0_a),
1711
+
SH_PFC_PIN_GROUP(i2c0_b),
1712
+
SH_PFC_PIN_GROUP(i2c0_c),
1713
+
SH_PFC_PIN_GROUP(i2c0_d),
1714
+
SH_PFC_PIN_GROUP(i2c0_e),
1715
+
SH_PFC_PIN_GROUP(i2c1_a),
1716
+
SH_PFC_PIN_GROUP(i2c1_b),
1717
+
SH_PFC_PIN_GROUP(i2c1_c),
1718
+
SH_PFC_PIN_GROUP(i2c1_d),
1719
+
SH_PFC_PIN_GROUP(i2c1_e),
1720
+
SH_PFC_PIN_GROUP(i2c2_a),
1721
+
SH_PFC_PIN_GROUP(i2c2_b),
1722
+
SH_PFC_PIN_GROUP(i2c2_c),
1723
+
SH_PFC_PIN_GROUP(i2c2_d),
1724
+
SH_PFC_PIN_GROUP(i2c3_a),
1725
+
SH_PFC_PIN_GROUP(i2c3_b),
1726
+
SH_PFC_PIN_GROUP(i2c3_c),
1727
+
SH_PFC_PIN_GROUP(i2c3_d),
1728
+
SH_PFC_PIN_GROUP(i2c3_e),
2193
1729
SH_PFC_PIN_GROUP(i2c4_a),
2194
1730
SH_PFC_PIN_GROUP(i2c4_b),
2195
1731
SH_PFC_PIN_GROUP(i2c4_c),
···
2230
1710
SH_PFC_PIN_GROUP(qspi0_ctrl),
2231
1711
SH_PFC_PIN_GROUP(qspi0_data2),
2232
1712
SH_PFC_PIN_GROUP(qspi0_data4),
1713
+
SH_PFC_PIN_GROUP(qspi1_ctrl),
1714
+
SH_PFC_PIN_GROUP(qspi1_data2),
1715
+
SH_PFC_PIN_GROUP(qspi1_data4),
2233
1716
SH_PFC_PIN_GROUP(scif0_data_a),
2234
1717
SH_PFC_PIN_GROUP(scif0_data_b),
2235
1718
SH_PFC_PIN_GROUP(scif0_data_c),
···
2266
1743
SH_PFC_PIN_GROUP(scif5_data_f),
2267
1744
SH_PFC_PIN_GROUP(scif_clk_a),
2268
1745
SH_PFC_PIN_GROUP(scif_clk_b),
1746
+
SH_PFC_PIN_GROUP(sdhi0_data1),
1747
+
SH_PFC_PIN_GROUP(sdhi0_data4),
1748
+
SH_PFC_PIN_GROUP(sdhi0_ctrl),
1749
+
SH_PFC_PIN_GROUP(sdhi0_cd),
1750
+
SH_PFC_PIN_GROUP(sdhi0_wp),
1751
+
SH_PFC_PIN_GROUP(sdhi1_data1),
1752
+
SH_PFC_PIN_GROUP(sdhi1_data4),
1753
+
SH_PFC_PIN_GROUP(sdhi1_ctrl),
1754
+
SH_PFC_PIN_GROUP(sdhi1_cd),
1755
+
SH_PFC_PIN_GROUP(sdhi1_wp),
2269
1756
SH_PFC_PIN_GROUP(sdhi2_data1),
2270
1757
SH_PFC_PIN_GROUP(sdhi2_data4),
2271
1758
SH_PFC_PIN_GROUP(sdhi2_ctrl),
···
2283
1750
SH_PFC_PIN_GROUP(sdhi2_wp),
2284
1751
SH_PFC_PIN_GROUP(usb0),
2285
1752
SH_PFC_PIN_GROUP(usb1),
1753
+
VIN_DATA_PIN_GROUP(vin0_data, 24),
1754
+
VIN_DATA_PIN_GROUP(vin0_data, 20),
1755
+
SH_PFC_PIN_GROUP(vin0_data18),
1756
+
VIN_DATA_PIN_GROUP(vin0_data, 16),
1757
+
VIN_DATA_PIN_GROUP(vin0_data, 12),
1758
+
VIN_DATA_PIN_GROUP(vin0_data, 10),
1759
+
VIN_DATA_PIN_GROUP(vin0_data, 8),
1760
+
SH_PFC_PIN_GROUP(vin0_sync),
1761
+
SH_PFC_PIN_GROUP(vin0_field),
1762
+
SH_PFC_PIN_GROUP(vin0_clkenb),
1763
+
SH_PFC_PIN_GROUP(vin0_clk),
1764
+
VIN_DATA_PIN_GROUP(vin1_data, 12),
1765
+
VIN_DATA_PIN_GROUP(vin1_data, 10),
1766
+
VIN_DATA_PIN_GROUP(vin1_data, 8),
1767
+
SH_PFC_PIN_GROUP(vin1_sync),
1768
+
SH_PFC_PIN_GROUP(vin1_field),
1769
+
SH_PFC_PIN_GROUP(vin1_clkenb),
1770
+
SH_PFC_PIN_GROUP(vin1_clk),
2286
1771
};
2287
1772
2288
1773
static const char * const avb_groups[] = {
···
2331
1780
"du0_disp",
2332
1781
};
2333
1782
1783
+
static const char * const du1_groups[] = {
1784
+
"du1_rgb666",
1785
+
"du1_rgb888",
1786
+
"du1_clk0_out",
1787
+
"du1_clk1_out",
1788
+
"du1_clk_in",
1789
+
"du1_sync",
1790
+
"du1_oddf",
1791
+
"du1_cde",
1792
+
"du1_disp",
1793
+
};
1794
+
1795
+
static const char * const i2c0_groups[] = {
1796
+
"i2c0_a",
1797
+
"i2c0_b",
1798
+
"i2c0_c",
1799
+
"i2c0_d",
1800
+
"i2c0_e",
1801
+
};
1802
+
1803
+
static const char * const i2c1_groups[] = {
1804
+
"i2c1_a",
1805
+
"i2c1_b",
1806
+
"i2c1_c",
1807
+
"i2c1_d",
1808
+
"i2c1_e",
1809
+
};
1810
+
1811
+
static const char * const i2c2_groups[] = {
1812
+
"i2c2_a",
1813
+
"i2c2_b",
1814
+
"i2c2_c",
1815
+
"i2c2_d",
1816
+
};
1817
+
1818
+
static const char * const i2c3_groups[] = {
1819
+
"i2c3_a",
1820
+
"i2c3_b",
1821
+
"i2c3_c",
1822
+
"i2c3_d",
1823
+
"i2c3_e",
1824
+
};
1825
+
2334
1826
static const char * const i2c4_groups[] = {
2335
1827
"i2c4_a",
2336
1828
"i2c4_b",
···
2393
1799
"qspi0_ctrl",
2394
1800
"qspi0_data2",
2395
1801
"qspi0_data4",
1802
+
};
1803
+
1804
+
static const char * const qspi1_groups[] = {
1805
+
"qspi1_ctrl",
1806
+
"qspi1_data2",
1807
+
"qspi1_data4",
2396
1808
};
2397
1809
2398
1810
static const char * const scif0_groups[] = {
···
2455
1855
"scif_clk_b",
2456
1856
};
2457
1857
1858
+
static const char * const sdhi0_groups[] = {
1859
+
"sdhi0_data1",
1860
+
"sdhi0_data4",
1861
+
"sdhi0_ctrl",
1862
+
"sdhi0_cd",
1863
+
"sdhi0_wp",
1864
+
};
1865
+
1866
+
static const char * const sdhi1_groups[] = {
1867
+
"sdhi1_data1",
1868
+
"sdhi1_data4",
1869
+
"sdhi1_ctrl",
1870
+
"sdhi1_cd",
1871
+
"sdhi1_wp",
1872
+
};
1873
+
2458
1874
static const char * const sdhi2_groups[] = {
2459
1875
"sdhi2_data1",
2460
1876
"sdhi2_data4",
···
2487
1871
"usb1",
2488
1872
};
2489
1873
1874
+
static const char * const vin0_groups[] = {
1875
+
"vin0_data24",
1876
+
"vin0_data20",
1877
+
"vin0_data18",
1878
+
"vin0_data16",
1879
+
"vin0_data12",
1880
+
"vin0_data10",
1881
+
"vin0_data8",
1882
+
"vin0_sync",
1883
+
"vin0_field",
1884
+
"vin0_clkenb",
1885
+
"vin0_clk",
1886
+
};
1887
+
1888
+
static const char * const vin1_groups[] = {
1889
+
"vin1_data12",
1890
+
"vin1_data10",
1891
+
"vin1_data8",
1892
+
"vin1_sync",
1893
+
"vin1_field",
1894
+
"vin1_clkenb",
1895
+
"vin1_clk",
1896
+
};
1897
+
2490
1898
static const struct sh_pfc_function pinmux_functions[] = {
2491
1899
SH_PFC_FUNCTION(avb),
2492
1900
SH_PFC_FUNCTION(du0),
1901
+
SH_PFC_FUNCTION(du1),
1902
+
SH_PFC_FUNCTION(i2c0),
1903
+
SH_PFC_FUNCTION(i2c1),
1904
+
SH_PFC_FUNCTION(i2c2),
1905
+
SH_PFC_FUNCTION(i2c3),
2493
1906
SH_PFC_FUNCTION(i2c4),
2494
1907
SH_PFC_FUNCTION(mmc),
2495
1908
SH_PFC_FUNCTION(qspi0),
1909
+
SH_PFC_FUNCTION(qspi1),
2496
1910
SH_PFC_FUNCTION(scif0),
2497
1911
SH_PFC_FUNCTION(scif1),
2498
1912
SH_PFC_FUNCTION(scif2),
···
2530
1884
SH_PFC_FUNCTION(scif4),
2531
1885
SH_PFC_FUNCTION(scif5),
2532
1886
SH_PFC_FUNCTION(scif_clk),
1887
+
SH_PFC_FUNCTION(sdhi0),
1888
+
SH_PFC_FUNCTION(sdhi1),
2533
1889
SH_PFC_FUNCTION(sdhi2),
2534
1890
SH_PFC_FUNCTION(usb0),
2535
1891
SH_PFC_FUNCTION(usb1),
1892
+
SH_PFC_FUNCTION(vin0),
1893
+
SH_PFC_FUNCTION(vin1),
2536
1894
};
2537
1895
2538
1896
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
···
3379
2729
{ },
3380
2730
};
3381
2731
2732
+
static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2733
+
u32 *pocctrl)
2734
+
{
2735
+
int bit = -EINVAL;
2736
+
2737
+
*pocctrl = 0xe60600b0;
2738
+
2739
+
if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10))
2740
+
bit = 0;
2741
+
2742
+
if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22))
2743
+
bit = 2;
2744
+
2745
+
if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19))
2746
+
bit = 1;
2747
+
2748
+
return bit;
2749
+
}
2750
+
2751
+
static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
2752
+
.pin_to_pocctrl = r8a77470_pin_to_pocctrl,
2753
+
};
2754
+
3382
2755
#ifdef CONFIG_PINCTRL_PFC_R8A77470
3383
2756
const struct sh_pfc_soc_info r8a77470_pinmux_info = {
3384
2757
.name = "r8a77470_pfc",
2758
+
.ops = &r8a77470_pinmux_ops,
3385
2759
.unlock_reg = 0xe6060000, /* PMMR */
3386
2760
3387
2761
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+11
-11
drivers/pinctrl/sh-pfc/pfc-r8a7792.c
+11
-11
drivers/pinctrl/sh-pfc/pfc-r8a7792.c
···
1474
1474
VI1_CLK_MARK,
1475
1475
};
1476
1476
/* - VIN2 ------------------------------------------------------------------- */
1477
-
static const union vin_data vin2_data_pins = {
1477
+
static const union vin_data16 vin2_data_pins = {
1478
1478
.data16 = {
1479
1479
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1480
1480
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
···
1486
1486
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1487
1487
},
1488
1488
};
1489
-
static const union vin_data vin2_data_mux = {
1489
+
static const union vin_data16 vin2_data_mux = {
1490
1490
.data16 = {
1491
1491
VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1492
1492
VI2_D2_C2_MARK, VI2_D3_C3_MARK,
···
1524
1524
VI2_CLK_MARK,
1525
1525
};
1526
1526
/* - VIN3 ------------------------------------------------------------------- */
1527
-
static const union vin_data vin3_data_pins = {
1527
+
static const union vin_data16 vin3_data_pins = {
1528
1528
.data16 = {
1529
1529
RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1530
1530
RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
···
1536
1536
RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
1537
1537
},
1538
1538
};
1539
-
static const union vin_data vin3_data_mux = {
1539
+
static const union vin_data16 vin3_data_mux = {
1540
1540
.data16 = {
1541
1541
VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1542
1542
VI3_D2_C2_MARK, VI3_D3_C3_MARK,
···
1574
1574
VI3_CLK_MARK,
1575
1575
};
1576
1576
/* - VIN4 ------------------------------------------------------------------- */
1577
-
static const union vin_data vin4_data_pins = {
1577
+
static const union vin_data12 vin4_data_pins = {
1578
1578
.data12 = {
1579
1579
RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1580
1580
RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
···
1584
1584
RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
1585
1585
},
1586
1586
};
1587
-
static const union vin_data vin4_data_mux = {
1587
+
static const union vin_data12 vin4_data_mux = {
1588
1588
.data12 = {
1589
1589
VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1590
1590
VI4_D2_C2_MARK, VI4_D3_C3_MARK,
···
1620
1620
VI4_CLK_MARK,
1621
1621
};
1622
1622
/* - VIN5 ------------------------------------------------------------------- */
1623
-
static const union vin_data vin5_data_pins = {
1623
+
static const union vin_data12 vin5_data_pins = {
1624
1624
.data12 = {
1625
1625
RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1626
1626
RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
···
1630
1630
RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
1631
1631
},
1632
1632
};
1633
-
static const union vin_data vin5_data_mux = {
1633
+
static const union vin_data12 vin5_data_mux = {
1634
1634
.data12 = {
1635
1635
VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1636
1636
VI5_D2_C2_MARK, VI5_D3_C3_MARK,
···
1744
1744
VIN_DATA_PIN_GROUP(vin1_data, 12),
1745
1745
VIN_DATA_PIN_GROUP(vin1_data, 10),
1746
1746
VIN_DATA_PIN_GROUP(vin1_data, 8),
1747
-
VIN_DATA_PIN_GROUP(vin1_data_b, 24),
1748
-
VIN_DATA_PIN_GROUP(vin1_data_b, 20),
1747
+
VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
1748
+
VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
1749
1749
SH_PFC_PIN_GROUP(vin1_data18_b),
1750
-
VIN_DATA_PIN_GROUP(vin1_data_b, 16),
1750
+
VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
1751
1751
SH_PFC_PIN_GROUP(vin1_sync),
1752
1752
SH_PFC_PIN_GROUP(vin1_field),
1753
1753
SH_PFC_PIN_GROUP(vin1_clkenb),
+2
-2
drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+2
-2
drivers/pinctrl/sh-pfc/pfc-r8a7794.c
···
3704
3704
VI0_CLK_MARK,
3705
3705
};
3706
3706
/* - VIN1 ------------------------------------------------------------------- */
3707
-
static const union vin_data vin1_data_pins = {
3707
+
static const union vin_data12 vin1_data_pins = {
3708
3708
.data12 = {
3709
3709
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
3710
3710
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
···
3714
3714
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3715
3715
},
3716
3716
};
3717
-
static const union vin_data vin1_data_mux = {
3717
+
static const union vin_data12 vin1_data_mux = {
3718
3718
.data12 = {
3719
3719
VI1_DATA0_MARK, VI1_DATA1_MARK,
3720
3720
VI1_DATA2_MARK, VI1_DATA3_MARK,
+75
-22
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+75
-22
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
···
537
537
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
538
538
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
539
539
540
+
#define PINMUX_PHYS \
541
+
FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
542
+
540
543
enum {
541
544
PINMUX_RESERVED = 0,
542
545
···
565
562
PINMUX_IPSR
566
563
PINMUX_MOD_SELS
567
564
PINMUX_STATIC
565
+
PINMUX_PHYS
568
566
PINMUX_MARK_END,
569
567
#undef F_
570
568
#undef FM
···
578
574
PINMUX_SINGLE(AVS2),
579
575
PINMUX_SINGLE(HDMI0_CEC),
580
576
PINMUX_SINGLE(HDMI1_CEC),
581
-
PINMUX_SINGLE(I2C_SEL_0_1),
582
-
PINMUX_SINGLE(I2C_SEL_3_1),
583
-
PINMUX_SINGLE(I2C_SEL_5_1),
584
577
PINMUX_SINGLE(MSIOF0_RXD),
585
578
PINMUX_SINGLE(MSIOF0_SCK),
586
579
PINMUX_SINGLE(MSIOF0_TXD),
···
609
608
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
610
609
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
611
610
612
-
PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
613
-
PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
614
-
PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
611
+
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
612
+
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
613
+
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
614
+
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
615
615
616
-
PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
617
-
PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
618
-
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
616
+
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
617
+
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
618
+
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_TANS_A, I2C_SEL_5_0, SEL_SCIF4_0),
619
+
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
619
620
620
621
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
621
622
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
···
667
664
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
668
665
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
669
666
670
-
PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
671
-
PINMUX_IPSR_GPSR(IP1_23_20, A21),
672
-
PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
673
-
PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
674
-
PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
667
+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
668
+
PINMUX_IPSR_MSEL(IP1_23_20, A21, I2C_SEL_3_0),
669
+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
670
+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
671
+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
672
+
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
675
673
676
-
PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
677
-
PINMUX_IPSR_GPSR(IP1_27_24, A20),
678
-
PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
679
-
PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
674
+
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
675
+
PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0),
676
+
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
677
+
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
678
+
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
680
679
681
680
PINMUX_IPSR_GPSR(IP1_31_28, A0),
682
681
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
···
1072
1067
PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
1073
1068
PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1074
1069
1075
-
PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD),
1076
-
PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1070
+
PINMUX_IPSR_MSEL(IP10_19_16, SD1_CD, I2C_SEL_0_0),
1071
+
PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1072
+
PINMUX_IPSR_PHYS(IP10_19_16, SCL0, I2C_SEL_0_1),
1077
1073
1078
-
PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP),
1079
-
PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1),
1074
+
PINMUX_IPSR_MSEL(IP10_23_20, SD1_WP, I2C_SEL_0_0),
1075
+
PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1076
+
PINMUX_IPSR_PHYS(IP10_23_20, SDA0, I2C_SEL_0_1),
1080
1077
1081
1078
PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
1082
1079
PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
···
2273
2266
};
2274
2267
2275
2268
/* - I2C -------------------------------------------------------------------- */
2269
+
static const unsigned int i2c0_pins[] = {
2270
+
/* SCL, SDA */
2271
+
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2272
+
};
2273
+
2274
+
static const unsigned int i2c0_mux[] = {
2275
+
SCL0_MARK, SDA0_MARK,
2276
+
};
2277
+
2276
2278
static const unsigned int i2c1_a_pins[] = {
2277
2279
/* SDA, SCL */
2278
2280
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
···
2310
2294
static const unsigned int i2c2_b_mux[] = {
2311
2295
SDA2_B_MARK, SCL2_B_MARK,
2312
2296
};
2297
+
2298
+
static const unsigned int i2c3_pins[] = {
2299
+
/* SCL, SDA */
2300
+
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2301
+
};
2302
+
2303
+
static const unsigned int i2c3_mux[] = {
2304
+
SCL3_MARK, SDA3_MARK,
2305
+
};
2306
+
2307
+
static const unsigned int i2c5_pins[] = {
2308
+
/* SCL, SDA */
2309
+
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2310
+
};
2311
+
2312
+
static const unsigned int i2c5_mux[] = {
2313
+
SCL5_MARK, SDA5_MARK,
2314
+
};
2315
+
2313
2316
static const unsigned int i2c6_a_pins[] = {
2314
2317
/* SDA, SCL */
2315
2318
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
···
3971
3936
SH_PFC_PIN_GROUP(hscif4_clk),
3972
3937
SH_PFC_PIN_GROUP(hscif4_ctrl),
3973
3938
SH_PFC_PIN_GROUP(hscif4_data_b),
3939
+
SH_PFC_PIN_GROUP(i2c0),
3974
3940
SH_PFC_PIN_GROUP(i2c1_a),
3975
3941
SH_PFC_PIN_GROUP(i2c1_b),
3976
3942
SH_PFC_PIN_GROUP(i2c2_a),
3977
3943
SH_PFC_PIN_GROUP(i2c2_b),
3944
+
SH_PFC_PIN_GROUP(i2c3),
3945
+
SH_PFC_PIN_GROUP(i2c5),
3978
3946
SH_PFC_PIN_GROUP(i2c6_a),
3979
3947
SH_PFC_PIN_GROUP(i2c6_b),
3980
3948
SH_PFC_PIN_GROUP(i2c6_c),
···
4347
4309
"hscif4_data_b",
4348
4310
};
4349
4311
4312
+
static const char * const i2c0_groups[] = {
4313
+
"i2c0",
4314
+
};
4315
+
4350
4316
static const char * const i2c1_groups[] = {
4351
4317
"i2c1_a",
4352
4318
"i2c1_b",
···
4359
4317
static const char * const i2c2_groups[] = {
4360
4318
"i2c2_a",
4361
4319
"i2c2_b",
4320
+
};
4321
+
4322
+
static const char * const i2c3_groups[] = {
4323
+
"i2c3",
4324
+
};
4325
+
4326
+
static const char * const i2c5_groups[] = {
4327
+
"i2c5",
4362
4328
};
4363
4329
4364
4330
static const char * const i2c6_groups[] = {
···
4701
4651
SH_PFC_FUNCTION(hscif2),
4702
4652
SH_PFC_FUNCTION(hscif3),
4703
4653
SH_PFC_FUNCTION(hscif4),
4654
+
SH_PFC_FUNCTION(i2c0),
4704
4655
SH_PFC_FUNCTION(i2c1),
4705
4656
SH_PFC_FUNCTION(i2c2),
4657
+
SH_PFC_FUNCTION(i2c3),
4658
+
SH_PFC_FUNCTION(i2c5),
4706
4659
SH_PFC_FUNCTION(i2c6),
4707
4660
SH_PFC_FUNCTION(intc_ex),
4708
4661
SH_PFC_FUNCTION(msiof0),
+86
-33
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+86
-33
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
···
550
550
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
551
551
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
552
552
553
+
#define PINMUX_PHYS \
554
+
FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
555
+
553
556
enum {
554
557
PINMUX_RESERVED = 0,
555
558
···
578
575
PINMUX_IPSR
579
576
PINMUX_MOD_SELS
580
577
PINMUX_STATIC
578
+
PINMUX_PHYS
581
579
PINMUX_MARK_END,
582
580
#undef F_
583
581
#undef FM
···
592
588
PINMUX_SINGLE(CLKOUT),
593
589
PINMUX_SINGLE(HDMI0_CEC),
594
590
PINMUX_SINGLE(HDMI1_CEC),
595
-
PINMUX_SINGLE(I2C_SEL_0_1),
596
-
PINMUX_SINGLE(I2C_SEL_3_1),
597
-
PINMUX_SINGLE(I2C_SEL_5_1),
598
591
PINMUX_SINGLE(MSIOF0_RXD),
599
592
PINMUX_SINGLE(MSIOF0_SCK),
600
593
PINMUX_SINGLE(MSIOF0_TXD),
···
615
614
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
616
615
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
617
616
618
-
PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
619
-
PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
620
-
PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
621
-
PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
617
+
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
618
+
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
619
+
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
620
+
PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
621
+
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
622
622
623
-
PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
624
-
PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
625
-
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
623
+
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
624
+
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
625
+
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
626
+
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
626
627
627
628
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
628
629
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
···
677
674
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
678
675
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
679
676
680
-
PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
681
-
PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
682
-
PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
683
-
PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
677
+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
678
+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
679
+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
680
+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
681
+
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
684
682
685
-
PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
686
-
PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
687
-
PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
683
+
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
684
+
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
685
+
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
686
+
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
688
687
689
688
PINMUX_IPSR_GPSR(IP1_31_28, A0),
690
689
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
···
1118
1113
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1119
1114
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1120
1115
1121
-
PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1122
-
PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1116
+
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1117
+
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1118
+
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
1123
1119
1124
-
PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1125
-
PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1120
+
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1121
+
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1122
+
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
1126
1123
1127
1124
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1128
1125
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
···
2355
2348
};
2356
2349
2357
2350
/* - I2C -------------------------------------------------------------------- */
2351
+
static const unsigned int i2c0_pins[] = {
2352
+
/* SCL, SDA */
2353
+
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2354
+
};
2355
+
2356
+
static const unsigned int i2c0_mux[] = {
2357
+
SCL0_MARK, SDA0_MARK,
2358
+
};
2359
+
2358
2360
static const unsigned int i2c1_a_pins[] = {
2359
2361
/* SDA, SCL */
2360
2362
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
···
2392
2376
static const unsigned int i2c2_b_mux[] = {
2393
2377
SDA2_B_MARK, SCL2_B_MARK,
2394
2378
};
2379
+
2380
+
static const unsigned int i2c3_pins[] = {
2381
+
/* SCL, SDA */
2382
+
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2383
+
};
2384
+
2385
+
static const unsigned int i2c3_mux[] = {
2386
+
SCL3_MARK, SDA3_MARK,
2387
+
};
2388
+
2389
+
static const unsigned int i2c5_pins[] = {
2390
+
/* SCL, SDA */
2391
+
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2392
+
};
2393
+
2394
+
static const unsigned int i2c5_mux[] = {
2395
+
SCL5_MARK, SDA5_MARK,
2396
+
};
2397
+
2395
2398
static const unsigned int i2c6_a_pins[] = {
2396
2399
/* SDA, SCL */
2397
2400
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
···
4293
4258
SH_PFC_PIN_GROUP(hscif4_clk),
4294
4259
SH_PFC_PIN_GROUP(hscif4_ctrl),
4295
4260
SH_PFC_PIN_GROUP(hscif4_data_b),
4261
+
SH_PFC_PIN_GROUP(i2c0),
4296
4262
SH_PFC_PIN_GROUP(i2c1_a),
4297
4263
SH_PFC_PIN_GROUP(i2c1_b),
4298
4264
SH_PFC_PIN_GROUP(i2c2_a),
4299
4265
SH_PFC_PIN_GROUP(i2c2_b),
4266
+
SH_PFC_PIN_GROUP(i2c3),
4267
+
SH_PFC_PIN_GROUP(i2c5),
4300
4268
SH_PFC_PIN_GROUP(i2c6_a),
4301
4269
SH_PFC_PIN_GROUP(i2c6_b),
4302
4270
SH_PFC_PIN_GROUP(i2c6_c),
···
4512
4474
SH_PFC_PIN_GROUP(usb2),
4513
4475
SH_PFC_PIN_GROUP(usb2_ch3),
4514
4476
SH_PFC_PIN_GROUP(usb30),
4515
-
VIN_DATA_PIN_GROUP(vin4_data_a, 8),
4516
-
VIN_DATA_PIN_GROUP(vin4_data_a, 10),
4517
-
VIN_DATA_PIN_GROUP(vin4_data_a, 12),
4518
-
VIN_DATA_PIN_GROUP(vin4_data_a, 16),
4477
+
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4478
+
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4479
+
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4480
+
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4519
4481
SH_PFC_PIN_GROUP(vin4_data18_a),
4520
-
VIN_DATA_PIN_GROUP(vin4_data_a, 20),
4521
-
VIN_DATA_PIN_GROUP(vin4_data_a, 24),
4522
-
VIN_DATA_PIN_GROUP(vin4_data_b, 8),
4523
-
VIN_DATA_PIN_GROUP(vin4_data_b, 10),
4524
-
VIN_DATA_PIN_GROUP(vin4_data_b, 12),
4525
-
VIN_DATA_PIN_GROUP(vin4_data_b, 16),
4482
+
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4483
+
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4484
+
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4485
+
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4486
+
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4487
+
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4526
4488
SH_PFC_PIN_GROUP(vin4_data18_b),
4527
-
VIN_DATA_PIN_GROUP(vin4_data_b, 20),
4528
-
VIN_DATA_PIN_GROUP(vin4_data_b, 24),
4489
+
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4490
+
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4529
4491
SH_PFC_PIN_GROUP(vin4_sync),
4530
4492
SH_PFC_PIN_GROUP(vin4_field),
4531
4493
SH_PFC_PIN_GROUP(vin4_clkenb),
···
4700
4662
"hscif4_data_b",
4701
4663
};
4702
4664
4665
+
static const char * const i2c0_groups[] = {
4666
+
"i2c0",
4667
+
};
4668
+
4703
4669
static const char * const i2c1_groups[] = {
4704
4670
"i2c1_a",
4705
4671
"i2c1_b",
···
4712
4670
static const char * const i2c2_groups[] = {
4713
4671
"i2c2_a",
4714
4672
"i2c2_b",
4673
+
};
4674
+
4675
+
static const char * const i2c3_groups[] = {
4676
+
"i2c3",
4677
+
};
4678
+
4679
+
static const char * const i2c5_groups[] = {
4680
+
"i2c5",
4715
4681
};
4716
4682
4717
4683
static const char * const i2c6_groups[] = {
···
5082
5032
SH_PFC_FUNCTION(hscif2),
5083
5033
SH_PFC_FUNCTION(hscif3),
5084
5034
SH_PFC_FUNCTION(hscif4),
5035
+
SH_PFC_FUNCTION(i2c0),
5085
5036
SH_PFC_FUNCTION(i2c1),
5086
5037
SH_PFC_FUNCTION(i2c2),
5038
+
SH_PFC_FUNCTION(i2c3),
5039
+
SH_PFC_FUNCTION(i2c5),
5087
5040
SH_PFC_FUNCTION(i2c6),
5088
5041
SH_PFC_FUNCTION(intc_ex),
5089
5042
SH_PFC_FUNCTION(msiof0),
+89
-33
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+89
-33
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
···
556
556
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
557
557
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
558
558
559
+
#define PINMUX_PHYS \
560
+
FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
561
+
559
562
enum {
560
563
PINMUX_RESERVED = 0,
561
564
···
584
581
PINMUX_IPSR
585
582
PINMUX_MOD_SELS
586
583
PINMUX_STATIC
584
+
PINMUX_PHYS
587
585
PINMUX_MARK_END,
588
586
#undef F_
589
587
#undef FM
···
621
617
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
622
618
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
623
619
624
-
PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
625
-
PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
626
-
PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
620
+
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
621
+
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
622
+
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
623
+
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
627
624
628
-
PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
629
-
PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
630
-
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
625
+
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
626
+
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
627
+
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
628
+
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
631
629
632
630
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
633
631
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
···
681
675
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
682
676
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
683
677
684
-
PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
685
-
PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
686
-
PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
687
-
PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
678
+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
679
+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
680
+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
681
+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
682
+
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
688
683
689
-
PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
690
-
PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
691
-
PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
684
+
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
685
+
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
686
+
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
687
+
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
692
688
693
689
PINMUX_IPSR_GPSR(IP1_31_28, A0),
694
690
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
···
1123
1115
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
1124
1116
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1125
1117
1126
-
PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1127
-
PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
1128
-
PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1118
+
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1119
+
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0),
1120
+
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1121
+
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
1129
1122
1130
-
PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1131
-
PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
1132
-
PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1123
+
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1124
+
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0),
1125
+
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1126
+
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
1133
1127
1134
1128
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1135
1129
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
···
2357
2347
};
2358
2348
2359
2349
/* - I2C -------------------------------------------------------------------- */
2350
+
static const unsigned int i2c0_pins[] = {
2351
+
/* SCL, SDA */
2352
+
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2353
+
};
2354
+
2355
+
static const unsigned int i2c0_mux[] = {
2356
+
SCL0_MARK, SDA0_MARK,
2357
+
};
2358
+
2360
2359
static const unsigned int i2c1_a_pins[] = {
2361
2360
/* SDA, SCL */
2362
2361
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
···
2394
2375
static const unsigned int i2c2_b_mux[] = {
2395
2376
SDA2_B_MARK, SCL2_B_MARK,
2396
2377
};
2378
+
2379
+
static const unsigned int i2c3_pins[] = {
2380
+
/* SCL, SDA */
2381
+
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2382
+
};
2383
+
2384
+
static const unsigned int i2c3_mux[] = {
2385
+
SCL3_MARK, SDA3_MARK,
2386
+
};
2387
+
2388
+
static const unsigned int i2c5_pins[] = {
2389
+
/* SCL, SDA */
2390
+
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2391
+
};
2392
+
2393
+
static const unsigned int i2c5_mux[] = {
2394
+
SCL5_MARK, SDA5_MARK,
2395
+
};
2396
+
2397
2397
static const unsigned int i2c6_a_pins[] = {
2398
2398
/* SDA, SCL */
2399
2399
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
···
4162
4124
};
4163
4125
4164
4126
static const struct {
4165
-
struct sh_pfc_pin_group common[307];
4127
+
struct sh_pfc_pin_group common[310];
4166
4128
struct sh_pfc_pin_group automotive[33];
4167
4129
} pinmux_groups = {
4168
4130
.common = {
···
4235
4197
SH_PFC_PIN_GROUP(hscif4_clk),
4236
4198
SH_PFC_PIN_GROUP(hscif4_ctrl),
4237
4199
SH_PFC_PIN_GROUP(hscif4_data_b),
4200
+
SH_PFC_PIN_GROUP(i2c0),
4238
4201
SH_PFC_PIN_GROUP(i2c1_a),
4239
4202
SH_PFC_PIN_GROUP(i2c1_b),
4240
4203
SH_PFC_PIN_GROUP(i2c2_a),
4241
4204
SH_PFC_PIN_GROUP(i2c2_b),
4205
+
SH_PFC_PIN_GROUP(i2c3),
4206
+
SH_PFC_PIN_GROUP(i2c5),
4242
4207
SH_PFC_PIN_GROUP(i2c6_a),
4243
4208
SH_PFC_PIN_GROUP(i2c6_b),
4244
4209
SH_PFC_PIN_GROUP(i2c6_c),
···
4450
4409
SH_PFC_PIN_GROUP(usb0),
4451
4410
SH_PFC_PIN_GROUP(usb1),
4452
4411
SH_PFC_PIN_GROUP(usb30),
4453
-
VIN_DATA_PIN_GROUP(vin4_data_a, 8),
4454
-
VIN_DATA_PIN_GROUP(vin4_data_a, 10),
4455
-
VIN_DATA_PIN_GROUP(vin4_data_a, 12),
4456
-
VIN_DATA_PIN_GROUP(vin4_data_a, 16),
4412
+
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4413
+
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4414
+
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4415
+
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4457
4416
SH_PFC_PIN_GROUP(vin4_data18_a),
4458
-
VIN_DATA_PIN_GROUP(vin4_data_a, 20),
4459
-
VIN_DATA_PIN_GROUP(vin4_data_a, 24),
4460
-
VIN_DATA_PIN_GROUP(vin4_data_b, 8),
4461
-
VIN_DATA_PIN_GROUP(vin4_data_b, 10),
4462
-
VIN_DATA_PIN_GROUP(vin4_data_b, 12),
4463
-
VIN_DATA_PIN_GROUP(vin4_data_b, 16),
4417
+
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4418
+
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4419
+
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4420
+
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4421
+
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4422
+
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4464
4423
SH_PFC_PIN_GROUP(vin4_data18_b),
4465
-
VIN_DATA_PIN_GROUP(vin4_data_b, 20),
4466
-
VIN_DATA_PIN_GROUP(vin4_data_b, 24),
4424
+
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4425
+
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4467
4426
SH_PFC_PIN_GROUP(vin4_sync),
4468
4427
SH_PFC_PIN_GROUP(vin4_field),
4469
4428
SH_PFC_PIN_GROUP(vin4_clkenb),
···
4670
4629
"hscif4_data_b",
4671
4630
};
4672
4631
4632
+
static const char * const i2c0_groups[] = {
4633
+
"i2c0",
4634
+
};
4635
+
4673
4636
static const char * const i2c1_groups[] = {
4674
4637
"i2c1_a",
4675
4638
"i2c1_b",
···
4682
4637
static const char * const i2c2_groups[] = {
4683
4638
"i2c2_a",
4684
4639
"i2c2_b",
4640
+
};
4641
+
4642
+
static const char * const i2c3_groups[] = {
4643
+
"i2c3",
4644
+
};
4645
+
4646
+
static const char * const i2c5_groups[] = {
4647
+
"i2c5",
4685
4648
};
4686
4649
4687
4650
static const char * const i2c6_groups[] = {
···
5020
4967
};
5021
4968
5022
4969
static const struct {
5023
-
struct sh_pfc_function common[45];
4970
+
struct sh_pfc_function common[48];
5024
4971
struct sh_pfc_function automotive[6];
5025
4972
} pinmux_functions = {
5026
4973
.common = {
···
5036
4983
SH_PFC_FUNCTION(hscif2),
5037
4984
SH_PFC_FUNCTION(hscif3),
5038
4985
SH_PFC_FUNCTION(hscif4),
4986
+
SH_PFC_FUNCTION(i2c0),
5039
4987
SH_PFC_FUNCTION(i2c1),
5040
4988
SH_PFC_FUNCTION(i2c2),
4989
+
SH_PFC_FUNCTION(i2c3),
4990
+
SH_PFC_FUNCTION(i2c5),
5041
4991
SH_PFC_FUNCTION(i2c6),
5042
4992
SH_PFC_FUNCTION(intc_ex),
5043
4993
SH_PFC_FUNCTION(msiof0),
+370
drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+370
drivers/pinctrl/sh-pfc/pfc-r8a77965.c
···
1784
1784
AVB_AVTP_CAPTURE_B_MARK,
1785
1785
};
1786
1786
1787
+
/* - CAN ------------------------------------------------------------------ */
1788
+
static const unsigned int can0_data_a_pins[] = {
1789
+
/* TX, RX */
1790
+
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1791
+
};
1792
+
1793
+
static const unsigned int can0_data_a_mux[] = {
1794
+
CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1795
+
};
1796
+
1797
+
static const unsigned int can0_data_b_pins[] = {
1798
+
/* TX, RX */
1799
+
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1800
+
};
1801
+
1802
+
static const unsigned int can0_data_b_mux[] = {
1803
+
CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1804
+
};
1805
+
1806
+
static const unsigned int can1_data_pins[] = {
1807
+
/* TX, RX */
1808
+
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1809
+
};
1810
+
1811
+
static const unsigned int can1_data_mux[] = {
1812
+
CAN1_TX_MARK, CAN1_RX_MARK,
1813
+
};
1814
+
1815
+
/* - CAN Clock -------------------------------------------------------------- */
1816
+
static const unsigned int can_clk_pins[] = {
1817
+
/* CLK */
1818
+
RCAR_GP_PIN(1, 25),
1819
+
};
1820
+
1821
+
static const unsigned int can_clk_mux[] = {
1822
+
CAN_CLK_MARK,
1823
+
};
1824
+
1825
+
/* - CAN FD --------------------------------------------------------------- */
1826
+
static const unsigned int canfd0_data_a_pins[] = {
1827
+
/* TX, RX */
1828
+
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1829
+
};
1830
+
1831
+
static const unsigned int canfd0_data_a_mux[] = {
1832
+
CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1833
+
};
1834
+
1835
+
static const unsigned int canfd0_data_b_pins[] = {
1836
+
/* TX, RX */
1837
+
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1838
+
};
1839
+
1840
+
static const unsigned int canfd0_data_b_mux[] = {
1841
+
CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1842
+
};
1843
+
1844
+
static const unsigned int canfd1_data_pins[] = {
1845
+
/* TX, RX */
1846
+
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1847
+
};
1848
+
1849
+
static const unsigned int canfd1_data_mux[] = {
1850
+
CANFD1_TX_MARK, CANFD1_RX_MARK,
1851
+
};
1852
+
1787
1853
/* - DU --------------------------------------------------------------------- */
1788
1854
static const unsigned int du_rgb666_pins[] = {
1789
1855
/* R[7:2], G[7:2], B[7:2] */
···
3791
3725
USB30_PWEN_MARK, USB30_OVC_MARK,
3792
3726
};
3793
3727
3728
+
/* - VIN4 ------------------------------------------------------------------- */
3729
+
static const unsigned int vin4_data18_a_pins[] = {
3730
+
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3731
+
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3732
+
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3733
+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3734
+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3735
+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3736
+
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3737
+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3738
+
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3739
+
};
3740
+
3741
+
static const unsigned int vin4_data18_a_mux[] = {
3742
+
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3743
+
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3744
+
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3745
+
VI4_DATA10_MARK, VI4_DATA11_MARK,
3746
+
VI4_DATA12_MARK, VI4_DATA13_MARK,
3747
+
VI4_DATA14_MARK, VI4_DATA15_MARK,
3748
+
VI4_DATA18_MARK, VI4_DATA19_MARK,
3749
+
VI4_DATA20_MARK, VI4_DATA21_MARK,
3750
+
VI4_DATA22_MARK, VI4_DATA23_MARK,
3751
+
};
3752
+
3753
+
static const union vin_data vin4_data_a_pins = {
3754
+
.data24 = {
3755
+
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3756
+
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3757
+
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3758
+
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3759
+
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3760
+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3761
+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3762
+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3763
+
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3764
+
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3765
+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3766
+
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3767
+
},
3768
+
};
3769
+
3770
+
static const union vin_data vin4_data_a_mux = {
3771
+
.data24 = {
3772
+
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3773
+
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3774
+
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3775
+
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3776
+
VI4_DATA8_MARK, VI4_DATA9_MARK,
3777
+
VI4_DATA10_MARK, VI4_DATA11_MARK,
3778
+
VI4_DATA12_MARK, VI4_DATA13_MARK,
3779
+
VI4_DATA14_MARK, VI4_DATA15_MARK,
3780
+
VI4_DATA16_MARK, VI4_DATA17_MARK,
3781
+
VI4_DATA18_MARK, VI4_DATA19_MARK,
3782
+
VI4_DATA20_MARK, VI4_DATA21_MARK,
3783
+
VI4_DATA22_MARK, VI4_DATA23_MARK,
3784
+
},
3785
+
};
3786
+
3787
+
static const unsigned int vin4_data18_b_pins[] = {
3788
+
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3789
+
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3790
+
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3791
+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3792
+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3793
+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3794
+
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3795
+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3796
+
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3797
+
};
3798
+
3799
+
static const unsigned int vin4_data18_b_mux[] = {
3800
+
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3801
+
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3802
+
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3803
+
VI4_DATA10_MARK, VI4_DATA11_MARK,
3804
+
VI4_DATA12_MARK, VI4_DATA13_MARK,
3805
+
VI4_DATA14_MARK, VI4_DATA15_MARK,
3806
+
VI4_DATA18_MARK, VI4_DATA19_MARK,
3807
+
VI4_DATA20_MARK, VI4_DATA21_MARK,
3808
+
VI4_DATA22_MARK, VI4_DATA23_MARK,
3809
+
};
3810
+
3811
+
static const union vin_data vin4_data_b_pins = {
3812
+
.data24 = {
3813
+
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3814
+
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3815
+
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3816
+
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3817
+
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3818
+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3819
+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3820
+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3821
+
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3822
+
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3823
+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3824
+
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3825
+
},
3826
+
};
3827
+
3828
+
static const union vin_data vin4_data_b_mux = {
3829
+
.data24 = {
3830
+
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3831
+
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3832
+
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3833
+
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3834
+
VI4_DATA8_MARK, VI4_DATA9_MARK,
3835
+
VI4_DATA10_MARK, VI4_DATA11_MARK,
3836
+
VI4_DATA12_MARK, VI4_DATA13_MARK,
3837
+
VI4_DATA14_MARK, VI4_DATA15_MARK,
3838
+
VI4_DATA16_MARK, VI4_DATA17_MARK,
3839
+
VI4_DATA18_MARK, VI4_DATA19_MARK,
3840
+
VI4_DATA20_MARK, VI4_DATA21_MARK,
3841
+
VI4_DATA22_MARK, VI4_DATA23_MARK,
3842
+
},
3843
+
};
3844
+
3845
+
static const unsigned int vin4_sync_pins[] = {
3846
+
/* VSYNC_N, HSYNC_N */
3847
+
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3848
+
};
3849
+
3850
+
static const unsigned int vin4_sync_mux[] = {
3851
+
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
3852
+
};
3853
+
3854
+
static const unsigned int vin4_field_pins[] = {
3855
+
RCAR_GP_PIN(1, 16),
3856
+
};
3857
+
3858
+
static const unsigned int vin4_field_mux[] = {
3859
+
VI4_FIELD_MARK,
3860
+
};
3861
+
3862
+
static const unsigned int vin4_clkenb_pins[] = {
3863
+
RCAR_GP_PIN(1, 19),
3864
+
};
3865
+
3866
+
static const unsigned int vin4_clkenb_mux[] = {
3867
+
VI4_CLKENB_MARK,
3868
+
};
3869
+
3870
+
static const unsigned int vin4_clk_pins[] = {
3871
+
RCAR_GP_PIN(1, 27),
3872
+
};
3873
+
3874
+
static const unsigned int vin4_clk_mux[] = {
3875
+
VI4_CLK_MARK,
3876
+
};
3877
+
3878
+
/* - VIN5 ------------------------------------------------------------------- */
3879
+
static const union vin_data16 vin5_data_pins = {
3880
+
.data16 = {
3881
+
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3882
+
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3883
+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3884
+
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3885
+
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3886
+
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3887
+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3888
+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3889
+
},
3890
+
};
3891
+
3892
+
static const union vin_data16 vin5_data_mux = {
3893
+
.data16 = {
3894
+
VI5_DATA0_MARK, VI5_DATA1_MARK,
3895
+
VI5_DATA2_MARK, VI5_DATA3_MARK,
3896
+
VI5_DATA4_MARK, VI5_DATA5_MARK,
3897
+
VI5_DATA6_MARK, VI5_DATA7_MARK,
3898
+
VI5_DATA8_MARK, VI5_DATA9_MARK,
3899
+
VI5_DATA10_MARK, VI5_DATA11_MARK,
3900
+
VI5_DATA12_MARK, VI5_DATA13_MARK,
3901
+
VI5_DATA14_MARK, VI5_DATA15_MARK,
3902
+
},
3903
+
};
3904
+
3905
+
static const unsigned int vin5_sync_pins[] = {
3906
+
/* VSYNC_N, HSYNC_N */
3907
+
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
3908
+
};
3909
+
3910
+
static const unsigned int vin5_sync_mux[] = {
3911
+
VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
3912
+
};
3913
+
3914
+
static const unsigned int vin5_field_pins[] = {
3915
+
RCAR_GP_PIN(1, 11),
3916
+
};
3917
+
3918
+
static const unsigned int vin5_field_mux[] = {
3919
+
VI5_FIELD_MARK,
3920
+
};
3921
+
3922
+
static const unsigned int vin5_clkenb_pins[] = {
3923
+
RCAR_GP_PIN(1, 20),
3924
+
};
3925
+
3926
+
static const unsigned int vin5_clkenb_mux[] = {
3927
+
VI5_CLKENB_MARK,
3928
+
};
3929
+
3930
+
static const unsigned int vin5_clk_pins[] = {
3931
+
RCAR_GP_PIN(1, 21),
3932
+
};
3933
+
3934
+
static const unsigned int vin5_clk_mux[] = {
3935
+
VI5_CLK_MARK,
3936
+
};
3937
+
3794
3938
static const struct sh_pfc_pin_group pinmux_groups[] = {
3795
3939
SH_PFC_PIN_GROUP(audio_clk_a_a),
3796
3940
SH_PFC_PIN_GROUP(audio_clk_a_b),
···
4030
3754
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4031
3755
SH_PFC_PIN_GROUP(avb_avtp_match_b),
4032
3756
SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3757
+
SH_PFC_PIN_GROUP(can0_data_a),
3758
+
SH_PFC_PIN_GROUP(can0_data_b),
3759
+
SH_PFC_PIN_GROUP(can1_data),
3760
+
SH_PFC_PIN_GROUP(can_clk),
3761
+
SH_PFC_PIN_GROUP(canfd0_data_a),
3762
+
SH_PFC_PIN_GROUP(canfd0_data_b),
3763
+
SH_PFC_PIN_GROUP(canfd1_data),
4033
3764
SH_PFC_PIN_GROUP(du_rgb666),
4034
3765
SH_PFC_PIN_GROUP(du_rgb888),
4035
3766
SH_PFC_PIN_GROUP(du_clk_out_0),
···
4283
4000
SH_PFC_PIN_GROUP(usb0),
4284
4001
SH_PFC_PIN_GROUP(usb1),
4285
4002
SH_PFC_PIN_GROUP(usb30),
4003
+
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4004
+
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4005
+
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4006
+
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4007
+
SH_PFC_PIN_GROUP(vin4_data18_a),
4008
+
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4009
+
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4010
+
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4011
+
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4012
+
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4013
+
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4014
+
SH_PFC_PIN_GROUP(vin4_data18_b),
4015
+
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4016
+
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4017
+
SH_PFC_PIN_GROUP(vin4_sync),
4018
+
SH_PFC_PIN_GROUP(vin4_field),
4019
+
SH_PFC_PIN_GROUP(vin4_clkenb),
4020
+
SH_PFC_PIN_GROUP(vin4_clk),
4021
+
VIN_DATA_PIN_GROUP(vin5_data, 8),
4022
+
VIN_DATA_PIN_GROUP(vin5_data, 10),
4023
+
VIN_DATA_PIN_GROUP(vin5_data, 12),
4024
+
VIN_DATA_PIN_GROUP(vin5_data, 16),
4025
+
SH_PFC_PIN_GROUP(vin5_sync),
4026
+
SH_PFC_PIN_GROUP(vin5_field),
4027
+
SH_PFC_PIN_GROUP(vin5_clkenb),
4028
+
SH_PFC_PIN_GROUP(vin5_clk),
4286
4029
};
4287
4030
4288
4031
static const char * const audio_clk_groups[] = {
···
4343
4034
"avb_avtp_capture_a",
4344
4035
"avb_avtp_match_b",
4345
4036
"avb_avtp_capture_b",
4037
+
};
4038
+
4039
+
static const char * const can0_groups[] = {
4040
+
"can0_data_a",
4041
+
"can0_data_b",
4042
+
};
4043
+
4044
+
static const char * const can1_groups[] = {
4045
+
"can1_data",
4046
+
};
4047
+
4048
+
static const char * const can_clk_groups[] = {
4049
+
"can_clk",
4050
+
};
4051
+
4052
+
static const char * const canfd0_groups[] = {
4053
+
"canfd0_data_a",
4054
+
"canfd0_data_b",
4055
+
};
4056
+
4057
+
static const char * const canfd1_groups[] = {
4058
+
"canfd1_data",
4346
4059
};
4347
4060
4348
4061
static const char * const du_groups[] = {
···
4723
4392
"usb30",
4724
4393
};
4725
4394
4395
+
static const char * const vin4_groups[] = {
4396
+
"vin4_data8_a",
4397
+
"vin4_data10_a",
4398
+
"vin4_data12_a",
4399
+
"vin4_data16_a",
4400
+
"vin4_data18_a",
4401
+
"vin4_data20_a",
4402
+
"vin4_data24_a",
4403
+
"vin4_data8_b",
4404
+
"vin4_data10_b",
4405
+
"vin4_data12_b",
4406
+
"vin4_data16_b",
4407
+
"vin4_data18_b",
4408
+
"vin4_data20_b",
4409
+
"vin4_data24_b",
4410
+
"vin4_sync",
4411
+
"vin4_field",
4412
+
"vin4_clkenb",
4413
+
"vin4_clk",
4414
+
};
4415
+
4416
+
static const char * const vin5_groups[] = {
4417
+
"vin5_data8",
4418
+
"vin5_data10",
4419
+
"vin5_data12",
4420
+
"vin5_data16",
4421
+
"vin5_sync",
4422
+
"vin5_field",
4423
+
"vin5_clkenb",
4424
+
"vin5_clk",
4425
+
};
4426
+
4726
4427
static const struct sh_pfc_function pinmux_functions[] = {
4727
4428
SH_PFC_FUNCTION(audio_clk),
4728
4429
SH_PFC_FUNCTION(avb),
4430
+
SH_PFC_FUNCTION(can0),
4431
+
SH_PFC_FUNCTION(can1),
4432
+
SH_PFC_FUNCTION(can_clk),
4433
+
SH_PFC_FUNCTION(canfd0),
4434
+
SH_PFC_FUNCTION(canfd1),
4729
4435
SH_PFC_FUNCTION(du),
4730
4436
SH_PFC_FUNCTION(hscif0),
4731
4437
SH_PFC_FUNCTION(hscif1),
···
4800
4432
SH_PFC_FUNCTION(usb0),
4801
4433
SH_PFC_FUNCTION(usb1),
4802
4434
SH_PFC_FUNCTION(usb30),
4435
+
SH_PFC_FUNCTION(vin4),
4436
+
SH_PFC_FUNCTION(vin5),
4803
4437
};
4804
4438
4805
4439
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+70
drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+70
drivers/pinctrl/sh-pfc/pfc-r8a77970.c
···
1382
1382
PWM4_B_MARK,
1383
1383
};
1384
1384
1385
+
/* - QSPI0 ------------------------------------------------------------------ */
1386
+
static const unsigned int qspi0_ctrl_pins[] = {
1387
+
/* SPCLK, SSL */
1388
+
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1389
+
};
1390
+
static const unsigned int qspi0_ctrl_mux[] = {
1391
+
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1392
+
};
1393
+
static const unsigned int qspi0_data2_pins[] = {
1394
+
/* MOSI_IO0, MISO_IO1 */
1395
+
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1396
+
};
1397
+
static const unsigned int qspi0_data2_mux[] = {
1398
+
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1399
+
};
1400
+
static const unsigned int qspi0_data4_pins[] = {
1401
+
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
1402
+
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1403
+
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1404
+
};
1405
+
static const unsigned int qspi0_data4_mux[] = {
1406
+
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1407
+
QSPI0_IO2_MARK, QSPI0_IO3_MARK
1408
+
};
1409
+
1410
+
/* - QSPI1 ------------------------------------------------------------------ */
1411
+
static const unsigned int qspi1_ctrl_pins[] = {
1412
+
/* SPCLK, SSL */
1413
+
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1414
+
};
1415
+
static const unsigned int qspi1_ctrl_mux[] = {
1416
+
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1417
+
};
1418
+
static const unsigned int qspi1_data2_pins[] = {
1419
+
/* MOSI_IO0, MISO_IO1 */
1420
+
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1421
+
};
1422
+
static const unsigned int qspi1_data2_mux[] = {
1423
+
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1424
+
};
1425
+
static const unsigned int qspi1_data4_pins[] = {
1426
+
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
1427
+
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1428
+
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1429
+
};
1430
+
static const unsigned int qspi1_data4_mux[] = {
1431
+
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1432
+
QSPI1_IO2_MARK, QSPI1_IO3_MARK
1433
+
};
1434
+
1385
1435
/* - SCIF Clock ------------------------------------------------------------- */
1386
1436
static const unsigned int scif_clk_a_pins[] = {
1387
1437
/* SCIF_CLK */
···
1806
1756
SH_PFC_PIN_GROUP(pwm3_b),
1807
1757
SH_PFC_PIN_GROUP(pwm4_a),
1808
1758
SH_PFC_PIN_GROUP(pwm4_b),
1759
+
SH_PFC_PIN_GROUP(qspi0_ctrl),
1760
+
SH_PFC_PIN_GROUP(qspi0_data2),
1761
+
SH_PFC_PIN_GROUP(qspi0_data4),
1762
+
SH_PFC_PIN_GROUP(qspi1_ctrl),
1763
+
SH_PFC_PIN_GROUP(qspi1_data2),
1764
+
SH_PFC_PIN_GROUP(qspi1_data4),
1809
1765
SH_PFC_PIN_GROUP(scif_clk_a),
1810
1766
SH_PFC_PIN_GROUP(scif_clk_b),
1811
1767
SH_PFC_PIN_GROUP(scif0_data),
···
2006
1950
"pwm4_b",
2007
1951
};
2008
1952
1953
+
static const char * const qspi0_groups[] = {
1954
+
"qspi0_ctrl",
1955
+
"qspi0_data2",
1956
+
"qspi0_data4",
1957
+
};
1958
+
1959
+
static const char * const qspi1_groups[] = {
1960
+
"qspi1_ctrl",
1961
+
"qspi1_data2",
1962
+
"qspi1_data4",
1963
+
};
1964
+
2009
1965
static const char * const scif_clk_groups[] = {
2010
1966
"scif_clk_a",
2011
1967
"scif_clk_b",
···
2101
2033
SH_PFC_FUNCTION(pwm2),
2102
2034
SH_PFC_FUNCTION(pwm3),
2103
2035
SH_PFC_FUNCTION(pwm4),
2036
+
SH_PFC_FUNCTION(qspi0),
2037
+
SH_PFC_FUNCTION(qspi1),
2104
2038
SH_PFC_FUNCTION(scif_clk),
2105
2039
SH_PFC_FUNCTION(scif0),
2106
2040
SH_PFC_FUNCTION(scif1),
+70
drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+70
drivers/pinctrl/sh-pfc/pfc-r8a77980.c
···
1660
1660
PWM4_B_MARK,
1661
1661
};
1662
1662
1663
+
/* - QSPI0 ------------------------------------------------------------------ */
1664
+
static const unsigned int qspi0_ctrl_pins[] = {
1665
+
/* SPCLK, SSL */
1666
+
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1667
+
};
1668
+
static const unsigned int qspi0_ctrl_mux[] = {
1669
+
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1670
+
};
1671
+
static const unsigned int qspi0_data2_pins[] = {
1672
+
/* MOSI_IO0, MISO_IO1 */
1673
+
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1674
+
};
1675
+
static const unsigned int qspi0_data2_mux[] = {
1676
+
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1677
+
};
1678
+
static const unsigned int qspi0_data4_pins[] = {
1679
+
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
1680
+
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1681
+
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1682
+
};
1683
+
static const unsigned int qspi0_data4_mux[] = {
1684
+
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1685
+
QSPI0_IO2_MARK, QSPI0_IO3_MARK
1686
+
};
1687
+
1688
+
/* - QSPI1 ------------------------------------------------------------------ */
1689
+
static const unsigned int qspi1_ctrl_pins[] = {
1690
+
/* SPCLK, SSL */
1691
+
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1692
+
};
1693
+
static const unsigned int qspi1_ctrl_mux[] = {
1694
+
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1695
+
};
1696
+
static const unsigned int qspi1_data2_pins[] = {
1697
+
/* MOSI_IO0, MISO_IO1 */
1698
+
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1699
+
};
1700
+
static const unsigned int qspi1_data2_mux[] = {
1701
+
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1702
+
};
1703
+
static const unsigned int qspi1_data4_pins[] = {
1704
+
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
1705
+
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1706
+
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1707
+
};
1708
+
static const unsigned int qspi1_data4_mux[] = {
1709
+
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1710
+
QSPI1_IO2_MARK, QSPI1_IO3_MARK
1711
+
};
1712
+
1663
1713
/* - SCIF0 ------------------------------------------------------------------ */
1664
1714
static const unsigned int scif0_data_pins[] = {
1665
1715
/* RX0, TX0 */
···
2142
2092
SH_PFC_PIN_GROUP(pwm3_b),
2143
2093
SH_PFC_PIN_GROUP(pwm4_a),
2144
2094
SH_PFC_PIN_GROUP(pwm4_b),
2095
+
SH_PFC_PIN_GROUP(qspi0_ctrl),
2096
+
SH_PFC_PIN_GROUP(qspi0_data2),
2097
+
SH_PFC_PIN_GROUP(qspi0_data4),
2098
+
SH_PFC_PIN_GROUP(qspi1_ctrl),
2099
+
SH_PFC_PIN_GROUP(qspi1_data2),
2100
+
SH_PFC_PIN_GROUP(qspi1_data4),
2145
2101
SH_PFC_PIN_GROUP(scif0_data),
2146
2102
SH_PFC_PIN_GROUP(scif0_clk),
2147
2103
SH_PFC_PIN_GROUP(scif0_ctrl),
···
2372
2316
"pwm4_b",
2373
2317
};
2374
2318
2319
+
static const char * const qspi0_groups[] = {
2320
+
"qspi0_ctrl",
2321
+
"qspi0_data2",
2322
+
"qspi0_data4",
2323
+
};
2324
+
2325
+
static const char * const qspi1_groups[] = {
2326
+
"qspi1_ctrl",
2327
+
"qspi1_data2",
2328
+
"qspi1_data4",
2329
+
};
2330
+
2375
2331
static const char * const scif0_groups[] = {
2376
2332
"scif0_data",
2377
2333
"scif0_clk",
···
2480
2412
SH_PFC_FUNCTION(pwm2),
2481
2413
SH_PFC_FUNCTION(pwm3),
2482
2414
SH_PFC_FUNCTION(pwm4),
2415
+
SH_PFC_FUNCTION(qspi0),
2416
+
SH_PFC_FUNCTION(qspi1),
2483
2417
SH_PFC_FUNCTION(scif0),
2484
2418
SH_PFC_FUNCTION(scif1),
2485
2419
SH_PFC_FUNCTION(scif3),
+1434
-6
drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+1434
-6
drivers/pinctrl/sh-pfc/pfc-r8a77990.c
···
23
23
PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
24
24
PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
25
25
PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
26
-
PORT_GP_CFG_16(3, fn, sfx, CFG_FLAGS), \
27
-
PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS), \
26
+
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
27
+
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
28
+
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
29
+
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
30
+
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
31
+
PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
28
32
PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
29
33
PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS)
30
34
/*
···
1303
1299
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
1304
1300
};
1305
1301
1302
+
/* - AUDIO CLOCK ------------------------------------------------------------ */
1303
+
static const unsigned int audio_clk_a_pins[] = {
1304
+
/* CLK A */
1305
+
RCAR_GP_PIN(6, 8),
1306
+
};
1307
+
1308
+
static const unsigned int audio_clk_a_mux[] = {
1309
+
AUDIO_CLKA_MARK,
1310
+
};
1311
+
1312
+
static const unsigned int audio_clk_b_a_pins[] = {
1313
+
/* CLK B_A */
1314
+
RCAR_GP_PIN(5, 7),
1315
+
};
1316
+
1317
+
static const unsigned int audio_clk_b_a_mux[] = {
1318
+
AUDIO_CLKB_A_MARK,
1319
+
};
1320
+
1321
+
static const unsigned int audio_clk_b_b_pins[] = {
1322
+
/* CLK B_B */
1323
+
RCAR_GP_PIN(6, 7),
1324
+
};
1325
+
1326
+
static const unsigned int audio_clk_b_b_mux[] = {
1327
+
AUDIO_CLKB_B_MARK,
1328
+
};
1329
+
1330
+
static const unsigned int audio_clk_b_c_pins[] = {
1331
+
/* CLK B_C */
1332
+
RCAR_GP_PIN(6, 13),
1333
+
};
1334
+
1335
+
static const unsigned int audio_clk_b_c_mux[] = {
1336
+
AUDIO_CLKB_C_MARK,
1337
+
};
1338
+
1339
+
static const unsigned int audio_clk_c_a_pins[] = {
1340
+
/* CLK C_A */
1341
+
RCAR_GP_PIN(5, 16),
1342
+
};
1343
+
1344
+
static const unsigned int audio_clk_c_a_mux[] = {
1345
+
AUDIO_CLKC_A_MARK,
1346
+
};
1347
+
1348
+
static const unsigned int audio_clk_c_b_pins[] = {
1349
+
/* CLK C_B */
1350
+
RCAR_GP_PIN(6, 3),
1351
+
};
1352
+
1353
+
static const unsigned int audio_clk_c_b_mux[] = {
1354
+
AUDIO_CLKC_B_MARK,
1355
+
};
1356
+
1357
+
static const unsigned int audio_clk_c_c_pins[] = {
1358
+
/* CLK C_C */
1359
+
RCAR_GP_PIN(6, 14),
1360
+
};
1361
+
1362
+
static const unsigned int audio_clk_c_c_mux[] = {
1363
+
AUDIO_CLKC_C_MARK,
1364
+
};
1365
+
1366
+
static const unsigned int audio_clkout_a_pins[] = {
1367
+
/* CLKOUT_A */
1368
+
RCAR_GP_PIN(5, 3),
1369
+
};
1370
+
1371
+
static const unsigned int audio_clkout_a_mux[] = {
1372
+
AUDIO_CLKOUT_A_MARK,
1373
+
};
1374
+
1375
+
static const unsigned int audio_clkout_b_pins[] = {
1376
+
/* CLKOUT_B */
1377
+
RCAR_GP_PIN(5, 13),
1378
+
};
1379
+
1380
+
static const unsigned int audio_clkout_b_mux[] = {
1381
+
AUDIO_CLKOUT_B_MARK,
1382
+
};
1383
+
1384
+
static const unsigned int audio_clkout1_a_pins[] = {
1385
+
/* CLKOUT1_A */
1386
+
RCAR_GP_PIN(5, 4),
1387
+
};
1388
+
1389
+
static const unsigned int audio_clkout1_a_mux[] = {
1390
+
AUDIO_CLKOUT1_A_MARK,
1391
+
};
1392
+
1393
+
static const unsigned int audio_clkout1_b_pins[] = {
1394
+
/* CLKOUT1_B */
1395
+
RCAR_GP_PIN(5, 5),
1396
+
};
1397
+
1398
+
static const unsigned int audio_clkout1_b_mux[] = {
1399
+
AUDIO_CLKOUT1_B_MARK,
1400
+
};
1401
+
1402
+
static const unsigned int audio_clkout1_c_pins[] = {
1403
+
/* CLKOUT1_C */
1404
+
RCAR_GP_PIN(6, 7),
1405
+
};
1406
+
1407
+
static const unsigned int audio_clkout1_c_mux[] = {
1408
+
AUDIO_CLKOUT1_C_MARK,
1409
+
};
1410
+
1411
+
static const unsigned int audio_clkout2_a_pins[] = {
1412
+
/* CLKOUT2_A */
1413
+
RCAR_GP_PIN(5, 8),
1414
+
};
1415
+
1416
+
static const unsigned int audio_clkout2_a_mux[] = {
1417
+
AUDIO_CLKOUT2_A_MARK,
1418
+
};
1419
+
1420
+
static const unsigned int audio_clkout2_b_pins[] = {
1421
+
/* CLKOUT2_B */
1422
+
RCAR_GP_PIN(6, 4),
1423
+
};
1424
+
1425
+
static const unsigned int audio_clkout2_b_mux[] = {
1426
+
AUDIO_CLKOUT2_B_MARK,
1427
+
};
1428
+
1429
+
static const unsigned int audio_clkout2_c_pins[] = {
1430
+
/* CLKOUT2_C */
1431
+
RCAR_GP_PIN(6, 15),
1432
+
};
1433
+
1434
+
static const unsigned int audio_clkout2_c_mux[] = {
1435
+
AUDIO_CLKOUT2_C_MARK,
1436
+
};
1437
+
1438
+
static const unsigned int audio_clkout3_a_pins[] = {
1439
+
/* CLKOUT3_A */
1440
+
RCAR_GP_PIN(5, 9),
1441
+
};
1442
+
1443
+
static const unsigned int audio_clkout3_a_mux[] = {
1444
+
AUDIO_CLKOUT3_A_MARK,
1445
+
};
1446
+
1447
+
static const unsigned int audio_clkout3_b_pins[] = {
1448
+
/* CLKOUT3_B */
1449
+
RCAR_GP_PIN(5, 6),
1450
+
};
1451
+
1452
+
static const unsigned int audio_clkout3_b_mux[] = {
1453
+
AUDIO_CLKOUT3_B_MARK,
1454
+
};
1455
+
1456
+
static const unsigned int audio_clkout3_c_pins[] = {
1457
+
/* CLKOUT3_C */
1458
+
RCAR_GP_PIN(6, 16),
1459
+
};
1460
+
1461
+
static const unsigned int audio_clkout3_c_mux[] = {
1462
+
AUDIO_CLKOUT3_C_MARK,
1463
+
};
1464
+
1306
1465
/* - EtherAVB --------------------------------------------------------------- */
1307
1466
static const unsigned int avb_link_pins[] = {
1308
1467
/* AVB_LINK */
···
1536
1369
1537
1370
static const unsigned int avb_avtp_capture_a_mux[] = {
1538
1371
AVB_AVTP_CAPTURE_A_MARK,
1372
+
};
1373
+
1374
+
/* - CAN ------------------------------------------------------------------ */
1375
+
static const unsigned int can0_data_pins[] = {
1376
+
/* TX, RX */
1377
+
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1378
+
};
1379
+
1380
+
static const unsigned int can0_data_mux[] = {
1381
+
CAN0_TX_MARK, CAN0_RX_MARK,
1382
+
};
1383
+
1384
+
static const unsigned int can1_data_pins[] = {
1385
+
/* TX, RX */
1386
+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1387
+
};
1388
+
1389
+
static const unsigned int can1_data_mux[] = {
1390
+
CAN1_TX_MARK, CAN1_RX_MARK,
1391
+
};
1392
+
1393
+
/* - CAN Clock -------------------------------------------------------------- */
1394
+
static const unsigned int can_clk_pins[] = {
1395
+
/* CLK */
1396
+
RCAR_GP_PIN(0, 14),
1397
+
};
1398
+
1399
+
static const unsigned int can_clk_mux[] = {
1400
+
CAN_CLK_MARK,
1401
+
};
1402
+
1403
+
/* - CAN FD --------------------------------------------------------------- */
1404
+
static const unsigned int canfd0_data_pins[] = {
1405
+
/* TX, RX */
1406
+
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1407
+
};
1408
+
1409
+
static const unsigned int canfd0_data_mux[] = {
1410
+
CANFD0_TX_MARK, CANFD0_RX_MARK,
1411
+
};
1412
+
1413
+
static const unsigned int canfd1_data_pins[] = {
1414
+
/* TX, RX */
1415
+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1416
+
};
1417
+
1418
+
static const unsigned int canfd1_data_mux[] = {
1419
+
CANFD1_TX_MARK, CANFD1_RX_MARK,
1539
1420
};
1540
1421
1541
1422
/* - DU --------------------------------------------------------------------- */
···
1672
1457
};
1673
1458
static const unsigned int du_disp_mux[] = {
1674
1459
DU_DISP_MARK,
1460
+
};
1461
+
1462
+
/* - HSCIF0 --------------------------------------------------*/
1463
+
static const unsigned int hscif0_data_a_pins[] = {
1464
+
/* RX, TX */
1465
+
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1466
+
};
1467
+
1468
+
static const unsigned int hscif0_data_a_mux[] = {
1469
+
HRX0_A_MARK, HTX0_A_MARK,
1470
+
};
1471
+
1472
+
static const unsigned int hscif0_clk_a_pins[] = {
1473
+
/* SCK */
1474
+
RCAR_GP_PIN(5, 7),
1475
+
};
1476
+
1477
+
static const unsigned int hscif0_clk_a_mux[] = {
1478
+
HSCK0_A_MARK,
1479
+
};
1480
+
1481
+
static const unsigned int hscif0_ctrl_a_pins[] = {
1482
+
/* RTS, CTS */
1483
+
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1484
+
};
1485
+
1486
+
static const unsigned int hscif0_ctrl_a_mux[] = {
1487
+
HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1488
+
};
1489
+
1490
+
static const unsigned int hscif0_data_b_pins[] = {
1491
+
/* RX, TX */
1492
+
RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1493
+
};
1494
+
1495
+
static const unsigned int hscif0_data_b_mux[] = {
1496
+
HRX0_B_MARK, HTX0_B_MARK,
1497
+
};
1498
+
1499
+
static const unsigned int hscif0_clk_b_pins[] = {
1500
+
/* SCK */
1501
+
RCAR_GP_PIN(6, 13),
1502
+
};
1503
+
1504
+
static const unsigned int hscif0_clk_b_mux[] = {
1505
+
HSCK0_B_MARK,
1506
+
};
1507
+
1508
+
/* - HSCIF1 ------------------------------------------------- */
1509
+
static const unsigned int hscif1_data_a_pins[] = {
1510
+
/* RX, TX */
1511
+
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1512
+
};
1513
+
1514
+
static const unsigned int hscif1_data_a_mux[] = {
1515
+
HRX1_A_MARK, HTX1_A_MARK,
1516
+
};
1517
+
1518
+
static const unsigned int hscif1_clk_a_pins[] = {
1519
+
/* SCK */
1520
+
RCAR_GP_PIN(5, 0),
1521
+
};
1522
+
1523
+
static const unsigned int hscif1_clk_a_mux[] = {
1524
+
HSCK1_A_MARK,
1525
+
};
1526
+
1527
+
static const unsigned int hscif1_data_b_pins[] = {
1528
+
/* RX, TX */
1529
+
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1530
+
};
1531
+
1532
+
static const unsigned int hscif1_data_b_mux[] = {
1533
+
HRX1_B_MARK, HTX1_B_MARK,
1534
+
};
1535
+
1536
+
static const unsigned int hscif1_clk_b_pins[] = {
1537
+
/* SCK */
1538
+
RCAR_GP_PIN(3, 0),
1539
+
};
1540
+
1541
+
static const unsigned int hscif1_clk_b_mux[] = {
1542
+
HSCK1_B_MARK,
1543
+
};
1544
+
1545
+
static const unsigned int hscif1_ctrl_b_pins[] = {
1546
+
/* RTS, CTS */
1547
+
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
1548
+
};
1549
+
1550
+
static const unsigned int hscif1_ctrl_b_mux[] = {
1551
+
HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1552
+
};
1553
+
1554
+
/* - HSCIF2 ------------------------------------------------- */
1555
+
static const unsigned int hscif2_data_a_pins[] = {
1556
+
/* RX, TX */
1557
+
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1558
+
};
1559
+
1560
+
static const unsigned int hscif2_data_a_mux[] = {
1561
+
HRX2_A_MARK, HTX2_A_MARK,
1562
+
};
1563
+
1564
+
static const unsigned int hscif2_clk_a_pins[] = {
1565
+
/* SCK */
1566
+
RCAR_GP_PIN(6, 14),
1567
+
};
1568
+
1569
+
static const unsigned int hscif2_clk_a_mux[] = {
1570
+
HSCK2_A_MARK,
1571
+
};
1572
+
1573
+
static const unsigned int hscif2_ctrl_a_pins[] = {
1574
+
/* RTS, CTS */
1575
+
RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
1576
+
};
1577
+
1578
+
static const unsigned int hscif2_ctrl_a_mux[] = {
1579
+
HRTS2_N_A_MARK, HCTS2_N_A_MARK,
1580
+
};
1581
+
1582
+
static const unsigned int hscif2_data_b_pins[] = {
1583
+
/* RX, TX */
1584
+
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1585
+
};
1586
+
1587
+
static const unsigned int hscif2_data_b_mux[] = {
1588
+
HRX2_B_MARK, HTX2_B_MARK,
1589
+
};
1590
+
1591
+
/* - HSCIF3 ------------------------------------------------*/
1592
+
static const unsigned int hscif3_data_a_pins[] = {
1593
+
/* RX, TX */
1594
+
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1595
+
};
1596
+
1597
+
static const unsigned int hscif3_data_a_mux[] = {
1598
+
HRX3_A_MARK, HTX3_A_MARK,
1599
+
};
1600
+
1601
+
static const unsigned int hscif3_data_b_pins[] = {
1602
+
/* RX, TX */
1603
+
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1604
+
};
1605
+
1606
+
static const unsigned int hscif3_data_b_mux[] = {
1607
+
HRX3_B_MARK, HTX3_B_MARK,
1608
+
};
1609
+
1610
+
static const unsigned int hscif3_clk_b_pins[] = {
1611
+
/* SCK */
1612
+
RCAR_GP_PIN(0, 4),
1613
+
};
1614
+
1615
+
static const unsigned int hscif3_clk_b_mux[] = {
1616
+
HSCK3_B_MARK,
1617
+
};
1618
+
1619
+
static const unsigned int hscif3_data_c_pins[] = {
1620
+
/* RX, TX */
1621
+
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
1622
+
};
1623
+
1624
+
static const unsigned int hscif3_data_c_mux[] = {
1625
+
HRX3_C_MARK, HTX3_C_MARK,
1626
+
};
1627
+
1628
+
static const unsigned int hscif3_clk_c_pins[] = {
1629
+
/* SCK */
1630
+
RCAR_GP_PIN(2, 11),
1631
+
};
1632
+
1633
+
static const unsigned int hscif3_clk_c_mux[] = {
1634
+
HSCK3_C_MARK,
1635
+
};
1636
+
1637
+
static const unsigned int hscif3_ctrl_c_pins[] = {
1638
+
/* RTS, CTS */
1639
+
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
1640
+
};
1641
+
1642
+
static const unsigned int hscif3_ctrl_c_mux[] = {
1643
+
HRTS3_N_C_MARK, HCTS3_N_C_MARK,
1644
+
};
1645
+
1646
+
static const unsigned int hscif3_data_d_pins[] = {
1647
+
/* RX, TX */
1648
+
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),
1649
+
};
1650
+
1651
+
static const unsigned int hscif3_data_d_mux[] = {
1652
+
HRX3_D_MARK, HTX3_D_MARK,
1653
+
};
1654
+
1655
+
static const unsigned int hscif3_data_e_pins[] = {
1656
+
/* RX, TX */
1657
+
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1658
+
};
1659
+
1660
+
static const unsigned int hscif3_data_e_mux[] = {
1661
+
HRX3_E_MARK, HTX3_E_MARK,
1662
+
};
1663
+
1664
+
static const unsigned int hscif3_ctrl_e_pins[] = {
1665
+
/* RTS, CTS */
1666
+
RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
1667
+
};
1668
+
1669
+
static const unsigned int hscif3_ctrl_e_mux[] = {
1670
+
HRTS3_N_E_MARK, HCTS3_N_E_MARK,
1671
+
};
1672
+
1673
+
/* - HSCIF4 -------------------------------------------------- */
1674
+
static const unsigned int hscif4_data_a_pins[] = {
1675
+
/* RX, TX */
1676
+
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1677
+
};
1678
+
1679
+
static const unsigned int hscif4_data_a_mux[] = {
1680
+
HRX4_A_MARK, HTX4_A_MARK,
1681
+
};
1682
+
1683
+
static const unsigned int hscif4_clk_a_pins[] = {
1684
+
/* SCK */
1685
+
RCAR_GP_PIN(2, 0),
1686
+
};
1687
+
1688
+
static const unsigned int hscif4_clk_a_mux[] = {
1689
+
HSCK4_A_MARK,
1690
+
};
1691
+
1692
+
static const unsigned int hscif4_ctrl_a_pins[] = {
1693
+
/* RTS, CTS */
1694
+
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1695
+
};
1696
+
1697
+
static const unsigned int hscif4_ctrl_a_mux[] = {
1698
+
HRTS4_N_A_MARK, HCTS4_N_A_MARK,
1699
+
};
1700
+
1701
+
static const unsigned int hscif4_data_b_pins[] = {
1702
+
/* RX, TX */
1703
+
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
1704
+
};
1705
+
1706
+
static const unsigned int hscif4_data_b_mux[] = {
1707
+
HRX4_B_MARK, HTX4_B_MARK,
1708
+
};
1709
+
1710
+
static const unsigned int hscif4_clk_b_pins[] = {
1711
+
/* SCK */
1712
+
RCAR_GP_PIN(2, 6),
1713
+
};
1714
+
1715
+
static const unsigned int hscif4_clk_b_mux[] = {
1716
+
HSCK4_B_MARK,
1717
+
};
1718
+
1719
+
static const unsigned int hscif4_data_c_pins[] = {
1720
+
/* RX, TX */
1721
+
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1722
+
};
1723
+
1724
+
static const unsigned int hscif4_data_c_mux[] = {
1725
+
HRX4_C_MARK, HTX4_C_MARK,
1726
+
};
1727
+
1728
+
static const unsigned int hscif4_data_d_pins[] = {
1729
+
/* RX, TX */
1730
+
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
1731
+
};
1732
+
1733
+
static const unsigned int hscif4_data_d_mux[] = {
1734
+
HRX4_D_MARK, HTX4_D_MARK,
1735
+
};
1736
+
1737
+
static const unsigned int hscif4_data_e_pins[] = {
1738
+
/* RX, TX */
1739
+
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
1740
+
};
1741
+
1742
+
static const unsigned int hscif4_data_e_mux[] = {
1743
+
HRX4_E_MARK, HTX4_E_MARK,
1675
1744
};
1676
1745
1677
1746
/* - I2C -------------------------------------------------------------------- */
···
2885
2386
SCIF_CLK_B_MARK,
2886
2387
};
2887
2388
2389
+
/* - SDHI0 ------------------------------------------------------------------ */
2390
+
static const unsigned int sdhi0_data1_pins[] = {
2391
+
/* D0 */
2392
+
RCAR_GP_PIN(3, 2),
2393
+
};
2394
+
2395
+
static const unsigned int sdhi0_data1_mux[] = {
2396
+
SD0_DAT0_MARK,
2397
+
};
2398
+
2399
+
static const unsigned int sdhi0_data4_pins[] = {
2400
+
/* D[0:3] */
2401
+
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2402
+
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2403
+
};
2404
+
2405
+
static const unsigned int sdhi0_data4_mux[] = {
2406
+
SD0_DAT0_MARK, SD0_DAT1_MARK,
2407
+
SD0_DAT2_MARK, SD0_DAT3_MARK,
2408
+
};
2409
+
2410
+
static const unsigned int sdhi0_ctrl_pins[] = {
2411
+
/* CLK, CMD */
2412
+
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2413
+
};
2414
+
2415
+
static const unsigned int sdhi0_ctrl_mux[] = {
2416
+
SD0_CLK_MARK, SD0_CMD_MARK,
2417
+
};
2418
+
2419
+
static const unsigned int sdhi0_cd_pins[] = {
2420
+
/* CD */
2421
+
RCAR_GP_PIN(3, 12),
2422
+
};
2423
+
2424
+
static const unsigned int sdhi0_cd_mux[] = {
2425
+
SD0_CD_MARK,
2426
+
};
2427
+
2428
+
static const unsigned int sdhi0_wp_pins[] = {
2429
+
/* WP */
2430
+
RCAR_GP_PIN(3, 13),
2431
+
};
2432
+
2433
+
static const unsigned int sdhi0_wp_mux[] = {
2434
+
SD0_WP_MARK,
2435
+
};
2436
+
2437
+
/* - SDHI1 ------------------------------------------------------------------ */
2438
+
static const unsigned int sdhi1_data1_pins[] = {
2439
+
/* D0 */
2440
+
RCAR_GP_PIN(3, 8),
2441
+
};
2442
+
2443
+
static const unsigned int sdhi1_data1_mux[] = {
2444
+
SD1_DAT0_MARK,
2445
+
};
2446
+
2447
+
static const unsigned int sdhi1_data4_pins[] = {
2448
+
/* D[0:3] */
2449
+
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2450
+
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2451
+
};
2452
+
2453
+
static const unsigned int sdhi1_data4_mux[] = {
2454
+
SD1_DAT0_MARK, SD1_DAT1_MARK,
2455
+
SD1_DAT2_MARK, SD1_DAT3_MARK,
2456
+
};
2457
+
2458
+
static const unsigned int sdhi1_ctrl_pins[] = {
2459
+
/* CLK, CMD */
2460
+
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2461
+
};
2462
+
2463
+
static const unsigned int sdhi1_ctrl_mux[] = {
2464
+
SD1_CLK_MARK, SD1_CMD_MARK,
2465
+
};
2466
+
2467
+
static const unsigned int sdhi1_cd_pins[] = {
2468
+
/* CD */
2469
+
RCAR_GP_PIN(3, 14),
2470
+
};
2471
+
2472
+
static const unsigned int sdhi1_cd_mux[] = {
2473
+
SD1_CD_MARK,
2474
+
};
2475
+
2476
+
static const unsigned int sdhi1_wp_pins[] = {
2477
+
/* WP */
2478
+
RCAR_GP_PIN(3, 15),
2479
+
};
2480
+
2481
+
static const unsigned int sdhi1_wp_mux[] = {
2482
+
SD1_WP_MARK,
2483
+
};
2484
+
2485
+
/* - SDHI3 ------------------------------------------------------------------ */
2486
+
static const unsigned int sdhi3_data1_pins[] = {
2487
+
/* D0 */
2488
+
RCAR_GP_PIN(4, 2),
2489
+
};
2490
+
2491
+
static const unsigned int sdhi3_data1_mux[] = {
2492
+
SD3_DAT0_MARK,
2493
+
};
2494
+
2495
+
static const unsigned int sdhi3_data4_pins[] = {
2496
+
/* D[0:3] */
2497
+
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2498
+
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2499
+
};
2500
+
2501
+
static const unsigned int sdhi3_data4_mux[] = {
2502
+
SD3_DAT0_MARK, SD3_DAT1_MARK,
2503
+
SD3_DAT2_MARK, SD3_DAT3_MARK,
2504
+
};
2505
+
2506
+
static const unsigned int sdhi3_data8_pins[] = {
2507
+
/* D[0:7] */
2508
+
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2509
+
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2510
+
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2511
+
RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
2512
+
};
2513
+
2514
+
static const unsigned int sdhi3_data8_mux[] = {
2515
+
SD3_DAT0_MARK, SD3_DAT1_MARK,
2516
+
SD3_DAT2_MARK, SD3_DAT3_MARK,
2517
+
SD3_DAT4_MARK, SD3_DAT5_MARK,
2518
+
SD3_DAT6_MARK, SD3_DAT7_MARK,
2519
+
};
2520
+
2521
+
static const unsigned int sdhi3_ctrl_pins[] = {
2522
+
/* CLK, CMD */
2523
+
RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2524
+
};
2525
+
2526
+
static const unsigned int sdhi3_ctrl_mux[] = {
2527
+
SD3_CLK_MARK, SD3_CMD_MARK,
2528
+
};
2529
+
2530
+
static const unsigned int sdhi3_cd_pins[] = {
2531
+
/* CD */
2532
+
RCAR_GP_PIN(3, 12),
2533
+
};
2534
+
2535
+
static const unsigned int sdhi3_cd_mux[] = {
2536
+
SD3_CD_MARK,
2537
+
};
2538
+
2539
+
static const unsigned int sdhi3_wp_pins[] = {
2540
+
/* WP */
2541
+
RCAR_GP_PIN(3, 13),
2542
+
};
2543
+
2544
+
static const unsigned int sdhi3_wp_mux[] = {
2545
+
SD3_WP_MARK,
2546
+
};
2547
+
2548
+
static const unsigned int sdhi3_ds_pins[] = {
2549
+
/* DS */
2550
+
RCAR_GP_PIN(4, 10),
2551
+
};
2552
+
2553
+
static const unsigned int sdhi3_ds_mux[] = {
2554
+
SD3_DS_MARK,
2555
+
};
2556
+
2557
+
/* - SSI -------------------------------------------------------------------- */
2558
+
static const unsigned int ssi0_data_pins[] = {
2559
+
/* SDATA */
2560
+
RCAR_GP_PIN(6, 2),
2561
+
};
2562
+
2563
+
static const unsigned int ssi0_data_mux[] = {
2564
+
SSI_SDATA0_MARK,
2565
+
};
2566
+
2567
+
static const unsigned int ssi01239_ctrl_pins[] = {
2568
+
/* SCK, WS */
2569
+
RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
2570
+
};
2571
+
2572
+
static const unsigned int ssi01239_ctrl_mux[] = {
2573
+
SSI_SCK01239_MARK, SSI_WS01239_MARK,
2574
+
};
2575
+
2576
+
static const unsigned int ssi1_data_pins[] = {
2577
+
/* SDATA */
2578
+
RCAR_GP_PIN(6, 3),
2579
+
};
2580
+
2581
+
static const unsigned int ssi1_data_mux[] = {
2582
+
SSI_SDATA1_MARK,
2583
+
};
2584
+
2585
+
static const unsigned int ssi1_ctrl_pins[] = {
2586
+
/* SCK, WS */
2587
+
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2588
+
};
2589
+
2590
+
static const unsigned int ssi1_ctrl_mux[] = {
2591
+
SSI_SCK1_MARK, SSI_WS1_MARK,
2592
+
};
2593
+
2594
+
static const unsigned int ssi2_data_pins[] = {
2595
+
/* SDATA */
2596
+
RCAR_GP_PIN(6, 4),
2597
+
};
2598
+
2599
+
static const unsigned int ssi2_data_mux[] = {
2600
+
SSI_SDATA2_MARK,
2601
+
};
2602
+
2603
+
static const unsigned int ssi2_ctrl_a_pins[] = {
2604
+
/* SCK, WS */
2605
+
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2606
+
};
2607
+
2608
+
static const unsigned int ssi2_ctrl_a_mux[] = {
2609
+
SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
2610
+
};
2611
+
2612
+
static const unsigned int ssi2_ctrl_b_pins[] = {
2613
+
/* SCK, WS */
2614
+
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2615
+
};
2616
+
2617
+
static const unsigned int ssi2_ctrl_b_mux[] = {
2618
+
SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
2619
+
};
2620
+
2621
+
static const unsigned int ssi3_data_pins[] = {
2622
+
/* SDATA */
2623
+
RCAR_GP_PIN(6, 7),
2624
+
};
2625
+
2626
+
static const unsigned int ssi3_data_mux[] = {
2627
+
SSI_SDATA3_MARK,
2628
+
};
2629
+
2630
+
static const unsigned int ssi349_ctrl_pins[] = {
2631
+
/* SCK, WS */
2632
+
RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
2633
+
};
2634
+
2635
+
static const unsigned int ssi349_ctrl_mux[] = {
2636
+
SSI_SCK349_MARK, SSI_WS349_MARK,
2637
+
};
2638
+
2639
+
static const unsigned int ssi4_data_pins[] = {
2640
+
/* SDATA */
2641
+
RCAR_GP_PIN(6, 10),
2642
+
};
2643
+
2644
+
static const unsigned int ssi4_data_mux[] = {
2645
+
SSI_SDATA4_MARK,
2646
+
};
2647
+
2648
+
static const unsigned int ssi4_ctrl_pins[] = {
2649
+
/* SCK, WS */
2650
+
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
2651
+
};
2652
+
2653
+
static const unsigned int ssi4_ctrl_mux[] = {
2654
+
SSI_SCK4_MARK, SSI_WS4_MARK,
2655
+
};
2656
+
2657
+
static const unsigned int ssi5_data_pins[] = {
2658
+
/* SDATA */
2659
+
RCAR_GP_PIN(6, 13),
2660
+
};
2661
+
2662
+
static const unsigned int ssi5_data_mux[] = {
2663
+
SSI_SDATA5_MARK,
2664
+
};
2665
+
2666
+
static const unsigned int ssi5_ctrl_pins[] = {
2667
+
/* SCK, WS */
2668
+
RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
2669
+
};
2670
+
2671
+
static const unsigned int ssi5_ctrl_mux[] = {
2672
+
SSI_SCK5_MARK, SSI_WS5_MARK,
2673
+
};
2674
+
2675
+
static const unsigned int ssi6_data_pins[] = {
2676
+
/* SDATA */
2677
+
RCAR_GP_PIN(6, 16),
2678
+
};
2679
+
2680
+
static const unsigned int ssi6_data_mux[] = {
2681
+
SSI_SDATA6_MARK,
2682
+
};
2683
+
2684
+
static const unsigned int ssi6_ctrl_pins[] = {
2685
+
/* SCK, WS */
2686
+
RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2687
+
};
2688
+
2689
+
static const unsigned int ssi6_ctrl_mux[] = {
2690
+
SSI_SCK6_MARK, SSI_WS6_MARK,
2691
+
};
2692
+
2693
+
static const unsigned int ssi7_data_pins[] = {
2694
+
/* SDATA */
2695
+
RCAR_GP_PIN(5, 12),
2696
+
};
2697
+
2698
+
static const unsigned int ssi7_data_mux[] = {
2699
+
SSI_SDATA7_MARK,
2700
+
};
2701
+
2702
+
static const unsigned int ssi78_ctrl_pins[] = {
2703
+
/* SCK, WS */
2704
+
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
2705
+
};
2706
+
2707
+
static const unsigned int ssi78_ctrl_mux[] = {
2708
+
SSI_SCK78_MARK, SSI_WS78_MARK,
2709
+
};
2710
+
2711
+
static const unsigned int ssi8_data_pins[] = {
2712
+
/* SDATA */
2713
+
RCAR_GP_PIN(5, 13),
2714
+
};
2715
+
2716
+
static const unsigned int ssi8_data_mux[] = {
2717
+
SSI_SDATA8_MARK,
2718
+
};
2719
+
2720
+
static const unsigned int ssi9_data_pins[] = {
2721
+
/* SDATA */
2722
+
RCAR_GP_PIN(5, 16),
2723
+
};
2724
+
2725
+
static const unsigned int ssi9_data_mux[] = {
2726
+
SSI_SDATA9_MARK,
2727
+
};
2728
+
2729
+
static const unsigned int ssi9_ctrl_a_pins[] = {
2730
+
/* SCK, WS */
2731
+
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10),
2732
+
};
2733
+
2734
+
static const unsigned int ssi9_ctrl_a_mux[] = {
2735
+
SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
2736
+
};
2737
+
2738
+
static const unsigned int ssi9_ctrl_b_pins[] = {
2739
+
/* SCK, WS */
2740
+
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2741
+
};
2742
+
2743
+
static const unsigned int ssi9_ctrl_b_mux[] = {
2744
+
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
2745
+
};
2746
+
2888
2747
/* - USB0 ------------------------------------------------------------------- */
2889
2748
static const unsigned int usb0_a_pins[] = {
2890
2749
/* PWEN, OVC */
···
3290
2433
USB3HS0_ID_MARK,
3291
2434
};
3292
2435
2436
+
/* - VIN4 ------------------------------------------------------------------- */
2437
+
static const unsigned int vin4_data18_a_pins[] = {
2438
+
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2439
+
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
2440
+
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
2441
+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2442
+
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
2443
+
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2444
+
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
2445
+
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2446
+
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
2447
+
};
2448
+
2449
+
static const unsigned int vin4_data18_a_mux[] = {
2450
+
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
2451
+
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
2452
+
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
2453
+
VI4_DATA10_MARK, VI4_DATA11_MARK,
2454
+
VI4_DATA12_MARK, VI4_DATA13_MARK,
2455
+
VI4_DATA14_MARK, VI4_DATA15_MARK,
2456
+
VI4_DATA18_MARK, VI4_DATA19_MARK,
2457
+
VI4_DATA20_MARK, VI4_DATA21_MARK,
2458
+
VI4_DATA22_MARK, VI4_DATA23_MARK,
2459
+
};
2460
+
2461
+
static const union vin_data vin4_data_a_pins = {
2462
+
.data24 = {
2463
+
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2464
+
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2465
+
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
2466
+
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
2467
+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
2468
+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2469
+
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
2470
+
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2471
+
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
2472
+
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
2473
+
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2474
+
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
2475
+
},
2476
+
};
2477
+
2478
+
static const union vin_data vin4_data_a_mux = {
2479
+
.data24 = {
2480
+
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
2481
+
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
2482
+
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
2483
+
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
2484
+
VI4_DATA8_MARK, VI4_DATA9_MARK,
2485
+
VI4_DATA10_MARK, VI4_DATA11_MARK,
2486
+
VI4_DATA12_MARK, VI4_DATA13_MARK,
2487
+
VI4_DATA14_MARK, VI4_DATA15_MARK,
2488
+
VI4_DATA16_MARK, VI4_DATA17_MARK,
2489
+
VI4_DATA18_MARK, VI4_DATA19_MARK,
2490
+
VI4_DATA20_MARK, VI4_DATA21_MARK,
2491
+
VI4_DATA22_MARK, VI4_DATA23_MARK,
2492
+
},
2493
+
};
2494
+
2495
+
static const unsigned int vin4_data18_b_pins[] = {
2496
+
RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2497
+
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2498
+
RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
2499
+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2500
+
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
2501
+
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2502
+
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
2503
+
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2504
+
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
2505
+
};
2506
+
2507
+
static const unsigned int vin4_data18_b_mux[] = {
2508
+
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
2509
+
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
2510
+
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
2511
+
VI4_DATA10_MARK, VI4_DATA11_MARK,
2512
+
VI4_DATA12_MARK, VI4_DATA13_MARK,
2513
+
VI4_DATA14_MARK, VI4_DATA15_MARK,
2514
+
VI4_DATA18_MARK, VI4_DATA19_MARK,
2515
+
VI4_DATA20_MARK, VI4_DATA21_MARK,
2516
+
VI4_DATA22_MARK, VI4_DATA23_MARK,
2517
+
};
2518
+
2519
+
static const union vin_data vin4_data_b_pins = {
2520
+
.data24 = {
2521
+
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2522
+
RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2523
+
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2524
+
RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
2525
+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
2526
+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2527
+
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
2528
+
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2529
+
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
2530
+
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
2531
+
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2532
+
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
2533
+
},
2534
+
};
2535
+
2536
+
static const union vin_data vin4_data_b_mux = {
2537
+
.data24 = {
2538
+
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
2539
+
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
2540
+
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
2541
+
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
2542
+
VI4_DATA8_MARK, VI4_DATA9_MARK,
2543
+
VI4_DATA10_MARK, VI4_DATA11_MARK,
2544
+
VI4_DATA12_MARK, VI4_DATA13_MARK,
2545
+
VI4_DATA14_MARK, VI4_DATA15_MARK,
2546
+
VI4_DATA16_MARK, VI4_DATA17_MARK,
2547
+
VI4_DATA18_MARK, VI4_DATA19_MARK,
2548
+
VI4_DATA20_MARK, VI4_DATA21_MARK,
2549
+
VI4_DATA22_MARK, VI4_DATA23_MARK,
2550
+
},
2551
+
};
2552
+
2553
+
static const unsigned int vin4_sync_pins[] = {
2554
+
/* HSYNC, VSYNC */
2555
+
RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
2556
+
};
2557
+
2558
+
static const unsigned int vin4_sync_mux[] = {
2559
+
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
2560
+
};
2561
+
2562
+
static const unsigned int vin4_field_pins[] = {
2563
+
RCAR_GP_PIN(2, 23),
2564
+
};
2565
+
2566
+
static const unsigned int vin4_field_mux[] = {
2567
+
VI4_FIELD_MARK,
2568
+
};
2569
+
2570
+
static const unsigned int vin4_clkenb_pins[] = {
2571
+
RCAR_GP_PIN(1, 2),
2572
+
};
2573
+
2574
+
static const unsigned int vin4_clkenb_mux[] = {
2575
+
VI4_CLKENB_MARK,
2576
+
};
2577
+
2578
+
static const unsigned int vin4_clk_pins[] = {
2579
+
RCAR_GP_PIN(2, 22),
2580
+
};
2581
+
2582
+
static const unsigned int vin4_clk_mux[] = {
2583
+
VI4_CLK_MARK,
2584
+
};
2585
+
2586
+
/* - VIN5 ------------------------------------------------------------------- */
2587
+
static const union vin_data16 vin5_data_a_pins = {
2588
+
.data16 = {
2589
+
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2590
+
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
2591
+
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
2592
+
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2593
+
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
2594
+
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
2595
+
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
2596
+
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
2597
+
},
2598
+
};
2599
+
2600
+
static const union vin_data16 vin5_data_a_mux = {
2601
+
.data16 = {
2602
+
VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
2603
+
VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
2604
+
VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
2605
+
VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
2606
+
VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
2607
+
VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
2608
+
VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
2609
+
VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
2610
+
},
2611
+
};
2612
+
2613
+
static const unsigned int vin5_data8_b_pins[] = {
2614
+
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4),
2615
+
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12),
2616
+
RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
2617
+
RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
2618
+
};
2619
+
2620
+
static const unsigned int vin5_data8_b_mux[] = {
2621
+
VI5_DATA0_B_MARK, VI5_DATA1_B_MARK,
2622
+
VI5_DATA2_B_MARK, VI5_DATA3_B_MARK,
2623
+
VI5_DATA4_B_MARK, VI5_DATA5_B_MARK,
2624
+
VI5_DATA6_B_MARK, VI5_DATA7_B_MARK,
2625
+
};
2626
+
2627
+
static const unsigned int vin5_sync_a_pins[] = {
2628
+
/* HSYNC_N, VSYNC_N */
2629
+
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
2630
+
};
2631
+
2632
+
static const unsigned int vin5_sync_a_mux[] = {
2633
+
VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK,
2634
+
};
2635
+
2636
+
static const unsigned int vin5_field_a_pins[] = {
2637
+
RCAR_GP_PIN(1, 10),
2638
+
};
2639
+
2640
+
static const unsigned int vin5_field_a_mux[] = {
2641
+
VI5_FIELD_A_MARK,
2642
+
};
2643
+
2644
+
static const unsigned int vin5_clkenb_a_pins[] = {
2645
+
RCAR_GP_PIN(0, 1),
2646
+
};
2647
+
2648
+
static const unsigned int vin5_clkenb_a_mux[] = {
2649
+
VI5_CLKENB_A_MARK,
2650
+
};
2651
+
2652
+
static const unsigned int vin5_clk_a_pins[] = {
2653
+
RCAR_GP_PIN(1, 0),
2654
+
};
2655
+
2656
+
static const unsigned int vin5_clk_a_mux[] = {
2657
+
VI5_CLK_A_MARK,
2658
+
};
2659
+
2660
+
static const unsigned int vin5_clk_b_pins[] = {
2661
+
RCAR_GP_PIN(2, 22),
2662
+
};
2663
+
2664
+
static const unsigned int vin5_clk_b_mux[] = {
2665
+
VI5_CLK_B_MARK,
2666
+
};
2667
+
3293
2668
static const struct {
3294
-
struct sh_pfc_pin_group common[123];
3295
-
struct sh_pfc_pin_group automotive[0];
2669
+
struct sh_pfc_pin_group common[241];
2670
+
struct sh_pfc_pin_group automotive[2];
3296
2671
} pinmux_groups = {
3297
2672
.common = {
2673
+
SH_PFC_PIN_GROUP(audio_clk_a),
2674
+
SH_PFC_PIN_GROUP(audio_clk_b_a),
2675
+
SH_PFC_PIN_GROUP(audio_clk_b_b),
2676
+
SH_PFC_PIN_GROUP(audio_clk_b_c),
2677
+
SH_PFC_PIN_GROUP(audio_clk_c_a),
2678
+
SH_PFC_PIN_GROUP(audio_clk_c_b),
2679
+
SH_PFC_PIN_GROUP(audio_clk_c_c),
2680
+
SH_PFC_PIN_GROUP(audio_clkout_a),
2681
+
SH_PFC_PIN_GROUP(audio_clkout_b),
2682
+
SH_PFC_PIN_GROUP(audio_clkout1_a),
2683
+
SH_PFC_PIN_GROUP(audio_clkout1_b),
2684
+
SH_PFC_PIN_GROUP(audio_clkout1_c),
2685
+
SH_PFC_PIN_GROUP(audio_clkout2_a),
2686
+
SH_PFC_PIN_GROUP(audio_clkout2_b),
2687
+
SH_PFC_PIN_GROUP(audio_clkout2_c),
2688
+
SH_PFC_PIN_GROUP(audio_clkout3_a),
2689
+
SH_PFC_PIN_GROUP(audio_clkout3_b),
2690
+
SH_PFC_PIN_GROUP(audio_clkout3_c),
3298
2691
SH_PFC_PIN_GROUP(avb_link),
3299
2692
SH_PFC_PIN_GROUP(avb_magic),
3300
2693
SH_PFC_PIN_GROUP(avb_phy_int),
···
3552
2445
SH_PFC_PIN_GROUP(avb_avtp_pps),
3553
2446
SH_PFC_PIN_GROUP(avb_avtp_match_a),
3554
2447
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
2448
+
SH_PFC_PIN_GROUP(can0_data),
2449
+
SH_PFC_PIN_GROUP(can1_data),
2450
+
SH_PFC_PIN_GROUP(can_clk),
3555
2451
SH_PFC_PIN_GROUP(du_rgb666),
3556
2452
SH_PFC_PIN_GROUP(du_rgb888),
3557
2453
SH_PFC_PIN_GROUP(du_clk_in_0),
···
3564
2454
SH_PFC_PIN_GROUP(du_disp_cde),
3565
2455
SH_PFC_PIN_GROUP(du_cde),
3566
2456
SH_PFC_PIN_GROUP(du_disp),
2457
+
SH_PFC_PIN_GROUP(hscif0_data_a),
2458
+
SH_PFC_PIN_GROUP(hscif0_clk_a),
2459
+
SH_PFC_PIN_GROUP(hscif0_ctrl_a),
2460
+
SH_PFC_PIN_GROUP(hscif0_data_b),
2461
+
SH_PFC_PIN_GROUP(hscif0_clk_b),
2462
+
SH_PFC_PIN_GROUP(hscif1_data_a),
2463
+
SH_PFC_PIN_GROUP(hscif1_clk_a),
2464
+
SH_PFC_PIN_GROUP(hscif1_data_b),
2465
+
SH_PFC_PIN_GROUP(hscif1_clk_b),
2466
+
SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2467
+
SH_PFC_PIN_GROUP(hscif2_data_a),
2468
+
SH_PFC_PIN_GROUP(hscif2_clk_a),
2469
+
SH_PFC_PIN_GROUP(hscif2_ctrl_a),
2470
+
SH_PFC_PIN_GROUP(hscif2_data_b),
2471
+
SH_PFC_PIN_GROUP(hscif3_data_a),
2472
+
SH_PFC_PIN_GROUP(hscif3_data_b),
2473
+
SH_PFC_PIN_GROUP(hscif3_clk_b),
2474
+
SH_PFC_PIN_GROUP(hscif3_data_c),
2475
+
SH_PFC_PIN_GROUP(hscif3_clk_c),
2476
+
SH_PFC_PIN_GROUP(hscif3_ctrl_c),
2477
+
SH_PFC_PIN_GROUP(hscif3_data_d),
2478
+
SH_PFC_PIN_GROUP(hscif3_data_e),
2479
+
SH_PFC_PIN_GROUP(hscif3_ctrl_e),
2480
+
SH_PFC_PIN_GROUP(hscif4_data_a),
2481
+
SH_PFC_PIN_GROUP(hscif4_clk_a),
2482
+
SH_PFC_PIN_GROUP(hscif4_ctrl_a),
2483
+
SH_PFC_PIN_GROUP(hscif4_data_b),
2484
+
SH_PFC_PIN_GROUP(hscif4_clk_b),
2485
+
SH_PFC_PIN_GROUP(hscif4_data_c),
2486
+
SH_PFC_PIN_GROUP(hscif4_data_d),
2487
+
SH_PFC_PIN_GROUP(hscif4_data_e),
3567
2488
SH_PFC_PIN_GROUP(i2c1_a),
3568
2489
SH_PFC_PIN_GROUP(i2c1_b),
3569
2490
SH_PFC_PIN_GROUP(i2c1_c),
···
3697
2556
SH_PFC_PIN_GROUP(scif5_data_c),
3698
2557
SH_PFC_PIN_GROUP(scif_clk_a),
3699
2558
SH_PFC_PIN_GROUP(scif_clk_b),
2559
+
SH_PFC_PIN_GROUP(sdhi0_data1),
2560
+
SH_PFC_PIN_GROUP(sdhi0_data4),
2561
+
SH_PFC_PIN_GROUP(sdhi0_ctrl),
2562
+
SH_PFC_PIN_GROUP(sdhi0_cd),
2563
+
SH_PFC_PIN_GROUP(sdhi0_wp),
2564
+
SH_PFC_PIN_GROUP(sdhi1_data1),
2565
+
SH_PFC_PIN_GROUP(sdhi1_data4),
2566
+
SH_PFC_PIN_GROUP(sdhi1_ctrl),
2567
+
SH_PFC_PIN_GROUP(sdhi1_cd),
2568
+
SH_PFC_PIN_GROUP(sdhi1_wp),
2569
+
SH_PFC_PIN_GROUP(sdhi3_data1),
2570
+
SH_PFC_PIN_GROUP(sdhi3_data4),
2571
+
SH_PFC_PIN_GROUP(sdhi3_data8),
2572
+
SH_PFC_PIN_GROUP(sdhi3_ctrl),
2573
+
SH_PFC_PIN_GROUP(sdhi3_cd),
2574
+
SH_PFC_PIN_GROUP(sdhi3_wp),
2575
+
SH_PFC_PIN_GROUP(sdhi3_ds),
2576
+
SH_PFC_PIN_GROUP(ssi0_data),
2577
+
SH_PFC_PIN_GROUP(ssi01239_ctrl),
2578
+
SH_PFC_PIN_GROUP(ssi1_data),
2579
+
SH_PFC_PIN_GROUP(ssi1_ctrl),
2580
+
SH_PFC_PIN_GROUP(ssi2_data),
2581
+
SH_PFC_PIN_GROUP(ssi2_ctrl_a),
2582
+
SH_PFC_PIN_GROUP(ssi2_ctrl_b),
2583
+
SH_PFC_PIN_GROUP(ssi3_data),
2584
+
SH_PFC_PIN_GROUP(ssi349_ctrl),
2585
+
SH_PFC_PIN_GROUP(ssi4_data),
2586
+
SH_PFC_PIN_GROUP(ssi4_ctrl),
2587
+
SH_PFC_PIN_GROUP(ssi5_data),
2588
+
SH_PFC_PIN_GROUP(ssi5_ctrl),
2589
+
SH_PFC_PIN_GROUP(ssi6_data),
2590
+
SH_PFC_PIN_GROUP(ssi6_ctrl),
2591
+
SH_PFC_PIN_GROUP(ssi7_data),
2592
+
SH_PFC_PIN_GROUP(ssi78_ctrl),
2593
+
SH_PFC_PIN_GROUP(ssi8_data),
2594
+
SH_PFC_PIN_GROUP(ssi9_data),
2595
+
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
2596
+
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3700
2597
SH_PFC_PIN_GROUP(usb0_a),
3701
2598
SH_PFC_PIN_GROUP(usb0_b),
3702
2599
SH_PFC_PIN_GROUP(usb0_id),
3703
2600
SH_PFC_PIN_GROUP(usb30),
3704
2601
SH_PFC_PIN_GROUP(usb30_id),
2602
+
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
2603
+
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
2604
+
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
2605
+
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
2606
+
SH_PFC_PIN_GROUP(vin4_data18_a),
2607
+
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
2608
+
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
2609
+
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
2610
+
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
2611
+
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
2612
+
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
2613
+
SH_PFC_PIN_GROUP(vin4_data18_b),
2614
+
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
2615
+
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
2616
+
SH_PFC_PIN_GROUP(vin4_sync),
2617
+
SH_PFC_PIN_GROUP(vin4_field),
2618
+
SH_PFC_PIN_GROUP(vin4_clkenb),
2619
+
SH_PFC_PIN_GROUP(vin4_clk),
2620
+
VIN_DATA_PIN_GROUP(vin5_data, 8, _a),
2621
+
VIN_DATA_PIN_GROUP(vin5_data, 10, _a),
2622
+
VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
2623
+
VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
2624
+
SH_PFC_PIN_GROUP(vin5_data8_b),
2625
+
SH_PFC_PIN_GROUP(vin5_sync_a),
2626
+
SH_PFC_PIN_GROUP(vin5_field_a),
2627
+
SH_PFC_PIN_GROUP(vin5_clkenb_a),
2628
+
SH_PFC_PIN_GROUP(vin5_clk_a),
2629
+
SH_PFC_PIN_GROUP(vin5_clk_b),
2630
+
},
2631
+
.automotive = {
2632
+
SH_PFC_PIN_GROUP(canfd0_data),
2633
+
SH_PFC_PIN_GROUP(canfd1_data),
3705
2634
}
2635
+
};
2636
+
2637
+
static const char * const audio_clk_groups[] = {
2638
+
"audio_clk_a",
2639
+
"audio_clk_b_a",
2640
+
"audio_clk_b_b",
2641
+
"audio_clk_b_c",
2642
+
"audio_clk_c_a",
2643
+
"audio_clk_c_b",
2644
+
"audio_clk_c_c",
2645
+
"audio_clkout_a",
2646
+
"audio_clkout_b",
2647
+
"audio_clkout1_a",
2648
+
"audio_clkout1_b",
2649
+
"audio_clkout1_c",
2650
+
"audio_clkout2_a",
2651
+
"audio_clkout2_b",
2652
+
"audio_clkout2_c",
2653
+
"audio_clkout3_a",
2654
+
"audio_clkout3_b",
2655
+
"audio_clkout3_c",
3706
2656
};
3707
2657
3708
2658
static const char * const avb_groups[] = {
···
3806
2574
"avb_avtp_capture_a",
3807
2575
};
3808
2576
2577
+
static const char * const can0_groups[] = {
2578
+
"can0_data",
2579
+
};
2580
+
2581
+
static const char * const can1_groups[] = {
2582
+
"can1_data",
2583
+
};
2584
+
2585
+
static const char * const can_clk_groups[] = {
2586
+
"can_clk",
2587
+
};
2588
+
2589
+
static const char * const canfd0_groups[] = {
2590
+
"canfd0_data",
2591
+
};
2592
+
2593
+
static const char * const canfd1_groups[] = {
2594
+
"canfd1_data",
2595
+
};
2596
+
3809
2597
static const char * const du_groups[] = {
3810
2598
"du_rgb666",
3811
2599
"du_rgb888",
···
3836
2584
"du_disp_cde",
3837
2585
"du_cde",
3838
2586
"du_disp",
2587
+
};
2588
+
2589
+
static const char * const hscif0_groups[] = {
2590
+
"hscif0_data_a",
2591
+
"hscif0_clk_a",
2592
+
"hscif0_ctrl_a",
2593
+
"hscif0_data_b",
2594
+
"hscif0_clk_b",
2595
+
};
2596
+
2597
+
static const char * const hscif1_groups[] = {
2598
+
"hscif1_data_a",
2599
+
"hscif1_clk_a",
2600
+
"hscif1_data_b",
2601
+
"hscif1_clk_b",
2602
+
"hscif1_ctrl_b",
2603
+
};
2604
+
2605
+
static const char * const hscif2_groups[] = {
2606
+
"hscif2_data_a",
2607
+
"hscif2_clk_a",
2608
+
"hscif2_ctrl_a",
2609
+
"hscif2_data_b",
2610
+
};
2611
+
2612
+
static const char * const hscif3_groups[] = {
2613
+
"hscif3_data_a",
2614
+
"hscif3_data_b",
2615
+
"hscif3_clk_b",
2616
+
"hscif3_data_c",
2617
+
"hscif3_clk_c",
2618
+
"hscif3_ctrl_c",
2619
+
"hscif3_data_d",
2620
+
"hscif3_data_e",
2621
+
"hscif3_ctrl_e",
2622
+
};
2623
+
2624
+
static const char * const hscif4_groups[] = {
2625
+
"hscif4_data_a",
2626
+
"hscif4_clk_a",
2627
+
"hscif4_ctrl_a",
2628
+
"hscif4_data_b",
2629
+
"hscif4_clk_b",
2630
+
"hscif4_data_c",
2631
+
"hscif4_data_d",
2632
+
"hscif4_data_e",
3839
2633
};
3840
2634
3841
2635
static const char * const i2c1_groups[] = {
···
4061
2763
"scif_clk_b",
4062
2764
};
4063
2765
2766
+
static const char * const sdhi0_groups[] = {
2767
+
"sdhi0_data1",
2768
+
"sdhi0_data4",
2769
+
"sdhi0_ctrl",
2770
+
"sdhi0_cd",
2771
+
"sdhi0_wp",
2772
+
};
2773
+
2774
+
static const char * const sdhi1_groups[] = {
2775
+
"sdhi1_data1",
2776
+
"sdhi1_data4",
2777
+
"sdhi1_ctrl",
2778
+
"sdhi1_cd",
2779
+
"sdhi1_wp",
2780
+
};
2781
+
2782
+
static const char * const sdhi3_groups[] = {
2783
+
"sdhi3_data1",
2784
+
"sdhi3_data4",
2785
+
"sdhi3_data8",
2786
+
"sdhi3_ctrl",
2787
+
"sdhi3_cd",
2788
+
"sdhi3_wp",
2789
+
"sdhi3_ds",
2790
+
};
2791
+
2792
+
static const char * const ssi_groups[] = {
2793
+
"ssi0_data",
2794
+
"ssi01239_ctrl",
2795
+
"ssi1_data",
2796
+
"ssi1_ctrl",
2797
+
"ssi2_data",
2798
+
"ssi2_ctrl_a",
2799
+
"ssi2_ctrl_b",
2800
+
"ssi3_data",
2801
+
"ssi349_ctrl",
2802
+
"ssi4_data",
2803
+
"ssi4_ctrl",
2804
+
"ssi5_data",
2805
+
"ssi5_ctrl",
2806
+
"ssi6_data",
2807
+
"ssi6_ctrl",
2808
+
"ssi7_data",
2809
+
"ssi78_ctrl",
2810
+
"ssi8_data",
2811
+
"ssi9_data",
2812
+
"ssi9_ctrl_a",
2813
+
"ssi9_ctrl_b",
2814
+
};
2815
+
4064
2816
static const char * const usb0_groups[] = {
4065
2817
"usb0_a",
4066
2818
"usb0_b",
···
4122
2774
"usb30_id",
4123
2775
};
4124
2776
2777
+
static const char * const vin4_groups[] = {
2778
+
"vin4_data8_a",
2779
+
"vin4_data10_a",
2780
+
"vin4_data12_a",
2781
+
"vin4_data16_a",
2782
+
"vin4_data18_a",
2783
+
"vin4_data20_a",
2784
+
"vin4_data24_a",
2785
+
"vin4_data8_b",
2786
+
"vin4_data10_b",
2787
+
"vin4_data12_b",
2788
+
"vin4_data16_b",
2789
+
"vin4_data18_b",
2790
+
"vin4_data20_b",
2791
+
"vin4_data24_b",
2792
+
"vin4_sync",
2793
+
"vin4_field",
2794
+
"vin4_clkenb",
2795
+
"vin4_clk",
2796
+
};
2797
+
2798
+
static const char * const vin5_groups[] = {
2799
+
"vin5_data8_a",
2800
+
"vin5_data10_a",
2801
+
"vin5_data12_a",
2802
+
"vin5_data16_a",
2803
+
"vin5_data8_b",
2804
+
"vin5_sync_a",
2805
+
"vin5_field_a",
2806
+
"vin5_clkenb_a",
2807
+
"vin5_clk_a",
2808
+
"vin5_clk_b",
2809
+
};
2810
+
4125
2811
static const struct {
4126
-
struct sh_pfc_function common[29];
4127
-
struct sh_pfc_function automotive[0];
2812
+
struct sh_pfc_function common[44];
2813
+
struct sh_pfc_function automotive[2];
4128
2814
} pinmux_functions = {
4129
2815
.common = {
2816
+
SH_PFC_FUNCTION(audio_clk),
4130
2817
SH_PFC_FUNCTION(avb),
2818
+
SH_PFC_FUNCTION(can0),
2819
+
SH_PFC_FUNCTION(can1),
2820
+
SH_PFC_FUNCTION(can_clk),
4131
2821
SH_PFC_FUNCTION(du),
2822
+
SH_PFC_FUNCTION(hscif0),
2823
+
SH_PFC_FUNCTION(hscif1),
2824
+
SH_PFC_FUNCTION(hscif2),
2825
+
SH_PFC_FUNCTION(hscif3),
2826
+
SH_PFC_FUNCTION(hscif4),
4132
2827
SH_PFC_FUNCTION(i2c1),
4133
2828
SH_PFC_FUNCTION(i2c2),
4134
2829
SH_PFC_FUNCTION(i2c4),
···
4197
2806
SH_PFC_FUNCTION(scif4),
4198
2807
SH_PFC_FUNCTION(scif5),
4199
2808
SH_PFC_FUNCTION(scif_clk),
2809
+
SH_PFC_FUNCTION(sdhi0),
2810
+
SH_PFC_FUNCTION(sdhi1),
2811
+
SH_PFC_FUNCTION(sdhi3),
2812
+
SH_PFC_FUNCTION(ssi),
4200
2813
SH_PFC_FUNCTION(usb0),
4201
2814
SH_PFC_FUNCTION(usb30),
2815
+
SH_PFC_FUNCTION(vin4),
2816
+
SH_PFC_FUNCTION(vin5),
2817
+
},
2818
+
.automotive = {
2819
+
SH_PFC_FUNCTION(canfd0),
2820
+
SH_PFC_FUNCTION(canfd1),
4202
2821
}
4203
2822
};
4204
2823
···
4681
3280
{ },
4682
3281
};
4683
3282
3283
+
enum ioctrl_regs {
3284
+
IOCTRL30,
3285
+
};
3286
+
3287
+
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
3288
+
[IOCTRL30] = { 0xe6060380, },
3289
+
{ /* sentinel */ },
3290
+
};
3291
+
3292
+
static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
3293
+
u32 *pocctrl)
3294
+
{
3295
+
int bit = -EINVAL;
3296
+
3297
+
*pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
3298
+
3299
+
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
3300
+
bit = pin & 0x1f;
3301
+
3302
+
if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
3303
+
bit = (pin & 0x1f) + 19;
3304
+
3305
+
return bit;
3306
+
}
3307
+
4684
3308
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
4685
3309
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
4686
3310
[0] = RCAR_GP_PIN(2, 23), /* RD# */
···
4956
3530
}
4957
3531
4958
3532
static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
3533
+
.pin_to_pocctrl = r8a77990_pin_to_pocctrl,
4959
3534
.get_bias = r8a77990_pinmux_get_bias,
4960
3535
.set_bias = r8a77990_pinmux_set_bias,
4961
3536
};
···
4978
3551
4979
3552
.cfg_regs = pinmux_config_regs,
4980
3553
.bias_regs = pinmux_bias_regs,
3554
+
.ioctrl_regs = pinmux_ioctrl_regs,
4981
3555
4982
3556
.pinmux_data = pinmux_data,
4983
3557
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-6
drivers/pinctrl/sh-pfc/pfc-r8a77995.c
-6
drivers/pinctrl/sh-pfc/pfc-r8a77995.c
···
468
468
#undef FM
469
469
};
470
470
471
-
#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
472
-
PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
473
-
474
-
#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
475
-
PINMUX_DATA(fn##_MARK, FN_##msel)
476
-
477
471
static const u16 pinmux_data[] = {
478
472
PINMUX_DATA_GP_ALL(),
479
473
+45
-9
drivers/pinctrl/sh-pfc/sh_pfc.h
+45
-9
drivers/pinctrl/sh-pfc/sh_pfc.h
···
53
53
};
54
54
55
55
/*
56
-
* Using union vin_data saves memory occupied by the VIN data pins.
57
-
* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
58
-
* in this case.
56
+
* Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
57
+
* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
58
+
* in this case. It accepts an optional 'version' argument used when the
59
+
* same group can appear on a different set of pins.
59
60
*/
60
-
#define VIN_DATA_PIN_GROUP(n, s) \
61
-
{ \
62
-
.name = #n#s, \
63
-
.pins = n##_pins.data##s, \
64
-
.mux = n##_mux.data##s, \
65
-
.nr_pins = ARRAY_SIZE(n##_pins.data##s), \
61
+
#define VIN_DATA_PIN_GROUP(n, s, ...) \
62
+
{ \
63
+
.name = #n#s#__VA_ARGS__, \
64
+
.pins = n##__VA_ARGS__##_pins.data##s, \
65
+
.mux = n##__VA_ARGS__##_mux.data##s, \
66
+
.nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
66
67
}
68
+
69
+
union vin_data12 {
70
+
unsigned int data12[12];
71
+
unsigned int data10[10];
72
+
unsigned int data8[8];
73
+
};
74
+
75
+
union vin_data16 {
76
+
unsigned int data16[16];
77
+
unsigned int data12[12];
78
+
unsigned int data10[10];
79
+
unsigned int data8[8];
80
+
};
67
81
68
82
union vin_data {
69
83
unsigned int data24[24];
···
385
371
*/
386
372
#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
387
373
PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
374
+
375
+
/*
376
+
* Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
377
+
* an additional select register that controls physical multiplexing
378
+
* with another pin.
379
+
* - ipsr: IPSR field
380
+
* - fn: Function name, also referring to the IPSR field
381
+
* - psel: Physical multiplexing selector
382
+
* - msel: Module selector
383
+
*/
384
+
#define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
385
+
PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
386
+
387
+
/*
388
+
* Describe a pinmux configuration in which a pin is physically multiplexed
389
+
* with other pins.
390
+
* - ipsr: IPSR field
391
+
* - fn: Function name, also referring to the IPSR field
392
+
* - psel: Physical multiplexing selector
393
+
*/
394
+
#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
395
+
PINMUX_DATA(fn##_MARK, FN_##psel)
388
396
389
397
/*
390
398
* Describe a pinmux configuration for a single-function pin with GPIO
+47
include/dt-bindings/pinctrl/r7s9210-pinctrl.h
+47
include/dt-bindings/pinctrl/r7s9210-pinctrl.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Defines macros and constants for Renesas RZ/A2 pin controller pin
4
+
* muxing functions.
5
+
*/
6
+
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H
7
+
#define __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H
8
+
9
+
#define RZA2_PINS_PER_PORT 8
10
+
11
+
/* Port names as labeled in the Hardware Manual */
12
+
#define PORT0 0
13
+
#define PORT1 1
14
+
#define PORT2 2
15
+
#define PORT3 3
16
+
#define PORT4 4
17
+
#define PORT5 5
18
+
#define PORT6 6
19
+
#define PORT7 7
20
+
#define PORT8 8
21
+
#define PORT9 9
22
+
#define PORTA 10
23
+
#define PORTB 11
24
+
#define PORTC 12
25
+
#define PORTD 13
26
+
#define PORTE 14
27
+
#define PORTF 15
28
+
#define PORTG 16
29
+
#define PORTH 17
30
+
/* No I */
31
+
#define PORTJ 18
32
+
#define PORTK 19
33
+
#define PORTL 20
34
+
#define PORTM 21 /* Pins PM_0/1 are labeled JP_0/1 in HW manual */
35
+
36
+
/*
37
+
* Create the pin index from its bank and position numbers and store in
38
+
* the upper 16 bits the alternate function identifier
39
+
*/
40
+
#define RZA2_PINMUX(b, p, f) ((b) * RZA2_PINS_PER_PORT + (p) | (f << 16))
41
+
42
+
/*
43
+
* Convert a port and pin label to its global pin index
44
+
*/
45
+
#define RZA2_PIN(port, pin) ((port) * RZA2_PINS_PER_PORT + (pin))
46
+
47
+
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H */