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kernel
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linux
dt-bindings: clock: Introduce QCOM Video clock bindings
Add device tree bindings for video clock controller for
Qualcomm Technology Inc's SoCs.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Amit Nischal
and committed by
Stephen Boyd
84b66b21
06391edd
+54
+19
Documentation/devicetree/bindings/clock/qcom,videocc.txt
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Documentation/devicetree/bindings/clock/qcom,videocc.txt
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Qualcomm Video Clock & Reset Controller Binding
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-----------------------------------------------
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Required properties :
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- compatible : shall contain "qcom,sdm845-videocc"
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- reg : shall contain base register location and length
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- #clock-cells : from common clock binding, shall contain 1.
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- #power-domain-cells : from generic power domain binding, shall contain 1.
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Optional properties :
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- #reset-cells : from common reset binding, shall contain 1.
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Example:
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videocc: clock-controller@ab00000 {
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compatible = "qcom,sdm845-videocc";
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reg = <0xab00000 0x10000>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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};
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include/dt-bindings/clock/qcom,videocc-sdm845.h
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include/dt-bindings/clock/qcom,videocc-sdm845.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
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#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
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/* VIDEO_CC clock registers */
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#define VIDEO_CC_APB_CLK 0
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#define VIDEO_CC_AT_CLK 1
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#define VIDEO_CC_QDSS_TRIG_CLK 2
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#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3
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#define VIDEO_CC_VCODEC0_AXI_CLK 4
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#define VIDEO_CC_VCODEC0_CORE_CLK 5
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#define VIDEO_CC_VCODEC1_AXI_CLK 6
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#define VIDEO_CC_VCODEC1_CORE_CLK 7
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#define VIDEO_CC_VENUS_AHB_CLK 8
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#define VIDEO_CC_VENUS_CLK_SRC 9
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#define VIDEO_CC_VENUS_CTL_AXI_CLK 10
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#define VIDEO_CC_VENUS_CTL_CORE_CLK 11
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#define VIDEO_PLL0 12
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/* VIDEO_CC Resets */
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#define VIDEO_CC_VENUS_BCR 0
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#define VIDEO_CC_VCODEC0_BCR 1
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#define VIDEO_CC_VCODEC1_BCR 2
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#define VIDEO_CC_INTERFACE_BCR 3
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/* VIDEO_CC GDSCRs */
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#define VENUS_GDSC 0
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#define VCODEC0_GDSC 1
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#define VCODEC1_GDSC 2
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#endif