tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu: add BIF 5.0 register headers

These are register headers for the BIF (Bus InterFace) block on
the GPU.

Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher 848ebfd7 054e4c60

+13760
+1068
drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
··· 1 + /* 2 + * BIF_5_0 Register documentation 3 + * 4 + * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included 14 + * in all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + #ifndef BIF_5_0_D_H 25 + #define BIF_5_0_D_H 26 + 27 + #define mmMM_INDEX 0x0 28 + #define mmMM_INDEX_HI 0x6 29 + #define mmMM_DATA 0x1 30 + #define mmBIF_MM_INDACCESS_CNTL 0x1500 31 + #define mmBIF_DOORBELL_APER_EN 0x1501 32 + #define mmBUS_CNTL 0x1508 33 + #define mmCONFIG_CNTL 0x1509 34 + #define mmCONFIG_MEMSIZE 0x150a 35 + #define mmCONFIG_RESERVED 0x1502 36 + #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 37 + #define mmCONFIG_F0_BASE 0x150b 38 + #define mmCONFIG_APER_SIZE 0x150c 39 + #define mmCONFIG_REG_APER_SIZE 0x150d 40 + #define mmBIF_SCRATCH0 0x150e 41 + #define mmBIF_SCRATCH1 0x150f 42 + #define mmBIF_RLC_INTR_CNTL 0x1510 43 + #define mmBIF_BME_STATUS 0x1511 44 + #define mmBIF_ATOMIC_ERR_LOG 0x1512 45 + #define mmBX_RESET_EN 0x1514 46 + #define mmMM_CFGREGS_CNTL 0x1513 47 + #define mmHW_DEBUG 0x1515 48 + #define mmMASTER_CREDIT_CNTL 0x1516 49 + #define mmSLAVE_REQ_CREDIT_CNTL 0x1517 50 + #define mmBX_RESET_CNTL 0x1518 51 + #define mmINTERRUPT_CNTL 0x151a 52 + #define mmINTERRUPT_CNTL2 0x151b 53 + #define mmBIF_DEBUG_CNTL 0x151c 54 + #define mmBIF_DEBUG_MUX 0x151d 55 + #define mmBIF_DEBUG_OUT 0x151e 56 + #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 57 + #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 58 + #define mmCLKREQB_PAD_CNTL 0x1521 59 + #define mmCLKREQB_PERF_COUNTER 0x1522 60 + #define mmBIF_XDMA_LO 0x14c0 61 + #define mmBIF_XDMA_HI 0x14c1 62 + #define mmBIF_FEATURES_CONTROL_MISC 0x14c2 63 + #define mmBIF_DOORBELL_CNTL 0x14c3 64 + #define mmBIF_SLVARB_MODE 0x14c4 65 + #define mmBIF_CLK_CTRL 0x14c5 66 + #define mmBIF_FB_EN 0x1524 67 + #define mmBIF_BUSNUM_CNTL1 0x1525 68 + #define mmBIF_BUSNUM_LIST0 0x1526 69 + #define mmBIF_BUSNUM_LIST1 0x1527 70 + #define mmBIF_BUSNUM_CNTL2 0x152b 71 + #define mmBIF_BUSY_DELAY_CNTR 0x1529 72 + #define mmBIF_PERFMON_CNTL 0x152c 73 + #define mmBIF_PERFCOUNTER0_RESULT 0x152d 74 + #define mmBIF_PERFCOUNTER1_RESULT 0x152e 75 + #define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 76 + #define mmGPU_HDP_FLUSH_REQ 0x1537 77 + #define mmGPU_HDP_FLUSH_DONE 0x1538 78 + #define mmSLAVE_HANG_ERROR 0x153b 79 + #define mmCAPTURE_HOST_BUSNUM 0x153c 80 + #define mmHOST_BUSNUM 0x153d 81 + #define mmPEER_REG_RANGE0 0x153e 82 + #define mmPEER_REG_RANGE1 0x153f 83 + #define mmPEER0_FB_OFFSET_HI 0x14f3 84 + #define mmPEER0_FB_OFFSET_LO 0x14f2 85 + #define mmPEER1_FB_OFFSET_HI 0x14f1 86 + #define mmPEER1_FB_OFFSET_LO 0x14f0 87 + #define mmPEER2_FB_OFFSET_HI 0x14ef 88 + #define mmPEER2_FB_OFFSET_LO 0x14ee 89 + #define mmPEER3_FB_OFFSET_HI 0x14ed 90 + #define mmPEER3_FB_OFFSET_LO 0x14ec 91 + #define mmDBG_SMB_BYPASS_SRBM_ACCESS 0x14eb 92 + #define mmBIF_MST_TRANS_PENDING 0x14ea 93 + #define mmBIF_SLV_TRANS_PENDING 0x14e9 94 + #define mmBIF_DEVFUNCNUM_LIST0 0x14e8 95 + #define mmBIF_DEVFUNCNUM_LIST1 0x14e7 96 + #define mmBACO_CNTL 0x14e5 97 + #define mmBF_ANA_ISO_CNTL 0x14c7 98 + #define mmMEM_TYPE_CNTL 0x14e4 99 + #define mmBIF_BACO_DEBUG 0x14df 100 + #define mmBIF_BACO_DEBUG_LATCH 0x14dc 101 + #define mmBACO_CNTL_MISC 0x14db 102 + #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8 103 + #define mmBIF_VDDGFX_GFX0_LOWER 0x1428 104 + #define mmBIF_VDDGFX_GFX0_UPPER 0x1429 105 + #define mmBIF_VDDGFX_GFX1_LOWER 0x142a 106 + #define mmBIF_VDDGFX_GFX1_UPPER 0x142b 107 + #define mmBIF_VDDGFX_GFX2_LOWER 0x142c 108 + #define mmBIF_VDDGFX_GFX2_UPPER 0x142d 109 + #define mmBIF_VDDGFX_GFX3_LOWER 0x142e 110 + #define mmBIF_VDDGFX_GFX3_UPPER 0x142f 111 + #define mmBIF_VDDGFX_GFX4_LOWER 0x1430 112 + #define mmBIF_VDDGFX_GFX4_UPPER 0x1431 113 + #define mmBIF_VDDGFX_GFX5_LOWER 0x1432 114 + #define mmBIF_VDDGFX_GFX5_UPPER 0x1433 115 + #define mmBIF_VDDGFX_RSV1_LOWER 0x1434 116 + #define mmBIF_VDDGFX_RSV1_UPPER 0x1435 117 + #define mmBIF_VDDGFX_RSV2_LOWER 0x1436 118 + #define mmBIF_VDDGFX_RSV2_UPPER 0x1437 119 + #define mmBIF_VDDGFX_RSV3_LOWER 0x1438 120 + #define mmBIF_VDDGFX_RSV3_UPPER 0x1439 121 + #define mmBIF_VDDGFX_RSV4_LOWER 0x143a 122 + #define mmBIF_VDDGFX_RSV4_UPPER 0x143b 123 + #define mmBIF_VDDGFX_FB_CMP 0x143c 124 + #define mmBIF_SMU_INDEX 0x143d 125 + #define mmBIF_SMU_DATA 0x143e 126 + #define mmBIF_DOORBELL_GBLAPER1_LOWER 0x14fc 127 + #define mmBIF_DOORBELL_GBLAPER1_UPPER 0x14fd 128 + #define mmBIF_DOORBELL_GBLAPER2_LOWER 0x14fe 129 + #define mmBIF_DOORBELL_GBLAPER2_UPPER 0x14ff 130 + #define mmIMPCTL_RESET 0x14f5 131 + #define mmGARLIC_FLUSH_CNTL 0x1401 132 + #define mmGARLIC_FLUSH_ADDR_START_0 0x1402 133 + #define mmGARLIC_FLUSH_ADDR_START_1 0x1404 134 + #define mmGARLIC_FLUSH_ADDR_START_2 0x1406 135 + #define mmGARLIC_FLUSH_ADDR_START_3 0x1408 136 + #define mmGARLIC_FLUSH_ADDR_START_4 0x140a 137 + #define mmGARLIC_FLUSH_ADDR_START_5 0x140c 138 + #define mmGARLIC_FLUSH_ADDR_START_6 0x140e 139 + #define mmGARLIC_FLUSH_ADDR_START_7 0x1410 140 + #define mmGARLIC_FLUSH_ADDR_END_0 0x1403 141 + #define mmGARLIC_FLUSH_ADDR_END_1 0x1405 142 + #define mmGARLIC_FLUSH_ADDR_END_2 0x1407 143 + #define mmGARLIC_FLUSH_ADDR_END_3 0x1409 144 + #define mmGARLIC_FLUSH_ADDR_END_4 0x140b 145 + #define mmGARLIC_FLUSH_ADDR_END_5 0x140d 146 + #define mmGARLIC_FLUSH_ADDR_END_6 0x140f 147 + #define mmGARLIC_FLUSH_ADDR_END_7 0x1411 148 + #define mmGARLIC_FLUSH_REQ 0x1412 149 + #define mmGPU_GARLIC_FLUSH_REQ 0x1413 150 + #define mmGPU_GARLIC_FLUSH_DONE 0x1414 151 + #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x1426 152 + #define mmREMAP_HDP_REG_FLUSH_CNTL 0x1427 153 + #define mmBIOS_SCRATCH_0 0x5c9 154 + #define mmBIOS_SCRATCH_1 0x5ca 155 + #define mmBIOS_SCRATCH_2 0x5cb 156 + #define mmBIOS_SCRATCH_3 0x5cc 157 + #define mmBIOS_SCRATCH_4 0x5cd 158 + #define mmBIOS_SCRATCH_5 0x5ce 159 + #define mmBIOS_SCRATCH_6 0x5cf 160 + #define mmBIOS_SCRATCH_7 0x5d0 161 + #define mmBIOS_SCRATCH_8 0x5d1 162 + #define mmBIOS_SCRATCH_9 0x5d2 163 + #define mmBIOS_SCRATCH_10 0x5d3 164 + #define mmBIOS_SCRATCH_11 0x5d4 165 + #define mmBIOS_SCRATCH_12 0x5d5 166 + #define mmBIOS_SCRATCH_13 0x5d6 167 + #define mmBIOS_SCRATCH_14 0x5d7 168 + #define mmBIOS_SCRATCH_15 0x5d8 169 + #define mmBIF_RB_CNTL 0x1530 170 + #define mmBIF_RB_BASE 0x1531 171 + #define mmBIF_RB_RPTR 0x1532 172 + #define mmBIF_RB_WPTR 0x1533 173 + #define mmBIF_RB_WPTR_ADDR_HI 0x1534 174 + #define mmBIF_RB_WPTR_ADDR_LO 0x1535 175 + #define mmMAILBOX_INDEX 0x14c6 176 + #define mmMAILBOX_MSGBUF_TRN_DW0 0x14c8 177 + #define mmMAILBOX_MSGBUF_TRN_DW1 0x14c9 178 + #define mmMAILBOX_MSGBUF_TRN_DW2 0x14ca 179 + #define mmMAILBOX_MSGBUF_TRN_DW3 0x14cb 180 + #define mmMAILBOX_MSGBUF_RCV_DW0 0x14cc 181 + #define mmMAILBOX_MSGBUF_RCV_DW1 0x14cd 182 + #define mmMAILBOX_MSGBUF_RCV_DW2 0x14ce 183 + #define mmMAILBOX_MSGBUF_RCV_DW3 0x14cf 184 + #define mmMAILBOX_CONTROL 0x14d0 185 + #define mmMAILBOX_INT_CNTL 0x14d1 186 + #define mmBIF_VIRT_RESET_REQ 0x14d2 187 + #define mmVM_INIT_STATUS 0x14d3 188 + #define mmBIF_GPUIOV_RESET_NOTIFICATION 0x14d5 189 + #define mmBIF_GPUIOV_VM_INIT_STATUS 0x14d6 190 + #define mmBIF_GPUIOV_FB_TOTAL_FB_INFO 0x14d8 191 + #define mmBIF_GPUIOV_GPU_IDLE_LATENCY 0x141c 192 + #define mmBIF_GPUIOV_MMIO_MAP_RANGE0 0x141d 193 + #define mmBIF_GPUIOV_MMIO_MAP_RANGE1 0x141e 194 + #define mmBIF_GPUIOV_MMIO_MAP_RANGE2 0x141f 195 + #define mmBIF_GPUIOV_MMIO_MAP_RANGE3 0x1420 196 + #define mmBIF_GPUIOV_MMIO_MAP_RANGE4 0x1421 197 + #define mmBIF_GPUIOV_MMIO_MAP_RANGE5 0x1422 198 + #define mmBIF_GPU_IDLE_LATENCY 0x1415 199 + #define mmBIF_MMIO_MAP_RANGE0 0x1416 200 + #define mmBIF_MMIO_MAP_RANGE1 0x1417 201 + #define mmBIF_MMIO_MAP_RANGE2 0x1418 202 + #define mmBIF_MMIO_MAP_RANGE3 0x1419 203 + #define mmBIF_MMIO_MAP_RANGE4 0x141a 204 + #define mmBIF_MMIO_MAP_RANGE5 0x141b 205 + #define mmVENDOR_ID 0x0 206 + #define mmDEVICE_ID 0x0 207 + #define mmCOMMAND 0x1 208 + #define mmSTATUS 0x1 209 + #define mmREVISION_ID 0x2 210 + #define mmPROG_INTERFACE 0x2 211 + #define mmSUB_CLASS 0x2 212 + #define mmBASE_CLASS 0x2 213 + #define mmCACHE_LINE 0x3 214 + #define mmLATENCY 0x3 215 + #define mmHEADER 0x3 216 + #define mmBIST 0x3 217 + #define mmBASE_ADDR_1 0x4 218 + #define mmBASE_ADDR_2 0x5 219 + #define mmBASE_ADDR_3 0x6 220 + #define mmBASE_ADDR_4 0x7 221 + #define mmBASE_ADDR_5 0x8 222 + #define mmBASE_ADDR_6 0x9 223 + #define mmROM_BASE_ADDR 0xc 224 + #define mmCAP_PTR 0xd 225 + #define mmINTERRUPT_LINE 0xf 226 + #define mmINTERRUPT_PIN 0xf 227 + #define mmADAPTER_ID 0xb 228 + #define mmMIN_GRANT 0xf 229 + #define mmMAX_LATENCY 0xf 230 + #define mmVENDOR_CAP_LIST 0x12 231 + #define mmADAPTER_ID_W 0x13 232 + #define mmPMI_CAP_LIST 0x14 233 + #define mmPMI_CAP 0x14 234 + #define mmPMI_STATUS_CNTL 0x15 235 + #define mmPCIE_CAP_LIST 0x16 236 + #define mmPCIE_CAP 0x16 237 + #define mmDEVICE_CAP 0x17 238 + #define mmDEVICE_CNTL 0x18 239 + #define mmDEVICE_STATUS 0x18 240 + #define mmLINK_CAP 0x19 241 + #define mmLINK_CNTL 0x1a 242 + #define mmLINK_STATUS 0x1a 243 + #define mmDEVICE_CAP2 0x1f 244 + #define mmDEVICE_CNTL2 0x20 245 + #define mmDEVICE_STATUS2 0x20 246 + #define mmLINK_CAP2 0x21 247 + #define mmLINK_CNTL2 0x22 248 + #define mmLINK_STATUS2 0x22 249 + #define mmMSI_CAP_LIST 0x28 250 + #define mmMSI_MSG_CNTL 0x28 251 + #define mmMSI_MSG_ADDR_LO 0x29 252 + #define mmMSI_MSG_ADDR_HI 0x2a 253 + #define mmMSI_MSG_DATA_64 0x2b 254 + #define mmMSI_MSG_DATA 0x2a 255 + #define mmMSI_MASK 0x2b 256 + #define mmMSI_PENDING 0x2c 257 + #define mmMSI_MASK_64 0x2c 258 + #define mmMSI_PENDING_64 0x2d 259 + #define mmMSIX_CAP_LIST 0x30 260 + #define mmMSIX_MSG_CNTL 0x30 261 + #define mmMSIX_TABLE 0x31 262 + #define mmMSIX_PBA 0x32 263 + #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40 264 + #define mmPCIE_VENDOR_SPECIFIC_HDR 0x41 265 + #define mmPCIE_VENDOR_SPECIFIC1 0x42 266 + #define mmPCIE_VENDOR_SPECIFIC2 0x43 267 + #define mmPCIE_VC_ENH_CAP_LIST 0x44 268 + #define mmPCIE_PORT_VC_CAP_REG1 0x45 269 + #define mmPCIE_PORT_VC_CAP_REG2 0x46 270 + #define mmPCIE_PORT_VC_CNTL 0x47 271 + #define mmPCIE_PORT_VC_STATUS 0x47 272 + #define mmPCIE_VC0_RESOURCE_CAP 0x48 273 + #define mmPCIE_VC0_RESOURCE_CNTL 0x49 274 + #define mmPCIE_VC0_RESOURCE_STATUS 0x4a 275 + #define mmPCIE_VC1_RESOURCE_CAP 0x4b 276 + #define mmPCIE_VC1_RESOURCE_CNTL 0x4c 277 + #define mmPCIE_VC1_RESOURCE_STATUS 0x4d 278 + #define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50 279 + #define mmPCIE_DEV_SERIAL_NUM_DW1 0x51 280 + #define mmPCIE_DEV_SERIAL_NUM_DW2 0x52 281 + #define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54 282 + #define mmPCIE_UNCORR_ERR_STATUS 0x55 283 + #define mmPCIE_UNCORR_ERR_MASK 0x56 284 + #define mmPCIE_UNCORR_ERR_SEVERITY 0x57 285 + #define mmPCIE_CORR_ERR_STATUS 0x58 286 + #define mmPCIE_CORR_ERR_MASK 0x59 287 + #define mmPCIE_ADV_ERR_CAP_CNTL 0x5a 288 + #define mmPCIE_HDR_LOG0 0x5b 289 + #define mmPCIE_HDR_LOG1 0x5c 290 + #define mmPCIE_HDR_LOG2 0x5d 291 + #define mmPCIE_HDR_LOG3 0x5e 292 + #define mmPCIE_TLP_PREFIX_LOG0 0x62 293 + #define mmPCIE_TLP_PREFIX_LOG1 0x63 294 + #define mmPCIE_TLP_PREFIX_LOG2 0x64 295 + #define mmPCIE_TLP_PREFIX_LOG3 0x65 296 + #define mmPCIE_BAR_ENH_CAP_LIST 0x80 297 + #define mmPCIE_BAR1_CAP 0x81 298 + #define mmPCIE_BAR1_CNTL 0x82 299 + #define mmPCIE_BAR2_CAP 0x83 300 + #define mmPCIE_BAR2_CNTL 0x84 301 + #define mmPCIE_BAR3_CAP 0x85 302 + #define mmPCIE_BAR3_CNTL 0x86 303 + #define mmPCIE_BAR4_CAP 0x87 304 + #define mmPCIE_BAR4_CNTL 0x88 305 + #define mmPCIE_BAR5_CAP 0x89 306 + #define mmPCIE_BAR5_CNTL 0x8a 307 + #define mmPCIE_BAR6_CAP 0x8b 308 + #define mmPCIE_BAR6_CNTL 0x8c 309 + #define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90 310 + #define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91 311 + #define mmPCIE_PWR_BUDGET_DATA 0x92 312 + #define mmPCIE_PWR_BUDGET_CAP 0x93 313 + #define mmPCIE_DPA_ENH_CAP_LIST 0x94 314 + #define mmPCIE_DPA_CAP 0x95 315 + #define mmPCIE_DPA_LATENCY_INDICATOR 0x96 316 + #define mmPCIE_DPA_STATUS 0x97 317 + #define mmPCIE_DPA_CNTL 0x97 318 + #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98 319 + #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98 320 + #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98 321 + #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98 322 + #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99 323 + #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99 324 + #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99 325 + #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99 326 + #define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c 327 + #define mmPCIE_LINK_CNTL3 0x9d 328 + #define mmPCIE_LANE_ERROR_STATUS 0x9e 329 + #define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f 330 + #define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f 331 + #define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0 332 + #define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0 333 + #define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1 334 + #define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1 335 + #define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2 336 + #define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2 337 + #define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3 338 + #define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3 339 + #define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4 340 + #define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4 341 + #define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5 342 + #define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5 343 + #define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6 344 + #define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6 345 + #define mmPCIE_ACS_ENH_CAP_LIST 0xa8 346 + #define mmPCIE_ACS_CAP 0xa9 347 + #define mmPCIE_ACS_CNTL 0xa9 348 + #define mmPCIE_ATS_ENH_CAP_LIST 0xac 349 + #define mmPCIE_ATS_CAP 0xad 350 + #define mmPCIE_ATS_CNTL 0xad 351 + #define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0 352 + #define mmPCIE_PAGE_REQ_CNTL 0xb1 353 + #define mmPCIE_PAGE_REQ_STATUS 0xb1 354 + #define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2 355 + #define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3 356 + #define mmPCIE_PASID_ENH_CAP_LIST 0xb4 357 + #define mmPCIE_PASID_CAP 0xb5 358 + #define mmPCIE_PASID_CNTL 0xb5 359 + #define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8 360 + #define mmPCIE_TPH_REQR_CAP 0xb9 361 + #define mmPCIE_TPH_REQR_CNTL 0xba 362 + #define mmPCIE_MC_ENH_CAP_LIST 0xbc 363 + #define mmPCIE_MC_CAP 0xbd 364 + #define mmPCIE_MC_CNTL 0xbd 365 + #define mmPCIE_MC_ADDR0 0xbe 366 + #define mmPCIE_MC_ADDR1 0xbf 367 + #define mmPCIE_MC_RCV0 0xc0 368 + #define mmPCIE_MC_RCV1 0xc1 369 + #define mmPCIE_MC_BLOCK_ALL0 0xc2 370 + #define mmPCIE_MC_BLOCK_ALL1 0xc3 371 + #define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4 372 + #define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5 373 + #define mmPCIE_LTR_ENH_CAP_LIST 0xc8 374 + #define mmPCIE_LTR_CAP 0xc9 375 + #define mmPCIE_ARI_ENH_CAP_LIST 0xca 376 + #define mmPCIE_ARI_CAP 0xcb 377 + #define mmPCIE_ARI_CNTL 0xcb 378 + #define mmPCIE_SRIOV_ENH_CAP_LIST 0xcc 379 + #define mmPCIE_SRIOV_CAP 0xcd 380 + #define mmPCIE_SRIOV_CONTROL 0xce 381 + #define mmPCIE_SRIOV_STATUS 0xce 382 + #define mmPCIE_SRIOV_INITIAL_VFS 0xcf 383 + #define mmPCIE_SRIOV_TOTAL_VFS 0xcf 384 + #define mmPCIE_SRIOV_NUM_VFS 0xd0 385 + #define mmPCIE_SRIOV_FUNC_DEP_LINK 0xd0 386 + #define mmPCIE_SRIOV_FIRST_VF_OFFSET 0xd1 387 + #define mmPCIE_SRIOV_VF_STRIDE 0xd1 388 + #define mmPCIE_SRIOV_VF_DEVICE_ID 0xd2 389 + #define mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xd3 390 + #define mmPCIE_SRIOV_SYSTEM_PAGE_SIZE 0xd4 391 + #define mmPCIE_SRIOV_VF_BASE_ADDR_0 0xd5 392 + #define mmPCIE_SRIOV_VF_BASE_ADDR_1 0xd6 393 + #define mmPCIE_SRIOV_VF_BASE_ADDR_2 0xd7 394 + #define mmPCIE_SRIOV_VF_BASE_ADDR_3 0xd8 395 + #define mmPCIE_SRIOV_VF_BASE_ADDR_4 0xd9 396 + #define mmPCIE_SRIOV_VF_BASE_ADDR_5 0xda 397 + #define mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xdb 398 + #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x100 399 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x101 400 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x102 401 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC 0x103 402 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS 0x104 403 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x105 404 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION 0x106 405 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS 0x107 406 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x108 407 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x109 408 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS 0x10a 409 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x10b 410 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x10c 411 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x10d 412 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x10e 413 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x10f 414 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x110 415 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x111 416 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x112 417 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x113 418 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x114 419 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x115 420 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x116 421 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x117 422 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x118 423 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x119 424 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x11a 425 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x11b 426 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT 0x11c 427 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0 0x11d 428 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1 0x11e 429 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2 0x11f 430 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3 0x120 431 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4 0x121 432 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5 0x122 433 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0 0x124 434 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1 0x125 435 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2 0x126 436 + #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3 0x127 437 + #define mmPCIE_INDEX 0xe 438 + #define mmPCIE_DATA 0xf 439 + #define mmPCIE_INDEX_2 0xc 440 + #define mmPCIE_DATA_2 0xd 441 + #define ixPCIE_HOLD_TRAINING_A 0x1500820 442 + #define ixLNCNT_CONTROL 0x1508030 443 + #define ixCFG_LNC_WINDOW 0x1508031 444 + #define ixLNCNT_QUAN_THRD 0x1508032 445 + #define ixLNCNT_WEIGHT 0x1508033 446 + #define ixLNC_TOTAL_WACC 0x1508034 447 + #define ixLNC_BW_WACC 0x1508035 448 + #define ixLNC_CMN_WACC 0x1508036 449 + #define mmPCIE_EFUSE 0xfc0 450 + #define mmPCIE_EFUSE2 0xfc1 451 + #define mmPCIE_EFUSE3 0xfc2 452 + #define mmPCIE_EFUSE4 0xfc3 453 + #define mmPCIE_EFUSE5 0xfc4 454 + #define mmPCIE_EFUSE6 0xfc5 455 + #define mmPCIE_EFUSE7 0xfc6 456 + #define ixPCIE_WRAP_SCRATCH1 0x1308001 457 + #define ixPCIE_WRAP_SCRATCH2 0x1308002 458 + #define ixPCIE_WRAP_REG_TARG_MISC 0x1308005 459 + #define ixPCIE_WRAP_DTM_MISC 0x1308006 460 + #define ixPCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1308007 461 + #define ixPCIE_WRAP_MISC 0x1308008 462 + #define ixPCIE_WRAP_PIF_MISC 0x1308009 463 + #define ixPCIE_RXDET_OVERRIDE 0x130800a 464 + #define ixREG_ADAPT_pciecore0_CONTROL 0x1308090 465 + #define ixREG_ADAPT_pwregt_CONTROL 0x1308096 466 + #define ixREG_ADAPT_pwregr_CONTROL 0x1308097 467 + #define ixREG_ADAPT_pif0_CONTROL 0x1308098 468 + #define ixPCIE_RESERVED 0x1400000 469 + #define ixPCIE_SCRATCH 0x1400001 470 + #define ixPCIE_HW_DEBUG 0x1400002 471 + #define ixPCIE_RX_NUM_NAK 0x140000e 472 + #define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f 473 + #define ixPCIE_CNTL 0x1400010 474 + #define ixPCIE_CONFIG_CNTL 0x1400011 475 + #define ixPCIE_DEBUG_CNTL 0x1400012 476 + #define ixPCIE_INT_CNTL 0x140001a 477 + #define ixPCIE_INT_STATUS 0x140001b 478 + #define ixPCIE_CNTL2 0x140001c 479 + #define ixPCIE_RX_CNTL2 0x140001d 480 + #define ixPCIE_TX_F0_ATTR_CNTL 0x140001e 481 + #define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f 482 + #define ixPCIE_CI_CNTL 0x1400020 483 + #define ixPCIE_BUS_CNTL 0x1400021 484 + #define ixPCIE_LC_STATE6 0x1400022 485 + #define ixPCIE_LC_STATE7 0x1400023 486 + #define ixPCIE_LC_STATE8 0x1400024 487 + #define ixPCIE_LC_STATE9 0x1400025 488 + #define ixPCIE_LC_STATE10 0x1400026 489 + #define ixPCIE_LC_STATE11 0x1400027 490 + #define ixPCIE_LC_STATUS1 0x1400028 491 + #define ixPCIE_LC_STATUS2 0x1400029 492 + #define ixPCIE_WPR_CNTL 0x1400030 493 + #define ixPCIE_RX_LAST_TLP0 0x1400031 494 + #define ixPCIE_RX_LAST_TLP1 0x1400032 495 + #define ixPCIE_RX_LAST_TLP2 0x1400033 496 + #define ixPCIE_RX_LAST_TLP3 0x1400034 497 + #define ixPCIE_TX_LAST_TLP0 0x1400035 498 + #define ixPCIE_TX_LAST_TLP1 0x1400036 499 + #define ixPCIE_TX_LAST_TLP2 0x1400037 500 + #define ixPCIE_TX_LAST_TLP3 0x1400038 501 + #define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a 502 + #define ixPCIE_I2C_REG_DATA 0x140003b 503 + #define ixPCIE_CFG_CNTL 0x140003c 504 + #define ixPCIE_LC_PM_CNTL 0x140003d 505 + #define ixPCIE_P_CNTL 0x1400040 506 + #define ixPCIE_P_BUF_STATUS 0x1400041 507 + #define ixPCIE_P_DECODER_STATUS 0x1400042 508 + #define ixPCIE_P_MISC_STATUS 0x1400043 509 + #define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050 510 + #define ixPCIE_OBFF_CNTL 0x1400061 511 + #define ixPCIE_TX_LTR_CNTL 0x1400060 512 + #define ixPCIE_IDLE_STATUS 0x1400062 513 + #define ixPCIE_PERF_COUNT_CNTL 0x1400080 514 + #define ixPCIE_PERF_CNTL_TXCLK 0x1400081 515 + #define ixPCIE_PERF_COUNT0_TXCLK 0x1400082 516 + #define ixPCIE_PERF_COUNT1_TXCLK 0x1400083 517 + #define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084 518 + #define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085 519 + #define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086 520 + #define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087 521 + #define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088 522 + #define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089 523 + #define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a 524 + #define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b 525 + #define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c 526 + #define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d 527 + #define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e 528 + #define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f 529 + #define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 530 + #define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 531 + #define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 532 + #define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 533 + #define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 534 + #define ixPCIE_PERF_CNTL_TXCLK2 0x1400095 535 + #define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096 536 + #define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097 537 + #define ixPCIE_STRAP_F0 0x14000b0 538 + #define ixPCIE_STRAP_F1 0x14000b1 539 + #define ixPCIE_STRAP_F2 0x14000b2 540 + #define ixPCIE_STRAP_F3 0x14000b3 541 + #define ixPCIE_STRAP_F4 0x14000b4 542 + #define ixPCIE_STRAP_F5 0x14000b5 543 + #define ixPCIE_STRAP_F6 0x14000b6 544 + #define ixPCIE_STRAP_MSIX 0x14000b7 545 + #define ixPCIE_STRAP_MISC 0x14000c0 546 + #define ixPCIE_STRAP_MISC2 0x14000c1 547 + #define ixPCIE_STRAP_PI 0x14000c2 548 + #define ixPCIE_STRAP_I2C_BD 0x14000c4 549 + #define ixPCIE_PRBS_CLR 0x14000c8 550 + #define ixPCIE_PRBS_STATUS1 0x14000c9 551 + #define ixPCIE_PRBS_STATUS2 0x14000ca 552 + #define ixPCIE_PRBS_FREERUN 0x14000cb 553 + #define ixPCIE_PRBS_MISC 0x14000cc 554 + #define ixPCIE_PRBS_USER_PATTERN 0x14000cd 555 + #define ixPCIE_PRBS_LO_BITCNT 0x14000ce 556 + #define ixPCIE_PRBS_HI_BITCNT 0x14000cf 557 + #define ixPCIE_PRBS_ERRCNT_0 0x14000d0 558 + #define ixPCIE_PRBS_ERRCNT_1 0x14000d1 559 + #define ixPCIE_PRBS_ERRCNT_2 0x14000d2 560 + #define ixPCIE_PRBS_ERRCNT_3 0x14000d3 561 + #define ixPCIE_PRBS_ERRCNT_4 0x14000d4 562 + #define ixPCIE_PRBS_ERRCNT_5 0x14000d5 563 + #define ixPCIE_PRBS_ERRCNT_6 0x14000d6 564 + #define ixPCIE_PRBS_ERRCNT_7 0x14000d7 565 + #define ixPCIE_PRBS_ERRCNT_8 0x14000d8 566 + #define ixPCIE_PRBS_ERRCNT_9 0x14000d9 567 + #define ixPCIE_PRBS_ERRCNT_10 0x14000da 568 + #define ixPCIE_PRBS_ERRCNT_11 0x14000db 569 + #define ixPCIE_PRBS_ERRCNT_12 0x14000dc 570 + #define ixPCIE_PRBS_ERRCNT_13 0x14000dd 571 + #define ixPCIE_PRBS_ERRCNT_14 0x14000de 572 + #define ixPCIE_PRBS_ERRCNT_15 0x14000df 573 + #define ixPCIE_F0_DPA_CAP 0x14000e0 574 + #define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4 575 + #define ixPCIE_F0_DPA_CNTL 0x14000e5 576 + #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7 577 + #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8 578 + #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9 579 + #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea 580 + #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb 581 + #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec 582 + #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed 583 + #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee 584 + #define mmSWRST_COMMAND_STATUS 0x14a0 585 + #define mmSWRST_GENERAL_CONTROL 0x14a1 586 + #define mmSWRST_COMMAND_0 0x14a2 587 + #define mmSWRST_COMMAND_1 0x14a3 588 + #define mmSWRST_CONTROL_0 0x14a4 589 + #define mmSWRST_CONTROL_1 0x14a5 590 + #define mmSWRST_CONTROL_2 0x14a6 591 + #define mmSWRST_CONTROL_3 0x14a7 592 + #define mmSWRST_CONTROL_4 0x14a8 593 + #define mmSWRST_CONTROL_5 0x14a9 594 + #define mmSWRST_CONTROL_6 0x14aa 595 + #define mmSWRST_EP_COMMAND_0 0x14ab 596 + #define mmSWRST_EP_CONTROL_0 0x14ac 597 + #define mmCPM_CONTROL 0x14b8 598 + #define mmGSKT_CONTROL 0x14bf 599 + #define ixLM_CONTROL 0x1400120 600 + #define ixLM_PCIETXMUX0 0x1400121 601 + #define ixLM_PCIETXMUX1 0x1400122 602 + #define ixLM_PCIETXMUX2 0x1400123 603 + #define ixLM_PCIETXMUX3 0x1400124 604 + #define ixLM_PCIERXMUX0 0x1400125 605 + #define ixLM_PCIERXMUX1 0x1400126 606 + #define ixLM_PCIERXMUX2 0x1400127 607 + #define ixLM_PCIERXMUX3 0x1400128 608 + #define ixLM_LANEENABLE 0x1400129 609 + #define ixLM_PRBSCONTROL 0x140012a 610 + #define ixLM_POWERCONTROL 0x140012b 611 + #define ixLM_POWERCONTROL1 0x140012c 612 + #define ixLM_POWERCONTROL2 0x140012d 613 + #define ixLM_POWERCONTROL3 0x140012e 614 + #define ixLM_POWERCONTROL4 0x140012f 615 + #define ixPB0_GLB_CTRL_REG0 0x1200004 616 + #define ixPB0_GLB_CTRL_REG1 0x1200008 617 + #define ixPB0_GLB_CTRL_REG2 0x120000c 618 + #define ixPB0_GLB_CTRL_REG3 0x1200010 619 + #define ixPB0_GLB_CTRL_REG4 0x1200014 620 + #define ixPB0_GLB_CTRL_REG5 0x1200018 621 + #define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c 622 + #define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020 623 + #define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024 624 + #define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028 625 + #define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c 626 + #define ixPB0_GLB_OVRD_REG0 0x1200030 627 + #define ixPB0_GLB_OVRD_REG1 0x1200034 628 + #define ixPB0_GLB_OVRD_REG2 0x1200038 629 + #define ixPB0_HW_DEBUG 0x1202004 630 + #define ixPB0_STRAP_GLB_REG0 0x1202020 631 + #define ixPB0_STRAP_TX_REG0 0x1202024 632 + #define ixPB0_STRAP_RX_REG0 0x1202028 633 + #define ixPB0_STRAP_RX_REG1 0x120202c 634 + #define ixPB0_STRAP_PLL_REG0 0x1202030 635 + #define ixPB0_STRAP_PIN_REG0 0x1202034 636 + #define ixPB0_STRAP_GLB_REG1 0x1202038 637 + #define ixPB0_STRAP_GLB_REG2 0x120203c 638 + #define ixPB0_DFT_JIT_INJ_REG0 0x1203000 639 + #define ixPB0_DFT_JIT_INJ_REG1 0x1203004 640 + #define ixPB0_DFT_JIT_INJ_REG2 0x1203008 641 + #define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c 642 + #define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010 643 + #define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000 644 + #define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010 645 + #define ixPB0_PLL_RO0_CTRL_REG0 0x1204440 646 + #define ixPB0_PLL_RO0_OVRD_REG0 0x1204450 647 + #define ixPB0_PLL_RO0_OVRD_REG1 0x1204454 648 + #define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460 649 + #define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464 650 + #define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468 651 + #define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c 652 + #define ixPB0_PLL_LC0_CTRL_REG0 0x1204480 653 + #define ixPB0_PLL_LC0_OVRD_REG0 0x1204490 654 + #define ixPB0_PLL_LC0_OVRD_REG1 0x1204494 655 + #define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500 656 + #define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504 657 + #define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508 658 + #define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c 659 + #define ixPB0_RX_GLB_CTRL_REG0 0x1206000 660 + #define ixPB0_RX_GLB_CTRL_REG1 0x1206004 661 + #define ixPB0_RX_GLB_CTRL_REG2 0x1206008 662 + #define ixPB0_RX_GLB_CTRL_REG3 0x120600c 663 + #define ixPB0_RX_GLB_CTRL_REG4 0x1206010 664 + #define ixPB0_RX_GLB_CTRL_REG5 0x1206014 665 + #define ixPB0_RX_GLB_CTRL_REG6 0x1206018 666 + #define ixPB0_RX_GLB_CTRL_REG7 0x120601c 667 + #define ixPB0_RX_GLB_CTRL_REG8 0x1206020 668 + #define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028 669 + #define ixPB0_RX_GLB_OVRD_REG0 0x1206030 670 + #define ixPB0_RX_GLB_OVRD_REG1 0x1206034 671 + #define ixPB0_RX_LANE0_CTRL_REG0 0x1206440 672 + #define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448 673 + #define ixPB0_RX_LANE1_CTRL_REG0 0x1206480 674 + #define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488 675 + #define ixPB0_RX_LANE2_CTRL_REG0 0x1206500 676 + #define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508 677 + #define ixPB0_RX_LANE3_CTRL_REG0 0x1206600 678 + #define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608 679 + #define ixPB0_RX_LANE4_CTRL_REG0 0x1206800 680 + #define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848 681 + #define ixPB0_RX_LANE5_CTRL_REG0 0x1206880 682 + #define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888 683 + #define ixPB0_RX_LANE6_CTRL_REG0 0x1206900 684 + #define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908 685 + #define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00 686 + #define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08 687 + #define ixPB0_RX_LANE8_CTRL_REG0 0x1207440 688 + #define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448 689 + #define ixPB0_RX_LANE9_CTRL_REG0 0x1207480 690 + #define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488 691 + #define ixPB0_RX_LANE10_CTRL_REG0 0x1207500 692 + #define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508 693 + #define ixPB0_RX_LANE11_CTRL_REG0 0x1207600 694 + #define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608 695 + #define ixPB0_RX_LANE12_CTRL_REG0 0x1207840 696 + #define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848 697 + #define ixPB0_RX_LANE13_CTRL_REG0 0x1207880 698 + #define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888 699 + #define ixPB0_RX_LANE14_CTRL_REG0 0x1207900 700 + #define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908 701 + #define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00 702 + #define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08 703 + #define ixPB0_TX_GLB_CTRL_REG0 0x1208000 704 + #define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004 705 + #define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010 706 + #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014 707 + #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018 708 + #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c 709 + #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020 710 + #define ixPB0_TX_GLB_OVRD_REG0 0x1208030 711 + #define ixPB0_TX_GLB_OVRD_REG1 0x1208034 712 + #define ixPB0_TX_GLB_OVRD_REG2 0x1208038 713 + #define ixPB0_TX_GLB_OVRD_REG3 0x120803c 714 + #define ixPB0_TX_GLB_OVRD_REG4 0x1208040 715 + #define ixPB0_TX_LANE0_CTRL_REG0 0x1208440 716 + #define ixPB0_TX_LANE0_OVRD_REG0 0x1208444 717 + #define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448 718 + #define ixPB0_TX_LANE1_CTRL_REG0 0x1208480 719 + #define ixPB0_TX_LANE1_OVRD_REG0 0x1208484 720 + #define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488 721 + #define ixPB0_TX_LANE2_CTRL_REG0 0x1208500 722 + #define ixPB0_TX_LANE2_OVRD_REG0 0x1208504 723 + #define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508 724 + #define ixPB0_TX_LANE3_CTRL_REG0 0x1208600 725 + #define ixPB0_TX_LANE3_OVRD_REG0 0x1208604 726 + #define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608 727 + #define ixPB0_TX_LANE4_CTRL_REG0 0x1208840 728 + #define ixPB0_TX_LANE4_OVRD_REG0 0x1208844 729 + #define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848 730 + #define ixPB0_TX_LANE5_CTRL_REG0 0x1208880 731 + #define ixPB0_TX_LANE5_OVRD_REG0 0x1208884 732 + #define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888 733 + #define ixPB0_TX_LANE6_CTRL_REG0 0x1208900 734 + #define ixPB0_TX_LANE6_OVRD_REG0 0x1208904 735 + #define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908 736 + #define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00 737 + #define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04 738 + #define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08 739 + #define ixPB0_TX_LANE8_CTRL_REG0 0x1209440 740 + #define ixPB0_TX_LANE8_OVRD_REG0 0x1209444 741 + #define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448 742 + #define ixPB0_TX_LANE9_CTRL_REG0 0x1209480 743 + #define ixPB0_TX_LANE9_OVRD_REG0 0x1209484 744 + #define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488 745 + #define ixPB0_TX_LANE10_CTRL_REG0 0x1209500 746 + #define ixPB0_TX_LANE10_OVRD_REG0 0x1209504 747 + #define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508 748 + #define ixPB0_TX_LANE11_CTRL_REG0 0x1209600 749 + #define ixPB0_TX_LANE11_OVRD_REG0 0x1209604 750 + #define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608 751 + #define ixPB0_TX_LANE12_CTRL_REG0 0x1209840 752 + #define ixPB0_TX_LANE12_OVRD_REG0 0x1209844 753 + #define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848 754 + #define ixPB0_TX_LANE13_CTRL_REG0 0x1209880 755 + #define ixPB0_TX_LANE13_OVRD_REG0 0x1209884 756 + #define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888 757 + #define ixPB0_TX_LANE14_CTRL_REG0 0x1209900 758 + #define ixPB0_TX_LANE14_OVRD_REG0 0x1209904 759 + #define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908 760 + #define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00 761 + #define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04 762 + #define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08 763 + #define ixPB1_GLB_CTRL_REG0 0x2200004 764 + #define ixPB1_GLB_CTRL_REG1 0x2200008 765 + #define ixPB1_GLB_CTRL_REG2 0x220000c 766 + #define ixPB1_GLB_CTRL_REG3 0x2200010 767 + #define ixPB1_GLB_CTRL_REG4 0x2200014 768 + #define ixPB1_GLB_CTRL_REG5 0x2200018 769 + #define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c 770 + #define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020 771 + #define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024 772 + #define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028 773 + #define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c 774 + #define ixPB1_GLB_OVRD_REG0 0x2200030 775 + #define ixPB1_GLB_OVRD_REG1 0x2200034 776 + #define ixPB1_GLB_OVRD_REG2 0x2200038 777 + #define ixPB1_HW_DEBUG 0x2202004 778 + #define ixPB1_STRAP_GLB_REG0 0x2202020 779 + #define ixPB1_STRAP_TX_REG0 0x2202024 780 + #define ixPB1_STRAP_RX_REG0 0x2202028 781 + #define ixPB1_STRAP_RX_REG1 0x220202c 782 + #define ixPB1_STRAP_PLL_REG0 0x2202030 783 + #define ixPB1_STRAP_PIN_REG0 0x2202034 784 + #define ixPB1_STRAP_GLB_REG1 0x2202038 785 + #define ixPB1_STRAP_GLB_REG2 0x220203c 786 + #define ixPB1_DFT_JIT_INJ_REG0 0x2203000 787 + #define ixPB1_DFT_JIT_INJ_REG1 0x2203004 788 + #define ixPB1_DFT_JIT_INJ_REG2 0x2203008 789 + #define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c 790 + #define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010 791 + #define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000 792 + #define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010 793 + #define ixPB1_PLL_RO0_CTRL_REG0 0x2204440 794 + #define ixPB1_PLL_RO0_OVRD_REG0 0x2204450 795 + #define ixPB1_PLL_RO0_OVRD_REG1 0x2204454 796 + #define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460 797 + #define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464 798 + #define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468 799 + #define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c 800 + #define ixPB1_PLL_LC0_CTRL_REG0 0x2204480 801 + #define ixPB1_PLL_LC0_OVRD_REG0 0x2204490 802 + #define ixPB1_PLL_LC0_OVRD_REG1 0x2204494 803 + #define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500 804 + #define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504 805 + #define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508 806 + #define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c 807 + #define ixPB1_RX_GLB_CTRL_REG0 0x2206000 808 + #define ixPB1_RX_GLB_CTRL_REG1 0x2206004 809 + #define ixPB1_RX_GLB_CTRL_REG2 0x2206008 810 + #define ixPB1_RX_GLB_CTRL_REG3 0x220600c 811 + #define ixPB1_RX_GLB_CTRL_REG4 0x2206010 812 + #define ixPB1_RX_GLB_CTRL_REG5 0x2206014 813 + #define ixPB1_RX_GLB_CTRL_REG6 0x2206018 814 + #define ixPB1_RX_GLB_CTRL_REG7 0x220601c 815 + #define ixPB1_RX_GLB_CTRL_REG8 0x2206020 816 + #define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028 817 + #define ixPB1_RX_GLB_OVRD_REG0 0x2206030 818 + #define ixPB1_RX_GLB_OVRD_REG1 0x2206034 819 + #define ixPB1_RX_LANE0_CTRL_REG0 0x2206440 820 + #define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448 821 + #define ixPB1_RX_LANE1_CTRL_REG0 0x2206480 822 + #define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488 823 + #define ixPB1_RX_LANE2_CTRL_REG0 0x2206500 824 + #define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508 825 + #define ixPB1_RX_LANE3_CTRL_REG0 0x2206600 826 + #define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608 827 + #define ixPB1_RX_LANE4_CTRL_REG0 0x2206800 828 + #define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848 829 + #define ixPB1_RX_LANE5_CTRL_REG0 0x2206880 830 + #define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888 831 + #define ixPB1_RX_LANE6_CTRL_REG0 0x2206900 832 + #define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908 833 + #define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00 834 + #define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08 835 + #define ixPB1_RX_LANE8_CTRL_REG0 0x2207440 836 + #define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448 837 + #define ixPB1_RX_LANE9_CTRL_REG0 0x2207480 838 + #define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488 839 + #define ixPB1_RX_LANE10_CTRL_REG0 0x2207500 840 + #define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508 841 + #define ixPB1_RX_LANE11_CTRL_REG0 0x2207600 842 + #define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608 843 + #define ixPB1_RX_LANE12_CTRL_REG0 0x2207840 844 + #define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848 845 + #define ixPB1_RX_LANE13_CTRL_REG0 0x2207880 846 + #define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888 847 + #define ixPB1_RX_LANE14_CTRL_REG0 0x2207900 848 + #define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908 849 + #define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00 850 + #define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08 851 + #define ixPB1_TX_GLB_CTRL_REG0 0x2208000 852 + #define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004 853 + #define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010 854 + #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014 855 + #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018 856 + #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c 857 + #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020 858 + #define ixPB1_TX_GLB_OVRD_REG0 0x2208030 859 + #define ixPB1_TX_GLB_OVRD_REG1 0x2208034 860 + #define ixPB1_TX_GLB_OVRD_REG2 0x2208038 861 + #define ixPB1_TX_GLB_OVRD_REG3 0x220803c 862 + #define ixPB1_TX_GLB_OVRD_REG4 0x2208040 863 + #define ixPB1_TX_LANE0_CTRL_REG0 0x2208440 864 + #define ixPB1_TX_LANE0_OVRD_REG0 0x2208444 865 + #define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448 866 + #define ixPB1_TX_LANE1_CTRL_REG0 0x2208480 867 + #define ixPB1_TX_LANE1_OVRD_REG0 0x2208484 868 + #define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488 869 + #define ixPB1_TX_LANE2_CTRL_REG0 0x2208500 870 + #define ixPB1_TX_LANE2_OVRD_REG0 0x2208504 871 + #define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508 872 + #define ixPB1_TX_LANE3_CTRL_REG0 0x2208600 873 + #define ixPB1_TX_LANE3_OVRD_REG0 0x2208604 874 + #define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608 875 + #define ixPB1_TX_LANE4_CTRL_REG0 0x2208840 876 + #define ixPB1_TX_LANE4_OVRD_REG0 0x2208844 877 + #define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848 878 + #define ixPB1_TX_LANE5_CTRL_REG0 0x2208880 879 + #define ixPB1_TX_LANE5_OVRD_REG0 0x2208884 880 + #define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888 881 + #define ixPB1_TX_LANE6_CTRL_REG0 0x2208900 882 + #define ixPB1_TX_LANE6_OVRD_REG0 0x2208904 883 + #define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908 884 + #define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00 885 + #define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04 886 + #define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08 887 + #define ixPB1_TX_LANE8_CTRL_REG0 0x2209440 888 + #define ixPB1_TX_LANE8_OVRD_REG0 0x2209444 889 + #define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448 890 + #define ixPB1_TX_LANE9_CTRL_REG0 0x2209480 891 + #define ixPB1_TX_LANE9_OVRD_REG0 0x2209484 892 + #define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488 893 + #define ixPB1_TX_LANE10_CTRL_REG0 0x2209500 894 + #define ixPB1_TX_LANE10_OVRD_REG0 0x2209504 895 + #define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508 896 + #define ixPB1_TX_LANE11_CTRL_REG0 0x2209600 897 + #define ixPB1_TX_LANE11_OVRD_REG0 0x2209604 898 + #define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608 899 + #define ixPB1_TX_LANE12_CTRL_REG0 0x2209840 900 + #define ixPB1_TX_LANE12_OVRD_REG0 0x2209844 901 + #define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848 902 + #define ixPB1_TX_LANE13_CTRL_REG0 0x2209880 903 + #define ixPB1_TX_LANE13_OVRD_REG0 0x2209884 904 + #define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888 905 + #define ixPB1_TX_LANE14_CTRL_REG0 0x2209900 906 + #define ixPB1_TX_LANE14_OVRD_REG0 0x2209904 907 + #define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908 908 + #define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00 909 + #define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04 910 + #define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08 911 + #define ixPB0_PIF_SCRATCH 0x1100001 912 + #define ixPB0_PIF_HW_DEBUG 0x1100002 913 + #define ixPB0_PIF_STRAP_0 0x1100003 914 + #define ixPB0_PIF_CTRL 0x1100004 915 + #define ixPB0_PIF_TX_CTRL 0x1100008 916 + #define ixPB0_PIF_TX_CTRL2 0x1100009 917 + #define ixPB0_PIF_RX_CTRL 0x110000a 918 + #define ixPB0_PIF_RX_CTRL2 0x110000b 919 + #define ixPB0_PIF_GLB_OVRD 0x110000c 920 + #define ixPB0_PIF_GLB_OVRD2 0x110000d 921 + #define ixPB0_PIF_BIF_CMD_STATUS 0x1100010 922 + #define ixPB0_PIF_CMD_BUS_CTRL 0x1100011 923 + #define ixPB0_PIF_CMD_BUS_GLB_OVRD 0x1100013 924 + #define ixPB0_PIF_LANE0_OVRD 0x1100014 925 + #define ixPB0_PIF_LANE0_OVRD2 0x1100015 926 + #define ixPB0_PIF_LANE1_OVRD 0x1100016 927 + #define ixPB0_PIF_LANE1_OVRD2 0x1100017 928 + #define ixPB0_PIF_LANE2_OVRD 0x1100018 929 + #define ixPB0_PIF_LANE2_OVRD2 0x1100019 930 + #define ixPB0_PIF_LANE3_OVRD 0x110001a 931 + #define ixPB0_PIF_LANE3_OVRD2 0x110001b 932 + #define ixPB0_PIF_LANE4_OVRD 0x110001c 933 + #define ixPB0_PIF_LANE4_OVRD2 0x110001d 934 + #define ixPB0_PIF_LANE5_OVRD 0x110001e 935 + #define ixPB0_PIF_LANE5_OVRD2 0x110001f 936 + #define ixPB0_PIF_LANE6_OVRD 0x1100020 937 + #define ixPB0_PIF_LANE6_OVRD2 0x1100021 938 + #define ixPB0_PIF_LANE7_OVRD 0x1100022 939 + #define ixPB0_PIF_LANE7_OVRD2 0x1100023 940 + #define ixPB1_PIF_SCRATCH 0x2100001 941 + #define ixPB1_PIF_HW_DEBUG 0x2100002 942 + #define ixPB1_PIF_STRAP_0 0x2100003 943 + #define ixPB1_PIF_CTRL 0x2100004 944 + #define ixPB1_PIF_TX_CTRL 0x2100008 945 + #define ixPB1_PIF_TX_CTRL2 0x2100009 946 + #define ixPB1_PIF_RX_CTRL 0x210000a 947 + #define ixPB1_PIF_RX_CTRL2 0x210000b 948 + #define ixPB1_PIF_GLB_OVRD 0x210000c 949 + #define ixPB1_PIF_GLB_OVRD2 0x210000d 950 + #define ixPB1_PIF_BIF_CMD_STATUS 0x2100010 951 + #define ixPB1_PIF_CMD_BUS_CTRL 0x2100011 952 + #define ixPB1_PIF_CMD_BUS_GLB_OVRD 0x2100013 953 + #define ixPB1_PIF_LANE0_OVRD 0x2100014 954 + #define ixPB1_PIF_LANE0_OVRD2 0x2100015 955 + #define ixPB1_PIF_LANE1_OVRD 0x2100016 956 + #define ixPB1_PIF_LANE1_OVRD2 0x2100017 957 + #define ixPB1_PIF_LANE2_OVRD 0x2100018 958 + #define ixPB1_PIF_LANE2_OVRD2 0x2100019 959 + #define ixPB1_PIF_LANE3_OVRD 0x210001a 960 + #define ixPB1_PIF_LANE3_OVRD2 0x210001b 961 + #define ixPB1_PIF_LANE4_OVRD 0x210001c 962 + #define ixPB1_PIF_LANE4_OVRD2 0x210001d 963 + #define ixPB1_PIF_LANE5_OVRD 0x210001e 964 + #define ixPB1_PIF_LANE5_OVRD2 0x210001f 965 + #define ixPB1_PIF_LANE6_OVRD 0x2100020 966 + #define ixPB1_PIF_LANE6_OVRD2 0x2100021 967 + #define ixPB1_PIF_LANE7_OVRD 0x2100022 968 + #define ixPB1_PIF_LANE7_OVRD2 0x2100023 969 + #define ixPCIEP_RESERVED 0x10010000 970 + #define ixPCIEP_SCRATCH 0x10010001 971 + #define ixPCIEP_HW_DEBUG 0x10010002 972 + #define ixPCIEP_PORT_CNTL 0x10010010 973 + #define ixPCIE_TX_CNTL 0x10010020 974 + #define ixPCIE_TX_REQUESTER_ID 0x10010021 975 + #define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022 976 + #define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023 977 + #define ixPCIE_TX_SEQ 0x10010024 978 + #define ixPCIE_TX_REPLAY 0x10010025 979 + #define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026 980 + #define ixPCIE_TX_CREDITS_ADVT_P 0x10010030 981 + #define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031 982 + #define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032 983 + #define ixPCIE_TX_CREDITS_INIT_P 0x10010033 984 + #define ixPCIE_TX_CREDITS_INIT_NP 0x10010034 985 + #define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035 986 + #define ixPCIE_TX_CREDITS_STATUS 0x10010036 987 + #define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037 988 + #define ixPCIE_P_PORT_LANE_STATUS 0x10010050 989 + #define ixPCIE_FC_P 0x10010060 990 + #define ixPCIE_FC_NP 0x10010061 991 + #define ixPCIE_FC_CPL 0x10010062 992 + #define ixPCIE_ERR_CNTL 0x1001006a 993 + #define ixPCIE_RX_CNTL 0x10010070 994 + #define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071 995 + #define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072 996 + #define ixPCIE_RX_CNTL3 0x10010074 997 + #define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080 998 + #define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081 999 + #define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082 1000 + #define ixPCIEP_ERROR_INJECT_PHYSICAL 0x10010083 1001 + #define ixPCIEP_ERROR_INJECT_TRANSACTION 0x10010084 1002 + #define ixPCIEP_SRIOV_PRIV_CTRL 0x10010085 1003 + #define ixPCIE_LC_CNTL 0x100100a0 1004 + #define ixPCIE_LC_CNTL2 0x100100b1 1005 + #define ixPCIE_LC_CNTL3 0x100100b5 1006 + #define ixPCIE_LC_CNTL4 0x100100b6 1007 + #define ixPCIE_LC_CNTL5 0x100100b7 1008 + #define ixPCIE_LC_CNTL6 0x100100bb 1009 + #define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2 1010 + #define ixPCIE_LC_TRAINING_CNTL 0x100100a1 1011 + #define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2 1012 + #define ixPCIE_LC_N_FTS_CNTL 0x100100a3 1013 + #define ixPCIE_LC_SPEED_CNTL 0x100100a4 1014 + #define ixPCIE_LC_CDR_CNTL 0x100100b3 1015 + #define ixPCIE_LC_LANE_CNTL 0x100100b4 1016 + #define ixPCIE_LC_FORCE_COEFF 0x100100b8 1017 + #define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9 1018 + #define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba 1019 + #define ixPCIE_LC_STATE0 0x100100a5 1020 + #define ixPCIE_LC_STATE1 0x100100a6 1021 + #define ixPCIE_LC_STATE2 0x100100a7 1022 + #define ixPCIE_LC_STATE3 0x100100a8 1023 + #define ixPCIE_LC_STATE4 0x100100a9 1024 + #define ixPCIE_LC_STATE5 0x100100aa 1025 + #define ixPCIEP_STRAP_LC 0x100100c0 1026 + #define ixPCIEP_STRAP_MISC 0x100100c1 1027 + #define ixPCIEP_BCH_ECC_CNTL 0x100100d0 1028 + #define ixPCIEP_HPGI_PRIVATE 0x100100d2 1029 + #define ixPCIEP_HPGI 0x100100da 1030 + #define mmPCIEMSIX_VECT0_ADDR_LO 0x6000 1031 + #define mmPCIEMSIX_VECT0_ADDR_HI 0x6001 1032 + #define mmPCIEMSIX_VECT0_MSG_DATA 0x6002 1033 + #define mmPCIEMSIX_VECT0_CONTROL 0x6003 1034 + #define mmPCIEMSIX_VECT1_ADDR_LO 0x6004 1035 + #define mmPCIEMSIX_VECT1_ADDR_HI 0x6005 1036 + #define mmPCIEMSIX_VECT1_MSG_DATA 0x6006 1037 + #define mmPCIEMSIX_VECT1_CONTROL 0x6007 1038 + #define mmPCIEMSIX_VECT2_ADDR_LO 0x6008 1039 + #define mmPCIEMSIX_VECT2_ADDR_HI 0x6009 1040 + #define mmPCIEMSIX_VECT2_MSG_DATA 0x600a 1041 + #define mmPCIEMSIX_VECT2_CONTROL 0x600b 1042 + #define mmPCIEMSIX_VECT3_ADDR_LO 0x600c 1043 + #define mmPCIEMSIX_VECT3_ADDR_HI 0x600d 1044 + #define mmPCIEMSIX_VECT3_MSG_DATA 0x600e 1045 + #define mmPCIEMSIX_VECT3_CONTROL 0x600f 1046 + #define mmPCIEMSIX_PBA 0x6200 1047 + #define mmBIF_RFE_SNOOP_REG 0x27 1048 + #define mmBIF_RFE_WARMRST_CNTL 0x1459 1049 + #define mmBIF_RFE_SOFTRST_CNTL 0x1441 1050 + #define mmBIF_RFE_IMPRST_CNTL 0x1458 1051 + #define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442 1052 + #define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443 1053 + #define mmBIF_PWDN_COMMAND 0x1444 1054 + #define mmBIF_PWDN_STATUS 0x1445 1055 + #define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446 1056 + #define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447 1057 + #define mmBIF_RFE_MST_SMBUS_CMDSTATUS 0x1448 1058 + #define mmBIF_RFE_MST_BX_CMDSTATUS 0x1449 1059 + #define mmBIF_RFE_MST_TMOUT_STATUS 0x144b 1060 + #define mmBIF_RFE_MMCFG_CNTL 0x144c 1061 + #define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455 1062 + #define mmBIF_IMPCTL_SMPLCNTL 0x1450 1063 + #define mmBIF_IMPCTL_RXCNTL 0x1451 1064 + #define mmBIF_IMPCTL_TXCNTL_pd 0x1452 1065 + #define mmBIF_IMPCTL_TXCNTL_pu 0x1453 1066 + #define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454 1067 + 1068 + #endif /* BIF_5_0_D_H */
+1198
drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h
··· 1 + /* 2 + * BIF_5_0 Register documentation 3 + * 4 + * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included 14 + * in all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + #ifndef BIF_5_0_ENUM_H 25 + #define BIF_5_0_ENUM_H 26 + 27 + typedef enum SurfaceEndian { 28 + ENDIAN_NONE = 0x0, 29 + ENDIAN_8IN16 = 0x1, 30 + ENDIAN_8IN32 = 0x2, 31 + ENDIAN_8IN64 = 0x3, 32 + } SurfaceEndian; 33 + typedef enum ArrayMode { 34 + ARRAY_LINEAR_GENERAL = 0x0, 35 + ARRAY_LINEAR_ALIGNED = 0x1, 36 + ARRAY_1D_TILED_THIN1 = 0x2, 37 + ARRAY_1D_TILED_THICK = 0x3, 38 + ARRAY_2D_TILED_THIN1 = 0x4, 39 + ARRAY_PRT_TILED_THIN1 = 0x5, 40 + ARRAY_PRT_2D_TILED_THIN1 = 0x6, 41 + ARRAY_2D_TILED_THICK = 0x7, 42 + ARRAY_2D_TILED_XTHICK = 0x8, 43 + ARRAY_PRT_TILED_THICK = 0x9, 44 + ARRAY_PRT_2D_TILED_THICK = 0xa, 45 + ARRAY_PRT_3D_TILED_THIN1 = 0xb, 46 + ARRAY_3D_TILED_THIN1 = 0xc, 47 + ARRAY_3D_TILED_THICK = 0xd, 48 + ARRAY_3D_TILED_XTHICK = 0xe, 49 + ARRAY_PRT_3D_TILED_THICK = 0xf, 50 + } ArrayMode; 51 + typedef enum PipeTiling { 52 + CONFIG_1_PIPE = 0x0, 53 + CONFIG_2_PIPE = 0x1, 54 + CONFIG_4_PIPE = 0x2, 55 + CONFIG_8_PIPE = 0x3, 56 + } PipeTiling; 57 + typedef enum BankTiling { 58 + CONFIG_4_BANK = 0x0, 59 + CONFIG_8_BANK = 0x1, 60 + } BankTiling; 61 + typedef enum GroupInterleave { 62 + CONFIG_256B_GROUP = 0x0, 63 + CONFIG_512B_GROUP = 0x1, 64 + } GroupInterleave; 65 + typedef enum RowTiling { 66 + CONFIG_1KB_ROW = 0x0, 67 + CONFIG_2KB_ROW = 0x1, 68 + CONFIG_4KB_ROW = 0x2, 69 + CONFIG_8KB_ROW = 0x3, 70 + CONFIG_1KB_ROW_OPT = 0x4, 71 + CONFIG_2KB_ROW_OPT = 0x5, 72 + CONFIG_4KB_ROW_OPT = 0x6, 73 + CONFIG_8KB_ROW_OPT = 0x7, 74 + } RowTiling; 75 + typedef enum BankSwapBytes { 76 + CONFIG_128B_SWAPS = 0x0, 77 + CONFIG_256B_SWAPS = 0x1, 78 + CONFIG_512B_SWAPS = 0x2, 79 + CONFIG_1KB_SWAPS = 0x3, 80 + } BankSwapBytes; 81 + typedef enum SampleSplitBytes { 82 + CONFIG_1KB_SPLIT = 0x0, 83 + CONFIG_2KB_SPLIT = 0x1, 84 + CONFIG_4KB_SPLIT = 0x2, 85 + CONFIG_8KB_SPLIT = 0x3, 86 + } SampleSplitBytes; 87 + typedef enum NumPipes { 88 + ADDR_CONFIG_1_PIPE = 0x0, 89 + ADDR_CONFIG_2_PIPE = 0x1, 90 + ADDR_CONFIG_4_PIPE = 0x2, 91 + ADDR_CONFIG_8_PIPE = 0x3, 92 + } NumPipes; 93 + typedef enum PipeInterleaveSize { 94 + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 95 + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 96 + } PipeInterleaveSize; 97 + typedef enum BankInterleaveSize { 98 + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 99 + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 100 + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 101 + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 102 + } BankInterleaveSize; 103 + typedef enum NumShaderEngines { 104 + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 105 + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 106 + } NumShaderEngines; 107 + typedef enum ShaderEngineTileSize { 108 + ADDR_CONFIG_SE_TILE_16 = 0x0, 109 + ADDR_CONFIG_SE_TILE_32 = 0x1, 110 + } ShaderEngineTileSize; 111 + typedef enum NumGPUs { 112 + ADDR_CONFIG_1_GPU = 0x0, 113 + ADDR_CONFIG_2_GPU = 0x1, 114 + ADDR_CONFIG_4_GPU = 0x2, 115 + } NumGPUs; 116 + typedef enum MultiGPUTileSize { 117 + ADDR_CONFIG_GPU_TILE_16 = 0x0, 118 + ADDR_CONFIG_GPU_TILE_32 = 0x1, 119 + ADDR_CONFIG_GPU_TILE_64 = 0x2, 120 + ADDR_CONFIG_GPU_TILE_128 = 0x3, 121 + } MultiGPUTileSize; 122 + typedef enum RowSize { 123 + ADDR_CONFIG_1KB_ROW = 0x0, 124 + ADDR_CONFIG_2KB_ROW = 0x1, 125 + ADDR_CONFIG_4KB_ROW = 0x2, 126 + } RowSize; 127 + typedef enum NumLowerPipes { 128 + ADDR_CONFIG_1_LOWER_PIPES = 0x0, 129 + ADDR_CONFIG_2_LOWER_PIPES = 0x1, 130 + } NumLowerPipes; 131 + typedef enum DebugBlockId { 132 + DBG_CLIENT_BLKID_RESERVED = 0x0, 133 + DBG_CLIENT_BLKID_dbg = 0x1, 134 + DBG_CLIENT_BLKID_scf2 = 0x2, 135 + DBG_CLIENT_BLKID_mcd5 = 0x3, 136 + DBG_CLIENT_BLKID_vmc = 0x4, 137 + DBG_CLIENT_BLKID_sx30 = 0x5, 138 + DBG_CLIENT_BLKID_mcd2 = 0x6, 139 + DBG_CLIENT_BLKID_bci1 = 0x7, 140 + DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, 141 + DBG_CLIENT_BLKID_mcc0 = 0x9, 142 + DBG_CLIENT_BLKID_uvdf_0 = 0xa, 143 + DBG_CLIENT_BLKID_uvdf_1 = 0xb, 144 + DBG_CLIENT_BLKID_uvdf_2 = 0xc, 145 + DBG_CLIENT_BLKID_uvdi_0 = 0xd, 146 + DBG_CLIENT_BLKID_bci0 = 0xe, 147 + DBG_CLIENT_BLKID_vcec0_0 = 0xf, 148 + DBG_CLIENT_BLKID_cb100 = 0x10, 149 + DBG_CLIENT_BLKID_cb001 = 0x11, 150 + DBG_CLIENT_BLKID_mcd4 = 0x12, 151 + DBG_CLIENT_BLKID_tmonw00 = 0x13, 152 + DBG_CLIENT_BLKID_cb101 = 0x14, 153 + DBG_CLIENT_BLKID_sx10 = 0x15, 154 + DBG_CLIENT_BLKID_cb301 = 0x16, 155 + DBG_CLIENT_BLKID_tmonw01 = 0x17, 156 + DBG_CLIENT_BLKID_vcea0_0 = 0x18, 157 + DBG_CLIENT_BLKID_vcea0_1 = 0x19, 158 + DBG_CLIENT_BLKID_vcea0_2 = 0x1a, 159 + DBG_CLIENT_BLKID_vcea0_3 = 0x1b, 160 + DBG_CLIENT_BLKID_scf1 = 0x1c, 161 + DBG_CLIENT_BLKID_sx20 = 0x1d, 162 + DBG_CLIENT_BLKID_spim1 = 0x1e, 163 + DBG_CLIENT_BLKID_pa10 = 0x1f, 164 + DBG_CLIENT_BLKID_pa00 = 0x20, 165 + DBG_CLIENT_BLKID_gmcon = 0x21, 166 + DBG_CLIENT_BLKID_mcb = 0x22, 167 + DBG_CLIENT_BLKID_vgt0 = 0x23, 168 + DBG_CLIENT_BLKID_pc0 = 0x24, 169 + DBG_CLIENT_BLKID_bci2 = 0x25, 170 + DBG_CLIENT_BLKID_uvdb_0 = 0x26, 171 + DBG_CLIENT_BLKID_spim3 = 0x27, 172 + DBG_CLIENT_BLKID_cpc_0 = 0x28, 173 + DBG_CLIENT_BLKID_cpc_1 = 0x29, 174 + DBG_CLIENT_BLKID_uvdm_0 = 0x2a, 175 + DBG_CLIENT_BLKID_uvdm_1 = 0x2b, 176 + DBG_CLIENT_BLKID_uvdm_2 = 0x2c, 177 + DBG_CLIENT_BLKID_uvdm_3 = 0x2d, 178 + DBG_CLIENT_BLKID_cb000 = 0x2e, 179 + DBG_CLIENT_BLKID_spim0 = 0x2f, 180 + DBG_CLIENT_BLKID_mcc2 = 0x30, 181 + DBG_CLIENT_BLKID_ds0 = 0x31, 182 + DBG_CLIENT_BLKID_srbm = 0x32, 183 + DBG_CLIENT_BLKID_ih = 0x33, 184 + DBG_CLIENT_BLKID_sem = 0x34, 185 + DBG_CLIENT_BLKID_sdma_0 = 0x35, 186 + DBG_CLIENT_BLKID_sdma_1 = 0x36, 187 + DBG_CLIENT_BLKID_hdp = 0x37, 188 + DBG_CLIENT_BLKID_acp_0 = 0x38, 189 + DBG_CLIENT_BLKID_acp_1 = 0x39, 190 + DBG_CLIENT_BLKID_cb200 = 0x3a, 191 + DBG_CLIENT_BLKID_scf3 = 0x3b, 192 + DBG_CLIENT_BLKID_vceb1_0 = 0x3c, 193 + DBG_CLIENT_BLKID_vcea1_0 = 0x3d, 194 + DBG_CLIENT_BLKID_vcea1_1 = 0x3e, 195 + DBG_CLIENT_BLKID_vcea1_2 = 0x3f, 196 + DBG_CLIENT_BLKID_vcea1_3 = 0x40, 197 + DBG_CLIENT_BLKID_bci3 = 0x41, 198 + DBG_CLIENT_BLKID_mcd0 = 0x42, 199 + DBG_CLIENT_BLKID_pa11 = 0x43, 200 + DBG_CLIENT_BLKID_pa01 = 0x44, 201 + DBG_CLIENT_BLKID_cb201 = 0x45, 202 + DBG_CLIENT_BLKID_spim2 = 0x46, 203 + DBG_CLIENT_BLKID_vgt2 = 0x47, 204 + DBG_CLIENT_BLKID_pc2 = 0x48, 205 + DBG_CLIENT_BLKID_smu_0 = 0x49, 206 + DBG_CLIENT_BLKID_smu_1 = 0x4a, 207 + DBG_CLIENT_BLKID_smu_2 = 0x4b, 208 + DBG_CLIENT_BLKID_cb1 = 0x4c, 209 + DBG_CLIENT_BLKID_ia0 = 0x4d, 210 + DBG_CLIENT_BLKID_wd = 0x4e, 211 + DBG_CLIENT_BLKID_ia1 = 0x4f, 212 + DBG_CLIENT_BLKID_vcec1_0 = 0x50, 213 + DBG_CLIENT_BLKID_scf0 = 0x51, 214 + DBG_CLIENT_BLKID_vgt1 = 0x52, 215 + DBG_CLIENT_BLKID_pc1 = 0x53, 216 + DBG_CLIENT_BLKID_cb0 = 0x54, 217 + DBG_CLIENT_BLKID_gdc_one_0 = 0x55, 218 + DBG_CLIENT_BLKID_gdc_one_1 = 0x56, 219 + DBG_CLIENT_BLKID_gdc_one_2 = 0x57, 220 + DBG_CLIENT_BLKID_gdc_one_3 = 0x58, 221 + DBG_CLIENT_BLKID_gdc_one_4 = 0x59, 222 + DBG_CLIENT_BLKID_gdc_one_5 = 0x5a, 223 + DBG_CLIENT_BLKID_gdc_one_6 = 0x5b, 224 + DBG_CLIENT_BLKID_gdc_one_7 = 0x5c, 225 + DBG_CLIENT_BLKID_gdc_one_8 = 0x5d, 226 + DBG_CLIENT_BLKID_gdc_one_9 = 0x5e, 227 + DBG_CLIENT_BLKID_gdc_one_10 = 0x5f, 228 + DBG_CLIENT_BLKID_gdc_one_11 = 0x60, 229 + DBG_CLIENT_BLKID_gdc_one_12 = 0x61, 230 + DBG_CLIENT_BLKID_gdc_one_13 = 0x62, 231 + DBG_CLIENT_BLKID_gdc_one_14 = 0x63, 232 + DBG_CLIENT_BLKID_gdc_one_15 = 0x64, 233 + DBG_CLIENT_BLKID_gdc_one_16 = 0x65, 234 + DBG_CLIENT_BLKID_gdc_one_17 = 0x66, 235 + DBG_CLIENT_BLKID_gdc_one_18 = 0x67, 236 + DBG_CLIENT_BLKID_gdc_one_19 = 0x68, 237 + DBG_CLIENT_BLKID_gdc_one_20 = 0x69, 238 + DBG_CLIENT_BLKID_gdc_one_21 = 0x6a, 239 + DBG_CLIENT_BLKID_gdc_one_22 = 0x6b, 240 + DBG_CLIENT_BLKID_gdc_one_23 = 0x6c, 241 + DBG_CLIENT_BLKID_gdc_one_24 = 0x6d, 242 + DBG_CLIENT_BLKID_gdc_one_25 = 0x6e, 243 + DBG_CLIENT_BLKID_gdc_one_26 = 0x6f, 244 + DBG_CLIENT_BLKID_gdc_one_27 = 0x70, 245 + DBG_CLIENT_BLKID_gdc_one_28 = 0x71, 246 + DBG_CLIENT_BLKID_gdc_one_29 = 0x72, 247 + DBG_CLIENT_BLKID_gdc_one_30 = 0x73, 248 + DBG_CLIENT_BLKID_gdc_one_31 = 0x74, 249 + DBG_CLIENT_BLKID_gdc_one_32 = 0x75, 250 + DBG_CLIENT_BLKID_gdc_one_33 = 0x76, 251 + DBG_CLIENT_BLKID_gdc_one_34 = 0x77, 252 + DBG_CLIENT_BLKID_gdc_one_35 = 0x78, 253 + DBG_CLIENT_BLKID_vceb0_0 = 0x79, 254 + DBG_CLIENT_BLKID_vgt3 = 0x7a, 255 + DBG_CLIENT_BLKID_pc3 = 0x7b, 256 + DBG_CLIENT_BLKID_mcd3 = 0x7c, 257 + DBG_CLIENT_BLKID_uvdu_0 = 0x7d, 258 + DBG_CLIENT_BLKID_uvdu_1 = 0x7e, 259 + DBG_CLIENT_BLKID_uvdu_2 = 0x7f, 260 + DBG_CLIENT_BLKID_uvdu_3 = 0x80, 261 + DBG_CLIENT_BLKID_uvdu_4 = 0x81, 262 + DBG_CLIENT_BLKID_uvdu_5 = 0x82, 263 + DBG_CLIENT_BLKID_uvdu_6 = 0x83, 264 + DBG_CLIENT_BLKID_cb300 = 0x84, 265 + DBG_CLIENT_BLKID_mcd1 = 0x85, 266 + DBG_CLIENT_BLKID_sx00 = 0x86, 267 + DBG_CLIENT_BLKID_uvdc_0 = 0x87, 268 + DBG_CLIENT_BLKID_uvdc_1 = 0x88, 269 + DBG_CLIENT_BLKID_mcc3 = 0x89, 270 + DBG_CLIENT_BLKID_cpg_0 = 0x8a, 271 + DBG_CLIENT_BLKID_cpg_1 = 0x8b, 272 + DBG_CLIENT_BLKID_gck = 0x8c, 273 + DBG_CLIENT_BLKID_mcc1 = 0x8d, 274 + DBG_CLIENT_BLKID_cpf_0 = 0x8e, 275 + DBG_CLIENT_BLKID_cpf_1 = 0x8f, 276 + DBG_CLIENT_BLKID_rlc = 0x90, 277 + DBG_CLIENT_BLKID_grbm = 0x91, 278 + DBG_CLIENT_BLKID_sammsp = 0x92, 279 + DBG_CLIENT_BLKID_dci_pg = 0x93, 280 + DBG_CLIENT_BLKID_dci_0 = 0x94, 281 + DBG_CLIENT_BLKID_dccg0_0 = 0x95, 282 + DBG_CLIENT_BLKID_dccg0_1 = 0x96, 283 + DBG_CLIENT_BLKID_dcfe01_0 = 0x97, 284 + DBG_CLIENT_BLKID_dcfe02_0 = 0x98, 285 + DBG_CLIENT_BLKID_dcfe03_0 = 0x99, 286 + DBG_CLIENT_BLKID_dcfe04_0 = 0x9a, 287 + DBG_CLIENT_BLKID_dcfe05_0 = 0x9b, 288 + DBG_CLIENT_BLKID_dcfe06_0 = 0x9c, 289 + DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d, 290 + } DebugBlockId; 291 + typedef enum DebugBlockId_OLD { 292 + DBG_BLOCK_ID_RESERVED = 0x0, 293 + DBG_BLOCK_ID_DBG = 0x1, 294 + DBG_BLOCK_ID_VMC = 0x2, 295 + DBG_BLOCK_ID_PDMA = 0x3, 296 + DBG_BLOCK_ID_CG = 0x4, 297 + DBG_BLOCK_ID_SRBM = 0x5, 298 + DBG_BLOCK_ID_GRBM = 0x6, 299 + DBG_BLOCK_ID_RLC = 0x7, 300 + DBG_BLOCK_ID_CSC = 0x8, 301 + DBG_BLOCK_ID_SEM = 0x9, 302 + DBG_BLOCK_ID_IH = 0xa, 303 + DBG_BLOCK_ID_SC = 0xb, 304 + DBG_BLOCK_ID_SQ = 0xc, 305 + DBG_BLOCK_ID_AVP = 0xd, 306 + DBG_BLOCK_ID_GMCON = 0xe, 307 + DBG_BLOCK_ID_SMU = 0xf, 308 + DBG_BLOCK_ID_DMA0 = 0x10, 309 + DBG_BLOCK_ID_DMA1 = 0x11, 310 + DBG_BLOCK_ID_SPIM = 0x12, 311 + DBG_BLOCK_ID_GDS = 0x13, 312 + DBG_BLOCK_ID_SPIS = 0x14, 313 + DBG_BLOCK_ID_UNUSED0 = 0x15, 314 + DBG_BLOCK_ID_PA0 = 0x16, 315 + DBG_BLOCK_ID_PA1 = 0x17, 316 + DBG_BLOCK_ID_CP0 = 0x18, 317 + DBG_BLOCK_ID_CP1 = 0x19, 318 + DBG_BLOCK_ID_CP2 = 0x1a, 319 + DBG_BLOCK_ID_UNUSED1 = 0x1b, 320 + DBG_BLOCK_ID_UVDU = 0x1c, 321 + DBG_BLOCK_ID_UVDM = 0x1d, 322 + DBG_BLOCK_ID_VCE = 0x1e, 323 + DBG_BLOCK_ID_UNUSED2 = 0x1f, 324 + DBG_BLOCK_ID_VGT0 = 0x20, 325 + DBG_BLOCK_ID_VGT1 = 0x21, 326 + DBG_BLOCK_ID_IA = 0x22, 327 + DBG_BLOCK_ID_UNUSED3 = 0x23, 328 + DBG_BLOCK_ID_SCT0 = 0x24, 329 + DBG_BLOCK_ID_SCT1 = 0x25, 330 + DBG_BLOCK_ID_SPM0 = 0x26, 331 + DBG_BLOCK_ID_SPM1 = 0x27, 332 + DBG_BLOCK_ID_TCAA = 0x28, 333 + DBG_BLOCK_ID_TCAB = 0x29, 334 + DBG_BLOCK_ID_TCCA = 0x2a, 335 + DBG_BLOCK_ID_TCCB = 0x2b, 336 + DBG_BLOCK_ID_MCC0 = 0x2c, 337 + DBG_BLOCK_ID_MCC1 = 0x2d, 338 + DBG_BLOCK_ID_MCC2 = 0x2e, 339 + DBG_BLOCK_ID_MCC3 = 0x2f, 340 + DBG_BLOCK_ID_SX0 = 0x30, 341 + DBG_BLOCK_ID_SX1 = 0x31, 342 + DBG_BLOCK_ID_SX2 = 0x32, 343 + DBG_BLOCK_ID_SX3 = 0x33, 344 + DBG_BLOCK_ID_UNUSED4 = 0x34, 345 + DBG_BLOCK_ID_UNUSED5 = 0x35, 346 + DBG_BLOCK_ID_UNUSED6 = 0x36, 347 + DBG_BLOCK_ID_UNUSED7 = 0x37, 348 + DBG_BLOCK_ID_PC0 = 0x38, 349 + DBG_BLOCK_ID_PC1 = 0x39, 350 + DBG_BLOCK_ID_UNUSED8 = 0x3a, 351 + DBG_BLOCK_ID_UNUSED9 = 0x3b, 352 + DBG_BLOCK_ID_UNUSED10 = 0x3c, 353 + DBG_BLOCK_ID_UNUSED11 = 0x3d, 354 + DBG_BLOCK_ID_MCB = 0x3e, 355 + DBG_BLOCK_ID_UNUSED12 = 0x3f, 356 + DBG_BLOCK_ID_SCB0 = 0x40, 357 + DBG_BLOCK_ID_SCB1 = 0x41, 358 + DBG_BLOCK_ID_UNUSED13 = 0x42, 359 + DBG_BLOCK_ID_UNUSED14 = 0x43, 360 + DBG_BLOCK_ID_SCF0 = 0x44, 361 + DBG_BLOCK_ID_SCF1 = 0x45, 362 + DBG_BLOCK_ID_UNUSED15 = 0x46, 363 + DBG_BLOCK_ID_UNUSED16 = 0x47, 364 + DBG_BLOCK_ID_BCI0 = 0x48, 365 + DBG_BLOCK_ID_BCI1 = 0x49, 366 + DBG_BLOCK_ID_BCI2 = 0x4a, 367 + DBG_BLOCK_ID_BCI3 = 0x4b, 368 + DBG_BLOCK_ID_UNUSED17 = 0x4c, 369 + DBG_BLOCK_ID_UNUSED18 = 0x4d, 370 + DBG_BLOCK_ID_UNUSED19 = 0x4e, 371 + DBG_BLOCK_ID_UNUSED20 = 0x4f, 372 + DBG_BLOCK_ID_CB00 = 0x50, 373 + DBG_BLOCK_ID_CB01 = 0x51, 374 + DBG_BLOCK_ID_CB02 = 0x52, 375 + DBG_BLOCK_ID_CB03 = 0x53, 376 + DBG_BLOCK_ID_CB04 = 0x54, 377 + DBG_BLOCK_ID_UNUSED21 = 0x55, 378 + DBG_BLOCK_ID_UNUSED22 = 0x56, 379 + DBG_BLOCK_ID_UNUSED23 = 0x57, 380 + DBG_BLOCK_ID_CB10 = 0x58, 381 + DBG_BLOCK_ID_CB11 = 0x59, 382 + DBG_BLOCK_ID_CB12 = 0x5a, 383 + DBG_BLOCK_ID_CB13 = 0x5b, 384 + DBG_BLOCK_ID_CB14 = 0x5c, 385 + DBG_BLOCK_ID_UNUSED24 = 0x5d, 386 + DBG_BLOCK_ID_UNUSED25 = 0x5e, 387 + DBG_BLOCK_ID_UNUSED26 = 0x5f, 388 + DBG_BLOCK_ID_TCP0 = 0x60, 389 + DBG_BLOCK_ID_TCP1 = 0x61, 390 + DBG_BLOCK_ID_TCP2 = 0x62, 391 + DBG_BLOCK_ID_TCP3 = 0x63, 392 + DBG_BLOCK_ID_TCP4 = 0x64, 393 + DBG_BLOCK_ID_TCP5 = 0x65, 394 + DBG_BLOCK_ID_TCP6 = 0x66, 395 + DBG_BLOCK_ID_TCP7 = 0x67, 396 + DBG_BLOCK_ID_TCP8 = 0x68, 397 + DBG_BLOCK_ID_TCP9 = 0x69, 398 + DBG_BLOCK_ID_TCP10 = 0x6a, 399 + DBG_BLOCK_ID_TCP11 = 0x6b, 400 + DBG_BLOCK_ID_TCP12 = 0x6c, 401 + DBG_BLOCK_ID_TCP13 = 0x6d, 402 + DBG_BLOCK_ID_TCP14 = 0x6e, 403 + DBG_BLOCK_ID_TCP15 = 0x6f, 404 + DBG_BLOCK_ID_TCP16 = 0x70, 405 + DBG_BLOCK_ID_TCP17 = 0x71, 406 + DBG_BLOCK_ID_TCP18 = 0x72, 407 + DBG_BLOCK_ID_TCP19 = 0x73, 408 + DBG_BLOCK_ID_TCP20 = 0x74, 409 + DBG_BLOCK_ID_TCP21 = 0x75, 410 + DBG_BLOCK_ID_TCP22 = 0x76, 411 + DBG_BLOCK_ID_TCP23 = 0x77, 412 + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, 413 + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, 414 + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, 415 + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, 416 + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, 417 + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, 418 + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, 419 + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, 420 + DBG_BLOCK_ID_DB00 = 0x80, 421 + DBG_BLOCK_ID_DB01 = 0x81, 422 + DBG_BLOCK_ID_DB02 = 0x82, 423 + DBG_BLOCK_ID_DB03 = 0x83, 424 + DBG_BLOCK_ID_DB04 = 0x84, 425 + DBG_BLOCK_ID_UNUSED27 = 0x85, 426 + DBG_BLOCK_ID_UNUSED28 = 0x86, 427 + DBG_BLOCK_ID_UNUSED29 = 0x87, 428 + DBG_BLOCK_ID_DB10 = 0x88, 429 + DBG_BLOCK_ID_DB11 = 0x89, 430 + DBG_BLOCK_ID_DB12 = 0x8a, 431 + DBG_BLOCK_ID_DB13 = 0x8b, 432 + DBG_BLOCK_ID_DB14 = 0x8c, 433 + DBG_BLOCK_ID_UNUSED30 = 0x8d, 434 + DBG_BLOCK_ID_UNUSED31 = 0x8e, 435 + DBG_BLOCK_ID_UNUSED32 = 0x8f, 436 + DBG_BLOCK_ID_TCC0 = 0x90, 437 + DBG_BLOCK_ID_TCC1 = 0x91, 438 + DBG_BLOCK_ID_TCC2 = 0x92, 439 + DBG_BLOCK_ID_TCC3 = 0x93, 440 + DBG_BLOCK_ID_TCC4 = 0x94, 441 + DBG_BLOCK_ID_TCC5 = 0x95, 442 + DBG_BLOCK_ID_TCC6 = 0x96, 443 + DBG_BLOCK_ID_TCC7 = 0x97, 444 + DBG_BLOCK_ID_SPS00 = 0x98, 445 + DBG_BLOCK_ID_SPS01 = 0x99, 446 + DBG_BLOCK_ID_SPS02 = 0x9a, 447 + DBG_BLOCK_ID_SPS10 = 0x9b, 448 + DBG_BLOCK_ID_SPS11 = 0x9c, 449 + DBG_BLOCK_ID_SPS12 = 0x9d, 450 + DBG_BLOCK_ID_UNUSED33 = 0x9e, 451 + DBG_BLOCK_ID_UNUSED34 = 0x9f, 452 + DBG_BLOCK_ID_TA00 = 0xa0, 453 + DBG_BLOCK_ID_TA01 = 0xa1, 454 + DBG_BLOCK_ID_TA02 = 0xa2, 455 + DBG_BLOCK_ID_TA03 = 0xa3, 456 + DBG_BLOCK_ID_TA04 = 0xa4, 457 + DBG_BLOCK_ID_TA05 = 0xa5, 458 + DBG_BLOCK_ID_TA06 = 0xa6, 459 + DBG_BLOCK_ID_TA07 = 0xa7, 460 + DBG_BLOCK_ID_TA08 = 0xa8, 461 + DBG_BLOCK_ID_TA09 = 0xa9, 462 + DBG_BLOCK_ID_TA0A = 0xaa, 463 + DBG_BLOCK_ID_TA0B = 0xab, 464 + DBG_BLOCK_ID_UNUSED35 = 0xac, 465 + DBG_BLOCK_ID_UNUSED36 = 0xad, 466 + DBG_BLOCK_ID_UNUSED37 = 0xae, 467 + DBG_BLOCK_ID_UNUSED38 = 0xaf, 468 + DBG_BLOCK_ID_TA10 = 0xb0, 469 + DBG_BLOCK_ID_TA11 = 0xb1, 470 + DBG_BLOCK_ID_TA12 = 0xb2, 471 + DBG_BLOCK_ID_TA13 = 0xb3, 472 + DBG_BLOCK_ID_TA14 = 0xb4, 473 + DBG_BLOCK_ID_TA15 = 0xb5, 474 + DBG_BLOCK_ID_TA16 = 0xb6, 475 + DBG_BLOCK_ID_TA17 = 0xb7, 476 + DBG_BLOCK_ID_TA18 = 0xb8, 477 + DBG_BLOCK_ID_TA19 = 0xb9, 478 + DBG_BLOCK_ID_TA1A = 0xba, 479 + DBG_BLOCK_ID_TA1B = 0xbb, 480 + DBG_BLOCK_ID_UNUSED39 = 0xbc, 481 + DBG_BLOCK_ID_UNUSED40 = 0xbd, 482 + DBG_BLOCK_ID_UNUSED41 = 0xbe, 483 + DBG_BLOCK_ID_UNUSED42 = 0xbf, 484 + DBG_BLOCK_ID_TD00 = 0xc0, 485 + DBG_BLOCK_ID_TD01 = 0xc1, 486 + DBG_BLOCK_ID_TD02 = 0xc2, 487 + DBG_BLOCK_ID_TD03 = 0xc3, 488 + DBG_BLOCK_ID_TD04 = 0xc4, 489 + DBG_BLOCK_ID_TD05 = 0xc5, 490 + DBG_BLOCK_ID_TD06 = 0xc6, 491 + DBG_BLOCK_ID_TD07 = 0xc7, 492 + DBG_BLOCK_ID_TD08 = 0xc8, 493 + DBG_BLOCK_ID_TD09 = 0xc9, 494 + DBG_BLOCK_ID_TD0A = 0xca, 495 + DBG_BLOCK_ID_TD0B = 0xcb, 496 + DBG_BLOCK_ID_UNUSED43 = 0xcc, 497 + DBG_BLOCK_ID_UNUSED44 = 0xcd, 498 + DBG_BLOCK_ID_UNUSED45 = 0xce, 499 + DBG_BLOCK_ID_UNUSED46 = 0xcf, 500 + DBG_BLOCK_ID_TD10 = 0xd0, 501 + DBG_BLOCK_ID_TD11 = 0xd1, 502 + DBG_BLOCK_ID_TD12 = 0xd2, 503 + DBG_BLOCK_ID_TD13 = 0xd3, 504 + DBG_BLOCK_ID_TD14 = 0xd4, 505 + DBG_BLOCK_ID_TD15 = 0xd5, 506 + DBG_BLOCK_ID_TD16 = 0xd6, 507 + DBG_BLOCK_ID_TD17 = 0xd7, 508 + DBG_BLOCK_ID_TD18 = 0xd8, 509 + DBG_BLOCK_ID_TD19 = 0xd9, 510 + DBG_BLOCK_ID_TD1A = 0xda, 511 + DBG_BLOCK_ID_TD1B = 0xdb, 512 + DBG_BLOCK_ID_UNUSED47 = 0xdc, 513 + DBG_BLOCK_ID_UNUSED48 = 0xdd, 514 + DBG_BLOCK_ID_UNUSED49 = 0xde, 515 + DBG_BLOCK_ID_UNUSED50 = 0xdf, 516 + DBG_BLOCK_ID_MCD0 = 0xe0, 517 + DBG_BLOCK_ID_MCD1 = 0xe1, 518 + DBG_BLOCK_ID_MCD2 = 0xe2, 519 + DBG_BLOCK_ID_MCD3 = 0xe3, 520 + DBG_BLOCK_ID_MCD4 = 0xe4, 521 + DBG_BLOCK_ID_MCD5 = 0xe5, 522 + DBG_BLOCK_ID_UNUSED51 = 0xe6, 523 + DBG_BLOCK_ID_UNUSED52 = 0xe7, 524 + } DebugBlockId_OLD; 525 + typedef enum DebugBlockId_BY2 { 526 + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 527 + DBG_BLOCK_ID_VMC_BY2 = 0x1, 528 + DBG_BLOCK_ID_CG_BY2 = 0x2, 529 + DBG_BLOCK_ID_GRBM_BY2 = 0x3, 530 + DBG_BLOCK_ID_CSC_BY2 = 0x4, 531 + DBG_BLOCK_ID_IH_BY2 = 0x5, 532 + DBG_BLOCK_ID_SQ_BY2 = 0x6, 533 + DBG_BLOCK_ID_GMCON_BY2 = 0x7, 534 + DBG_BLOCK_ID_DMA0_BY2 = 0x8, 535 + DBG_BLOCK_ID_SPIM_BY2 = 0x9, 536 + DBG_BLOCK_ID_SPIS_BY2 = 0xa, 537 + DBG_BLOCK_ID_PA0_BY2 = 0xb, 538 + DBG_BLOCK_ID_CP0_BY2 = 0xc, 539 + DBG_BLOCK_ID_CP2_BY2 = 0xd, 540 + DBG_BLOCK_ID_UVDU_BY2 = 0xe, 541 + DBG_BLOCK_ID_VCE_BY2 = 0xf, 542 + DBG_BLOCK_ID_VGT0_BY2 = 0x10, 543 + DBG_BLOCK_ID_IA_BY2 = 0x11, 544 + DBG_BLOCK_ID_SCT0_BY2 = 0x12, 545 + DBG_BLOCK_ID_SPM0_BY2 = 0x13, 546 + DBG_BLOCK_ID_TCAA_BY2 = 0x14, 547 + DBG_BLOCK_ID_TCCA_BY2 = 0x15, 548 + DBG_BLOCK_ID_MCC0_BY2 = 0x16, 549 + DBG_BLOCK_ID_MCC2_BY2 = 0x17, 550 + DBG_BLOCK_ID_SX0_BY2 = 0x18, 551 + DBG_BLOCK_ID_SX2_BY2 = 0x19, 552 + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, 553 + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, 554 + DBG_BLOCK_ID_PC0_BY2 = 0x1c, 555 + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 556 + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, 557 + DBG_BLOCK_ID_MCB_BY2 = 0x1f, 558 + DBG_BLOCK_ID_SCB0_BY2 = 0x20, 559 + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, 560 + DBG_BLOCK_ID_SCF0_BY2 = 0x22, 561 + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, 562 + DBG_BLOCK_ID_BCI0_BY2 = 0x24, 563 + DBG_BLOCK_ID_BCI2_BY2 = 0x25, 564 + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, 565 + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, 566 + DBG_BLOCK_ID_CB00_BY2 = 0x28, 567 + DBG_BLOCK_ID_CB02_BY2 = 0x29, 568 + DBG_BLOCK_ID_CB04_BY2 = 0x2a, 569 + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, 570 + DBG_BLOCK_ID_CB10_BY2 = 0x2c, 571 + DBG_BLOCK_ID_CB12_BY2 = 0x2d, 572 + DBG_BLOCK_ID_CB14_BY2 = 0x2e, 573 + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, 574 + DBG_BLOCK_ID_TCP0_BY2 = 0x30, 575 + DBG_BLOCK_ID_TCP2_BY2 = 0x31, 576 + DBG_BLOCK_ID_TCP4_BY2 = 0x32, 577 + DBG_BLOCK_ID_TCP6_BY2 = 0x33, 578 + DBG_BLOCK_ID_TCP8_BY2 = 0x34, 579 + DBG_BLOCK_ID_TCP10_BY2 = 0x35, 580 + DBG_BLOCK_ID_TCP12_BY2 = 0x36, 581 + DBG_BLOCK_ID_TCP14_BY2 = 0x37, 582 + DBG_BLOCK_ID_TCP16_BY2 = 0x38, 583 + DBG_BLOCK_ID_TCP18_BY2 = 0x39, 584 + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 585 + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 586 + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 587 + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 588 + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 589 + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 590 + DBG_BLOCK_ID_DB00_BY2 = 0x40, 591 + DBG_BLOCK_ID_DB02_BY2 = 0x41, 592 + DBG_BLOCK_ID_DB04_BY2 = 0x42, 593 + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, 594 + DBG_BLOCK_ID_DB10_BY2 = 0x44, 595 + DBG_BLOCK_ID_DB12_BY2 = 0x45, 596 + DBG_BLOCK_ID_DB14_BY2 = 0x46, 597 + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, 598 + DBG_BLOCK_ID_TCC0_BY2 = 0x48, 599 + DBG_BLOCK_ID_TCC2_BY2 = 0x49, 600 + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, 601 + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, 602 + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, 603 + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, 604 + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, 605 + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, 606 + DBG_BLOCK_ID_TA00_BY2 = 0x50, 607 + DBG_BLOCK_ID_TA02_BY2 = 0x51, 608 + DBG_BLOCK_ID_TA04_BY2 = 0x52, 609 + DBG_BLOCK_ID_TA06_BY2 = 0x53, 610 + DBG_BLOCK_ID_TA08_BY2 = 0x54, 611 + DBG_BLOCK_ID_TA0A_BY2 = 0x55, 612 + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, 613 + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, 614 + DBG_BLOCK_ID_TA10_BY2 = 0x58, 615 + DBG_BLOCK_ID_TA12_BY2 = 0x59, 616 + DBG_BLOCK_ID_TA14_BY2 = 0x5a, 617 + DBG_BLOCK_ID_TA16_BY2 = 0x5b, 618 + DBG_BLOCK_ID_TA18_BY2 = 0x5c, 619 + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, 620 + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, 621 + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, 622 + DBG_BLOCK_ID_TD00_BY2 = 0x60, 623 + DBG_BLOCK_ID_TD02_BY2 = 0x61, 624 + DBG_BLOCK_ID_TD04_BY2 = 0x62, 625 + DBG_BLOCK_ID_TD06_BY2 = 0x63, 626 + DBG_BLOCK_ID_TD08_BY2 = 0x64, 627 + DBG_BLOCK_ID_TD0A_BY2 = 0x65, 628 + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, 629 + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, 630 + DBG_BLOCK_ID_TD10_BY2 = 0x68, 631 + DBG_BLOCK_ID_TD12_BY2 = 0x69, 632 + DBG_BLOCK_ID_TD14_BY2 = 0x6a, 633 + DBG_BLOCK_ID_TD16_BY2 = 0x6b, 634 + DBG_BLOCK_ID_TD18_BY2 = 0x6c, 635 + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, 636 + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, 637 + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, 638 + DBG_BLOCK_ID_MCD0_BY2 = 0x70, 639 + DBG_BLOCK_ID_MCD2_BY2 = 0x71, 640 + DBG_BLOCK_ID_MCD4_BY2 = 0x72, 641 + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, 642 + } DebugBlockId_BY2; 643 + typedef enum DebugBlockId_BY4 { 644 + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 645 + DBG_BLOCK_ID_CG_BY4 = 0x1, 646 + DBG_BLOCK_ID_CSC_BY4 = 0x2, 647 + DBG_BLOCK_ID_SQ_BY4 = 0x3, 648 + DBG_BLOCK_ID_DMA0_BY4 = 0x4, 649 + DBG_BLOCK_ID_SPIS_BY4 = 0x5, 650 + DBG_BLOCK_ID_CP0_BY4 = 0x6, 651 + DBG_BLOCK_ID_UVDU_BY4 = 0x7, 652 + DBG_BLOCK_ID_VGT0_BY4 = 0x8, 653 + DBG_BLOCK_ID_SCT0_BY4 = 0x9, 654 + DBG_BLOCK_ID_TCAA_BY4 = 0xa, 655 + DBG_BLOCK_ID_MCC0_BY4 = 0xb, 656 + DBG_BLOCK_ID_SX0_BY4 = 0xc, 657 + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, 658 + DBG_BLOCK_ID_PC0_BY4 = 0xe, 659 + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, 660 + DBG_BLOCK_ID_SCB0_BY4 = 0x10, 661 + DBG_BLOCK_ID_SCF0_BY4 = 0x11, 662 + DBG_BLOCK_ID_BCI0_BY4 = 0x12, 663 + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, 664 + DBG_BLOCK_ID_CB00_BY4 = 0x14, 665 + DBG_BLOCK_ID_CB04_BY4 = 0x15, 666 + DBG_BLOCK_ID_CB10_BY4 = 0x16, 667 + DBG_BLOCK_ID_CB14_BY4 = 0x17, 668 + DBG_BLOCK_ID_TCP0_BY4 = 0x18, 669 + DBG_BLOCK_ID_TCP4_BY4 = 0x19, 670 + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 671 + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 672 + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 673 + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 674 + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 675 + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 676 + DBG_BLOCK_ID_DB_BY4 = 0x20, 677 + DBG_BLOCK_ID_DB04_BY4 = 0x21, 678 + DBG_BLOCK_ID_DB10_BY4 = 0x22, 679 + DBG_BLOCK_ID_DB14_BY4 = 0x23, 680 + DBG_BLOCK_ID_TCC0_BY4 = 0x24, 681 + DBG_BLOCK_ID_TCC4_BY4 = 0x25, 682 + DBG_BLOCK_ID_SPS00_BY4 = 0x26, 683 + DBG_BLOCK_ID_SPS11_BY4 = 0x27, 684 + DBG_BLOCK_ID_TA00_BY4 = 0x28, 685 + DBG_BLOCK_ID_TA04_BY4 = 0x29, 686 + DBG_BLOCK_ID_TA08_BY4 = 0x2a, 687 + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, 688 + DBG_BLOCK_ID_TA10_BY4 = 0x2c, 689 + DBG_BLOCK_ID_TA14_BY4 = 0x2d, 690 + DBG_BLOCK_ID_TA18_BY4 = 0x2e, 691 + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, 692 + DBG_BLOCK_ID_TD00_BY4 = 0x30, 693 + DBG_BLOCK_ID_TD04_BY4 = 0x31, 694 + DBG_BLOCK_ID_TD08_BY4 = 0x32, 695 + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, 696 + DBG_BLOCK_ID_TD10_BY4 = 0x34, 697 + DBG_BLOCK_ID_TD14_BY4 = 0x35, 698 + DBG_BLOCK_ID_TD18_BY4 = 0x36, 699 + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, 700 + DBG_BLOCK_ID_MCD0_BY4 = 0x38, 701 + DBG_BLOCK_ID_MCD4_BY4 = 0x39, 702 + } DebugBlockId_BY4; 703 + typedef enum DebugBlockId_BY8 { 704 + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 705 + DBG_BLOCK_ID_CSC_BY8 = 0x1, 706 + DBG_BLOCK_ID_DMA0_BY8 = 0x2, 707 + DBG_BLOCK_ID_CP0_BY8 = 0x3, 708 + DBG_BLOCK_ID_VGT0_BY8 = 0x4, 709 + DBG_BLOCK_ID_TCAA_BY8 = 0x5, 710 + DBG_BLOCK_ID_SX0_BY8 = 0x6, 711 + DBG_BLOCK_ID_PC0_BY8 = 0x7, 712 + DBG_BLOCK_ID_SCB0_BY8 = 0x8, 713 + DBG_BLOCK_ID_BCI0_BY8 = 0x9, 714 + DBG_BLOCK_ID_CB00_BY8 = 0xa, 715 + DBG_BLOCK_ID_CB10_BY8 = 0xb, 716 + DBG_BLOCK_ID_TCP0_BY8 = 0xc, 717 + DBG_BLOCK_ID_TCP8_BY8 = 0xd, 718 + DBG_BLOCK_ID_TCP16_BY8 = 0xe, 719 + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 720 + DBG_BLOCK_ID_DB00_BY8 = 0x10, 721 + DBG_BLOCK_ID_DB10_BY8 = 0x11, 722 + DBG_BLOCK_ID_TCC0_BY8 = 0x12, 723 + DBG_BLOCK_ID_SPS00_BY8 = 0x13, 724 + DBG_BLOCK_ID_TA00_BY8 = 0x14, 725 + DBG_BLOCK_ID_TA08_BY8 = 0x15, 726 + DBG_BLOCK_ID_TA10_BY8 = 0x16, 727 + DBG_BLOCK_ID_TA18_BY8 = 0x17, 728 + DBG_BLOCK_ID_TD00_BY8 = 0x18, 729 + DBG_BLOCK_ID_TD08_BY8 = 0x19, 730 + DBG_BLOCK_ID_TD10_BY8 = 0x1a, 731 + DBG_BLOCK_ID_TD18_BY8 = 0x1b, 732 + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, 733 + } DebugBlockId_BY8; 734 + typedef enum DebugBlockId_BY16 { 735 + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 736 + DBG_BLOCK_ID_DMA0_BY16 = 0x1, 737 + DBG_BLOCK_ID_VGT0_BY16 = 0x2, 738 + DBG_BLOCK_ID_SX0_BY16 = 0x3, 739 + DBG_BLOCK_ID_SCB0_BY16 = 0x4, 740 + DBG_BLOCK_ID_CB00_BY16 = 0x5, 741 + DBG_BLOCK_ID_TCP0_BY16 = 0x6, 742 + DBG_BLOCK_ID_TCP16_BY16 = 0x7, 743 + DBG_BLOCK_ID_DB00_BY16 = 0x8, 744 + DBG_BLOCK_ID_TCC0_BY16 = 0x9, 745 + DBG_BLOCK_ID_TA00_BY16 = 0xa, 746 + DBG_BLOCK_ID_TA10_BY16 = 0xb, 747 + DBG_BLOCK_ID_TD00_BY16 = 0xc, 748 + DBG_BLOCK_ID_TD10_BY16 = 0xd, 749 + DBG_BLOCK_ID_MCD0_BY16 = 0xe, 750 + } DebugBlockId_BY16; 751 + typedef enum ColorTransform { 752 + DCC_CT_AUTO = 0x0, 753 + DCC_CT_NONE = 0x1, 754 + ABGR_TO_A_BG_G_RB = 0x2, 755 + BGRA_TO_BG_G_RB_A = 0x3, 756 + } ColorTransform; 757 + typedef enum CompareRef { 758 + REF_NEVER = 0x0, 759 + REF_LESS = 0x1, 760 + REF_EQUAL = 0x2, 761 + REF_LEQUAL = 0x3, 762 + REF_GREATER = 0x4, 763 + REF_NOTEQUAL = 0x5, 764 + REF_GEQUAL = 0x6, 765 + REF_ALWAYS = 0x7, 766 + } CompareRef; 767 + typedef enum ReadSize { 768 + READ_256_BITS = 0x0, 769 + READ_512_BITS = 0x1, 770 + } ReadSize; 771 + typedef enum DepthFormat { 772 + DEPTH_INVALID = 0x0, 773 + DEPTH_16 = 0x1, 774 + DEPTH_X8_24 = 0x2, 775 + DEPTH_8_24 = 0x3, 776 + DEPTH_X8_24_FLOAT = 0x4, 777 + DEPTH_8_24_FLOAT = 0x5, 778 + DEPTH_32_FLOAT = 0x6, 779 + DEPTH_X24_8_32_FLOAT = 0x7, 780 + } DepthFormat; 781 + typedef enum ZFormat { 782 + Z_INVALID = 0x0, 783 + Z_16 = 0x1, 784 + Z_24 = 0x2, 785 + Z_32_FLOAT = 0x3, 786 + } ZFormat; 787 + typedef enum StencilFormat { 788 + STENCIL_INVALID = 0x0, 789 + STENCIL_8 = 0x1, 790 + } StencilFormat; 791 + typedef enum CmaskMode { 792 + CMASK_CLEAR_NONE = 0x0, 793 + CMASK_CLEAR_ONE = 0x1, 794 + CMASK_CLEAR_ALL = 0x2, 795 + CMASK_ANY_EXPANDED = 0x3, 796 + CMASK_ALPHA0_FRAG1 = 0x4, 797 + CMASK_ALPHA0_FRAG2 = 0x5, 798 + CMASK_ALPHA0_FRAG4 = 0x6, 799 + CMASK_ALPHA0_FRAGS = 0x7, 800 + CMASK_ALPHA1_FRAG1 = 0x8, 801 + CMASK_ALPHA1_FRAG2 = 0x9, 802 + CMASK_ALPHA1_FRAG4 = 0xa, 803 + CMASK_ALPHA1_FRAGS = 0xb, 804 + CMASK_ALPHAX_FRAG1 = 0xc, 805 + CMASK_ALPHAX_FRAG2 = 0xd, 806 + CMASK_ALPHAX_FRAG4 = 0xe, 807 + CMASK_ALPHAX_FRAGS = 0xf, 808 + } CmaskMode; 809 + typedef enum QuadExportFormat { 810 + EXPORT_UNUSED = 0x0, 811 + EXPORT_32_R = 0x1, 812 + EXPORT_32_GR = 0x2, 813 + EXPORT_32_AR = 0x3, 814 + EXPORT_FP16_ABGR = 0x4, 815 + EXPORT_UNSIGNED16_ABGR = 0x5, 816 + EXPORT_SIGNED16_ABGR = 0x6, 817 + EXPORT_32_ABGR = 0x7, 818 + } QuadExportFormat; 819 + typedef enum QuadExportFormatOld { 820 + EXPORT_4P_32BPC_ABGR = 0x0, 821 + EXPORT_4P_16BPC_ABGR = 0x1, 822 + EXPORT_4P_32BPC_GR = 0x2, 823 + EXPORT_4P_32BPC_AR = 0x3, 824 + EXPORT_2P_32BPC_ABGR = 0x4, 825 + EXPORT_8P_32BPC_R = 0x5, 826 + } QuadExportFormatOld; 827 + typedef enum ColorFormat { 828 + COLOR_INVALID = 0x0, 829 + COLOR_8 = 0x1, 830 + COLOR_16 = 0x2, 831 + COLOR_8_8 = 0x3, 832 + COLOR_32 = 0x4, 833 + COLOR_16_16 = 0x5, 834 + COLOR_10_11_11 = 0x6, 835 + COLOR_11_11_10 = 0x7, 836 + COLOR_10_10_10_2 = 0x8, 837 + COLOR_2_10_10_10 = 0x9, 838 + COLOR_8_8_8_8 = 0xa, 839 + COLOR_32_32 = 0xb, 840 + COLOR_16_16_16_16 = 0xc, 841 + COLOR_RESERVED_13 = 0xd, 842 + COLOR_32_32_32_32 = 0xe, 843 + COLOR_RESERVED_15 = 0xf, 844 + COLOR_5_6_5 = 0x10, 845 + COLOR_1_5_5_5 = 0x11, 846 + COLOR_5_5_5_1 = 0x12, 847 + COLOR_4_4_4_4 = 0x13, 848 + COLOR_8_24 = 0x14, 849 + COLOR_24_8 = 0x15, 850 + COLOR_X24_8_32_FLOAT = 0x16, 851 + COLOR_RESERVED_23 = 0x17, 852 + } ColorFormat; 853 + typedef enum SurfaceFormat { 854 + FMT_INVALID = 0x0, 855 + FMT_8 = 0x1, 856 + FMT_16 = 0x2, 857 + FMT_8_8 = 0x3, 858 + FMT_32 = 0x4, 859 + FMT_16_16 = 0x5, 860 + FMT_10_11_11 = 0x6, 861 + FMT_11_11_10 = 0x7, 862 + FMT_10_10_10_2 = 0x8, 863 + FMT_2_10_10_10 = 0x9, 864 + FMT_8_8_8_8 = 0xa, 865 + FMT_32_32 = 0xb, 866 + FMT_16_16_16_16 = 0xc, 867 + FMT_32_32_32 = 0xd, 868 + FMT_32_32_32_32 = 0xe, 869 + FMT_RESERVED_4 = 0xf, 870 + FMT_5_6_5 = 0x10, 871 + FMT_1_5_5_5 = 0x11, 872 + FMT_5_5_5_1 = 0x12, 873 + FMT_4_4_4_4 = 0x13, 874 + FMT_8_24 = 0x14, 875 + FMT_24_8 = 0x15, 876 + FMT_X24_8_32_FLOAT = 0x16, 877 + FMT_RESERVED_33 = 0x17, 878 + FMT_11_11_10_FLOAT = 0x18, 879 + FMT_16_FLOAT = 0x19, 880 + FMT_32_FLOAT = 0x1a, 881 + FMT_16_16_FLOAT = 0x1b, 882 + FMT_8_24_FLOAT = 0x1c, 883 + FMT_24_8_FLOAT = 0x1d, 884 + FMT_32_32_FLOAT = 0x1e, 885 + FMT_10_11_11_FLOAT = 0x1f, 886 + FMT_16_16_16_16_FLOAT = 0x20, 887 + FMT_3_3_2 = 0x21, 888 + FMT_6_5_5 = 0x22, 889 + FMT_32_32_32_32_FLOAT = 0x23, 890 + FMT_RESERVED_36 = 0x24, 891 + FMT_1 = 0x25, 892 + FMT_1_REVERSED = 0x26, 893 + FMT_GB_GR = 0x27, 894 + FMT_BG_RG = 0x28, 895 + FMT_32_AS_8 = 0x29, 896 + FMT_32_AS_8_8 = 0x2a, 897 + FMT_5_9_9_9_SHAREDEXP = 0x2b, 898 + FMT_8_8_8 = 0x2c, 899 + FMT_16_16_16 = 0x2d, 900 + FMT_16_16_16_FLOAT = 0x2e, 901 + FMT_4_4 = 0x2f, 902 + FMT_32_32_32_FLOAT = 0x30, 903 + FMT_BC1 = 0x31, 904 + FMT_BC2 = 0x32, 905 + FMT_BC3 = 0x33, 906 + FMT_BC4 = 0x34, 907 + FMT_BC5 = 0x35, 908 + FMT_BC6 = 0x36, 909 + FMT_BC7 = 0x37, 910 + FMT_32_AS_32_32_32_32 = 0x38, 911 + FMT_APC3 = 0x39, 912 + FMT_APC4 = 0x3a, 913 + FMT_APC5 = 0x3b, 914 + FMT_APC6 = 0x3c, 915 + FMT_APC7 = 0x3d, 916 + FMT_CTX1 = 0x3e, 917 + FMT_RESERVED_63 = 0x3f, 918 + } SurfaceFormat; 919 + typedef enum BUF_DATA_FORMAT { 920 + BUF_DATA_FORMAT_INVALID = 0x0, 921 + BUF_DATA_FORMAT_8 = 0x1, 922 + BUF_DATA_FORMAT_16 = 0x2, 923 + BUF_DATA_FORMAT_8_8 = 0x3, 924 + BUF_DATA_FORMAT_32 = 0x4, 925 + BUF_DATA_FORMAT_16_16 = 0x5, 926 + BUF_DATA_FORMAT_10_11_11 = 0x6, 927 + BUF_DATA_FORMAT_11_11_10 = 0x7, 928 + BUF_DATA_FORMAT_10_10_10_2 = 0x8, 929 + BUF_DATA_FORMAT_2_10_10_10 = 0x9, 930 + BUF_DATA_FORMAT_8_8_8_8 = 0xa, 931 + BUF_DATA_FORMAT_32_32 = 0xb, 932 + BUF_DATA_FORMAT_16_16_16_16 = 0xc, 933 + BUF_DATA_FORMAT_32_32_32 = 0xd, 934 + BUF_DATA_FORMAT_32_32_32_32 = 0xe, 935 + BUF_DATA_FORMAT_RESERVED_15 = 0xf, 936 + } BUF_DATA_FORMAT; 937 + typedef enum IMG_DATA_FORMAT { 938 + IMG_DATA_FORMAT_INVALID = 0x0, 939 + IMG_DATA_FORMAT_8 = 0x1, 940 + IMG_DATA_FORMAT_16 = 0x2, 941 + IMG_DATA_FORMAT_8_8 = 0x3, 942 + IMG_DATA_FORMAT_32 = 0x4, 943 + IMG_DATA_FORMAT_16_16 = 0x5, 944 + IMG_DATA_FORMAT_10_11_11 = 0x6, 945 + IMG_DATA_FORMAT_11_11_10 = 0x7, 946 + IMG_DATA_FORMAT_10_10_10_2 = 0x8, 947 + IMG_DATA_FORMAT_2_10_10_10 = 0x9, 948 + IMG_DATA_FORMAT_8_8_8_8 = 0xa, 949 + IMG_DATA_FORMAT_32_32 = 0xb, 950 + IMG_DATA_FORMAT_16_16_16_16 = 0xc, 951 + IMG_DATA_FORMAT_32_32_32 = 0xd, 952 + IMG_DATA_FORMAT_32_32_32_32 = 0xe, 953 + IMG_DATA_FORMAT_RESERVED_15 = 0xf, 954 + IMG_DATA_FORMAT_5_6_5 = 0x10, 955 + IMG_DATA_FORMAT_1_5_5_5 = 0x11, 956 + IMG_DATA_FORMAT_5_5_5_1 = 0x12, 957 + IMG_DATA_FORMAT_4_4_4_4 = 0x13, 958 + IMG_DATA_FORMAT_8_24 = 0x14, 959 + IMG_DATA_FORMAT_24_8 = 0x15, 960 + IMG_DATA_FORMAT_X24_8_32 = 0x16, 961 + IMG_DATA_FORMAT_RESERVED_23 = 0x17, 962 + IMG_DATA_FORMAT_RESERVED_24 = 0x18, 963 + IMG_DATA_FORMAT_RESERVED_25 = 0x19, 964 + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 965 + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 966 + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 967 + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 968 + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 969 + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 970 + IMG_DATA_FORMAT_GB_GR = 0x20, 971 + IMG_DATA_FORMAT_BG_RG = 0x21, 972 + IMG_DATA_FORMAT_5_9_9_9 = 0x22, 973 + IMG_DATA_FORMAT_BC1 = 0x23, 974 + IMG_DATA_FORMAT_BC2 = 0x24, 975 + IMG_DATA_FORMAT_BC3 = 0x25, 976 + IMG_DATA_FORMAT_BC4 = 0x26, 977 + IMG_DATA_FORMAT_BC5 = 0x27, 978 + IMG_DATA_FORMAT_BC6 = 0x28, 979 + IMG_DATA_FORMAT_BC7 = 0x29, 980 + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 981 + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 982 + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 983 + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 984 + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 985 + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 986 + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 987 + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 988 + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 989 + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 990 + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 991 + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 992 + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 993 + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 994 + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 995 + IMG_DATA_FORMAT_4_4 = 0x39, 996 + IMG_DATA_FORMAT_6_5_5 = 0x3a, 997 + IMG_DATA_FORMAT_1 = 0x3b, 998 + IMG_DATA_FORMAT_1_REVERSED = 0x3c, 999 + IMG_DATA_FORMAT_32_AS_8 = 0x3d, 1000 + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 1001 + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 1002 + } IMG_DATA_FORMAT; 1003 + typedef enum BUF_NUM_FORMAT { 1004 + BUF_NUM_FORMAT_UNORM = 0x0, 1005 + BUF_NUM_FORMAT_SNORM = 0x1, 1006 + BUF_NUM_FORMAT_USCALED = 0x2, 1007 + BUF_NUM_FORMAT_SSCALED = 0x3, 1008 + BUF_NUM_FORMAT_UINT = 0x4, 1009 + BUF_NUM_FORMAT_SINT = 0x5, 1010 + BUF_NUM_FORMAT_RESERVED_6 = 0x6, 1011 + BUF_NUM_FORMAT_FLOAT = 0x7, 1012 + } BUF_NUM_FORMAT; 1013 + typedef enum IMG_NUM_FORMAT { 1014 + IMG_NUM_FORMAT_UNORM = 0x0, 1015 + IMG_NUM_FORMAT_SNORM = 0x1, 1016 + IMG_NUM_FORMAT_USCALED = 0x2, 1017 + IMG_NUM_FORMAT_SSCALED = 0x3, 1018 + IMG_NUM_FORMAT_UINT = 0x4, 1019 + IMG_NUM_FORMAT_SINT = 0x5, 1020 + IMG_NUM_FORMAT_RESERVED_6 = 0x6, 1021 + IMG_NUM_FORMAT_FLOAT = 0x7, 1022 + IMG_NUM_FORMAT_RESERVED_8 = 0x8, 1023 + IMG_NUM_FORMAT_SRGB = 0x9, 1024 + IMG_NUM_FORMAT_RESERVED_10 = 0xa, 1025 + IMG_NUM_FORMAT_RESERVED_11 = 0xb, 1026 + IMG_NUM_FORMAT_RESERVED_12 = 0xc, 1027 + IMG_NUM_FORMAT_RESERVED_13 = 0xd, 1028 + IMG_NUM_FORMAT_RESERVED_14 = 0xe, 1029 + IMG_NUM_FORMAT_RESERVED_15 = 0xf, 1030 + } IMG_NUM_FORMAT; 1031 + typedef enum TileType { 1032 + ARRAY_COLOR_TILE = 0x0, 1033 + ARRAY_DEPTH_TILE = 0x1, 1034 + } TileType; 1035 + typedef enum NonDispTilingOrder { 1036 + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 1037 + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 1038 + } NonDispTilingOrder; 1039 + typedef enum MicroTileMode { 1040 + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 1041 + ADDR_SURF_THIN_MICRO_TILING = 0x1, 1042 + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 1043 + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 1044 + ADDR_SURF_THICK_MICRO_TILING = 0x4, 1045 + } MicroTileMode; 1046 + typedef enum TileSplit { 1047 + ADDR_SURF_TILE_SPLIT_64B = 0x0, 1048 + ADDR_SURF_TILE_SPLIT_128B = 0x1, 1049 + ADDR_SURF_TILE_SPLIT_256B = 0x2, 1050 + ADDR_SURF_TILE_SPLIT_512B = 0x3, 1051 + ADDR_SURF_TILE_SPLIT_1KB = 0x4, 1052 + ADDR_SURF_TILE_SPLIT_2KB = 0x5, 1053 + ADDR_SURF_TILE_SPLIT_4KB = 0x6, 1054 + } TileSplit; 1055 + typedef enum SampleSplit { 1056 + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 1057 + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 1058 + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 1059 + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 1060 + } SampleSplit; 1061 + typedef enum PipeConfig { 1062 + ADDR_SURF_P2 = 0x0, 1063 + ADDR_SURF_P2_RESERVED0 = 0x1, 1064 + ADDR_SURF_P2_RESERVED1 = 0x2, 1065 + ADDR_SURF_P2_RESERVED2 = 0x3, 1066 + ADDR_SURF_P4_8x16 = 0x4, 1067 + ADDR_SURF_P4_16x16 = 0x5, 1068 + ADDR_SURF_P4_16x32 = 0x6, 1069 + ADDR_SURF_P4_32x32 = 0x7, 1070 + ADDR_SURF_P8_16x16_8x16 = 0x8, 1071 + ADDR_SURF_P8_16x32_8x16 = 0x9, 1072 + ADDR_SURF_P8_32x32_8x16 = 0xa, 1073 + ADDR_SURF_P8_16x32_16x16 = 0xb, 1074 + ADDR_SURF_P8_32x32_16x16 = 0xc, 1075 + ADDR_SURF_P8_32x32_16x32 = 0xd, 1076 + ADDR_SURF_P8_32x64_32x32 = 0xe, 1077 + ADDR_SURF_P8_RESERVED0 = 0xf, 1078 + ADDR_SURF_P16_32x32_8x16 = 0x10, 1079 + ADDR_SURF_P16_32x32_16x16 = 0x11, 1080 + } PipeConfig; 1081 + typedef enum NumBanks { 1082 + ADDR_SURF_2_BANK = 0x0, 1083 + ADDR_SURF_4_BANK = 0x1, 1084 + ADDR_SURF_8_BANK = 0x2, 1085 + ADDR_SURF_16_BANK = 0x3, 1086 + } NumBanks; 1087 + typedef enum BankWidth { 1088 + ADDR_SURF_BANK_WIDTH_1 = 0x0, 1089 + ADDR_SURF_BANK_WIDTH_2 = 0x1, 1090 + ADDR_SURF_BANK_WIDTH_4 = 0x2, 1091 + ADDR_SURF_BANK_WIDTH_8 = 0x3, 1092 + } BankWidth; 1093 + typedef enum BankHeight { 1094 + ADDR_SURF_BANK_HEIGHT_1 = 0x0, 1095 + ADDR_SURF_BANK_HEIGHT_2 = 0x1, 1096 + ADDR_SURF_BANK_HEIGHT_4 = 0x2, 1097 + ADDR_SURF_BANK_HEIGHT_8 = 0x3, 1098 + } BankHeight; 1099 + typedef enum BankWidthHeight { 1100 + ADDR_SURF_BANK_WH_1 = 0x0, 1101 + ADDR_SURF_BANK_WH_2 = 0x1, 1102 + ADDR_SURF_BANK_WH_4 = 0x2, 1103 + ADDR_SURF_BANK_WH_8 = 0x3, 1104 + } BankWidthHeight; 1105 + typedef enum MacroTileAspect { 1106 + ADDR_SURF_MACRO_ASPECT_1 = 0x0, 1107 + ADDR_SURF_MACRO_ASPECT_2 = 0x1, 1108 + ADDR_SURF_MACRO_ASPECT_4 = 0x2, 1109 + ADDR_SURF_MACRO_ASPECT_8 = 0x3, 1110 + } MacroTileAspect; 1111 + typedef enum GATCL1RequestType { 1112 + GATCL1_TYPE_NORMAL = 0x0, 1113 + GATCL1_TYPE_SHOOTDOWN = 0x1, 1114 + GATCL1_TYPE_BYPASS = 0x2, 1115 + } GATCL1RequestType; 1116 + typedef enum TCC_CACHE_POLICIES { 1117 + TCC_CACHE_POLICY_LRU = 0x0, 1118 + TCC_CACHE_POLICY_STREAM = 0x1, 1119 + } TCC_CACHE_POLICIES; 1120 + typedef enum MTYPE { 1121 + MTYPE_NC_NV = 0x0, 1122 + MTYPE_NC = 0x1, 1123 + MTYPE_CC = 0x2, 1124 + MTYPE_UC = 0x3, 1125 + } MTYPE; 1126 + typedef enum PERFMON_COUNTER_MODE { 1127 + PERFMON_COUNTER_MODE_ACCUM = 0x0, 1128 + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 1129 + PERFMON_COUNTER_MODE_MAX = 0x2, 1130 + PERFMON_COUNTER_MODE_DIRTY = 0x3, 1131 + PERFMON_COUNTER_MODE_SAMPLE = 0x4, 1132 + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 1133 + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 1134 + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 1135 + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 1136 + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 1137 + PERFMON_COUNTER_MODE_RESERVED = 0xf, 1138 + } PERFMON_COUNTER_MODE; 1139 + typedef enum PERFMON_SPM_MODE { 1140 + PERFMON_SPM_MODE_OFF = 0x0, 1141 + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 1142 + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 1143 + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 1144 + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 1145 + PERFMON_SPM_MODE_RESERVED_5 = 0x5, 1146 + PERFMON_SPM_MODE_RESERVED_6 = 0x6, 1147 + PERFMON_SPM_MODE_RESERVED_7 = 0x7, 1148 + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 1149 + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 1150 + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 1151 + } PERFMON_SPM_MODE; 1152 + typedef enum SurfaceTiling { 1153 + ARRAY_LINEAR = 0x0, 1154 + ARRAY_TILED = 0x1, 1155 + } SurfaceTiling; 1156 + typedef enum SurfaceArray { 1157 + ARRAY_1D = 0x0, 1158 + ARRAY_2D = 0x1, 1159 + ARRAY_3D = 0x2, 1160 + ARRAY_3D_SLICE = 0x3, 1161 + } SurfaceArray; 1162 + typedef enum ColorArray { 1163 + ARRAY_2D_ALT_COLOR = 0x0, 1164 + ARRAY_2D_COLOR = 0x1, 1165 + ARRAY_3D_SLICE_COLOR = 0x3, 1166 + } ColorArray; 1167 + typedef enum DepthArray { 1168 + ARRAY_2D_ALT_DEPTH = 0x0, 1169 + ARRAY_2D_DEPTH = 0x1, 1170 + } DepthArray; 1171 + typedef enum ENUM_NUM_SIMD_PER_CU { 1172 + NUM_SIMD_PER_CU = 0x4, 1173 + } ENUM_NUM_SIMD_PER_CU; 1174 + typedef enum MEM_PWR_FORCE_CTRL { 1175 + NO_FORCE_REQUEST = 0x0, 1176 + FORCE_LIGHT_SLEEP_REQUEST = 0x1, 1177 + FORCE_DEEP_SLEEP_REQUEST = 0x2, 1178 + FORCE_SHUT_DOWN_REQUEST = 0x3, 1179 + } MEM_PWR_FORCE_CTRL; 1180 + typedef enum MEM_PWR_FORCE_CTRL2 { 1181 + NO_FORCE_REQ = 0x0, 1182 + FORCE_LIGHT_SLEEP_REQ = 0x1, 1183 + } MEM_PWR_FORCE_CTRL2; 1184 + typedef enum MEM_PWR_DIS_CTRL { 1185 + ENABLE_MEM_PWR_CTRL = 0x0, 1186 + DISABLE_MEM_PWR_CTRL = 0x1, 1187 + } MEM_PWR_DIS_CTRL; 1188 + typedef enum MEM_PWR_SEL_CTRL { 1189 + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, 1190 + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, 1191 + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, 1192 + } MEM_PWR_SEL_CTRL; 1193 + typedef enum MEM_PWR_SEL_CTRL2 { 1194 + DYNAMIC_DEEP_SLEEP_EN = 0x0, 1195 + DYNAMIC_LIGHT_SLEEP_EN = 0x1, 1196 + } MEM_PWR_SEL_CTRL2; 1197 + 1198 + #endif /* BIF_5_0_ENUM_H */
+11494
drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h
··· 1 + /* 2 + * BIF_5_0 Register documentation 3 + * 4 + * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included 14 + * in all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + #ifndef BIF_5_0_SH_MASK_H 25 + #define BIF_5_0_SH_MASK_H 26 + 27 + #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff 28 + #define MM_INDEX__MM_OFFSET__SHIFT 0x0 29 + #define MM_INDEX__MM_APER_MASK 0x80000000 30 + #define MM_INDEX__MM_APER__SHIFT 0x1f 31 + #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff 32 + #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 33 + #define MM_DATA__MM_DATA_MASK 0xffffffff 34 + #define MM_DATA__MM_DATA__SHIFT 0x0 35 + #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2 36 + #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 37 + #define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x1 38 + #define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 39 + #define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1 40 + #define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0 41 + #define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2 42 + #define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1 43 + #define BUS_CNTL__PMI_IO_DIS_MASK 0x4 44 + #define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 45 + #define BUS_CNTL__PMI_MEM_DIS_MASK 0x8 46 + #define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 47 + #define BUS_CNTL__PMI_BM_DIS_MASK 0x10 48 + #define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 49 + #define BUS_CNTL__PMI_INT_DIS_MASK 0x20 50 + #define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5 51 + #define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40 52 + #define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 53 + #define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80 54 + #define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 55 + #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100 56 + #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8 57 + #define BUS_CNTL__SET_AZ_TC_MASK 0x1c00 58 + #define BUS_CNTL__SET_AZ_TC__SHIFT 0xa 59 + #define BUS_CNTL__SET_MC_TC_MASK 0xe000 60 + #define BUS_CNTL__SET_MC_TC__SHIFT 0xd 61 + #define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000 62 + #define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 63 + #define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000 64 + #define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 65 + #define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000 66 + #define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 67 + #define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1 68 + #define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 69 + #define CONFIG_CNTL__VGA_DIS_MASK 0x2 70 + #define CONFIG_CNTL__VGA_DIS__SHIFT 0x1 71 + #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4 72 + #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 73 + #define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18 74 + #define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 75 + #define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff 76 + #define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 77 + #define CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xffffffff 78 + #define CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 79 + #define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x1 80 + #define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 81 + #define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000 82 + #define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f 83 + #define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff 84 + #define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 85 + #define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff 86 + #define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 87 + #define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff 88 + #define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 89 + #define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff 90 + #define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 91 + #define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff 92 + #define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 93 + #define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT_MASK 0x1 94 + #define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT__SHIFT 0x0 95 + #define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT_MASK 0x100 96 + #define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT__SHIFT 0x8 97 + #define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x1 98 + #define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 99 + #define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x10000 100 + #define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 101 + #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x1 102 + #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 103 + #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x2 104 + #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 105 + #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x10000 106 + #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 107 + #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x20000 108 + #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 109 + #define BX_RESET_EN__COR_RESET_EN_MASK 0x1 110 + #define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 111 + #define BX_RESET_EN__REG_RESET_EN_MASK 0x2 112 + #define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 113 + #define BX_RESET_EN__STY_RESET_EN_MASK 0x4 114 + #define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 115 + #define BX_RESET_EN__FLR_TWICE_EN_MASK 0x100 116 + #define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 117 + #define BX_RESET_EN__FLR_TIMER_SEL_MASK 0x600 118 + #define BX_RESET_EN__FLR_TIMER_SEL__SHIFT 0x9 119 + #define BX_RESET_EN__DB_APER_RESET_EN_MASK 0x8000 120 + #define BX_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf 121 + #define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x10000 122 + #define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 123 + #define BX_RESET_EN__PF_FLR_NEWHDL_EN_MASK 0x20000 124 + #define BX_RESET_EN__PF_FLR_NEWHDL_EN__SHIFT 0x11 125 + #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7 126 + #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 127 + #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8 128 + #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3 129 + #define HW_DEBUG__HW_00_DEBUG_MASK 0x1 130 + #define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 131 + #define HW_DEBUG__HW_01_DEBUG_MASK 0x2 132 + #define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 133 + #define HW_DEBUG__HW_02_DEBUG_MASK 0x4 134 + #define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 135 + #define HW_DEBUG__HW_03_DEBUG_MASK 0x8 136 + #define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 137 + #define HW_DEBUG__HW_04_DEBUG_MASK 0x10 138 + #define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 139 + #define HW_DEBUG__HW_05_DEBUG_MASK 0x20 140 + #define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 141 + #define HW_DEBUG__HW_06_DEBUG_MASK 0x40 142 + #define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 143 + #define HW_DEBUG__HW_07_DEBUG_MASK 0x80 144 + #define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 145 + #define HW_DEBUG__HW_08_DEBUG_MASK 0x100 146 + #define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 147 + #define HW_DEBUG__HW_09_DEBUG_MASK 0x200 148 + #define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 149 + #define HW_DEBUG__HW_10_DEBUG_MASK 0x400 150 + #define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa 151 + #define HW_DEBUG__HW_11_DEBUG_MASK 0x800 152 + #define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb 153 + #define HW_DEBUG__HW_12_DEBUG_MASK 0x1000 154 + #define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc 155 + #define HW_DEBUG__HW_13_DEBUG_MASK 0x2000 156 + #define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd 157 + #define HW_DEBUG__HW_14_DEBUG_MASK 0x4000 158 + #define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe 159 + #define HW_DEBUG__HW_15_DEBUG_MASK 0x8000 160 + #define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf 161 + #define HW_DEBUG__HW_16_DEBUG_MASK 0x10000 162 + #define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 163 + #define HW_DEBUG__HW_17_DEBUG_MASK 0x20000 164 + #define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 165 + #define HW_DEBUG__HW_18_DEBUG_MASK 0x40000 166 + #define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 167 + #define HW_DEBUG__HW_19_DEBUG_MASK 0x80000 168 + #define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 169 + #define HW_DEBUG__HW_20_DEBUG_MASK 0x100000 170 + #define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 171 + #define HW_DEBUG__HW_21_DEBUG_MASK 0x200000 172 + #define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 173 + #define HW_DEBUG__HW_22_DEBUG_MASK 0x400000 174 + #define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 175 + #define HW_DEBUG__HW_23_DEBUG_MASK 0x800000 176 + #define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 177 + #define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 178 + #define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 179 + #define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 180 + #define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 181 + #define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 182 + #define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a 183 + #define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 184 + #define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b 185 + #define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 186 + #define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c 187 + #define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 188 + #define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d 189 + #define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 190 + #define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e 191 + #define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 192 + #define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f 193 + #define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f 194 + #define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0 195 + #define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000 196 + #define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10 197 + #define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f 198 + #define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0 199 + #define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0 200 + #define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5 201 + #define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00 202 + #define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa 203 + #define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000 204 + #define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf 205 + #define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000 206 + #define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14 207 + #define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000 208 + #define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19 209 + #define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1 210 + #define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 211 + #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1 212 + #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 213 + #define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2 214 + #define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 215 + #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8 216 + #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 217 + #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0 218 + #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 219 + #define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100 220 + #define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 221 + #define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00 222 + #define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9 223 + #define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000 224 + #define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd 225 + #define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000 226 + #define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf 227 + #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff 228 + #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 229 + #define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1 230 + #define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0 231 + #define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2 232 + #define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1 233 + #define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4 234 + #define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2 235 + #define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8 236 + #define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3 237 + #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10 238 + #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4 239 + #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20 240 + #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5 241 + #define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40 242 + #define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6 243 + #define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80 244 + #define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7 245 + #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00 246 + #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8 247 + #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000 248 + #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10 249 + #define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000 250 + #define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18 251 + #define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000 252 + #define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e 253 + #define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f 254 + #define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0 255 + #define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00 256 + #define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8 257 + #define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff 258 + #define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0 259 + #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1 260 + #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 261 + #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1 262 + #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 263 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1 264 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 265 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2 266 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 267 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4 268 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 269 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18 270 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 271 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20 272 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 273 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40 274 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 275 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80 276 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 277 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100 278 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 279 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200 280 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 281 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400 282 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa 283 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800 284 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb 285 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000 286 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc 287 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x2000 288 + #define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd 289 + #define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER_MASK 0xff000000 290 + #define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x18 291 + #define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER_MASK 0xffffffff 292 + #define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x0 293 + #define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff 294 + #define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 295 + #define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000 296 + #define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f 297 + #define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff 298 + #define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 299 + #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1 300 + #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 301 + #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2 302 + #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 303 + #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4 304 + #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 305 + #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8 306 + #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 307 + #define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10 308 + #define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 309 + #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20 310 + #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 311 + #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40 312 + #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 313 + #define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80 314 + #define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7 315 + #define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100 316 + #define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8 317 + #define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200 318 + #define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 319 + #define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400 320 + #define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa 321 + #define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800 322 + #define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb 323 + #define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000 324 + #define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc 325 + #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x2000 326 + #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd 327 + #define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x8000 328 + #define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf 329 + #define BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x10000 330 + #define BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x10 331 + #define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x20000 332 + #define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 333 + #define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x40000 334 + #define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 335 + #define BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN_MASK 0x80000 336 + #define BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN__SHIFT 0x13 337 + #define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS_MASK 0x100000 338 + #define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS__SHIFT 0x14 339 + #define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS_MASK 0x200000 340 + #define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS__SHIFT 0x15 341 + #define BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS_MASK 0x400000 342 + #define BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS__SHIFT 0x16 343 + #define BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS_MASK 0x800000 344 + #define BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS__SHIFT 0x17 345 + #define BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS_MASK 0x1000000 346 + #define BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS__SHIFT 0x18 347 + #define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1 348 + #define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 349 + #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2 350 + #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 351 + #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4 352 + #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 353 + #define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8 354 + #define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 355 + #define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x10 356 + #define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 357 + #define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x20 358 + #define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5 359 + #define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000 360 + #define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 361 + #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x1000000 362 + #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 363 + #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x2000000 364 + #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 365 + #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x4000000 366 + #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a 367 + #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x8000000 368 + #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b 369 + #define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3 370 + #define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0 371 + #define BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK 0x1 372 + #define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x0 373 + #define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS_MASK 0x2 374 + #define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x1 375 + #define BIF_FB_EN__FB_READ_EN_MASK 0x1 376 + #define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 377 + #define BIF_FB_EN__FB_WRITE_EN_MASK 0x2 378 + #define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 379 + #define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff 380 + #define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 381 + #define BIF_BUSNUM_LIST0__ID0_MASK 0xff 382 + #define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0 383 + #define BIF_BUSNUM_LIST0__ID1_MASK 0xff00 384 + #define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8 385 + #define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000 386 + #define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10 387 + #define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000 388 + #define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18 389 + #define BIF_BUSNUM_LIST1__ID4_MASK 0xff 390 + #define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0 391 + #define BIF_BUSNUM_LIST1__ID5_MASK 0xff00 392 + #define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8 393 + #define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000 394 + #define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10 395 + #define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000 396 + #define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18 397 + #define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff 398 + #define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 399 + #define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100 400 + #define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 401 + #define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000 402 + #define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 403 + #define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000 404 + #define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 405 + #define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f 406 + #define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 407 + #define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1 408 + #define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0 409 + #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2 410 + #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1 411 + #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4 412 + #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2 413 + #define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00 414 + #define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8 415 + #define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000 416 + #define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd 417 + #define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff 418 + #define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 419 + #define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff 420 + #define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 421 + #define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe 422 + #define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1 423 + #define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1 424 + #define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 425 + #define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2 426 + #define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 427 + #define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4 428 + #define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 429 + #define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8 430 + #define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 431 + #define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10 432 + #define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 433 + #define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20 434 + #define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 435 + #define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40 436 + #define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 437 + #define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80 438 + #define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 439 + #define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100 440 + #define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 441 + #define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200 442 + #define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 443 + #define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400 444 + #define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa 445 + #define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800 446 + #define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb 447 + #define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1 448 + #define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 449 + #define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2 450 + #define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 451 + #define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4 452 + #define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 453 + #define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8 454 + #define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 455 + #define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10 456 + #define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 457 + #define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20 458 + #define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 459 + #define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40 460 + #define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 461 + #define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80 462 + #define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 463 + #define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100 464 + #define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 465 + #define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200 466 + #define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 467 + #define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400 468 + #define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa 469 + #define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800 470 + #define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb 471 + #define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1 472 + #define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0 473 + #define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2 474 + #define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1 475 + #define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4 476 + #define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2 477 + #define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8 478 + #define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3 479 + #define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10 480 + #define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4 481 + #define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20 482 + #define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5 483 + #define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80 484 + #define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7 485 + #define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100 486 + #define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8 487 + #define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200 488 + #define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9 489 + #define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1 490 + #define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 491 + #define HOST_BUSNUM__HOST_ID_MASK 0xffff 492 + #define HOST_BUSNUM__HOST_ID__SHIFT 0x0 493 + #define PEER_REG_RANGE0__START_ADDR_MASK 0xffff 494 + #define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 495 + #define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000 496 + #define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 497 + #define PEER_REG_RANGE1__START_ADDR_MASK 0xffff 498 + #define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 499 + #define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000 500 + #define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 501 + #define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff 502 + #define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 503 + #define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff 504 + #define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 505 + #define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000 506 + #define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f 507 + #define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff 508 + #define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 509 + #define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff 510 + #define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 511 + #define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000 512 + #define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f 513 + #define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff 514 + #define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 515 + #define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff 516 + #define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 517 + #define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000 518 + #define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f 519 + #define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff 520 + #define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 521 + #define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff 522 + #define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 523 + #define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000 524 + #define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f 525 + #define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN_MASK 0x1 526 + #define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN__SHIFT 0x0 527 + #define BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0xffffffff 528 + #define BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 529 + #define BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0xffffffff 530 + #define BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x0 531 + #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff 532 + #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 533 + #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00 534 + #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 535 + #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000 536 + #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 537 + #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000 538 + #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 539 + #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff 540 + #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 541 + #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00 542 + #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 543 + #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000 544 + #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 545 + #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000 546 + #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 547 + #define BACO_CNTL__BACO_EN_MASK 0x1 548 + #define BACO_CNTL__BACO_EN__SHIFT 0x0 549 + #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2 550 + #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1 551 + #define BACO_CNTL__BACO_ISO_DIS_MASK 0x4 552 + #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2 553 + #define BACO_CNTL__BACO_POWER_OFF_MASK 0x8 554 + #define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 555 + #define BACO_CNTL__BACO_RESET_EN_MASK 0x10 556 + #define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4 557 + #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20 558 + #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5 559 + #define BACO_CNTL__BACO_MODE_MASK 0x40 560 + #define BACO_CNTL__BACO_MODE__SHIFT 0x6 561 + #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80 562 + #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7 563 + #define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100 564 + #define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8 565 + #define BACO_CNTL__PWRGOOD_BF_MASK 0x200 566 + #define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9 567 + #define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400 568 + #define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa 569 + #define BACO_CNTL__PWRGOOD_MEM_MASK 0x800 570 + #define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb 571 + #define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000 572 + #define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc 573 + #define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000 574 + #define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd 575 + #define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000 576 + #define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10 577 + #define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000 578 + #define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11 579 + #define BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK 0x40000 580 + #define BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT 0x12 581 + #define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1 582 + #define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0 583 + #define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2 584 + #define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1 585 + #define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1 586 + #define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 587 + #define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1 588 + #define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0 589 + #define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1 590 + #define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0 591 + #define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1 592 + #define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 593 + #define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2 594 + #define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 595 + #define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc 596 + #define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2 597 + #define BACO_CNTL_MISC__BACO_REFCLK_SEL_MASK 0x10 598 + #define BACO_CNTL_MISC__BACO_REFCLK_SEL__SHIFT 0x4 599 + #define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x1 600 + #define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 601 + #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc 602 + #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 603 + #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000 604 + #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e 605 + #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000 606 + #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f 607 + #define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc 608 + #define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 609 + #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc 610 + #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 611 + #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000 612 + #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e 613 + #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000 614 + #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f 615 + #define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc 616 + #define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 617 + #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc 618 + #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 619 + #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000 620 + #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e 621 + #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000 622 + #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f 623 + #define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc 624 + #define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 625 + #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc 626 + #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 627 + #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000 628 + #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e 629 + #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000 630 + #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f 631 + #define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc 632 + #define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 633 + #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc 634 + #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 635 + #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000 636 + #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e 637 + #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000 638 + #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f 639 + #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc 640 + #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 641 + #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc 642 + #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 643 + #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000 644 + #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e 645 + #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000 646 + #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f 647 + #define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc 648 + #define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 649 + #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc 650 + #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 651 + #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000 652 + #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e 653 + #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000 654 + #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f 655 + #define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc 656 + #define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 657 + #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc 658 + #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 659 + #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000 660 + #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e 661 + #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000 662 + #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f 663 + #define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc 664 + #define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 665 + #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc 666 + #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 667 + #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000 668 + #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e 669 + #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000 670 + #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f 671 + #define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc 672 + #define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 673 + #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc 674 + #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 675 + #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000 676 + #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e 677 + #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000 678 + #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f 679 + #define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc 680 + #define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 681 + #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x1 682 + #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 683 + #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2 684 + #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 685 + #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4 686 + #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 687 + #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8 688 + #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 689 + #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x10 690 + #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 691 + #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x20 692 + #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 693 + #define BIF_SMU_INDEX__BIF_SMU_INDEX_MASK 0x7fffc 694 + #define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2 695 + #define BIF_SMU_DATA__BIF_SMU_DATA_MASK 0x7fffc 696 + #define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2 697 + #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0xffc 698 + #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 699 + #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000 700 + #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f 701 + #define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0xffc 702 + #define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 703 + #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0xffc 704 + #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 705 + #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000 706 + #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f 707 + #define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0xffc 708 + #define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 709 + #define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1 710 + #define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0 711 + #define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1 712 + #define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0 713 + #define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2 714 + #define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1 715 + #define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4 716 + #define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2 717 + #define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8 718 + #define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3 719 + #define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10 720 + #define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4 721 + #define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20 722 + #define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5 723 + #define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40 724 + #define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6 725 + #define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80 726 + #define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7 727 + #define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100 728 + #define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8 729 + #define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200 730 + #define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9 731 + #define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400 732 + #define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa 733 + #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800 734 + #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb 735 + #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000 736 + #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc 737 + #define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000 738 + #define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd 739 + #define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000 740 + #define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe 741 + #define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK 0x8000 742 + #define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT 0xf 743 + #define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000 744 + #define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10 745 + #define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK 0x20000 746 + #define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT 0x11 747 + #define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK 0x40000 748 + #define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT 0x12 749 + #define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000 750 + #define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e 751 + #define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000 752 + #define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f 753 + #define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1 754 + #define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0 755 + #define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2 756 + #define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1 757 + #define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc 758 + #define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2 759 + #define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1 760 + #define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0 761 + #define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2 762 + #define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1 763 + #define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc 764 + #define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2 765 + #define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1 766 + #define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0 767 + #define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2 768 + #define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1 769 + #define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc 770 + #define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2 771 + #define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1 772 + #define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0 773 + #define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2 774 + #define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1 775 + #define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc 776 + #define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2 777 + #define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1 778 + #define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0 779 + #define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2 780 + #define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1 781 + #define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc 782 + #define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2 783 + #define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1 784 + #define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0 785 + #define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2 786 + #define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1 787 + #define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc 788 + #define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2 789 + #define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1 790 + #define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0 791 + #define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2 792 + #define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1 793 + #define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc 794 + #define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2 795 + #define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1 796 + #define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0 797 + #define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2 798 + #define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1 799 + #define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc 800 + #define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2 801 + #define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc 802 + #define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2 803 + #define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc 804 + #define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2 805 + #define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc 806 + #define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2 807 + #define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc 808 + #define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2 809 + #define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc 810 + #define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2 811 + #define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc 812 + #define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2 813 + #define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc 814 + #define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2 815 + #define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc 816 + #define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2 817 + #define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1 818 + #define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0 819 + #define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1 820 + #define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0 821 + #define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2 822 + #define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1 823 + #define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4 824 + #define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2 825 + #define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8 826 + #define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3 827 + #define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10 828 + #define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4 829 + #define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20 830 + #define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5 831 + #define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40 832 + #define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6 833 + #define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80 834 + #define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7 835 + #define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100 836 + #define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8 837 + #define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200 838 + #define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9 839 + #define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400 840 + #define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa 841 + #define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800 842 + #define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb 843 + #define GPU_GARLIC_FLUSH_REQ__SDMA2_MASK 0x1000 844 + #define GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT 0xc 845 + #define GPU_GARLIC_FLUSH_REQ__SDMA3_MASK 0x2000 846 + #define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT 0xd 847 + #define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1 848 + #define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0 849 + #define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2 850 + #define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1 851 + #define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4 852 + #define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2 853 + #define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8 854 + #define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3 855 + #define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10 856 + #define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4 857 + #define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20 858 + #define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5 859 + #define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40 860 + #define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6 861 + #define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80 862 + #define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7 863 + #define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100 864 + #define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8 865 + #define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200 866 + #define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9 867 + #define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400 868 + #define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa 869 + #define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800 870 + #define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb 871 + #define GPU_GARLIC_FLUSH_DONE__SDMA2_MASK 0x1000 872 + #define GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT 0xc 873 + #define GPU_GARLIC_FLUSH_DONE__SDMA3_MASK 0x2000 874 + #define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT 0xd 875 + #define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x7fffc 876 + #define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 877 + #define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x7fffc 878 + #define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 879 + #define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff 880 + #define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 881 + #define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff 882 + #define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 883 + #define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff 884 + #define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 885 + #define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff 886 + #define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 887 + #define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff 888 + #define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 889 + #define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff 890 + #define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 891 + #define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff 892 + #define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 893 + #define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff 894 + #define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 895 + #define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff 896 + #define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 897 + #define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff 898 + #define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 899 + #define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff 900 + #define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 901 + #define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff 902 + #define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 903 + #define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff 904 + #define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 905 + #define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff 906 + #define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 907 + #define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff 908 + #define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 909 + #define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff 910 + #define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 911 + #define BIF_RB_CNTL__RB_ENABLE_MASK 0x1 912 + #define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 913 + #define BIF_RB_CNTL__RB_SIZE_MASK 0x3e 914 + #define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 915 + #define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 916 + #define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 917 + #define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00 918 + #define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 919 + #define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x20000 920 + #define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 921 + #define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 922 + #define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 923 + #define BIF_RB_BASE__ADDR_MASK 0xffffffff 924 + #define BIF_RB_BASE__ADDR__SHIFT 0x0 925 + #define BIF_RB_RPTR__OFFSET_MASK 0x3fffc 926 + #define BIF_RB_RPTR__OFFSET__SHIFT 0x2 927 + #define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x1 928 + #define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 929 + #define BIF_RB_WPTR__OFFSET_MASK 0x3fffc 930 + #define BIF_RB_WPTR__OFFSET__SHIFT 0x2 931 + #define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0xff 932 + #define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 933 + #define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc 934 + #define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 935 + #define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0xf 936 + #define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 937 + #define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xffffffff 938 + #define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 939 + #define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xffffffff 940 + #define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 941 + #define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xffffffff 942 + #define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 943 + #define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xffffffff 944 + #define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 945 + #define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xffffffff 946 + #define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 947 + #define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xffffffff 948 + #define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 949 + #define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xffffffff 950 + #define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 951 + #define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xffffffff 952 + #define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 953 + #define MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x1 954 + #define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 955 + #define MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x2 956 + #define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 957 + #define MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x100 958 + #define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 959 + #define MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x200 960 + #define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 961 + #define MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x1 962 + #define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 963 + #define MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x2 964 + #define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 965 + #define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF_MASK 0xffff 966 + #define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF__SHIFT 0x0 967 + #define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF_MASK 0x80000000 968 + #define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF__SHIFT 0x1f 969 + #define VM_INIT_STATUS__VM_INIT_STATUS_MASK 0x1 970 + #define VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0 971 + #define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffff 972 + #define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0 973 + #define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK 0xffffffff 974 + #define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0 975 + #define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE_MASK 0xffff 976 + #define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE__SHIFT 0x0 977 + #define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED_MASK 0xffff0000 978 + #define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED__SHIFT 0x10 979 + #define BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK 0xffffffff 980 + #define BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT 0x0 981 + #define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK 0xffff 982 + #define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT 0x0 983 + #define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK 0xffff0000 984 + #define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT 0x10 985 + #define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK 0xffff 986 + #define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT 0x0 987 + #define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK 0xffff0000 988 + #define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT 0x10 989 + #define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK 0xffff 990 + #define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT 0x0 991 + #define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK 0xffff0000 992 + #define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT 0x10 993 + #define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK 0xffff 994 + #define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT 0x0 995 + #define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK 0xffff0000 996 + #define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT 0x10 997 + #define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK 0xffff 998 + #define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT 0x0 999 + #define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK 0xffff0000 1000 + #define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT 0x10 1001 + #define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK 0xffff 1002 + #define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT 0x0 1003 + #define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK 0xffff0000 1004 + #define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT 0x10 1005 + #define BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK 0xffffffff 1006 + #define BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT 0x0 1007 + #define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK 0xffff 1008 + #define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT 0x0 1009 + #define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK 0xffff0000 1010 + #define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT 0x10 1011 + #define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK 0xffff 1012 + #define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT 0x0 1013 + #define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK 0xffff0000 1014 + #define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT 0x10 1015 + #define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK 0xffff 1016 + #define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT 0x0 1017 + #define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK 0xffff0000 1018 + #define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT 0x10 1019 + #define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK 0xffff 1020 + #define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT 0x0 1021 + #define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK 0xffff0000 1022 + #define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT 0x10 1023 + #define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK 0xffff 1024 + #define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT 0x0 1025 + #define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK 0xffff0000 1026 + #define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT 0x10 1027 + #define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK 0xffff 1028 + #define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT 0x0 1029 + #define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK 0xffff0000 1030 + #define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT 0x10 1031 + #define VENDOR_ID__VENDOR_ID_MASK 0xffff 1032 + #define VENDOR_ID__VENDOR_ID__SHIFT 0x0 1033 + #define DEVICE_ID__DEVICE_ID_MASK 0xffff 1034 + #define DEVICE_ID__DEVICE_ID__SHIFT 0x0 1035 + #define COMMAND__IO_ACCESS_EN_MASK 0x1 1036 + #define COMMAND__IO_ACCESS_EN__SHIFT 0x0 1037 + #define COMMAND__MEM_ACCESS_EN_MASK 0x2 1038 + #define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 1039 + #define COMMAND__BUS_MASTER_EN_MASK 0x4 1040 + #define COMMAND__BUS_MASTER_EN__SHIFT 0x2 1041 + #define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 1042 + #define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 1043 + #define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 1044 + #define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 1045 + #define COMMAND__PAL_SNOOP_EN_MASK 0x20 1046 + #define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 1047 + #define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 1048 + #define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 1049 + #define COMMAND__AD_STEPPING_MASK 0x80 1050 + #define COMMAND__AD_STEPPING__SHIFT 0x7 1051 + #define COMMAND__SERR_EN_MASK 0x100 1052 + #define COMMAND__SERR_EN__SHIFT 0x8 1053 + #define COMMAND__FAST_B2B_EN_MASK 0x200 1054 + #define COMMAND__FAST_B2B_EN__SHIFT 0x9 1055 + #define COMMAND__INT_DIS_MASK 0x400 1056 + #define COMMAND__INT_DIS__SHIFT 0xa 1057 + #define STATUS__INT_STATUS_MASK 0x8 1058 + #define STATUS__INT_STATUS__SHIFT 0x3 1059 + #define STATUS__CAP_LIST_MASK 0x10 1060 + #define STATUS__CAP_LIST__SHIFT 0x4 1061 + #define STATUS__PCI_66_EN_MASK 0x20 1062 + #define STATUS__PCI_66_EN__SHIFT 0x5 1063 + #define STATUS__FAST_BACK_CAPABLE_MASK 0x80 1064 + #define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 1065 + #define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100 1066 + #define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 1067 + #define STATUS__DEVSEL_TIMING_MASK 0x600 1068 + #define STATUS__DEVSEL_TIMING__SHIFT 0x9 1069 + #define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800 1070 + #define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb 1071 + #define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000 1072 + #define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc 1073 + #define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000 1074 + #define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd 1075 + #define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000 1076 + #define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe 1077 + #define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000 1078 + #define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf 1079 + #define REVISION_ID__MINOR_REV_ID_MASK 0xf 1080 + #define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 1081 + #define REVISION_ID__MAJOR_REV_ID_MASK 0xf0 1082 + #define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 1083 + #define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff 1084 + #define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 1085 + #define SUB_CLASS__SUB_CLASS_MASK 0xff 1086 + #define SUB_CLASS__SUB_CLASS__SHIFT 0x0 1087 + #define BASE_CLASS__BASE_CLASS_MASK 0xff 1088 + #define BASE_CLASS__BASE_CLASS__SHIFT 0x0 1089 + #define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff 1090 + #define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 1091 + #define LATENCY__LATENCY_TIMER_MASK 0xff 1092 + #define LATENCY__LATENCY_TIMER__SHIFT 0x0 1093 + #define HEADER__HEADER_TYPE_MASK 0x7f 1094 + #define HEADER__HEADER_TYPE__SHIFT 0x0 1095 + #define HEADER__DEVICE_TYPE_MASK 0x80 1096 + #define HEADER__DEVICE_TYPE__SHIFT 0x7 1097 + #define BIST__BIST_COMP_MASK 0xf 1098 + #define BIST__BIST_COMP__SHIFT 0x0 1099 + #define BIST__BIST_STRT_MASK 0x40 1100 + #define BIST__BIST_STRT__SHIFT 0x6 1101 + #define BIST__BIST_CAP_MASK 0x80 1102 + #define BIST__BIST_CAP__SHIFT 0x7 1103 + #define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff 1104 + #define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 1105 + #define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff 1106 + #define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 1107 + #define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff 1108 + #define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 1109 + #define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff 1110 + #define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 1111 + #define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff 1112 + #define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 1113 + #define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff 1114 + #define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 1115 + #define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff 1116 + #define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 1117 + #define CAP_PTR__CAP_PTR_MASK 0xff 1118 + #define CAP_PTR__CAP_PTR__SHIFT 0x0 1119 + #define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff 1120 + #define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 1121 + #define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff 1122 + #define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 1123 + #define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff 1124 + #define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 1125 + #define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000 1126 + #define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 1127 + #define MIN_GRANT__MIN_GNT_MASK 0xff 1128 + #define MIN_GRANT__MIN_GNT__SHIFT 0x0 1129 + #define MAX_LATENCY__MAX_LAT_MASK 0xff 1130 + #define MAX_LATENCY__MAX_LAT__SHIFT 0x0 1131 + #define VENDOR_CAP_LIST__CAP_ID_MASK 0xff 1132 + #define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 1133 + #define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00 1134 + #define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 1135 + #define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000 1136 + #define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 1137 + #define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff 1138 + #define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 1139 + #define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000 1140 + #define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 1141 + #define PMI_CAP_LIST__CAP_ID_MASK 0xff 1142 + #define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 1143 + #define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 1144 + #define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 1145 + #define PMI_CAP__VERSION_MASK 0x7 1146 + #define PMI_CAP__VERSION__SHIFT 0x0 1147 + #define PMI_CAP__PME_CLOCK_MASK 0x8 1148 + #define PMI_CAP__PME_CLOCK__SHIFT 0x3 1149 + #define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20 1150 + #define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 1151 + #define PMI_CAP__AUX_CURRENT_MASK 0x1c0 1152 + #define PMI_CAP__AUX_CURRENT__SHIFT 0x6 1153 + #define PMI_CAP__D1_SUPPORT_MASK 0x200 1154 + #define PMI_CAP__D1_SUPPORT__SHIFT 0x9 1155 + #define PMI_CAP__D2_SUPPORT_MASK 0x400 1156 + #define PMI_CAP__D2_SUPPORT__SHIFT 0xa 1157 + #define PMI_CAP__PME_SUPPORT_MASK 0xf800 1158 + #define PMI_CAP__PME_SUPPORT__SHIFT 0xb 1159 + #define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 1160 + #define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 1161 + #define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 1162 + #define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 1163 + #define PMI_STATUS_CNTL__PME_EN_MASK 0x100 1164 + #define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 1165 + #define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 1166 + #define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 1167 + #define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 1168 + #define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd 1169 + #define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 1170 + #define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf 1171 + #define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 1172 + #define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 1173 + #define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 1174 + #define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 1175 + #define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 1176 + #define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 1177 + #define PCIE_CAP_LIST__CAP_ID_MASK 0xff 1178 + #define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 1179 + #define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 1180 + #define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 1181 + #define PCIE_CAP__VERSION_MASK 0xf 1182 + #define PCIE_CAP__VERSION__SHIFT 0x0 1183 + #define PCIE_CAP__DEVICE_TYPE_MASK 0xf0 1184 + #define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 1185 + #define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100 1186 + #define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 1187 + #define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00 1188 + #define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 1189 + #define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 1190 + #define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 1191 + #define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 1192 + #define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 1193 + #define DEVICE_CAP__EXTENDED_TAG_MASK 0x20 1194 + #define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 1195 + #define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 1196 + #define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 1197 + #define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 1198 + #define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 1199 + #define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 1200 + #define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf 1201 + #define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 1202 + #define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 1203 + #define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 1204 + #define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a 1205 + #define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 1206 + #define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c 1207 + #define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 1208 + #define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 1209 + #define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 1210 + #define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 1211 + #define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 1212 + #define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 1213 + #define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 1214 + #define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 1215 + #define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 1216 + #define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 1217 + #define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 1218 + #define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 1219 + #define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 1220 + #define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 1221 + #define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 1222 + #define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 1223 + #define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 1224 + #define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa 1225 + #define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 1226 + #define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb 1227 + #define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 1228 + #define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc 1229 + #define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000 1230 + #define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf 1231 + #define DEVICE_STATUS__CORR_ERR_MASK 0x1 1232 + #define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 1233 + #define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2 1234 + #define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 1235 + #define DEVICE_STATUS__FATAL_ERR_MASK 0x4 1236 + #define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 1237 + #define DEVICE_STATUS__USR_DETECTED_MASK 0x8 1238 + #define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 1239 + #define DEVICE_STATUS__AUX_PWR_MASK 0x10 1240 + #define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 1241 + #define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20 1242 + #define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 1243 + #define LINK_CAP__LINK_SPEED_MASK 0xf 1244 + #define LINK_CAP__LINK_SPEED__SHIFT 0x0 1245 + #define LINK_CAP__LINK_WIDTH_MASK 0x3f0 1246 + #define LINK_CAP__LINK_WIDTH__SHIFT 0x4 1247 + #define LINK_CAP__PM_SUPPORT_MASK 0xc00 1248 + #define LINK_CAP__PM_SUPPORT__SHIFT 0xa 1249 + #define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 1250 + #define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc 1251 + #define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 1252 + #define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf 1253 + #define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 1254 + #define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 1255 + #define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 1256 + #define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 1257 + #define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 1258 + #define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 1259 + #define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 1260 + #define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 1261 + #define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 1262 + #define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 1263 + #define LINK_CAP__PORT_NUMBER_MASK 0xff000000 1264 + #define LINK_CAP__PORT_NUMBER__SHIFT 0x18 1265 + #define LINK_CNTL__PM_CONTROL_MASK 0x3 1266 + #define LINK_CNTL__PM_CONTROL__SHIFT 0x0 1267 + #define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 1268 + #define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 1269 + #define LINK_CNTL__LINK_DIS_MASK 0x10 1270 + #define LINK_CNTL__LINK_DIS__SHIFT 0x4 1271 + #define LINK_CNTL__RETRAIN_LINK_MASK 0x20 1272 + #define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 1273 + #define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 1274 + #define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 1275 + #define LINK_CNTL__EXTENDED_SYNC_MASK 0x80 1276 + #define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 1277 + #define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 1278 + #define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 1279 + #define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 1280 + #define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 1281 + #define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 1282 + #define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa 1283 + #define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 1284 + #define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb 1285 + #define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf 1286 + #define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 1287 + #define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0 1288 + #define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 1289 + #define LINK_STATUS__LINK_TRAINING_MASK 0x800 1290 + #define LINK_STATUS__LINK_TRAINING__SHIFT 0xb 1291 + #define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000 1292 + #define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc 1293 + #define LINK_STATUS__DL_ACTIVE_MASK 0x2000 1294 + #define LINK_STATUS__DL_ACTIVE__SHIFT 0xd 1295 + #define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000 1296 + #define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe 1297 + #define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000 1298 + #define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf 1299 + #define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf 1300 + #define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 1301 + #define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 1302 + #define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 1303 + #define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 1304 + #define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 1305 + #define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 1306 + #define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 1307 + #define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 1308 + #define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 1309 + #define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 1310 + #define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 1311 + #define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 1312 + #define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 1313 + #define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 1314 + #define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa 1315 + #define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 1316 + #define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb 1317 + #define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 1318 + #define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc 1319 + #define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 1320 + #define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 1321 + #define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 1322 + #define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 1323 + #define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 1324 + #define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 1325 + #define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 1326 + #define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 1327 + #define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf 1328 + #define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 1329 + #define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 1330 + #define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 1331 + #define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 1332 + #define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 1333 + #define DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 1334 + #define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 1335 + #define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 1336 + #define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 1337 + #define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 1338 + #define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 1339 + #define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 1340 + #define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 1341 + #define DEVICE_CNTL2__LTR_EN_MASK 0x400 1342 + #define DEVICE_CNTL2__LTR_EN__SHIFT 0xa 1343 + #define DEVICE_CNTL2__OBFF_EN_MASK 0x6000 1344 + #define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd 1345 + #define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 1346 + #define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf 1347 + #define DEVICE_STATUS2__RESERVED_MASK 0xffff 1348 + #define DEVICE_STATUS2__RESERVED__SHIFT 0x0 1349 + #define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe 1350 + #define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 1351 + #define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 1352 + #define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 1353 + #define LINK_CAP2__RESERVED_MASK 0xfffffe00 1354 + #define LINK_CAP2__RESERVED__SHIFT 0x9 1355 + #define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf 1356 + #define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 1357 + #define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 1358 + #define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 1359 + #define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 1360 + #define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 1361 + #define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 1362 + #define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 1363 + #define LINK_CNTL2__XMIT_MARGIN_MASK 0x380 1364 + #define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 1365 + #define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 1366 + #define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa 1367 + #define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 1368 + #define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb 1369 + #define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 1370 + #define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc 1371 + #define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1 1372 + #define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 1373 + #define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2 1374 + #define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 1375 + #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4 1376 + #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 1377 + #define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8 1378 + #define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 1379 + #define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10 1380 + #define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 1381 + #define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20 1382 + #define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 1383 + #define MSI_CAP_LIST__CAP_ID_MASK 0xff 1384 + #define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 1385 + #define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 1386 + #define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 1387 + #define MSI_MSG_CNTL__MSI_EN_MASK 0x1 1388 + #define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 1389 + #define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe 1390 + #define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 1391 + #define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70 1392 + #define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 1393 + #define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80 1394 + #define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 1395 + #define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x100 1396 + #define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 1397 + #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc 1398 + #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 1399 + #define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff 1400 + #define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 1401 + #define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff 1402 + #define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 1403 + #define MSI_MSG_DATA__MSI_DATA_MASK 0xffff 1404 + #define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 1405 + #define MSI_MASK__MSI_MASK_MASK 0xffffffff 1406 + #define MSI_MASK__MSI_MASK__SHIFT 0x0 1407 + #define MSI_PENDING__MSI_PENDING_MASK 0xffffffff 1408 + #define MSI_PENDING__MSI_PENDING__SHIFT 0x0 1409 + #define MSI_MASK_64__MSI_MASK_64_MASK 0xffffffff 1410 + #define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 1411 + #define MSI_PENDING_64__MSI_PENDING_64_MASK 0xffffffff 1412 + #define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 1413 + #define MSIX_CAP_LIST__CAP_ID_MASK 0xff 1414 + #define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 1415 + #define MSIX_CAP_LIST__NEXT_PTR_MASK 0xff00 1416 + #define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 1417 + #define MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x7ff 1418 + #define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 1419 + #define MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000 1420 + #define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe 1421 + #define MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000 1422 + #define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf 1423 + #define MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x7 1424 + #define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 1425 + #define MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xfffffff8 1426 + #define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 1427 + #define MSIX_PBA__MSIX_PBA_BIR_MASK 0x7 1428 + #define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 1429 + #define MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xfffffff8 1430 + #define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 1431 + #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1432 + #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1433 + #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1434 + #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1435 + #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1436 + #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1437 + #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff 1438 + #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 1439 + #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 1440 + #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 1441 + #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 1442 + #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 1443 + #define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff 1444 + #define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 1445 + #define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff 1446 + #define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 1447 + #define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1448 + #define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1449 + #define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1450 + #define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1451 + #define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1452 + #define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1453 + #define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 1454 + #define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 1455 + #define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 1456 + #define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 1457 + #define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 1458 + #define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 1459 + #define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 1460 + #define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa 1461 + #define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff 1462 + #define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 1463 + #define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 1464 + #define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 1465 + #define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 1466 + #define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 1467 + #define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe 1468 + #define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 1469 + #define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1 1470 + #define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 1471 + #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff 1472 + #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 1473 + #define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 1474 + #define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf 1475 + #define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 1476 + #define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 1477 + #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 1478 + #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 1479 + #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 1480 + #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 1481 + #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe 1482 + #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 1483 + #define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 1484 + #define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 1485 + #define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 1486 + #define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 1487 + #define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 1488 + #define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 1489 + #define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 1490 + #define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f 1491 + #define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 1492 + #define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 1493 + #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 1494 + #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 1495 + #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff 1496 + #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 1497 + #define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 1498 + #define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf 1499 + #define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 1500 + #define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 1501 + #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 1502 + #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 1503 + #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 1504 + #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 1505 + #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe 1506 + #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 1507 + #define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 1508 + #define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 1509 + #define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 1510 + #define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 1511 + #define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 1512 + #define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 1513 + #define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 1514 + #define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f 1515 + #define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 1516 + #define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 1517 + #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 1518 + #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 1519 + #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1520 + #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1521 + #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1522 + #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1523 + #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1524 + #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1525 + #define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff 1526 + #define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 1527 + #define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff 1528 + #define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 1529 + #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1530 + #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1531 + #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1532 + #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1533 + #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1534 + #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1535 + #define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 1536 + #define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 1537 + #define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 1538 + #define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 1539 + #define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 1540 + #define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc 1541 + #define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 1542 + #define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd 1543 + #define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 1544 + #define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe 1545 + #define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 1546 + #define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf 1547 + #define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 1548 + #define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 1549 + #define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 1550 + #define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 1551 + #define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 1552 + #define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 1553 + #define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 1554 + #define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 1555 + #define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 1556 + #define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 1557 + #define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 1558 + #define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 1559 + #define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 1560 + #define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 1561 + #define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 1562 + #define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 1563 + #define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 1564 + #define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 1565 + #define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 1566 + #define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 1567 + #define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 1568 + #define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 1569 + #define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 1570 + #define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 1571 + #define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 1572 + #define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc 1573 + #define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 1574 + #define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd 1575 + #define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 1576 + #define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe 1577 + #define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 1578 + #define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf 1579 + #define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 1580 + #define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 1581 + #define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 1582 + #define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 1583 + #define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 1584 + #define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 1585 + #define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 1586 + #define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 1587 + #define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 1588 + #define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 1589 + #define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 1590 + #define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 1591 + #define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 1592 + #define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 1593 + #define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 1594 + #define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 1595 + #define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 1596 + #define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 1597 + #define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 1598 + #define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 1599 + #define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 1600 + #define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 1601 + #define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 1602 + #define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 1603 + #define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 1604 + #define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc 1605 + #define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 1606 + #define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd 1607 + #define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 1608 + #define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe 1609 + #define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 1610 + #define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf 1611 + #define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 1612 + #define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 1613 + #define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 1614 + #define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 1615 + #define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 1616 + #define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 1617 + #define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 1618 + #define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 1619 + #define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 1620 + #define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 1621 + #define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 1622 + #define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 1623 + #define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 1624 + #define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 1625 + #define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 1626 + #define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 1627 + #define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 1628 + #define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 1629 + #define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 1630 + #define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 1631 + #define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 1632 + #define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 1633 + #define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 1634 + #define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 1635 + #define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 1636 + #define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 1637 + #define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 1638 + #define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 1639 + #define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 1640 + #define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc 1641 + #define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 1642 + #define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd 1643 + #define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 1644 + #define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe 1645 + #define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 1646 + #define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf 1647 + #define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 1648 + #define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 1649 + #define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 1650 + #define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 1651 + #define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 1652 + #define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 1653 + #define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 1654 + #define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 1655 + #define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 1656 + #define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc 1657 + #define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 1658 + #define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd 1659 + #define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 1660 + #define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe 1661 + #define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 1662 + #define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf 1663 + #define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f 1664 + #define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 1665 + #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 1666 + #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 1667 + #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 1668 + #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 1669 + #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 1670 + #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 1671 + #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 1672 + #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 1673 + #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 1674 + #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 1675 + #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 1676 + #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa 1677 + #define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 1678 + #define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb 1679 + #define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff 1680 + #define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 1681 + #define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff 1682 + #define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 1683 + #define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff 1684 + #define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 1685 + #define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff 1686 + #define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 1687 + #define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff 1688 + #define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 1689 + #define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff 1690 + #define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 1691 + #define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff 1692 + #define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 1693 + #define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff 1694 + #define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 1695 + #define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1696 + #define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1697 + #define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1698 + #define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1699 + #define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1700 + #define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1701 + #define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 1702 + #define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 1703 + #define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7 1704 + #define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 1705 + #define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0 1706 + #define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 1707 + #define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00 1708 + #define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 1709 + #define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 1710 + #define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 1711 + #define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7 1712 + #define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 1713 + #define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0 1714 + #define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 1715 + #define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00 1716 + #define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 1717 + #define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 1718 + #define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 1719 + #define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7 1720 + #define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 1721 + #define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0 1722 + #define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 1723 + #define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00 1724 + #define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 1725 + #define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 1726 + #define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 1727 + #define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7 1728 + #define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 1729 + #define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0 1730 + #define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 1731 + #define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00 1732 + #define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 1733 + #define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 1734 + #define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 1735 + #define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7 1736 + #define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 1737 + #define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0 1738 + #define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 1739 + #define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00 1740 + #define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 1741 + #define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 1742 + #define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 1743 + #define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7 1744 + #define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 1745 + #define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0 1746 + #define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 1747 + #define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00 1748 + #define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 1749 + #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1750 + #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1751 + #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1752 + #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1753 + #define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1754 + #define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1755 + #define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff 1756 + #define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 1757 + #define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff 1758 + #define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 1759 + #define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300 1760 + #define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 1761 + #define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00 1762 + #define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa 1763 + #define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000 1764 + #define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd 1765 + #define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000 1766 + #define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf 1767 + #define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000 1768 + #define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 1769 + #define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1 1770 + #define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 1771 + #define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1772 + #define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1773 + #define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1774 + #define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1775 + #define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1776 + #define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1777 + #define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f 1778 + #define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 1779 + #define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 1780 + #define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 1781 + #define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 1782 + #define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc 1783 + #define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 1784 + #define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 1785 + #define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 1786 + #define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 1787 + #define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff 1788 + #define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 1789 + #define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f 1790 + #define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 1791 + #define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100 1792 + #define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 1793 + #define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f 1794 + #define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 1795 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff 1796 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1797 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff 1798 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1799 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff 1800 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1801 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff 1802 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1803 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff 1804 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1805 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff 1806 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1807 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff 1808 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1809 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff 1810 + #define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 1811 + #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1812 + #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1813 + #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1814 + #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1815 + #define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1816 + #define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1817 + #define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 1818 + #define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 1819 + #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 1820 + #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 1821 + #define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc 1822 + #define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 1823 + #define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff 1824 + #define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 1825 + #define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 1826 + #define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 1827 + #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1828 + #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1829 + #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1830 + #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1831 + #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1832 + #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1833 + #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1834 + #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1835 + #define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1836 + #define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1837 + #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1838 + #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1839 + #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1840 + #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1841 + #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1842 + #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1843 + #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1844 + #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1845 + #define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1846 + #define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1847 + #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1848 + #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1849 + #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1850 + #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1851 + #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1852 + #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1853 + #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1854 + #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1855 + #define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1856 + #define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1857 + #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1858 + #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1859 + #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1860 + #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1861 + #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1862 + #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1863 + #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1864 + #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1865 + #define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1866 + #define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1867 + #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1868 + #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1869 + #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1870 + #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1871 + #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1872 + #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1873 + #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1874 + #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1875 + #define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1876 + #define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1877 + #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1878 + #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1879 + #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1880 + #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1881 + #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1882 + #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1883 + #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1884 + #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1885 + #define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1886 + #define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1887 + #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1888 + #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1889 + #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1890 + #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1891 + #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1892 + #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1893 + #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1894 + #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1895 + #define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1896 + #define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1897 + #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1898 + #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1899 + #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1900 + #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1901 + #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1902 + #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1903 + #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1904 + #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1905 + #define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1906 + #define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1907 + #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1908 + #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1909 + #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1910 + #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1911 + #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1912 + #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1913 + #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1914 + #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1915 + #define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1916 + #define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1917 + #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1918 + #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1919 + #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1920 + #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1921 + #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1922 + #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1923 + #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1924 + #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1925 + #define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1926 + #define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1927 + #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1928 + #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1929 + #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1930 + #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1931 + #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1932 + #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1933 + #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1934 + #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1935 + #define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1936 + #define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1937 + #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1938 + #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1939 + #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1940 + #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1941 + #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1942 + #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1943 + #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1944 + #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1945 + #define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1946 + #define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1947 + #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1948 + #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1949 + #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1950 + #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1951 + #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1952 + #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1953 + #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1954 + #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1955 + #define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1956 + #define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1957 + #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1958 + #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1959 + #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1960 + #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1961 + #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1962 + #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1963 + #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1964 + #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1965 + #define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1966 + #define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1967 + #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1968 + #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1969 + #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1970 + #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1971 + #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1972 + #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1973 + #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1974 + #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1975 + #define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1976 + #define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1977 + #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf 1978 + #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 1979 + #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 1980 + #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 1981 + #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 1982 + #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 1983 + #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 1984 + #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 1985 + #define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 1986 + #define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 1987 + #define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff 1988 + #define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 1989 + #define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 1990 + #define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 1991 + #define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 1992 + #define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 1993 + #define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 1994 + #define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 1995 + #define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 1996 + #define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 1997 + #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 1998 + #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 1999 + #define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 2000 + #define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 2001 + #define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 2002 + #define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 2003 + #define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 2004 + #define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 2005 + #define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 2006 + #define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 2007 + #define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 2008 + #define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 2009 + #define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1 2010 + #define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 2011 + #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2 2012 + #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 2013 + #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4 2014 + #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 2015 + #define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8 2016 + #define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 2017 + #define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10 2018 + #define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 2019 + #define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20 2020 + #define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 2021 + #define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40 2022 + #define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 2023 + #define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff 2024 + #define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 2025 + #define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 2026 + #define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 2027 + #define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 2028 + #define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 2029 + #define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f 2030 + #define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 2031 + #define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20 2032 + #define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 2033 + #define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40 2034 + #define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 2035 + #define PCIE_ATS_CNTL__STU_MASK 0x1f 2036 + #define PCIE_ATS_CNTL__STU__SHIFT 0x0 2037 + #define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000 2038 + #define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf 2039 + #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff 2040 + #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 2041 + #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 2042 + #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 2043 + #define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 2044 + #define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 2045 + #define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1 2046 + #define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 2047 + #define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2 2048 + #define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 2049 + #define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1 2050 + #define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 2051 + #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2 2052 + #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 2053 + #define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100 2054 + #define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 2055 + #define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000 2056 + #define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf 2057 + #define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff 2058 + #define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 2059 + #define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff 2060 + #define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 2061 + #define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff 2062 + #define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 2063 + #define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 2064 + #define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 2065 + #define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 2066 + #define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 2067 + #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2 2068 + #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 2069 + #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4 2070 + #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 2071 + #define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00 2072 + #define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 2073 + #define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1 2074 + #define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 2075 + #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2 2076 + #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 2077 + #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4 2078 + #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 2079 + #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff 2080 + #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 2081 + #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 2082 + #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 2083 + #define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 2084 + #define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 2085 + #define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1 2086 + #define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 2087 + #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2 2088 + #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 2089 + #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4 2090 + #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 2091 + #define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100 2092 + #define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 2093 + #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600 2094 + #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 2095 + #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000 2096 + #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 2097 + #define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7 2098 + #define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 2099 + #define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300 2100 + #define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 2101 + #define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff 2102 + #define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 2103 + #define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 2104 + #define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 2105 + #define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 2106 + #define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 2107 + #define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f 2108 + #define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 2109 + #define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00 2110 + #define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 2111 + #define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 2112 + #define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf 2113 + #define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f 2114 + #define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 2115 + #define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000 2116 + #define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf 2117 + #define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f 2118 + #define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 2119 + #define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 2120 + #define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc 2121 + #define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff 2122 + #define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 2123 + #define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff 2124 + #define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 2125 + #define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff 2126 + #define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 2127 + #define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff 2128 + #define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 2129 + #define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff 2130 + #define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 2131 + #define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff 2132 + #define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 2133 + #define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff 2134 + #define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 2135 + #define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff 2136 + #define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 2137 + #define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 2138 + #define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 2139 + #define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 2140 + #define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 2141 + #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff 2142 + #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 2143 + #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00 2144 + #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa 2145 + #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000 2146 + #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 2147 + #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000 2148 + #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a 2149 + #define PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0xffff 2150 + #define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 2151 + #define PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 2152 + #define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 2153 + #define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 2154 + #define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 2155 + #define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x1 2156 + #define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 2157 + #define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x2 2158 + #define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 2159 + #define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xff00 2160 + #define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 2161 + #define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x1 2162 + #define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 2163 + #define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x2 2164 + #define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 2165 + #define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x70 2166 + #define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 2167 + #define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0xffff 2168 + #define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 2169 + #define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 2170 + #define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 2171 + #define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 2172 + #define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 2173 + #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x1 2174 + #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 2175 + #define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x2 2176 + #define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 2177 + #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xffe00000 2178 + #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 2179 + #define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x1 2180 + #define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 2181 + #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x2 2182 + #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 2183 + #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x4 2184 + #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 2185 + #define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x8 2186 + #define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 2187 + #define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x10 2188 + #define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 2189 + #define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x1 2190 + #define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 2191 + #define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xffff 2192 + #define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 2193 + #define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xffff 2194 + #define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 2195 + #define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xffff 2196 + #define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 2197 + #define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xff 2198 + #define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 2199 + #define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xffff 2200 + #define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 2201 + #define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xffff 2202 + #define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 2203 + #define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xffff 2204 + #define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 2205 + #define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xffffffff 2206 + #define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 2207 + #define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xffffffff 2208 + #define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 2209 + #define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xffffffff 2210 + #define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 2211 + #define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xffffffff 2212 + #define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 2213 + #define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xffffffff 2214 + #define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 2215 + #define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xffffffff 2216 + #define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 2217 + #define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xffffffff 2218 + #define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 2219 + #define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xffffffff 2220 + #define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 2221 + #define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xffffffff 2222 + #define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x0 2223 + #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0xffff 2224 + #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 2225 + #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0xf0000 2226 + #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 2227 + #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xfff00000 2228 + #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 2229 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0xffff 2230 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 2231 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0xf0000 2232 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 2233 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xfff00000 2234 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 2235 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x1 2236 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 2237 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xffff0000 2238 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 2239 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL_MASK 0xff 2240 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL__SHIFT 0x0 2241 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID_MASK 0xff00 2242 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID__SHIFT 0x8 2243 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID_MASK 0xff0000 2244 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID__SHIFT 0x10 2245 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS_MASK 0xff 2246 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS__SHIFT 0x0 2247 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x1 2248 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 2249 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffff 2250 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0 2251 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK 0xffffffff 2252 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0 2253 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE_MASK 0x7f 2254 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE__SHIFT 0x0 2255 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x80 2256 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 2257 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET_MASK 0xfffc0000 2258 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET__SHIFT 0x12 2259 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xffff 2260 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x0 2261 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0xffff0000 2262 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x10 2263 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff 2264 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 2265 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET_MASK 0xff00 2266 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET__SHIFT 0x8 2267 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET_MASK 0xff0000 2268 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET__SHIFT 0x10 2269 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET_MASK 0xff000000 2270 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET__SHIFT 0x18 2271 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET_MASK 0xffff 2272 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET__SHIFT 0x0 2273 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE_MASK 0xffff0000 2274 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE__SHIFT 0x10 2275 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET_MASK 0xffff 2276 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET__SHIFT 0x0 2277 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE_MASK 0xffff0000 2278 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE__SHIFT 0x10 2279 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET_MASK 0xffff 2280 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET__SHIFT 0x0 2281 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE_MASK 0xffff0000 2282 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE__SHIFT 0x10 2283 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET_MASK 0xffff 2284 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET__SHIFT 0x0 2285 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE_MASK 0xffff0000 2286 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE__SHIFT 0x10 2287 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET_MASK 0xffff 2288 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET__SHIFT 0x0 2289 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE_MASK 0xffff0000 2290 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE__SHIFT 0x10 2291 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET_MASK 0xffff 2292 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET__SHIFT 0x0 2293 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE_MASK 0xffff0000 2294 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE__SHIFT 0x10 2295 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET_MASK 0xffff 2296 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET__SHIFT 0x0 2297 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE_MASK 0xffff0000 2298 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE__SHIFT 0x10 2299 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET_MASK 0xffff 2300 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET__SHIFT 0x0 2301 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE_MASK 0xffff0000 2302 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE__SHIFT 0x10 2303 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET_MASK 0xffff 2304 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET__SHIFT 0x0 2305 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE_MASK 0xffff0000 2306 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE__SHIFT 0x10 2307 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET_MASK 0xffff 2308 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET__SHIFT 0x0 2309 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE_MASK 0xffff0000 2310 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE__SHIFT 0x10 2311 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET_MASK 0xffff 2312 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET__SHIFT 0x0 2313 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE_MASK 0xffff0000 2314 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE__SHIFT 0x10 2315 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET_MASK 0xffff 2316 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET__SHIFT 0x0 2317 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE_MASK 0xffff0000 2318 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE__SHIFT 0x10 2319 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET_MASK 0xffff 2320 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET__SHIFT 0x0 2321 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE_MASK 0xffff0000 2322 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE__SHIFT 0x10 2323 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET_MASK 0xffff 2324 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET__SHIFT 0x0 2325 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE_MASK 0xffff0000 2326 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE__SHIFT 0x10 2327 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET_MASK 0xffff 2328 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET__SHIFT 0x0 2329 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE_MASK 0xffff0000 2330 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE__SHIFT 0x10 2331 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET_MASK 0xffff 2332 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET__SHIFT 0x0 2333 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE_MASK 0xffff0000 2334 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE__SHIFT 0x10 2335 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY_MASK 0xffffffff 2336 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY__SHIFT 0x0 2337 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER_MASK 0xffff 2338 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER__SHIFT 0x0 2339 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER_MASK 0xffff0000 2340 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER__SHIFT 0x10 2341 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER_MASK 0xffff 2342 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER__SHIFT 0x0 2343 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER_MASK 0xffff0000 2344 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER__SHIFT 0x10 2345 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER_MASK 0xffff 2346 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER__SHIFT 0x0 2347 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER_MASK 0xffff0000 2348 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER__SHIFT 0x10 2349 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER_MASK 0xffff 2350 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER__SHIFT 0x0 2351 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER_MASK 0xffff0000 2352 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER__SHIFT 0x10 2353 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER_MASK 0xffff 2354 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER__SHIFT 0x0 2355 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER_MASK 0xffff0000 2356 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER__SHIFT 0x10 2357 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER_MASK 0xffff 2358 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER__SHIFT 0x0 2359 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER_MASK 0xffff0000 2360 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER__SHIFT 0x10 2361 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA_MASK 0xffffffff 2362 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA__SHIFT 0x0 2363 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA_MASK 0xffffffff 2364 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA__SHIFT 0x0 2365 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA_MASK 0xffffffff 2366 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA__SHIFT 0x0 2367 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA_MASK 0xffffffff 2368 + #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA__SHIFT 0x0 2369 + #define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff 2370 + #define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 2371 + #define PCIE_DATA__PCIE_DATA_MASK 0xffffffff 2372 + #define PCIE_DATA__PCIE_DATA__SHIFT 0x0 2373 + #define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff 2374 + #define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0 2375 + #define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff 2376 + #define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0 2377 + #define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A_MASK 0x1 2378 + #define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A__SHIFT 0x0 2379 + #define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1 2380 + #define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0 2381 + #define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2 2382 + #define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1 2383 + #define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4 2384 + #define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2 2385 + #define LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8 2386 + #define LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3 2387 + #define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10 2388 + #define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4 2389 + #define CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff 2390 + #define CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0 2391 + #define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7 2392 + #define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0 2393 + #define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70 2394 + #define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4 2395 + #define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff 2396 + #define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0 2397 + #define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000 2398 + #define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10 2399 + #define LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff 2400 + #define LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0 2401 + #define LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff 2402 + #define LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0 2403 + #define LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff 2404 + #define LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0 2405 + #define PCIE_EFUSE__PCIE_EFUSE_VALID_MASK 0x2 2406 + #define PCIE_EFUSE__PCIE_EFUSE_VALID__SHIFT 0x1 2407 + #define PCIE_EFUSE__PPHY_EFUSE_VALID_MASK 0x4 2408 + #define PCIE_EFUSE__PPHY_EFUSE_VALID__SHIFT 0x2 2409 + #define PCIE_EFUSE__SPARE_5_3_EFUSE0_MASK 0x38 2410 + #define PCIE_EFUSE__SPARE_5_3_EFUSE0__SHIFT 0x3 2411 + #define PCIE_EFUSE__ISTRAP_ARBEN0_MASK 0x40 2412 + #define PCIE_EFUSE__ISTRAP_ARBEN0__SHIFT 0x6 2413 + #define PCIE_EFUSE__SPARE_26_7_EFUSE0_MASK 0x7ffff80 2414 + #define PCIE_EFUSE__SPARE_26_7_EFUSE0__SHIFT 0x7 2415 + #define PCIE_EFUSE__CHIP_BIF_MODE_MASK 0x8000000 2416 + #define PCIE_EFUSE__CHIP_BIF_MODE__SHIFT 0x1b 2417 + #define PCIE_EFUSE__SPARE_31_28_EFUSE0_MASK 0xf0000000 2418 + #define PCIE_EFUSE__SPARE_31_28_EFUSE0__SHIFT 0x1c 2419 + #define PCIE_EFUSE2__SPARE_31_1_EFUSE2_MASK 0xfffffffe 2420 + #define PCIE_EFUSE2__SPARE_31_1_EFUSE2__SHIFT 0x1 2421 + #define PCIE_EFUSE3__STRAP_CEC_ID_MASK 0x1fffe 2422 + #define PCIE_EFUSE3__STRAP_CEC_ID__SHIFT 0x1 2423 + #define PCIE_EFUSE3__STRAP_BIF_KILL_GEN3_MASK 0x20000 2424 + #define PCIE_EFUSE3__STRAP_BIF_KILL_GEN3__SHIFT 0x11 2425 + #define PCIE_EFUSE3__SPARE_14_PCIEFUSE3_MASK 0xfffc0000 2426 + #define PCIE_EFUSE3__SPARE_14_PCIEFUSE3__SHIFT 0x12 2427 + #define PCIE_EFUSE4__CC_WRITE_DISABLE_MASK 0x1 2428 + #define PCIE_EFUSE4__CC_WRITE_DISABLE__SHIFT 0x0 2429 + #define PCIE_EFUSE4__SPARE_3_PCIEFUSE4_MASK 0xe 2430 + #define PCIE_EFUSE4__SPARE_3_PCIEFUSE4__SHIFT 0x1 2431 + #define PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID_MASK 0xffff0 2432 + #define PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID__SHIFT 0x4 2433 + #define PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID_MASK 0xf00000 2434 + #define PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID__SHIFT 0x14 2435 + #define PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID_MASK 0xf000000 2436 + #define PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID__SHIFT 0x18 2437 + #define PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK 0xf0000000 2438 + #define PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT 0x1c 2439 + #define PCIE_EFUSE5__STRAP_AZALIA_DID_MASK 0x1fffe 2440 + #define PCIE_EFUSE5__STRAP_AZALIA_DID__SHIFT 0x1 2441 + #define PCIE_EFUSE5__SPARE_16_PCIEFUSE5_MASK 0xfffe0000 2442 + #define PCIE_EFUSE5__SPARE_16_PCIEFUSE5__SHIFT 0x11 2443 + #define PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES_MASK 0x1fffe 2444 + #define PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES__SHIFT 0x1 2445 + #define PCIE_EFUSE6__SPARE_15_PCIEFUSE6_MASK 0xfffe0000 2446 + #define PCIE_EFUSE6__SPARE_15_PCIEFUSE6__SHIFT 0x11 2447 + #define PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID_MASK 0x1fffe 2448 + #define PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID__SHIFT 0x1 2449 + #define PCIE_EFUSE7__SPARE_15_PCIEFUSE7_MASK 0xfffe0000 2450 + #define PCIE_EFUSE7__SPARE_15_PCIEFUSE7__SHIFT 0x11 2451 + #define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff 2452 + #define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0 2453 + #define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff 2454 + #define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0 2455 + #define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1 2456 + #define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0 2457 + #define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1 2458 + #define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0 2459 + #define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1 2460 + #define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0 2461 + #define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2 2462 + #define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1 2463 + #define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY_MASK 0x2 2464 + #define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY__SHIFT 0x1 2465 + #define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4 2466 + #define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2 2467 + #define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7 2468 + #define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0 2469 + #define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70 2470 + #define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4 2471 + #define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80 2472 + #define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7 2473 + #define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100 2474 + #define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8 2475 + #define PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xffff 2476 + #define PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0 2477 + #define PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000 2478 + #define PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10 2479 + #define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1 2480 + #define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0 2481 + #define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1 2482 + #define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0 2483 + #define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1 2484 + #define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0 2485 + #define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1 2486 + #define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0 2487 + #define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff 2488 + #define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 2489 + #define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff 2490 + #define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 2491 + #define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1 2492 + #define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 2493 + #define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2 2494 + #define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 2495 + #define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4 2496 + #define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 2497 + #define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8 2498 + #define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 2499 + #define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10 2500 + #define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 2501 + #define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20 2502 + #define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 2503 + #define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40 2504 + #define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 2505 + #define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80 2506 + #define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 2507 + #define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100 2508 + #define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 2509 + #define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200 2510 + #define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 2511 + #define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400 2512 + #define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa 2513 + #define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800 2514 + #define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb 2515 + #define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 2516 + #define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc 2517 + #define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 2518 + #define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd 2519 + #define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 2520 + #define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe 2521 + #define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 2522 + #define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf 2523 + #define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff 2524 + #define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 2525 + #define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff 2526 + #define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 2527 + #define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1 2528 + #define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 2529 + #define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe 2530 + #define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 2531 + #define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80 2532 + #define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 2533 + #define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100 2534 + #define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 2535 + #define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200 2536 + #define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 2537 + #define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00 2538 + #define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa 2539 + #define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000 2540 + #define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf 2541 + #define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000 2542 + #define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 2543 + #define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000 2544 + #define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 2545 + #define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000 2546 + #define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 2547 + #define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000 2548 + #define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 2549 + #define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000 2550 + #define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14 2551 + #define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000 2552 + #define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 2553 + #define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000 2554 + #define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 2555 + #define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000 2556 + #define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 2557 + #define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000 2558 + #define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18 2559 + #define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000 2560 + #define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e 2561 + #define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000 2562 + #define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f 2563 + #define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf 2564 + #define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 2565 + #define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000 2566 + #define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 2567 + #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000 2568 + #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 2569 + #define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000 2570 + #define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 2571 + #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000 2572 + #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 2573 + #define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000 2574 + #define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 2575 + #define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000 2576 + #define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 2577 + #define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff 2578 + #define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0 2579 + #define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100 2580 + #define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8 2581 + #define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000 2582 + #define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10 2583 + #define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1 2584 + #define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 2585 + #define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2 2586 + #define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 2587 + #define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4 2588 + #define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 2589 + #define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8 2590 + #define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 2591 + #define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10 2592 + #define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 2593 + #define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40 2594 + #define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 2595 + #define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80 2596 + #define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7 2597 + #define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100 2598 + #define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8 2599 + #define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1 2600 + #define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 2601 + #define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2 2602 + #define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 2603 + #define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4 2604 + #define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 2605 + #define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8 2606 + #define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 2607 + #define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10 2608 + #define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 2609 + #define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40 2610 + #define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 2611 + #define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80 2612 + #define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7 2613 + #define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100 2614 + #define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8 2615 + #define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1 2616 + #define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 2617 + #define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e 2618 + #define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 2619 + #define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0 2620 + #define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 2621 + #define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800 2622 + #define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb 2623 + #define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000 2624 + #define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc 2625 + #define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000 2626 + #define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd 2627 + #define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000 2628 + #define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe 2629 + #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 2630 + #define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 2631 + #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000 2632 + #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 2633 + #define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000 2634 + #define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 2635 + #define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000 2636 + #define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 2637 + #define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000 2638 + #define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 2639 + #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000 2640 + #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 2641 + #define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000 2642 + #define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 2643 + #define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000 2644 + #define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 2645 + #define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000 2646 + #define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 2647 + #define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000 2648 + #define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d 2649 + #define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000 2650 + #define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e 2651 + #define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000 2652 + #define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f 2653 + #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1 2654 + #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 2655 + #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2 2656 + #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 2657 + #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4 2658 + #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 2659 + #define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8 2660 + #define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 2661 + #define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10 2662 + #define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 2663 + #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20 2664 + #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 2665 + #define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100 2666 + #define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 2667 + #define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00 2668 + #define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 2669 + #define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000 2670 + #define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc 2671 + #define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000 2672 + #define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd 2673 + #define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000 2674 + #define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe 2675 + #define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000 2676 + #define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 2677 + #define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000 2678 + #define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c 2679 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3 2680 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 2681 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc 2682 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 2683 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30 2684 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 2685 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0 2686 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 2687 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300 2688 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 2689 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00 2690 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa 2691 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000 2692 + #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc 2693 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3 2694 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0 2695 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc 2696 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2 2697 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30 2698 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4 2699 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0 2700 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6 2701 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300 2702 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8 2703 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00 2704 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa 2705 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000 2706 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc 2707 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000 2708 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10 2709 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000 2710 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12 2711 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000 2712 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14 2713 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000 2714 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16 2715 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000 2716 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18 2717 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000 2718 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a 2719 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000 2720 + #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c 2721 + #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4 2722 + #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 2723 + #define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8 2724 + #define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 2725 + #define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10 2726 + #define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 2727 + #define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0 2728 + #define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 2729 + #define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100 2730 + #define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 2731 + #define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200 2732 + #define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 2733 + #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400 2734 + #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa 2735 + #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800 2736 + #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb 2737 + #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000 2738 + #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc 2739 + #define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000 2740 + #define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd 2741 + #define PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH_MASK 0x70000 2742 + #define PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH__SHIFT 0x10 2743 + #define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40 2744 + #define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 2745 + #define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80 2746 + #define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 2747 + #define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000 2748 + #define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc 2749 + #define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f 2750 + #define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 2751 + #define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00 2752 + #define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 2753 + #define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000 2754 + #define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 2755 + #define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000 2756 + #define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 2757 + #define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f 2758 + #define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 2759 + #define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00 2760 + #define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 2761 + #define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000 2762 + #define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 2763 + #define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000 2764 + #define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 2765 + #define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f 2766 + #define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 2767 + #define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00 2768 + #define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 2769 + #define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000 2770 + #define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 2771 + #define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000 2772 + #define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 2773 + #define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f 2774 + #define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 2775 + #define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00 2776 + #define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 2777 + #define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000 2778 + #define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 2779 + #define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000 2780 + #define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 2781 + #define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f 2782 + #define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 2783 + #define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00 2784 + #define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 2785 + #define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000 2786 + #define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 2787 + #define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000 2788 + #define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 2789 + #define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f 2790 + #define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 2791 + #define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00 2792 + #define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 2793 + #define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000 2794 + #define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 2795 + #define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000 2796 + #define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 2797 + #define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1 2798 + #define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 2799 + #define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2 2800 + #define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 2801 + #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c 2802 + #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 2803 + #define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0 2804 + #define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 2805 + #define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff 2806 + #define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 2807 + #define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000 2808 + #define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 2809 + #define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1 2810 + #define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 2811 + #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2 2812 + #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 2813 + #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4 2814 + #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 2815 + #define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8 2816 + #define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 2817 + #define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10 2818 + #define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 2819 + #define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20 2820 + #define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 2821 + #define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40 2822 + #define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 2823 + #define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff 2824 + #define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 2825 + #define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff 2826 + #define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 2827 + #define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff 2828 + #define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 2829 + #define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff 2830 + #define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 2831 + #define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff 2832 + #define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 2833 + #define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff 2834 + #define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 2835 + #define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff 2836 + #define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 2837 + #define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff 2838 + #define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 2839 + #define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff 2840 + #define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 2841 + #define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff 2842 + #define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 2843 + #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1 2844 + #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 2845 + #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2 2846 + #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 2847 + #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4 2848 + #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 2849 + #define PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1 2850 + #define PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0 2851 + #define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1 2852 + #define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 2853 + #define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2 2854 + #define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 2855 + #define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4 2856 + #define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2 2857 + #define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8 2858 + #define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3 2859 + #define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10 2860 + #define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 2861 + #define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20 2862 + #define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 2863 + #define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40 2864 + #define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 2865 + #define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80 2866 + #define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 2867 + #define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100 2868 + #define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 2869 + #define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000 2870 + #define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc 2871 + #define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000 2872 + #define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd 2873 + #define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000 2874 + #define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe 2875 + #define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000 2876 + #define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 2877 + #define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff 2878 + #define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 2879 + #define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000 2880 + #define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 2881 + #define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff 2882 + #define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 2883 + #define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff 2884 + #define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 2885 + #define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000 2886 + #define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 2887 + #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff 2888 + #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 2889 + #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00 2890 + #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 2891 + #define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1 2892 + #define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0 2893 + #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2 2894 + #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1 2895 + #define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4 2896 + #define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2 2897 + #define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8 2898 + #define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3 2899 + #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0 2900 + #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4 2901 + #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00 2902 + #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8 2903 + #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000 2904 + #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc 2905 + #define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000 2906 + #define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10 2907 + #define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000 2908 + #define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11 2909 + #define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000 2910 + #define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12 2911 + #define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0_MASK 0x80000 2912 + #define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x13 2913 + #define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000 2914 + #define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14 2915 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7 2916 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 2917 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38 2918 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 2919 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40 2920 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 2921 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380 2922 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 2923 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00 2924 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa 2925 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000 2926 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd 2927 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000 2928 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe 2929 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000 2930 + #define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf 2931 + #define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x10000 2932 + #define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 2933 + #define PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS_MASK 0x1 2934 + #define PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS__SHIFT 0x0 2935 + #define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS_MASK 0x2 2936 + #define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS__SHIFT 0x1 2937 + #define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS_MASK 0x4 2938 + #define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS__SHIFT 0x2 2939 + #define PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE_MASK 0x8 2940 + #define PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE__SHIFT 0x3 2941 + #define PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE_MASK 0x10 2942 + #define PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE__SHIFT 0x4 2943 + #define PCIE_IDLE_STATUS__TX_PBUF_IDLE_MASK 0x20 2944 + #define PCIE_IDLE_STATUS__TX_PBUF_IDLE__SHIFT 0x5 2945 + #define PCIE_IDLE_STATUS__TX_NPBUF_IDLE_MASK 0x40 2946 + #define PCIE_IDLE_STATUS__TX_NPBUF_IDLE__SHIFT 0x6 2947 + #define PCIE_IDLE_STATUS__TX_CPLBUF_IDLE_MASK 0x80 2948 + #define PCIE_IDLE_STATUS__TX_CPLBUF_IDLE__SHIFT 0x7 2949 + #define PCIE_IDLE_STATUS__TX_MSGBUF_IDLE_MASK 0x100 2950 + #define PCIE_IDLE_STATUS__TX_MSGBUF_IDLE__SHIFT 0x8 2951 + #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1 2952 + #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 2953 + #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2 2954 + #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 2955 + #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4 2956 + #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 2957 + #define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff 2958 + #define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 2959 + #define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00 2960 + #define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 2961 + #define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000 2962 + #define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 2963 + #define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000 2964 + #define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 2965 + #define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff 2966 + #define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 2967 + #define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff 2968 + #define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 2969 + #define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff 2970 + #define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 2971 + #define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00 2972 + #define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 2973 + #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000 2974 + #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 2975 + #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000 2976 + #define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 2977 + #define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff 2978 + #define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 2979 + #define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff 2980 + #define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 2981 + #define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff 2982 + #define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 2983 + #define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00 2984 + #define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 2985 + #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000 2986 + #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 2987 + #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000 2988 + #define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 2989 + #define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff 2990 + #define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 2991 + #define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff 2992 + #define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 2993 + #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff 2994 + #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 2995 + #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00 2996 + #define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 2997 + #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000 2998 + #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 2999 + #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000 3000 + #define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 3001 + #define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff 3002 + #define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 3003 + #define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff 3004 + #define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 3005 + #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff 3006 + #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 3007 + #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00 3008 + #define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 3009 + #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000 3010 + #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 3011 + #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000 3012 + #define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 3013 + #define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff 3014 + #define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 3015 + #define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff 3016 + #define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 3017 + #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff 3018 + #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 3019 + #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00 3020 + #define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 3021 + #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000 3022 + #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 3023 + #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000 3024 + #define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 3025 + #define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff 3026 + #define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 3027 + #define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff 3028 + #define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 3029 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf 3030 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 3031 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0 3032 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 3033 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00 3034 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 3035 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000 3036 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc 3037 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 3038 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 3039 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 3040 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 3041 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000 3042 + #define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 3043 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf 3044 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 3045 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0 3046 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 3047 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00 3048 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 3049 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000 3050 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc 3051 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 3052 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 3053 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 3054 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 3055 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000 3056 + #define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 3057 + #define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff 3058 + #define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 3059 + #define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00 3060 + #define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 3061 + #define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000 3062 + #define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 3063 + #define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000 3064 + #define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 3065 + #define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff 3066 + #define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 3067 + #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff 3068 + #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 3069 + #define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1 3070 + #define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 3071 + #define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2 3072 + #define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 3073 + #define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4 3074 + #define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 3075 + #define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8 3076 + #define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 3077 + #define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10 3078 + #define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 3079 + #define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20 3080 + #define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 3081 + #define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40 3082 + #define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 3083 + #define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80 3084 + #define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 3085 + #define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100 3086 + #define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 3087 + #define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200 3088 + #define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 3089 + #define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400 3090 + #define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa 3091 + #define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800 3092 + #define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb 3093 + #define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000 3094 + #define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc 3095 + #define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000 3096 + #define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd 3097 + #define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000 3098 + #define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe 3099 + #define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000 3100 + #define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf 3101 + #define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000 3102 + #define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 3103 + #define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000 3104 + #define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 3105 + #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000 3106 + #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12 3107 + #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000 3108 + #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13 3109 + #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000 3110 + #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14 3111 + #define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000 3112 + #define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 3113 + #define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000 3114 + #define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18 3115 + #define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 3116 + #define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b 3117 + #define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000 3118 + #define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c 3119 + #define PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000 3120 + #define PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d 3121 + #define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000 3122 + #define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e 3123 + #define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2 3124 + #define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 3125 + #define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4 3126 + #define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2 3127 + #define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8 3128 + #define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3 3129 + #define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10 3130 + #define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4 3131 + #define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20 3132 + #define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5 3133 + #define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40 3134 + #define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6 3135 + #define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80 3136 + #define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7 3137 + #define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100 3138 + #define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8 3139 + #define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200 3140 + #define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9 3141 + #define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400 3142 + #define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa 3143 + #define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800 3144 + #define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb 3145 + #define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000 3146 + #define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc 3147 + #define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000 3148 + #define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd 3149 + #define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000 3150 + #define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe 3151 + #define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000 3152 + #define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf 3153 + #define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000 3154 + #define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 3155 + #define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN_MASK 0x40000 3156 + #define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN__SHIFT 0x12 3157 + #define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN_MASK 0x80000 3158 + #define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN__SHIFT 0x13 3159 + #define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN_MASK 0x100000 3160 + #define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN__SHIFT 0x14 3161 + #define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP_MASK 0xe00000 3162 + #define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP__SHIFT 0x15 3163 + #define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 3164 + #define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b 3165 + #define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2 3166 + #define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 3167 + #define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4 3168 + #define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2 3169 + #define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8 3170 + #define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3 3171 + #define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10 3172 + #define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4 3173 + #define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20 3174 + #define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5 3175 + #define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40 3176 + #define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6 3177 + #define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80 3178 + #define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7 3179 + #define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100 3180 + #define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8 3181 + #define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200 3182 + #define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9 3183 + #define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400 3184 + #define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa 3185 + #define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800 3186 + #define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb 3187 + #define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000 3188 + #define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc 3189 + #define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000 3190 + #define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd 3191 + #define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000 3192 + #define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe 3193 + #define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000 3194 + #define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf 3195 + #define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000 3196 + #define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 3197 + #define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN_MASK 0x40000 3198 + #define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN__SHIFT 0x12 3199 + #define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN_MASK 0x80000 3200 + #define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN__SHIFT 0x13 3201 + #define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN_MASK 0x100000 3202 + #define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN__SHIFT 0x14 3203 + #define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP_MASK 0xe00000 3204 + #define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP__SHIFT 0x15 3205 + #define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 3206 + #define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b 3207 + #define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff 3208 + #define PCIE_STRAP_F3__RESERVED__SHIFT 0x0 3209 + #define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff 3210 + #define PCIE_STRAP_F4__RESERVED__SHIFT 0x0 3211 + #define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff 3212 + #define PCIE_STRAP_F5__RESERVED__SHIFT 0x0 3213 + #define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff 3214 + #define PCIE_STRAP_F6__RESERVED__SHIFT 0x0 3215 + #define PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN_MASK 0x1 3216 + #define PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN__SHIFT 0x0 3217 + #define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR_MASK 0xe 3218 + #define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR__SHIFT 0x1 3219 + #define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET_MASK 0xfffff000 3220 + #define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET__SHIFT 0xc 3221 + #define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10 3222 + #define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 3223 + #define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00 3224 + #define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8 3225 + #define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000 3226 + #define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd 3227 + #define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000 3228 + #define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe 3229 + #define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000 3230 + #define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf 3231 + #define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000 3232 + #define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 3233 + #define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000 3234 + #define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19 3235 + #define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000 3236 + #define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a 3237 + #define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000 3238 + #define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c 3239 + #define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000 3240 + #define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d 3241 + #define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000 3242 + #define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e 3243 + #define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000 3244 + #define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f 3245 + #define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2 3246 + #define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 3247 + #define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4 3248 + #define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 3249 + #define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8 3250 + #define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 3251 + #define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10 3252 + #define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 3253 + #define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1 3254 + #define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 3255 + #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000 3256 + #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c 3257 + #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000 3258 + #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d 3259 + #define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f 3260 + #define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 3261 + #define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80 3262 + #define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7 3263 + #define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff 3264 + #define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 3265 + #define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000 3266 + #define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10 3267 + #define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000 3268 + #define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 3269 + #define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff 3270 + #define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 3271 + #define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000 3272 + #define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 3273 + #define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff 3274 + #define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 3275 + #define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff 3276 + #define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 3277 + #define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1 3278 + #define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 3279 + #define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe 3280 + #define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 3281 + #define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10 3282 + #define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4 3283 + #define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20 3284 + #define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5 3285 + #define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0 3286 + #define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6 3287 + #define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00 3288 + #define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8 3289 + #define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000 3290 + #define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe 3291 + #define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000 3292 + #define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 3293 + #define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff 3294 + #define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 3295 + #define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff 3296 + #define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 3297 + #define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff 3298 + #define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 3299 + #define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff 3300 + #define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 3301 + #define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff 3302 + #define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 3303 + #define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff 3304 + #define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 3305 + #define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff 3306 + #define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 3307 + #define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff 3308 + #define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 3309 + #define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff 3310 + #define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 3311 + #define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff 3312 + #define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 3313 + #define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff 3314 + #define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 3315 + #define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff 3316 + #define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 3317 + #define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff 3318 + #define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 3319 + #define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff 3320 + #define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 3321 + #define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff 3322 + #define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 3323 + #define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff 3324 + #define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 3325 + #define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff 3326 + #define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 3327 + #define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff 3328 + #define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 3329 + #define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff 3330 + #define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 3331 + #define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 3332 + #define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 3333 + #define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 3334 + #define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc 3335 + #define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 3336 + #define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 3337 + #define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 3338 + #define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 3339 + #define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff 3340 + #define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 3341 + #define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f 3342 + #define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 3343 + #define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x100 3344 + #define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 3345 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff 3346 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 3347 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff 3348 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 3349 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff 3350 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 3351 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff 3352 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 3353 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff 3354 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 3355 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff 3356 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 3357 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff 3358 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 3359 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff 3360 + #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 3361 + #define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1 3362 + #define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0 3363 + #define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2 3364 + #define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1 3365 + #define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000 3366 + #define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10 3367 + #define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000 3368 + #define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11 3369 + #define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1 3370 + #define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0 3371 + #define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2 3372 + #define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1 3373 + #define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c 3374 + #define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2 3375 + #define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100 3376 + #define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8 3377 + #define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200 3378 + #define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9 3379 + #define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400 3380 + #define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa 3381 + #define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000 3382 + #define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc 3383 + #define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000 3384 + #define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd 3385 + #define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000 3386 + #define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe 3387 + #define SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000 3388 + #define SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10 3389 + #define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000 3390 + #define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11 3391 + #define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN_MASK 0x10000000 3392 + #define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN__SHIFT 0x1c 3393 + #define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR_MASK 0x60000000 3394 + #define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR__SHIFT 0x1d 3395 + #define SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000 3396 + #define SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf 3397 + #define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000 3398 + #define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10 3399 + #define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000 3400 + #define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11 3401 + #define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000 3402 + #define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12 3403 + #define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000 3404 + #define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13 3405 + #define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000 3406 + #define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14 3407 + #define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000 3408 + #define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15 3409 + #define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000 3410 + #define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16 3411 + #define SWRST_COMMAND_1__SWITCHCLK_MASK 0x1 3412 + #define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0 3413 + #define SWRST_COMMAND_1__RESETPCFG_MASK 0x2 3414 + #define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1 3415 + #define SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4 3416 + #define SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2 3417 + #define SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8 3418 + #define SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3 3419 + #define SWRST_COMMAND_1__RESETSRBM0_MASK 0x10 3420 + #define SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4 3421 + #define SWRST_COMMAND_1__RESETSRBM1_MASK 0x20 3422 + #define SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5 3423 + #define SWRST_COMMAND_1__RESETLC_MASK 0x40 3424 + #define SWRST_COMMAND_1__RESETLC__SHIFT 0x6 3425 + #define SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100 3426 + #define SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8 3427 + #define SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200 3428 + #define SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9 3429 + #define SWRST_COMMAND_1__RESETMNTR_MASK 0x2000 3430 + #define SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd 3431 + #define SWRST_COMMAND_1__RESETHLTR_MASK 0x4000 3432 + #define SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe 3433 + #define SWRST_COMMAND_1__RESETCPM_MASK 0x8000 3434 + #define SWRST_COMMAND_1__RESETCPM__SHIFT 0xf 3435 + #define SWRST_COMMAND_1__RESETPIF0_MASK 0x10000 3436 + #define SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10 3437 + #define SWRST_COMMAND_1__RESETPIF1_MASK 0x20000 3438 + #define SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11 3439 + #define SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000 3440 + #define SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14 3441 + #define SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000 3442 + #define SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15 3443 + #define SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000 3444 + #define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18 3445 + #define SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000 3446 + #define SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19 3447 + #define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000 3448 + #define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c 3449 + #define SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000 3450 + #define SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d 3451 + #define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000 3452 + #define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf 3453 + #define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000 3454 + #define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10 3455 + #define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000 3456 + #define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11 3457 + #define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000 3458 + #define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12 3459 + #define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000 3460 + #define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13 3461 + #define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000 3462 + #define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14 3463 + #define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000 3464 + #define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15 3465 + #define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000 3466 + #define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16 3467 + #define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1 3468 + #define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0 3469 + #define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2 3470 + #define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1 3471 + #define SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4 3472 + #define SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2 3473 + #define SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8 3474 + #define SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3 3475 + #define SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10 3476 + #define SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4 3477 + #define SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20 3478 + #define SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5 3479 + #define SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40 3480 + #define SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6 3481 + #define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100 3482 + #define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8 3483 + #define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200 3484 + #define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9 3485 + #define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000 3486 + #define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd 3487 + #define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000 3488 + #define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe 3489 + #define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000 3490 + #define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf 3491 + #define SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000 3492 + #define SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10 3493 + #define SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000 3494 + #define SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11 3495 + #define SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000 3496 + #define SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14 3497 + #define SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000 3498 + #define SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15 3499 + #define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000 3500 + #define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18 3501 + #define SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000 3502 + #define SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19 3503 + #define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000 3504 + #define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c 3505 + #define SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000 3506 + #define SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d 3507 + #define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000 3508 + #define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf 3509 + #define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000 3510 + #define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10 3511 + #define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000 3512 + #define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11 3513 + #define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000 3514 + #define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12 3515 + #define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000 3516 + #define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13 3517 + #define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000 3518 + #define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14 3519 + #define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000 3520 + #define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15 3521 + #define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000 3522 + #define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16 3523 + #define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1 3524 + #define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0 3525 + #define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2 3526 + #define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1 3527 + #define SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4 3528 + #define SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2 3529 + #define SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8 3530 + #define SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3 3531 + #define SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10 3532 + #define SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4 3533 + #define SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20 3534 + #define SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5 3535 + #define SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40 3536 + #define SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6 3537 + #define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100 3538 + #define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8 3539 + #define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200 3540 + #define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9 3541 + #define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000 3542 + #define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd 3543 + #define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000 3544 + #define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe 3545 + #define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000 3546 + #define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf 3547 + #define SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000 3548 + #define SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10 3549 + #define SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000 3550 + #define SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11 3551 + #define SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000 3552 + #define SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14 3553 + #define SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000 3554 + #define SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15 3555 + #define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000 3556 + #define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18 3557 + #define SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000 3558 + #define SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19 3559 + #define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000 3560 + #define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c 3561 + #define SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000 3562 + #define SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d 3563 + #define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000 3564 + #define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe 3565 + #define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000 3566 + #define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10 3567 + #define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000 3568 + #define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11 3569 + #define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000 3570 + #define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12 3571 + #define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000 3572 + #define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13 3573 + #define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000 3574 + #define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14 3575 + #define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000 3576 + #define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15 3577 + #define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000 3578 + #define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16 3579 + #define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1 3580 + #define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0 3581 + #define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2 3582 + #define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1 3583 + #define SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4 3584 + #define SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2 3585 + #define SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8 3586 + #define SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3 3587 + #define SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10 3588 + #define SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4 3589 + #define SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20 3590 + #define SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5 3591 + #define SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40 3592 + #define SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6 3593 + #define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100 3594 + #define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8 3595 + #define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200 3596 + #define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9 3597 + #define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000 3598 + #define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd 3599 + #define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000 3600 + #define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe 3601 + #define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000 3602 + #define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf 3603 + #define SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000 3604 + #define SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10 3605 + #define SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000 3606 + #define SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11 3607 + #define SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000 3608 + #define SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14 3609 + #define SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000 3610 + #define SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15 3611 + #define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000 3612 + #define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18 3613 + #define SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000 3614 + #define SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19 3615 + #define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000 3616 + #define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c 3617 + #define SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000 3618 + #define SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d 3619 + #define SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1 3620 + #define SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0 3621 + #define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100 3622 + #define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8 3623 + #define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x1 3624 + #define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0 3625 + #define SWRST_EP_COMMAND_0__EP_SOFT_RESET_MASK 0x2 3626 + #define SWRST_EP_COMMAND_0__EP_SOFT_RESET__SHIFT 0x1 3627 + #define SWRST_EP_COMMAND_0__EP_DRV_RESET_MASK 0x4 3628 + #define SWRST_EP_COMMAND_0__EP_DRV_RESET__SHIFT 0x2 3629 + #define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x100 3630 + #define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8 3631 + #define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x200 3632 + #define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9 3633 + #define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x400 3634 + #define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa 3635 + #define SWRST_EP_COMMAND_0__EP_FLR0_RESET_MASK 0x10000 3636 + #define SWRST_EP_COMMAND_0__EP_FLR0_RESET__SHIFT 0x10 3637 + #define SWRST_EP_COMMAND_0__EP_FLR1_RESET_MASK 0x20000 3638 + #define SWRST_EP_COMMAND_0__EP_FLR1_RESET__SHIFT 0x11 3639 + #define SWRST_EP_COMMAND_0__EP_FLR2_RESET_MASK 0x40000 3640 + #define SWRST_EP_COMMAND_0__EP_FLR2_RESET__SHIFT 0x12 3641 + #define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x1 3642 + #define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0 3643 + #define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN_MASK 0x2 3644 + #define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN__SHIFT 0x1 3645 + #define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN_MASK 0x4 3646 + #define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN__SHIFT 0x2 3647 + #define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x100 3648 + #define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8 3649 + #define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x200 3650 + #define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9 3651 + #define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x400 3652 + #define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa 3653 + #define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN_MASK 0x10000 3654 + #define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN__SHIFT 0x10 3655 + #define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN_MASK 0x20000 3656 + #define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN__SHIFT 0x11 3657 + #define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN_MASK 0x40000 3658 + #define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN__SHIFT 0x12 3659 + #define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN_MASK 0x80000 3660 + #define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN__SHIFT 0x13 3661 + #define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST_MASK 0xf00000 3662 + #define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST__SHIFT 0x14 3663 + #define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1 3664 + #define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0 3665 + #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2 3666 + #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1 3667 + #define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4 3668 + #define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2 3669 + #define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8 3670 + #define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3 3671 + #define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10 3672 + #define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4 3673 + #define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20 3674 + #define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5 3675 + #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40 3676 + #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6 3677 + #define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80 3678 + #define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7 3679 + #define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100 3680 + #define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8 3681 + #define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200 3682 + #define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9 3683 + #define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400 3684 + #define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa 3685 + #define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800 3686 + #define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb 3687 + #define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000 3688 + #define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc 3689 + #define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000 3690 + #define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd 3691 + #define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000 3692 + #define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe 3693 + #define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000 3694 + #define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf 3695 + #define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000 3696 + #define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10 3697 + #define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000 3698 + #define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11 3699 + #define CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000 3700 + #define CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14 3701 + #define CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000 3702 + #define CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15 3703 + #define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000 3704 + #define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16 3705 + #define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000 3706 + #define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17 3707 + #define CPM_CONTROL__SPARE_REGS_MASK 0xff000000 3708 + #define CPM_CONTROL__SPARE_REGS__SHIFT 0x18 3709 + #define GSKT_CONTROL__GSKT_TxFifoBypass_MASK 0x1 3710 + #define GSKT_CONTROL__GSKT_TxFifoBypass__SHIFT 0x0 3711 + #define GSKT_CONTROL__GSKT_TxFifoDelay_MASK 0x2 3712 + #define GSKT_CONTROL__GSKT_TxFifoDelay__SHIFT 0x1 3713 + #define GSKT_CONTROL__GSKT_TxFifoDelay2_MASK 0x4 3714 + #define GSKT_CONTROL__GSKT_TxFifoDelay2__SHIFT 0x2 3715 + #define GSKT_CONTROL__GSKT_SpareRegs_MASK 0xf8 3716 + #define GSKT_CONTROL__GSKT_SpareRegs__SHIFT 0x3 3717 + #define LM_CONTROL__LoopbackSelect_MASK 0x1e 3718 + #define LM_CONTROL__LoopbackSelect__SHIFT 0x1 3719 + #define LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20 3720 + #define LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5 3721 + #define LM_CONTROL__LoopbackHalfRate_MASK 0xc0 3722 + #define LM_CONTROL__LoopbackHalfRate__SHIFT 0x6 3723 + #define LM_CONTROL__LoopbackFifoPtr_MASK 0x700 3724 + #define LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8 3725 + #define LM_PCIETXMUX0__TXLANE0_MASK 0xff 3726 + #define LM_PCIETXMUX0__TXLANE0__SHIFT 0x0 3727 + #define LM_PCIETXMUX0__TXLANE1_MASK 0xff00 3728 + #define LM_PCIETXMUX0__TXLANE1__SHIFT 0x8 3729 + #define LM_PCIETXMUX0__TXLANE2_MASK 0xff0000 3730 + #define LM_PCIETXMUX0__TXLANE2__SHIFT 0x10 3731 + #define LM_PCIETXMUX0__TXLANE3_MASK 0xff000000 3732 + #define LM_PCIETXMUX0__TXLANE3__SHIFT 0x18 3733 + #define LM_PCIETXMUX1__TXLANE4_MASK 0xff 3734 + #define LM_PCIETXMUX1__TXLANE4__SHIFT 0x0 3735 + #define LM_PCIETXMUX1__TXLANE5_MASK 0xff00 3736 + #define LM_PCIETXMUX1__TXLANE5__SHIFT 0x8 3737 + #define LM_PCIETXMUX1__TXLANE6_MASK 0xff0000 3738 + #define LM_PCIETXMUX1__TXLANE6__SHIFT 0x10 3739 + #define LM_PCIETXMUX1__TXLANE7_MASK 0xff000000 3740 + #define LM_PCIETXMUX1__TXLANE7__SHIFT 0x18 3741 + #define LM_PCIETXMUX2__TXLANE8_MASK 0xff 3742 + #define LM_PCIETXMUX2__TXLANE8__SHIFT 0x0 3743 + #define LM_PCIETXMUX2__TXLANE9_MASK 0xff00 3744 + #define LM_PCIETXMUX2__TXLANE9__SHIFT 0x8 3745 + #define LM_PCIETXMUX2__TXLANE10_MASK 0xff0000 3746 + #define LM_PCIETXMUX2__TXLANE10__SHIFT 0x10 3747 + #define LM_PCIETXMUX2__TXLANE11_MASK 0xff000000 3748 + #define LM_PCIETXMUX2__TXLANE11__SHIFT 0x18 3749 + #define LM_PCIETXMUX3__TXLANE12_MASK 0xff 3750 + #define LM_PCIETXMUX3__TXLANE12__SHIFT 0x0 3751 + #define LM_PCIETXMUX3__TXLANE13_MASK 0xff00 3752 + #define LM_PCIETXMUX3__TXLANE13__SHIFT 0x8 3753 + #define LM_PCIETXMUX3__TXLANE14_MASK 0xff0000 3754 + #define LM_PCIETXMUX3__TXLANE14__SHIFT 0x10 3755 + #define LM_PCIETXMUX3__TXLANE15_MASK 0xff000000 3756 + #define LM_PCIETXMUX3__TXLANE15__SHIFT 0x18 3757 + #define LM_PCIERXMUX0__RXLANE0_MASK 0xff 3758 + #define LM_PCIERXMUX0__RXLANE0__SHIFT 0x0 3759 + #define LM_PCIERXMUX0__RXLANE1_MASK 0xff00 3760 + #define LM_PCIERXMUX0__RXLANE1__SHIFT 0x8 3761 + #define LM_PCIERXMUX0__RXLANE2_MASK 0xff0000 3762 + #define LM_PCIERXMUX0__RXLANE2__SHIFT 0x10 3763 + #define LM_PCIERXMUX0__RXLANE3_MASK 0xff000000 3764 + #define LM_PCIERXMUX0__RXLANE3__SHIFT 0x18 3765 + #define LM_PCIERXMUX1__RXLANE4_MASK 0xff 3766 + #define LM_PCIERXMUX1__RXLANE4__SHIFT 0x0 3767 + #define LM_PCIERXMUX1__RXLANE5_MASK 0xff00 3768 + #define LM_PCIERXMUX1__RXLANE5__SHIFT 0x8 3769 + #define LM_PCIERXMUX1__RXLANE6_MASK 0xff0000 3770 + #define LM_PCIERXMUX1__RXLANE6__SHIFT 0x10 3771 + #define LM_PCIERXMUX1__RXLANE7_MASK 0xff000000 3772 + #define LM_PCIERXMUX1__RXLANE7__SHIFT 0x18 3773 + #define LM_PCIERXMUX2__RXLANE8_MASK 0xff 3774 + #define LM_PCIERXMUX2__RXLANE8__SHIFT 0x0 3775 + #define LM_PCIERXMUX2__RXLANE9_MASK 0xff00 3776 + #define LM_PCIERXMUX2__RXLANE9__SHIFT 0x8 3777 + #define LM_PCIERXMUX2__RXLANE10_MASK 0xff0000 3778 + #define LM_PCIERXMUX2__RXLANE10__SHIFT 0x10 3779 + #define LM_PCIERXMUX2__RXLANE11_MASK 0xff000000 3780 + #define LM_PCIERXMUX2__RXLANE11__SHIFT 0x18 3781 + #define LM_PCIERXMUX3__RXLANE12_MASK 0xff 3782 + #define LM_PCIERXMUX3__RXLANE12__SHIFT 0x0 3783 + #define LM_PCIERXMUX3__RXLANE13_MASK 0xff00 3784 + #define LM_PCIERXMUX3__RXLANE13__SHIFT 0x8 3785 + #define LM_PCIERXMUX3__RXLANE14_MASK 0xff0000 3786 + #define LM_PCIERXMUX3__RXLANE14__SHIFT 0x10 3787 + #define LM_PCIERXMUX3__RXLANE15_MASK 0xff000000 3788 + #define LM_PCIERXMUX3__RXLANE15__SHIFT 0x18 3789 + #define LM_LANEENABLE__LANE_enable_MASK 0xffff 3790 + #define LM_LANEENABLE__LANE_enable__SHIFT 0x0 3791 + #define LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff 3792 + #define LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0 3793 + #define LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000 3794 + #define LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c 3795 + #define LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000 3796 + #define LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d 3797 + #define LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000 3798 + #define LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e 3799 + #define LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000 3800 + #define LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f 3801 + #define LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7 3802 + #define LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0 3803 + #define LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38 3804 + #define LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3 3805 + #define LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0 3806 + #define LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6 3807 + #define LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700 3808 + #define LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8 3809 + #define LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800 3810 + #define LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb 3811 + #define LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000 3812 + #define LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe 3813 + #define LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000 3814 + #define LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10 3815 + #define LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000 3816 + #define LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13 3817 + #define LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000 3818 + #define LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16 3819 + #define LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000 3820 + #define LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18 3821 + #define LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000 3822 + #define LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b 3823 + #define LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000 3824 + #define LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e 3825 + #define LM_POWERCONTROL1__LMTxEn0_MASK 0x1 3826 + #define LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0 3827 + #define LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2 3828 + #define LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1 3829 + #define LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c 3830 + #define LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2 3831 + #define LM_POWERCONTROL1__LMSkipBit0_MASK 0x20 3832 + #define LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5 3833 + #define LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40 3834 + #define LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6 3835 + #define LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80 3836 + #define LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7 3837 + #define LM_POWERCONTROL1__LMDeemph0_MASK 0x100 3838 + #define LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8 3839 + #define LM_POWERCONTROL1__LMTxEn1_MASK 0x200 3840 + #define LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9 3841 + #define LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400 3842 + #define LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa 3843 + #define LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800 3844 + #define LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb 3845 + #define LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000 3846 + #define LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe 3847 + #define LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000 3848 + #define LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf 3849 + #define LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000 3850 + #define LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10 3851 + #define LM_POWERCONTROL1__LMDeemph1_MASK 0x20000 3852 + #define LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11 3853 + #define LM_POWERCONTROL1__LMTxEn2_MASK 0x40000 3854 + #define LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12 3855 + #define LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000 3856 + #define LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13 3857 + #define LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000 3858 + #define LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14 3859 + #define LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000 3860 + #define LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17 3861 + #define LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000 3862 + #define LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18 3863 + #define LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000 3864 + #define LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19 3865 + #define LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000 3866 + #define LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a 3867 + #define LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000 3868 + #define LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b 3869 + #define LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000 3870 + #define LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d 3871 + #define LM_POWERCONTROL2__LMTxEn3_MASK 0x1 3872 + #define LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0 3873 + #define LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2 3874 + #define LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1 3875 + #define LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c 3876 + #define LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2 3877 + #define LM_POWERCONTROL2__LMSkipBit3_MASK 0x20 3878 + #define LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5 3879 + #define LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40 3880 + #define LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6 3881 + #define LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80 3882 + #define LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7 3883 + #define LM_POWERCONTROL2__LMDeemph3_MASK 0x100 3884 + #define LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8 3885 + #define LM_POWERCONTROL2__TxCoeffID2_MASK 0x600 3886 + #define LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9 3887 + #define LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800 3888 + #define LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb 3889 + #define LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000 3890 + #define LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd 3891 + #define LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000 3892 + #define LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13 3893 + #define LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000 3894 + #define LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19 3895 + #define LM_POWERCONTROL3__TxCoeff3_MASK 0x3f 3896 + #define LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0 3897 + #define LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0 3898 + #define LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6 3899 + #define LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000 3900 + #define LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc 3901 + #define LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000 3902 + #define LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12 3903 + #define LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000 3904 + #define LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18 3905 + #define LM_POWERCONTROL4__LinkNum0_MASK 0x7 3906 + #define LM_POWERCONTROL4__LinkNum0__SHIFT 0x0 3907 + #define LM_POWERCONTROL4__LinkNum1_MASK 0x38 3908 + #define LM_POWERCONTROL4__LinkNum1__SHIFT 0x3 3909 + #define LM_POWERCONTROL4__LinkNum2_MASK 0x1c0 3910 + #define LM_POWERCONTROL4__LinkNum2__SHIFT 0x6 3911 + #define LM_POWERCONTROL4__LinkNum3_MASK 0xe00 3912 + #define LM_POWERCONTROL4__LinkNum3__SHIFT 0x9 3913 + #define LM_POWERCONTROL4__LaneNum0_MASK 0xf000 3914 + #define LM_POWERCONTROL4__LaneNum0__SHIFT 0xc 3915 + #define LM_POWERCONTROL4__LaneNum1_MASK 0xf0000 3916 + #define LM_POWERCONTROL4__LaneNum1__SHIFT 0x10 3917 + #define LM_POWERCONTROL4__LaneNum2_MASK 0xf00000 3918 + #define LM_POWERCONTROL4__LaneNum2__SHIFT 0x14 3919 + #define LM_POWERCONTROL4__LaneNum3_MASK 0xf000000 3920 + #define LM_POWERCONTROL4__LaneNum3__SHIFT 0x18 3921 + #define LM_POWERCONTROL4__SpcMode0_MASK 0x10000000 3922 + #define LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c 3923 + #define LM_POWERCONTROL4__SpcMode1_MASK 0x20000000 3924 + #define LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d 3925 + #define LM_POWERCONTROL4__SpcMode2_MASK 0x40000000 3926 + #define LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e 3927 + #define LM_POWERCONTROL4__SpcMode3_MASK 0x80000000 3928 + #define LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f 3929 + #define PB0_GLB_CTRL_REG0__BACKUP_MASK 0xffff 3930 + #define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x0 3931 + #define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000 3932 + #define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10 3933 + #define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000 3934 + #define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14 3935 + #define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000 3936 + #define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17 3937 + #define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000 3938 + #define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18 3939 + #define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000 3940 + #define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19 3941 + #define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000 3942 + #define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a 3943 + #define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000 3944 + #define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e 3945 + #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1 3946 + #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0 3947 + #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e 3948 + #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1 3949 + #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80 3950 + #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7 3951 + #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00 3952 + #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8 3953 + #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000 3954 + #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe 3955 + #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000 3956 + #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf 3957 + #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000 3958 + #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16 3959 + #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000 3960 + #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17 3961 + #define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000 3962 + #define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e 3963 + #define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000 3964 + #define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f 3965 + #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1 3966 + #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0 3967 + #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe 3968 + #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1 3969 + #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100 3970 + #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8 3971 + #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00 3972 + #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9 3973 + #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000 3974 + #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10 3975 + #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000 3976 + #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11 3977 + #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000 3978 + #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18 3979 + #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000 3980 + #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19 3981 + #define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f 3982 + #define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0 3983 + #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60 3984 + #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5 3985 + #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180 3986 + #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7 3987 + #define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600 3988 + #define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9 3989 + #define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800 3990 + #define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb 3991 + #define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000 3992 + #define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc 3993 + #define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000 3994 + #define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe 3995 + #define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000 3996 + #define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12 3997 + #define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000 3998 + #define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15 3999 + #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000 4000 + #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16 4001 + #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000 4002 + #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17 4003 + #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000 4004 + #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b 4005 + #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000 4006 + #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c 4007 + #define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000 4008 + #define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f 4009 + #define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff 4010 + #define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0 4011 + #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000 4012 + #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10 4013 + #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000 4014 + #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12 4015 + #define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000 4016 + #define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16 4017 + #define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000 4018 + #define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a 4019 + #define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000 4020 + #define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b 4021 + #define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000 4022 + #define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c 4023 + #define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff 4024 + #define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0 4025 + #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK 0x1 4026 + #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT 0x0 4027 + #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2 4028 + #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT 0x1 4029 + #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK 0x4 4030 + #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2 4031 + #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK 0x8 4032 + #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT 0x3 4033 + #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK 0x10 4034 + #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT 0x4 4035 + #define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00 4036 + #define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8 4037 + #define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000 4038 + #define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc 4039 + #define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000 4040 + #define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10 4041 + #define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000 4042 + #define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14 4043 + #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK 0x1 4044 + #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT 0x0 4045 + #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2 4046 + #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT 0x1 4047 + #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK 0x4 4048 + #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2 4049 + #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000 4050 + #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc 4051 + #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000 4052 + #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd 4053 + #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000 4054 + #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe 4055 + #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000 4056 + #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf 4057 + #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK 0x30000 4058 + #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT 0x10 4059 + #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000 4060 + #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12 4061 + #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK 0x300000 4062 + #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT 0x14 4063 + #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000 4064 + #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16 4065 + #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK 0x3000000 4066 + #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT 0x18 4067 + #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000 4068 + #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a 4069 + #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK 0x30000000 4070 + #define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT 0x1c 4071 + #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000 4072 + #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e 4073 + #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK 0x1 4074 + #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT 0x0 4075 + #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2 4076 + #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT 0x1 4077 + #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK 0x4 4078 + #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2 4079 + #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000 4080 + #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc 4081 + #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000 4082 + #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd 4083 + #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000 4084 + #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe 4085 + #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000 4086 + #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf 4087 + #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK 0x30000 4088 + #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT 0x10 4089 + #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000 4090 + #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12 4091 + #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK 0x300000 4092 + #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT 0x14 4093 + #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000 4094 + #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16 4095 + #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK 0x3000000 4096 + #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT 0x18 4097 + #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000 4098 + #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a 4099 + #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK 0x30000000 4100 + #define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT 0x1c 4101 + #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000 4102 + #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e 4103 + #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK 0x1 4104 + #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT 0x0 4105 + #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2 4106 + #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT 0x1 4107 + #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK 0x4 4108 + #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2 4109 + #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000 4110 + #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc 4111 + #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000 4112 + #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd 4113 + #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000 4114 + #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe 4115 + #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000 4116 + #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf 4117 + #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK 0x30000 4118 + #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT 0x10 4119 + #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000 4120 + #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12 4121 + #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK 0x300000 4122 + #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT 0x14 4123 + #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000 4124 + #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16 4125 + #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK 0x3000000 4126 + #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT 0x18 4127 + #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000 4128 + #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a 4129 + #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK 0x30000000 4130 + #define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT 0x1c 4131 + #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000 4132 + #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e 4133 + #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK 0x1 4134 + #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT 0x0 4135 + #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2 4136 + #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT 0x1 4137 + #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK 0x4 4138 + #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2 4139 + #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000 4140 + #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc 4141 + #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000 4142 + #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd 4143 + #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000 4144 + #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe 4145 + #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000 4146 + #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf 4147 + #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK 0x30000 4148 + #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT 0x10 4149 + #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000 4150 + #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12 4151 + #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK 0x300000 4152 + #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT 0x14 4153 + #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000 4154 + #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16 4155 + #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK 0x3000000 4156 + #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT 0x18 4157 + #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000 4158 + #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a 4159 + #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK 0x30000000 4160 + #define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT 0x1c 4161 + #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000 4162 + #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e 4163 + #define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff 4164 + #define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0 4165 + #define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000 4166 + #define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10 4167 + #define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1 4168 + #define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0 4169 + #define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2 4170 + #define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1 4171 + #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4 4172 + #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2 4173 + #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8 4174 + #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3 4175 + #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000 4176 + #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf 4177 + #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000 4178 + #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10 4179 + #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1 4180 + #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0 4181 + #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2 4182 + #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1 4183 + #define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK 0x4 4184 + #define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2 4185 + #define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK 0x8 4186 + #define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT 0x3 4187 + #define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK 0x10 4188 + #define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT 0x4 4189 + #define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK 0x20 4190 + #define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT 0x5 4191 + #define PB0_HW_DEBUG__HW_00_DEBUG_MASK 0x1 4192 + #define PB0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 4193 + #define PB0_HW_DEBUG__HW_01_DEBUG_MASK 0x2 4194 + #define PB0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 4195 + #define PB0_HW_DEBUG__HW_02_DEBUG_MASK 0x4 4196 + #define PB0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 4197 + #define PB0_HW_DEBUG__HW_03_DEBUG_MASK 0x8 4198 + #define PB0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 4199 + #define PB0_HW_DEBUG__HW_04_DEBUG_MASK 0x10 4200 + #define PB0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 4201 + #define PB0_HW_DEBUG__HW_05_DEBUG_MASK 0x20 4202 + #define PB0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 4203 + #define PB0_HW_DEBUG__HW_06_DEBUG_MASK 0x40 4204 + #define PB0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 4205 + #define PB0_HW_DEBUG__HW_07_DEBUG_MASK 0x80 4206 + #define PB0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 4207 + #define PB0_HW_DEBUG__HW_08_DEBUG_MASK 0x100 4208 + #define PB0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 4209 + #define PB0_HW_DEBUG__HW_09_DEBUG_MASK 0x200 4210 + #define PB0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 4211 + #define PB0_HW_DEBUG__HW_10_DEBUG_MASK 0x400 4212 + #define PB0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa 4213 + #define PB0_HW_DEBUG__HW_11_DEBUG_MASK 0x800 4214 + #define PB0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb 4215 + #define PB0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 4216 + #define PB0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc 4217 + #define PB0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 4218 + #define PB0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd 4219 + #define PB0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 4220 + #define PB0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe 4221 + #define PB0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 4222 + #define PB0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf 4223 + #define PB0_HW_DEBUG__HW_16_DEBUG_MASK 0x10000 4224 + #define PB0_HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 4225 + #define PB0_HW_DEBUG__HW_17_DEBUG_MASK 0x20000 4226 + #define PB0_HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 4227 + #define PB0_HW_DEBUG__HW_18_DEBUG_MASK 0x40000 4228 + #define PB0_HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 4229 + #define PB0_HW_DEBUG__HW_19_DEBUG_MASK 0x80000 4230 + #define PB0_HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 4231 + #define PB0_HW_DEBUG__HW_20_DEBUG_MASK 0x100000 4232 + #define PB0_HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 4233 + #define PB0_HW_DEBUG__HW_21_DEBUG_MASK 0x200000 4234 + #define PB0_HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 4235 + #define PB0_HW_DEBUG__HW_22_DEBUG_MASK 0x400000 4236 + #define PB0_HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 4237 + #define PB0_HW_DEBUG__HW_23_DEBUG_MASK 0x800000 4238 + #define PB0_HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 4239 + #define PB0_HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 4240 + #define PB0_HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 4241 + #define PB0_HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 4242 + #define PB0_HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 4243 + #define PB0_HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 4244 + #define PB0_HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a 4245 + #define PB0_HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 4246 + #define PB0_HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b 4247 + #define PB0_HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 4248 + #define PB0_HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c 4249 + #define PB0_HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 4250 + #define PB0_HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d 4251 + #define PB0_HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 4252 + #define PB0_HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e 4253 + #define PB0_HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 4254 + #define PB0_HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f 4255 + #define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2 4256 + #define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1 4257 + #define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4 4258 + #define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2 4259 + #define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8 4260 + #define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3 4261 + #define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK 0x10 4262 + #define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT 0x4 4263 + #define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60 4264 + #define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5 4265 + #define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80 4266 + #define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7 4267 + #define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000 4268 + #define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc 4269 + #define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000 4270 + #define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd 4271 + #define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000 4272 + #define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe 4273 + #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000 4274 + #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf 4275 + #define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000 4276 + #define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10 4277 + #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000 4278 + #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14 4279 + #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000 4280 + #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15 4281 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e 4282 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1 4283 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0 4284 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5 4285 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00 4286 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9 4287 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000 4288 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe 4289 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000 4290 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13 4291 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000 4292 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17 4293 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000 4294 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b 4295 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000 4296 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c 4297 + #define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000 4298 + #define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d 4299 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000 4300 + #define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e 4301 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e 4302 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1 4303 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20 4304 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5 4305 + #define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40 4306 + #define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6 4307 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80 4308 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7 4309 + #define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300 4310 + #define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8 4311 + #define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00 4312 + #define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa 4313 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000 4314 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc 4315 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000 4316 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10 4317 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000 4318 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14 4319 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000 4320 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18 4321 + #define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000 4322 + #define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c 4323 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000 4324 + #define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f 4325 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2 4326 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1 4327 + #define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c 4328 + #define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2 4329 + #define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60 4330 + #define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5 4331 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80 4332 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7 4333 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700 4334 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8 4335 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800 4336 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb 4337 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000 4338 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf 4339 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000 4340 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19 4341 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000 4342 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d 4343 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000 4344 + #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f 4345 + #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe 4346 + #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1 4347 + #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0 4348 + #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4 4349 + #define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000 4350 + #define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd 4351 + #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000 4352 + #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf 4353 + #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000 4354 + #define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10 4355 + #define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000 4356 + #define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18 4357 + #define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2 4358 + #define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1 4359 + #define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4 4360 + #define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2 4361 + #define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK 0x6 4362 + #define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT 0x1 4363 + #define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK 0x18 4364 + #define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT 0x3 4365 + #define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK 0x60 4366 + #define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT 0x5 4367 + #define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK 0x80 4368 + #define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT 0x7 4369 + #define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK 0x300 4370 + #define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT 0x8 4371 + #define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK 0x400 4372 + #define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT 0xa 4373 + #define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK 0x1800 4374 + #define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT 0xb 4375 + #define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK 0x1c 4376 + #define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2 4377 + #define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK 0x60 4378 + #define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT 0x5 4379 + #define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK 0x180 4380 + #define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT 0x7 4381 + #define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK 0x600 4382 + #define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT 0x9 4383 + #define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK 0x1800 4384 + #define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT 0xb 4385 + #define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK 0x10000000 4386 + #define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT 0x1c 4387 + #define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK 0x20000000 4388 + #define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT 0x1d 4389 + #define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK 0xc0000000 4390 + #define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT 0x1e 4391 + #define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f 4392 + #define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0 4393 + #define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80 4394 + #define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7 4395 + #define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00 4396 + #define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8 4397 + #define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000 4398 + #define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14 4399 + #define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000 4400 + #define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15 4401 + #define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000 4402 + #define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16 4403 + #define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000 4404 + #define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17 4405 + #define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000 4406 + #define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18 4407 + #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff 4408 + #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0 4409 + #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100 4410 + #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8 4411 + #define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000 4412 + #define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10 4413 + #define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000 4414 + #define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11 4415 + #define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000 4416 + #define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14 4417 + #define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff 4418 + #define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0 4419 + #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1 4420 + #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0 4421 + #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e 4422 + #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1 4423 + #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff 4424 + #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0 4425 + #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00 4426 + #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8 4427 + #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000 4428 + #define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10 4429 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1 4430 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0 4431 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2 4432 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1 4433 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4 4434 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2 4435 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8 4436 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3 4437 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10 4438 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4 4439 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20 4440 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5 4441 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40 4442 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6 4443 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80 4444 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7 4445 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100 4446 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8 4447 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200 4448 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9 4449 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400 4450 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa 4451 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800 4452 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb 4453 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000 4454 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc 4455 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000 4456 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd 4457 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000 4458 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe 4459 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK 0x8000 4460 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT 0xf 4461 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK 0x10000 4462 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x10 4463 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK 0x20000 4464 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT 0x11 4465 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK 0x40000 4466 + #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x12 4467 + #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3 4468 + #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0 4469 + #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4 4470 + #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2 4471 + #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8 4472 + #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3 4473 + #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0 4474 + #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4 4475 + #define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800 4476 + #define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb 4477 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff 4478 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 4479 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100 4480 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8 4481 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00 4482 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9 4483 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000 4484 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc 4485 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000 4486 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd 4487 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000 4488 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe 4489 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000 4490 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf 4491 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000 4492 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c 4493 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000 4494 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e 4495 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000 4496 + #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f 4497 + #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f 4498 + #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0 4499 + #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20 4500 + #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5 4501 + #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0 4502 + #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6 4503 + #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100 4504 + #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8 4505 + #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200 4506 + #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9 4507 + #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400 4508 + #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa 4509 + #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800 4510 + #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb 4511 + #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000 4512 + #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc 4513 + #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000 4514 + #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd 4515 + #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000 4516 + #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe 4517 + #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000 4518 + #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13 4519 + #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000 4520 + #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16 4521 + #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 4522 + #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 4523 + #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 4524 + #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 4525 + #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70 4526 + #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4 4527 + #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK 0x300 4528 + #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT 0x8 4529 + #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 4530 + #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 4531 + #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 4532 + #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 4533 + #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70 4534 + #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4 4535 + #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK 0x300 4536 + #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT 0x8 4537 + #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 4538 + #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 4539 + #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 4540 + #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 4541 + #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70 4542 + #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4 4543 + #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK 0x300 4544 + #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT 0x8 4545 + #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 4546 + #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 4547 + #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 4548 + #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 4549 + #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70 4550 + #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4 4551 + #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK 0x300 4552 + #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT 0x8 4553 + #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3 4554 + #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0 4555 + #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4 4556 + #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2 4557 + #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8 4558 + #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3 4559 + #define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10 4560 + #define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4 4561 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7 4562 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 4563 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8 4564 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3 4565 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70 4566 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4 4567 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80 4568 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7 4569 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100 4570 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8 4571 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200 4572 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9 4573 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00 4574 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa 4575 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000 4576 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12 4577 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000 4578 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13 4579 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000 4580 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c 4581 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000 4582 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d 4583 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000 4584 + #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f 4585 + #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7 4586 + #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0 4587 + #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8 4588 + #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3 4589 + #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10 4590 + #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4 4591 + #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20 4592 + #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5 4593 + #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40 4594 + #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6 4595 + #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80 4596 + #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7 4597 + #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100 4598 + #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8 4599 + #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200 4600 + #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9 4601 + #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000 4602 + #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe 4603 + #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000 4604 + #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12 4605 + #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 4606 + #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 4607 + #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70 4608 + #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4 4609 + #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 4610 + #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 4611 + #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70 4612 + #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4 4613 + #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 4614 + #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 4615 + #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70 4616 + #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4 4617 + #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 4618 + #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 4619 + #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70 4620 + #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4 4621 + #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff 4622 + #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0 4623 + #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00 4624 + #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa 4625 + #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000 4626 + #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14 4627 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf 4628 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0 4629 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0 4630 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4 4631 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00 4632 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8 4633 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000 4634 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc 4635 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000 4636 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10 4637 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000 4638 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14 4639 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000 4640 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18 4641 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000 4642 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19 4643 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000 4644 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a 4645 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000 4646 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b 4647 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000 4648 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c 4649 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000 4650 + #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d 4651 + #define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000 4652 + #define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e 4653 + #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000 4654 + #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc 4655 + #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000 4656 + #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10 4657 + #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000 4658 + #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14 4659 + #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000 4660 + #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18 4661 + #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000 4662 + #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a 4663 + #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000 4664 + #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c 4665 + #define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000 4666 + #define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e 4667 + #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1 4668 + #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0 4669 + #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2 4670 + #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1 4671 + #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4 4672 + #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2 4673 + #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK 0x18 4674 + #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT 0x3 4675 + #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK 0x60 4676 + #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT 0x5 4677 + #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK 0x180 4678 + #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT 0x7 4679 + #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK 0xe00 4680 + #define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT 0x9 4681 + #define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK 0x3000 4682 + #define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT 0xc 4683 + #define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK 0xc000 4684 + #define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT 0xe 4685 + #define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK 0x30000 4686 + #define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT 0x10 4687 + #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000 4688 + #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14 4689 + #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000 4690 + #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18 4691 + #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000 4692 + #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c 4693 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7 4694 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0 4695 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38 4696 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3 4697 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0 4698 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6 4699 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00 4700 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9 4701 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000 4702 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc 4703 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000 4704 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf 4705 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000 4706 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14 4707 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000 4708 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18 4709 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000 4710 + #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c 4711 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f 4712 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0 4713 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0 4714 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5 4715 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00 4716 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa 4717 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000 4718 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf 4719 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000 4720 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10 4721 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000 4722 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11 4723 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000 4724 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12 4725 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000 4726 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13 4727 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000 4728 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14 4729 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000 4730 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b 4731 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000 4732 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c 4733 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000 4734 + #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d 4735 + #define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000 4736 + #define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f 4737 + #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf 4738 + #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0 4739 + #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0 4740 + #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4 4741 + #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00 4742 + #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8 4743 + #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000 4744 + #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc 4745 + #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000 4746 + #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10 4747 + #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000 4748 + #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14 4749 + #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000 4750 + #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18 4751 + #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000 4752 + #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a 4753 + #define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000 4754 + #define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b 4755 + #define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000 4756 + #define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c 4757 + #define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK 0x20000000 4758 + #define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT 0x1d 4759 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf 4760 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0 4761 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0 4762 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4 4763 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00 4764 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8 4765 + #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000 4766 + #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc 4767 + #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000 4768 + #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd 4769 + #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK 0x4000 4770 + #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT 0xe 4771 + #define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK 0x10000 4772 + #define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT 0x10 4773 + #define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK 0x20000 4774 + #define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT 0x11 4775 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000 4776 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12 4777 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000 4778 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15 4779 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000 4780 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18 4781 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000 4782 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b 4783 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000 4784 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c 4785 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000 4786 + #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d 4787 + #define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3 4788 + #define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0 4789 + #define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc 4790 + #define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2 4791 + #define PB0_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN_MASK 0x10 4792 + #define PB0_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN__SHIFT 0x4 4793 + #define PB0_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY_MASK 0x20 4794 + #define PB0_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY__SHIFT 0x5 4795 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK 0x1 4796 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT 0x0 4797 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK 0x2 4798 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT 0x1 4799 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK 0x4 4800 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT 0x2 4801 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK 0x8 4802 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT 0x3 4803 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK 0x10 4804 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT 0x4 4805 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK 0x20 4806 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT 0x5 4807 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK 0x40 4808 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT 0x6 4809 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK 0x80 4810 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT 0x7 4811 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK 0x100 4812 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT 0x8 4813 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK 0x200 4814 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT 0x9 4815 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK 0x400 4816 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT 0xa 4817 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK 0x800 4818 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT 0xb 4819 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK 0x1000 4820 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT 0xc 4821 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK 0x2000 4822 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT 0xd 4823 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK 0x4000 4824 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT 0xe 4825 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK 0x8000 4826 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT 0xf 4827 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK 0x10000 4828 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT 0x10 4829 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK 0x20000 4830 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT 0x11 4831 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK 0x40000 4832 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT 0x12 4833 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK 0x80000 4834 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT 0x13 4835 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK 0x100000 4836 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT 0x14 4837 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK 0x200000 4838 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT 0x15 4839 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK 0x400000 4840 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT 0x16 4841 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK 0x800000 4842 + #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT 0x17 4843 + #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1 4844 + #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0 4845 + #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2 4846 + #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1 4847 + #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4 4848 + #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2 4849 + #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8 4850 + #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3 4851 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0 4852 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6 4853 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100 4854 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8 4855 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200 4856 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9 4857 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400 4858 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa 4859 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800 4860 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb 4861 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000 4862 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc 4863 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000 4864 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd 4865 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000 4866 + #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe 4867 + #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000 4868 + #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf 4869 + #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000 4870 + #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10 4871 + #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000 4872 + #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11 4873 + #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000 4874 + #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12 4875 + #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000 4876 + #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13 4877 + #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000 4878 + #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14 4879 + #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000 4880 + #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15 4881 + #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000 4882 + #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16 4883 + #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000 4884 + #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c 4885 + #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000 4886 + #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d 4887 + #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000 4888 + #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e 4889 + #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000 4890 + #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f 4891 + #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1 4892 + #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0 4893 + #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2 4894 + #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1 4895 + #define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff 4896 + #define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0 4897 + #define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00 4898 + #define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa 4899 + #define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000 4900 + #define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc 4901 + #define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000 4902 + #define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd 4903 + #define PB0_RX_LANE0_CTRL_REG0__RX_TERM_EN_0_MASK 0x4000 4904 + #define PB0_RX_LANE0_CTRL_REG0__RX_TERM_EN_0__SHIFT 0xe 4905 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7 4906 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0 4907 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8 4908 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3 4909 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK 0x40 4910 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT 0x6 4911 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80 4912 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7 4913 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100 4914 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8 4915 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200 4916 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9 4917 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK 0x3fc00 4918 + #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT 0xa 4919 + #define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff 4920 + #define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0 4921 + #define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00 4922 + #define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa 4923 + #define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000 4924 + #define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc 4925 + #define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000 4926 + #define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd 4927 + #define PB0_RX_LANE1_CTRL_REG0__RX_TERM_EN_1_MASK 0x4000 4928 + #define PB0_RX_LANE1_CTRL_REG0__RX_TERM_EN_1__SHIFT 0xe 4929 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7 4930 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0 4931 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8 4932 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3 4933 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK 0x40 4934 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT 0x6 4935 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80 4936 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7 4937 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100 4938 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8 4939 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200 4940 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9 4941 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK 0x3fc00 4942 + #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT 0xa 4943 + #define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff 4944 + #define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0 4945 + #define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00 4946 + #define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa 4947 + #define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000 4948 + #define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc 4949 + #define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000 4950 + #define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd 4951 + #define PB0_RX_LANE2_CTRL_REG0__RX_TERM_EN_2_MASK 0x4000 4952 + #define PB0_RX_LANE2_CTRL_REG0__RX_TERM_EN_2__SHIFT 0xe 4953 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7 4954 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0 4955 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8 4956 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3 4957 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK 0x40 4958 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT 0x6 4959 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80 4960 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7 4961 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100 4962 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8 4963 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200 4964 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9 4965 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK 0x3fc00 4966 + #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT 0xa 4967 + #define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff 4968 + #define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0 4969 + #define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00 4970 + #define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa 4971 + #define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000 4972 + #define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc 4973 + #define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000 4974 + #define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd 4975 + #define PB0_RX_LANE3_CTRL_REG0__RX_TERM_EN_3_MASK 0x4000 4976 + #define PB0_RX_LANE3_CTRL_REG0__RX_TERM_EN_3__SHIFT 0xe 4977 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7 4978 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0 4979 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8 4980 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3 4981 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK 0x40 4982 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT 0x6 4983 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80 4984 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7 4985 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100 4986 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8 4987 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200 4988 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9 4989 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK 0x3fc00 4990 + #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT 0xa 4991 + #define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff 4992 + #define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0 4993 + #define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00 4994 + #define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa 4995 + #define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000 4996 + #define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc 4997 + #define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000 4998 + #define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd 4999 + #define PB0_RX_LANE4_CTRL_REG0__RX_TERM_EN_4_MASK 0x4000 5000 + #define PB0_RX_LANE4_CTRL_REG0__RX_TERM_EN_4__SHIFT 0xe 5001 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7 5002 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0 5003 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8 5004 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3 5005 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK 0x40 5006 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT 0x6 5007 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80 5008 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7 5009 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100 5010 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8 5011 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200 5012 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9 5013 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK 0x3fc00 5014 + #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT 0xa 5015 + #define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff 5016 + #define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0 5017 + #define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00 5018 + #define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa 5019 + #define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000 5020 + #define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc 5021 + #define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000 5022 + #define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd 5023 + #define PB0_RX_LANE5_CTRL_REG0__RX_TERM_EN_5_MASK 0x4000 5024 + #define PB0_RX_LANE5_CTRL_REG0__RX_TERM_EN_5__SHIFT 0xe 5025 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7 5026 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0 5027 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8 5028 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3 5029 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK 0x40 5030 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT 0x6 5031 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80 5032 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7 5033 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100 5034 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8 5035 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200 5036 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9 5037 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK 0x3fc00 5038 + #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT 0xa 5039 + #define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff 5040 + #define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0 5041 + #define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00 5042 + #define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa 5043 + #define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000 5044 + #define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc 5045 + #define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000 5046 + #define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd 5047 + #define PB0_RX_LANE6_CTRL_REG0__RX_TERM_EN_6_MASK 0x4000 5048 + #define PB0_RX_LANE6_CTRL_REG0__RX_TERM_EN_6__SHIFT 0xe 5049 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7 5050 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0 5051 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8 5052 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3 5053 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK 0x40 5054 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT 0x6 5055 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80 5056 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7 5057 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100 5058 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8 5059 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200 5060 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9 5061 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK 0x3fc00 5062 + #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT 0xa 5063 + #define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff 5064 + #define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0 5065 + #define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00 5066 + #define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa 5067 + #define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000 5068 + #define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc 5069 + #define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000 5070 + #define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd 5071 + #define PB0_RX_LANE7_CTRL_REG0__RX_TERM_EN_7_MASK 0x4000 5072 + #define PB0_RX_LANE7_CTRL_REG0__RX_TERM_EN_7__SHIFT 0xe 5073 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7 5074 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0 5075 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8 5076 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3 5077 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK 0x40 5078 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT 0x6 5079 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80 5080 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7 5081 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100 5082 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8 5083 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200 5084 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9 5085 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK 0x3fc00 5086 + #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT 0xa 5087 + #define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff 5088 + #define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0 5089 + #define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00 5090 + #define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa 5091 + #define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000 5092 + #define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc 5093 + #define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000 5094 + #define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd 5095 + #define PB0_RX_LANE8_CTRL_REG0__RX_TERM_EN_8_MASK 0x4000 5096 + #define PB0_RX_LANE8_CTRL_REG0__RX_TERM_EN_8__SHIFT 0xe 5097 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7 5098 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0 5099 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8 5100 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3 5101 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK 0x40 5102 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT 0x6 5103 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80 5104 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7 5105 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100 5106 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8 5107 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200 5108 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9 5109 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK 0x3fc00 5110 + #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT 0xa 5111 + #define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff 5112 + #define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0 5113 + #define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00 5114 + #define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa 5115 + #define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000 5116 + #define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc 5117 + #define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000 5118 + #define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd 5119 + #define PB0_RX_LANE9_CTRL_REG0__RX_TERM_EN_9_MASK 0x4000 5120 + #define PB0_RX_LANE9_CTRL_REG0__RX_TERM_EN_9__SHIFT 0xe 5121 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7 5122 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0 5123 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8 5124 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3 5125 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK 0x40 5126 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT 0x6 5127 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80 5128 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7 5129 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100 5130 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8 5131 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200 5132 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9 5133 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK 0x3fc00 5134 + #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT 0xa 5135 + #define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff 5136 + #define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0 5137 + #define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00 5138 + #define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa 5139 + #define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000 5140 + #define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc 5141 + #define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000 5142 + #define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd 5143 + #define PB0_RX_LANE10_CTRL_REG0__RX_TERM_EN_10_MASK 0x4000 5144 + #define PB0_RX_LANE10_CTRL_REG0__RX_TERM_EN_10__SHIFT 0xe 5145 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7 5146 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0 5147 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8 5148 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3 5149 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK 0x40 5150 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT 0x6 5151 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80 5152 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7 5153 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100 5154 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8 5155 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200 5156 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9 5157 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK 0x3fc00 5158 + #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT 0xa 5159 + #define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff 5160 + #define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0 5161 + #define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00 5162 + #define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa 5163 + #define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000 5164 + #define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc 5165 + #define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000 5166 + #define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd 5167 + #define PB0_RX_LANE11_CTRL_REG0__RX_TERM_EN_11_MASK 0x4000 5168 + #define PB0_RX_LANE11_CTRL_REG0__RX_TERM_EN_11__SHIFT 0xe 5169 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7 5170 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0 5171 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8 5172 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3 5173 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK 0x40 5174 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT 0x6 5175 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80 5176 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7 5177 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100 5178 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8 5179 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200 5180 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9 5181 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK 0x3fc00 5182 + #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT 0xa 5183 + #define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff 5184 + #define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0 5185 + #define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00 5186 + #define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa 5187 + #define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000 5188 + #define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc 5189 + #define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000 5190 + #define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd 5191 + #define PB0_RX_LANE12_CTRL_REG0__RX_TERM_EN_12_MASK 0x4000 5192 + #define PB0_RX_LANE12_CTRL_REG0__RX_TERM_EN_12__SHIFT 0xe 5193 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7 5194 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0 5195 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8 5196 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3 5197 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK 0x40 5198 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT 0x6 5199 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80 5200 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7 5201 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100 5202 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8 5203 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200 5204 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9 5205 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK 0x3fc00 5206 + #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT 0xa 5207 + #define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff 5208 + #define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0 5209 + #define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00 5210 + #define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa 5211 + #define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000 5212 + #define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc 5213 + #define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000 5214 + #define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd 5215 + #define PB0_RX_LANE13_CTRL_REG0__RX_TERM_EN_13_MASK 0x4000 5216 + #define PB0_RX_LANE13_CTRL_REG0__RX_TERM_EN_13__SHIFT 0xe 5217 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7 5218 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0 5219 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8 5220 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3 5221 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK 0x40 5222 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT 0x6 5223 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80 5224 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7 5225 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100 5226 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8 5227 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200 5228 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9 5229 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK 0x3fc00 5230 + #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT 0xa 5231 + #define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff 5232 + #define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0 5233 + #define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00 5234 + #define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa 5235 + #define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000 5236 + #define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc 5237 + #define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000 5238 + #define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd 5239 + #define PB0_RX_LANE14_CTRL_REG0__RX_TERM_EN_14_MASK 0x4000 5240 + #define PB0_RX_LANE14_CTRL_REG0__RX_TERM_EN_14__SHIFT 0xe 5241 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7 5242 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0 5243 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8 5244 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3 5245 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK 0x40 5246 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT 0x6 5247 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80 5248 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7 5249 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100 5250 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8 5251 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200 5252 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9 5253 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK 0x3fc00 5254 + #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT 0xa 5255 + #define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff 5256 + #define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0 5257 + #define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00 5258 + #define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa 5259 + #define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000 5260 + #define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc 5261 + #define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000 5262 + #define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd 5263 + #define PB0_RX_LANE15_CTRL_REG0__RX_TERM_EN_15_MASK 0x4000 5264 + #define PB0_RX_LANE15_CTRL_REG0__RX_TERM_EN_15__SHIFT 0xe 5265 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7 5266 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0 5267 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8 5268 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3 5269 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK 0x40 5270 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT 0x6 5271 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80 5272 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7 5273 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100 5274 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8 5275 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200 5276 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9 5277 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK 0x3fc00 5278 + #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT 0xa 5279 + #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7 5280 + #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0 5281 + #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38 5282 + #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3 5283 + #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700 5284 + #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8 5285 + #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800 5286 + #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb 5287 + #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000 5288 + #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe 5289 + #define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000 5290 + #define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11 5291 + #define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000 5292 + #define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13 5293 + #define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000 5294 + #define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14 5295 + #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000 5296 + #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15 5297 + #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000 5298 + #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16 5299 + #define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000 5300 + #define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17 5301 + #define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK 0x1000000 5302 + #define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT 0x18 5303 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1 5304 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0 5305 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2 5306 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1 5307 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4 5308 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2 5309 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8 5310 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3 5311 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10 5312 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4 5313 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20 5314 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5 5315 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40 5316 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6 5317 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80 5318 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7 5319 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100 5320 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8 5321 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200 5322 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9 5323 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400 5324 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa 5325 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800 5326 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb 5327 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000 5328 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc 5329 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000 5330 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd 5331 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000 5332 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe 5333 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000 5334 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf 5335 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000 5336 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10 5337 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000 5338 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11 5339 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000 5340 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12 5341 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000 5342 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13 5343 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000 5344 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14 5345 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000 5346 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15 5347 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000 5348 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16 5349 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000 5350 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17 5351 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000 5352 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18 5353 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000 5354 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19 5355 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000 5356 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a 5357 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000 5358 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b 5359 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000 5360 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c 5361 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000 5362 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d 5363 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000 5364 + #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e 5365 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK 0x1 5366 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT 0x0 5367 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK 0x2 5368 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT 0x1 5369 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK 0x4 5370 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT 0x2 5371 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK 0x8 5372 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT 0x3 5373 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK 0x100 5374 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT 0x8 5375 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK 0x200 5376 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT 0x9 5377 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK 0x400 5378 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT 0xa 5379 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK 0x800 5380 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT 0xb 5381 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK 0x1000 5382 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT 0xc 5383 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK 0x2000 5384 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT 0xd 5385 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK 0x4000 5386 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT 0xe 5387 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK 0x8000 5388 + #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT 0xf 5389 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1 5390 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0 5391 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2 5392 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1 5393 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4 5394 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2 5395 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8 5396 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3 5397 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10 5398 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4 5399 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20 5400 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5 5401 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40 5402 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6 5403 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80 5404 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7 5405 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100 5406 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8 5407 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200 5408 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9 5409 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400 5410 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa 5411 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800 5412 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb 5413 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000 5414 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc 5415 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000 5416 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd 5417 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000 5418 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe 5419 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000 5420 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf 5421 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000 5422 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10 5423 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000 5424 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11 5425 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000 5426 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12 5427 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000 5428 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13 5429 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000 5430 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14 5431 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000 5432 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15 5433 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000 5434 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16 5435 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000 5436 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17 5437 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000 5438 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18 5439 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000 5440 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19 5441 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000 5442 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a 5443 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000 5444 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b 5445 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000 5446 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c 5447 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000 5448 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d 5449 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000 5450 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e 5451 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000 5452 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f 5453 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1 5454 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0 5455 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2 5456 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1 5457 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4 5458 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2 5459 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8 5460 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3 5461 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10 5462 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4 5463 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20 5464 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5 5465 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40 5466 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6 5467 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80 5468 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7 5469 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100 5470 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8 5471 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200 5472 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9 5473 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400 5474 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa 5475 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800 5476 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb 5477 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000 5478 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc 5479 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000 5480 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd 5481 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000 5482 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe 5483 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000 5484 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf 5485 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000 5486 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10 5487 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000 5488 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11 5489 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000 5490 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12 5491 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000 5492 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13 5493 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000 5494 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14 5495 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000 5496 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15 5497 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000 5498 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16 5499 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000 5500 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17 5501 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000 5502 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18 5503 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000 5504 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19 5505 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000 5506 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a 5507 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000 5508 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b 5509 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000 5510 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c 5511 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000 5512 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d 5513 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000 5514 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e 5515 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000 5516 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f 5517 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1 5518 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0 5519 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2 5520 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1 5521 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4 5522 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2 5523 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8 5524 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3 5525 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10 5526 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4 5527 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20 5528 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5 5529 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40 5530 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6 5531 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80 5532 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7 5533 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100 5534 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8 5535 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200 5536 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9 5537 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400 5538 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa 5539 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800 5540 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb 5541 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000 5542 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc 5543 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000 5544 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd 5545 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000 5546 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe 5547 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000 5548 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf 5549 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000 5550 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10 5551 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000 5552 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11 5553 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000 5554 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12 5555 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000 5556 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13 5557 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000 5558 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14 5559 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000 5560 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15 5561 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000 5562 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16 5563 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000 5564 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17 5565 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000 5566 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18 5567 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000 5568 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19 5569 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000 5570 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a 5571 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000 5572 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b 5573 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000 5574 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c 5575 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000 5576 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d 5577 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000 5578 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e 5579 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000 5580 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f 5581 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1 5582 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0 5583 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2 5584 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1 5585 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4 5586 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2 5587 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8 5588 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3 5589 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10 5590 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4 5591 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20 5592 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5 5593 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40 5594 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6 5595 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80 5596 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7 5597 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100 5598 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8 5599 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200 5600 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9 5601 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400 5602 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa 5603 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800 5604 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb 5605 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000 5606 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc 5607 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000 5608 + #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd 5609 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7 5610 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0 5611 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8 5612 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3 5613 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0 5614 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4 5615 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100 5616 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8 5617 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00 5618 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9 5619 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000 5620 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd 5621 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000 5622 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe 5623 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000 5624 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13 5625 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000 5626 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14 5627 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000 5628 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19 5629 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000 5630 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a 5631 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000 5632 + #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e 5633 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf 5634 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0 5635 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10 5636 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4 5637 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20 5638 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5 5639 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40 5640 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6 5641 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80 5642 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7 5643 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100 5644 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8 5645 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200 5646 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9 5647 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400 5648 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa 5649 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800 5650 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb 5651 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000 5652 + #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc 5653 + #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000 5654 + #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd 5655 + #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000 5656 + #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe 5657 + #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000 5658 + #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf 5659 + #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000 5660 + #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19 5661 + #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000 5662 + #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a 5663 + #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000 5664 + #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b 5665 + #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000 5666 + #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c 5667 + #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000 5668 + #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d 5669 + #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000 5670 + #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e 5671 + #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000 5672 + #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f 5673 + #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1 5674 + #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0 5675 + #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2 5676 + #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1 5677 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4 5678 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2 5679 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8 5680 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3 5681 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10 5682 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4 5683 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20 5684 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5 5685 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40 5686 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6 5687 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80 5688 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7 5689 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100 5690 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8 5691 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200 5692 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9 5693 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400 5694 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa 5695 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800 5696 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb 5697 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000 5698 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc 5699 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000 5700 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10 5701 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000 5702 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14 5703 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000 5704 + #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19 5705 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf 5706 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0 5707 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0 5708 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4 5709 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100 5710 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8 5711 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200 5712 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9 5713 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00 5714 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa 5715 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000 5716 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe 5717 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000 5718 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12 5719 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000 5720 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17 5721 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000 5722 + #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c 5723 + #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf 5724 + #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0 5725 + #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10 5726 + #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4 5727 + #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20 5728 + #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5 5729 + #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1 5730 + #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0 5731 + #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2 5732 + #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1 5733 + #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4 5734 + #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2 5735 + #define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8 5736 + #define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3 5737 + #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1 5738 + #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0 5739 + #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2 5740 + #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1 5741 + #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4 5742 + #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2 5743 + #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8 5744 + #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3 5745 + #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10 5746 + #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4 5747 + #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20 5748 + #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5 5749 + #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40 5750 + #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6 5751 + #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80 5752 + #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7 5753 + #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7 5754 + #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0 5755 + #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70 5756 + #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4 5757 + #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80 5758 + #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7 5759 + #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300 5760 + #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8 5761 + #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00 5762 + #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa 5763 + #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1 5764 + #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0 5765 + #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2 5766 + #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1 5767 + #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4 5768 + #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2 5769 + #define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8 5770 + #define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3 5771 + #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1 5772 + #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0 5773 + #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2 5774 + #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1 5775 + #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4 5776 + #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2 5777 + #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8 5778 + #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3 5779 + #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10 5780 + #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4 5781 + #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20 5782 + #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5 5783 + #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40 5784 + #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6 5785 + #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80 5786 + #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7 5787 + #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7 5788 + #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0 5789 + #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70 5790 + #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4 5791 + #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80 5792 + #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7 5793 + #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300 5794 + #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8 5795 + #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00 5796 + #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa 5797 + #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1 5798 + #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0 5799 + #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2 5800 + #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1 5801 + #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4 5802 + #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2 5803 + #define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8 5804 + #define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3 5805 + #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1 5806 + #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0 5807 + #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2 5808 + #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1 5809 + #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4 5810 + #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2 5811 + #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8 5812 + #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3 5813 + #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10 5814 + #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4 5815 + #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20 5816 + #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5 5817 + #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40 5818 + #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6 5819 + #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80 5820 + #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7 5821 + #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7 5822 + #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0 5823 + #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70 5824 + #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4 5825 + #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80 5826 + #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7 5827 + #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300 5828 + #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8 5829 + #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00 5830 + #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa 5831 + #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1 5832 + #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0 5833 + #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2 5834 + #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1 5835 + #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4 5836 + #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2 5837 + #define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8 5838 + #define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3 5839 + #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1 5840 + #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0 5841 + #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2 5842 + #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1 5843 + #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4 5844 + #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2 5845 + #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8 5846 + #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3 5847 + #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10 5848 + #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4 5849 + #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20 5850 + #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5 5851 + #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40 5852 + #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6 5853 + #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80 5854 + #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7 5855 + #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7 5856 + #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0 5857 + #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70 5858 + #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4 5859 + #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80 5860 + #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7 5861 + #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300 5862 + #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8 5863 + #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00 5864 + #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa 5865 + #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1 5866 + #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0 5867 + #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2 5868 + #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1 5869 + #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4 5870 + #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2 5871 + #define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8 5872 + #define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3 5873 + #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1 5874 + #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0 5875 + #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2 5876 + #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1 5877 + #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4 5878 + #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2 5879 + #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8 5880 + #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3 5881 + #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10 5882 + #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4 5883 + #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20 5884 + #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5 5885 + #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40 5886 + #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6 5887 + #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80 5888 + #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7 5889 + #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7 5890 + #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0 5891 + #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70 5892 + #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4 5893 + #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80 5894 + #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7 5895 + #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300 5896 + #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8 5897 + #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00 5898 + #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa 5899 + #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1 5900 + #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0 5901 + #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2 5902 + #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1 5903 + #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4 5904 + #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2 5905 + #define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8 5906 + #define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3 5907 + #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1 5908 + #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0 5909 + #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2 5910 + #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1 5911 + #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4 5912 + #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2 5913 + #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8 5914 + #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3 5915 + #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10 5916 + #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4 5917 + #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20 5918 + #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5 5919 + #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40 5920 + #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6 5921 + #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80 5922 + #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7 5923 + #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7 5924 + #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0 5925 + #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70 5926 + #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4 5927 + #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80 5928 + #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7 5929 + #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300 5930 + #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8 5931 + #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00 5932 + #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa 5933 + #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1 5934 + #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0 5935 + #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2 5936 + #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1 5937 + #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4 5938 + #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2 5939 + #define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8 5940 + #define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3 5941 + #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1 5942 + #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0 5943 + #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2 5944 + #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1 5945 + #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4 5946 + #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2 5947 + #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8 5948 + #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3 5949 + #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10 5950 + #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4 5951 + #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20 5952 + #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5 5953 + #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40 5954 + #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6 5955 + #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80 5956 + #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7 5957 + #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7 5958 + #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0 5959 + #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70 5960 + #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4 5961 + #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80 5962 + #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7 5963 + #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300 5964 + #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8 5965 + #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00 5966 + #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa 5967 + #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1 5968 + #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0 5969 + #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2 5970 + #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1 5971 + #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4 5972 + #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2 5973 + #define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8 5974 + #define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3 5975 + #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1 5976 + #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0 5977 + #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2 5978 + #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1 5979 + #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4 5980 + #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2 5981 + #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8 5982 + #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3 5983 + #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10 5984 + #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4 5985 + #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20 5986 + #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5 5987 + #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40 5988 + #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6 5989 + #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80 5990 + #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7 5991 + #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7 5992 + #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0 5993 + #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70 5994 + #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4 5995 + #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80 5996 + #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7 5997 + #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300 5998 + #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8 5999 + #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00 6000 + #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa 6001 + #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1 6002 + #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0 6003 + #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2 6004 + #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1 6005 + #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4 6006 + #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2 6007 + #define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8 6008 + #define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3 6009 + #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1 6010 + #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0 6011 + #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2 6012 + #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1 6013 + #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4 6014 + #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2 6015 + #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8 6016 + #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3 6017 + #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10 6018 + #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4 6019 + #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20 6020 + #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5 6021 + #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40 6022 + #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6 6023 + #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80 6024 + #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7 6025 + #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7 6026 + #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0 6027 + #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70 6028 + #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4 6029 + #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80 6030 + #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7 6031 + #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300 6032 + #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8 6033 + #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00 6034 + #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa 6035 + #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1 6036 + #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0 6037 + #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2 6038 + #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1 6039 + #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4 6040 + #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2 6041 + #define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8 6042 + #define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3 6043 + #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1 6044 + #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0 6045 + #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2 6046 + #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1 6047 + #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4 6048 + #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2 6049 + #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8 6050 + #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3 6051 + #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10 6052 + #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4 6053 + #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20 6054 + #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5 6055 + #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40 6056 + #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6 6057 + #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80 6058 + #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7 6059 + #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7 6060 + #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0 6061 + #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70 6062 + #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4 6063 + #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80 6064 + #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7 6065 + #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300 6066 + #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8 6067 + #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00 6068 + #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa 6069 + #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1 6070 + #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0 6071 + #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2 6072 + #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1 6073 + #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4 6074 + #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2 6075 + #define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8 6076 + #define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3 6077 + #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1 6078 + #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0 6079 + #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2 6080 + #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1 6081 + #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4 6082 + #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2 6083 + #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8 6084 + #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3 6085 + #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10 6086 + #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4 6087 + #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20 6088 + #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5 6089 + #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40 6090 + #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6 6091 + #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80 6092 + #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7 6093 + #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7 6094 + #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0 6095 + #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70 6096 + #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4 6097 + #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80 6098 + #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7 6099 + #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300 6100 + #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8 6101 + #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00 6102 + #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa 6103 + #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1 6104 + #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0 6105 + #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2 6106 + #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1 6107 + #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4 6108 + #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2 6109 + #define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8 6110 + #define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3 6111 + #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1 6112 + #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0 6113 + #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2 6114 + #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1 6115 + #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4 6116 + #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2 6117 + #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8 6118 + #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3 6119 + #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10 6120 + #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4 6121 + #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20 6122 + #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5 6123 + #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40 6124 + #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6 6125 + #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80 6126 + #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7 6127 + #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7 6128 + #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0 6129 + #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70 6130 + #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4 6131 + #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80 6132 + #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7 6133 + #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300 6134 + #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8 6135 + #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00 6136 + #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa 6137 + #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1 6138 + #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0 6139 + #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2 6140 + #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1 6141 + #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4 6142 + #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2 6143 + #define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8 6144 + #define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3 6145 + #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1 6146 + #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0 6147 + #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2 6148 + #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1 6149 + #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4 6150 + #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2 6151 + #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8 6152 + #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3 6153 + #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10 6154 + #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4 6155 + #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20 6156 + #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5 6157 + #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40 6158 + #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6 6159 + #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80 6160 + #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7 6161 + #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7 6162 + #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0 6163 + #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70 6164 + #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4 6165 + #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80 6166 + #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7 6167 + #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300 6168 + #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8 6169 + #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00 6170 + #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa 6171 + #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1 6172 + #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0 6173 + #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2 6174 + #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1 6175 + #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4 6176 + #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2 6177 + #define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8 6178 + #define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3 6179 + #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1 6180 + #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0 6181 + #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2 6182 + #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1 6183 + #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4 6184 + #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2 6185 + #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8 6186 + #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3 6187 + #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10 6188 + #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4 6189 + #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20 6190 + #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5 6191 + #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40 6192 + #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6 6193 + #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80 6194 + #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7 6195 + #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7 6196 + #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0 6197 + #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70 6198 + #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4 6199 + #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80 6200 + #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7 6201 + #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300 6202 + #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8 6203 + #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00 6204 + #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa 6205 + #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1 6206 + #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0 6207 + #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2 6208 + #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1 6209 + #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4 6210 + #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2 6211 + #define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8 6212 + #define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3 6213 + #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1 6214 + #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0 6215 + #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2 6216 + #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1 6217 + #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4 6218 + #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2 6219 + #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8 6220 + #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3 6221 + #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10 6222 + #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4 6223 + #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20 6224 + #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5 6225 + #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40 6226 + #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6 6227 + #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80 6228 + #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7 6229 + #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7 6230 + #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0 6231 + #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70 6232 + #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4 6233 + #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80 6234 + #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7 6235 + #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300 6236 + #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8 6237 + #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00 6238 + #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa 6239 + #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1 6240 + #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0 6241 + #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2 6242 + #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1 6243 + #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4 6244 + #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2 6245 + #define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8 6246 + #define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3 6247 + #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1 6248 + #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0 6249 + #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2 6250 + #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1 6251 + #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4 6252 + #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2 6253 + #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8 6254 + #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3 6255 + #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10 6256 + #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4 6257 + #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20 6258 + #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5 6259 + #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40 6260 + #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6 6261 + #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80 6262 + #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7 6263 + #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7 6264 + #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0 6265 + #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70 6266 + #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4 6267 + #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80 6268 + #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7 6269 + #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300 6270 + #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8 6271 + #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00 6272 + #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa 6273 + #define PB1_GLB_CTRL_REG0__BACKUP_MASK 0xffff 6274 + #define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x0 6275 + #define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000 6276 + #define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10 6277 + #define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000 6278 + #define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14 6279 + #define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000 6280 + #define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17 6281 + #define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000 6282 + #define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18 6283 + #define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000 6284 + #define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19 6285 + #define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000 6286 + #define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a 6287 + #define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000 6288 + #define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e 6289 + #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1 6290 + #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0 6291 + #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e 6292 + #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1 6293 + #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80 6294 + #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7 6295 + #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00 6296 + #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8 6297 + #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000 6298 + #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe 6299 + #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000 6300 + #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf 6301 + #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000 6302 + #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16 6303 + #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000 6304 + #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17 6305 + #define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000 6306 + #define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e 6307 + #define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000 6308 + #define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f 6309 + #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1 6310 + #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0 6311 + #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe 6312 + #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1 6313 + #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100 6314 + #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8 6315 + #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00 6316 + #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9 6317 + #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000 6318 + #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10 6319 + #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000 6320 + #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11 6321 + #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000 6322 + #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18 6323 + #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000 6324 + #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19 6325 + #define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f 6326 + #define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0 6327 + #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60 6328 + #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5 6329 + #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180 6330 + #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7 6331 + #define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600 6332 + #define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9 6333 + #define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800 6334 + #define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb 6335 + #define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000 6336 + #define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc 6337 + #define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000 6338 + #define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe 6339 + #define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000 6340 + #define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12 6341 + #define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000 6342 + #define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15 6343 + #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000 6344 + #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16 6345 + #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000 6346 + #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17 6347 + #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000 6348 + #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b 6349 + #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000 6350 + #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c 6351 + #define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000 6352 + #define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f 6353 + #define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff 6354 + #define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0 6355 + #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000 6356 + #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10 6357 + #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000 6358 + #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12 6359 + #define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000 6360 + #define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16 6361 + #define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000 6362 + #define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a 6363 + #define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000 6364 + #define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b 6365 + #define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000 6366 + #define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c 6367 + #define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff 6368 + #define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0 6369 + #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK 0x1 6370 + #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT 0x0 6371 + #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2 6372 + #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT 0x1 6373 + #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK 0x4 6374 + #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2 6375 + #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK 0x8 6376 + #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT 0x3 6377 + #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK 0x10 6378 + #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT 0x4 6379 + #define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00 6380 + #define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8 6381 + #define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000 6382 + #define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc 6383 + #define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000 6384 + #define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10 6385 + #define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000 6386 + #define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14 6387 + #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK 0x1 6388 + #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT 0x0 6389 + #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2 6390 + #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT 0x1 6391 + #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK 0x4 6392 + #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2 6393 + #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000 6394 + #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc 6395 + #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000 6396 + #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd 6397 + #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000 6398 + #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe 6399 + #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000 6400 + #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf 6401 + #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK 0x30000 6402 + #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT 0x10 6403 + #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000 6404 + #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12 6405 + #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK 0x300000 6406 + #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT 0x14 6407 + #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000 6408 + #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16 6409 + #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK 0x3000000 6410 + #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT 0x18 6411 + #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000 6412 + #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a 6413 + #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK 0x30000000 6414 + #define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT 0x1c 6415 + #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000 6416 + #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e 6417 + #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK 0x1 6418 + #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT 0x0 6419 + #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2 6420 + #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT 0x1 6421 + #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK 0x4 6422 + #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2 6423 + #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000 6424 + #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc 6425 + #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000 6426 + #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd 6427 + #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000 6428 + #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe 6429 + #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000 6430 + #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf 6431 + #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK 0x30000 6432 + #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT 0x10 6433 + #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000 6434 + #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12 6435 + #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK 0x300000 6436 + #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT 0x14 6437 + #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000 6438 + #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16 6439 + #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK 0x3000000 6440 + #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT 0x18 6441 + #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000 6442 + #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a 6443 + #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK 0x30000000 6444 + #define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT 0x1c 6445 + #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000 6446 + #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e 6447 + #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK 0x1 6448 + #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT 0x0 6449 + #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2 6450 + #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT 0x1 6451 + #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK 0x4 6452 + #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2 6453 + #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000 6454 + #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc 6455 + #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000 6456 + #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd 6457 + #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000 6458 + #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe 6459 + #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000 6460 + #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf 6461 + #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK 0x30000 6462 + #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT 0x10 6463 + #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000 6464 + #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12 6465 + #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK 0x300000 6466 + #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT 0x14 6467 + #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000 6468 + #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16 6469 + #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK 0x3000000 6470 + #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT 0x18 6471 + #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000 6472 + #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a 6473 + #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK 0x30000000 6474 + #define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT 0x1c 6475 + #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000 6476 + #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e 6477 + #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK 0x1 6478 + #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT 0x0 6479 + #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2 6480 + #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT 0x1 6481 + #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK 0x4 6482 + #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2 6483 + #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000 6484 + #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc 6485 + #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000 6486 + #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd 6487 + #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000 6488 + #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe 6489 + #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000 6490 + #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf 6491 + #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK 0x30000 6492 + #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT 0x10 6493 + #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000 6494 + #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12 6495 + #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK 0x300000 6496 + #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT 0x14 6497 + #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000 6498 + #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16 6499 + #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK 0x3000000 6500 + #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT 0x18 6501 + #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000 6502 + #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a 6503 + #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK 0x30000000 6504 + #define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT 0x1c 6505 + #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000 6506 + #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e 6507 + #define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff 6508 + #define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0 6509 + #define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000 6510 + #define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10 6511 + #define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1 6512 + #define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0 6513 + #define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2 6514 + #define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1 6515 + #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4 6516 + #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2 6517 + #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8 6518 + #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3 6519 + #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000 6520 + #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf 6521 + #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000 6522 + #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10 6523 + #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1 6524 + #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0 6525 + #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2 6526 + #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1 6527 + #define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK 0x4 6528 + #define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2 6529 + #define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK 0x8 6530 + #define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT 0x3 6531 + #define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK 0x10 6532 + #define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT 0x4 6533 + #define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK 0x20 6534 + #define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT 0x5 6535 + #define PB1_HW_DEBUG__HW_00_DEBUG_MASK 0x1 6536 + #define PB1_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 6537 + #define PB1_HW_DEBUG__HW_01_DEBUG_MASK 0x2 6538 + #define PB1_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 6539 + #define PB1_HW_DEBUG__HW_02_DEBUG_MASK 0x4 6540 + #define PB1_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 6541 + #define PB1_HW_DEBUG__HW_03_DEBUG_MASK 0x8 6542 + #define PB1_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 6543 + #define PB1_HW_DEBUG__HW_04_DEBUG_MASK 0x10 6544 + #define PB1_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 6545 + #define PB1_HW_DEBUG__HW_05_DEBUG_MASK 0x20 6546 + #define PB1_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 6547 + #define PB1_HW_DEBUG__HW_06_DEBUG_MASK 0x40 6548 + #define PB1_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 6549 + #define PB1_HW_DEBUG__HW_07_DEBUG_MASK 0x80 6550 + #define PB1_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 6551 + #define PB1_HW_DEBUG__HW_08_DEBUG_MASK 0x100 6552 + #define PB1_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 6553 + #define PB1_HW_DEBUG__HW_09_DEBUG_MASK 0x200 6554 + #define PB1_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 6555 + #define PB1_HW_DEBUG__HW_10_DEBUG_MASK 0x400 6556 + #define PB1_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa 6557 + #define PB1_HW_DEBUG__HW_11_DEBUG_MASK 0x800 6558 + #define PB1_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb 6559 + #define PB1_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 6560 + #define PB1_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc 6561 + #define PB1_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 6562 + #define PB1_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd 6563 + #define PB1_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 6564 + #define PB1_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe 6565 + #define PB1_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 6566 + #define PB1_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf 6567 + #define PB1_HW_DEBUG__HW_16_DEBUG_MASK 0x10000 6568 + #define PB1_HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 6569 + #define PB1_HW_DEBUG__HW_17_DEBUG_MASK 0x20000 6570 + #define PB1_HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 6571 + #define PB1_HW_DEBUG__HW_18_DEBUG_MASK 0x40000 6572 + #define PB1_HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 6573 + #define PB1_HW_DEBUG__HW_19_DEBUG_MASK 0x80000 6574 + #define PB1_HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 6575 + #define PB1_HW_DEBUG__HW_20_DEBUG_MASK 0x100000 6576 + #define PB1_HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 6577 + #define PB1_HW_DEBUG__HW_21_DEBUG_MASK 0x200000 6578 + #define PB1_HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 6579 + #define PB1_HW_DEBUG__HW_22_DEBUG_MASK 0x400000 6580 + #define PB1_HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 6581 + #define PB1_HW_DEBUG__HW_23_DEBUG_MASK 0x800000 6582 + #define PB1_HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 6583 + #define PB1_HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 6584 + #define PB1_HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 6585 + #define PB1_HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 6586 + #define PB1_HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 6587 + #define PB1_HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 6588 + #define PB1_HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a 6589 + #define PB1_HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 6590 + #define PB1_HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b 6591 + #define PB1_HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 6592 + #define PB1_HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c 6593 + #define PB1_HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 6594 + #define PB1_HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d 6595 + #define PB1_HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 6596 + #define PB1_HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e 6597 + #define PB1_HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 6598 + #define PB1_HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f 6599 + #define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2 6600 + #define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1 6601 + #define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4 6602 + #define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2 6603 + #define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8 6604 + #define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3 6605 + #define PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK 0x10 6606 + #define PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT 0x4 6607 + #define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60 6608 + #define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5 6609 + #define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80 6610 + #define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7 6611 + #define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000 6612 + #define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc 6613 + #define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000 6614 + #define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd 6615 + #define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000 6616 + #define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe 6617 + #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000 6618 + #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf 6619 + #define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000 6620 + #define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10 6621 + #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000 6622 + #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14 6623 + #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000 6624 + #define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15 6625 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e 6626 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1 6627 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0 6628 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5 6629 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00 6630 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9 6631 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000 6632 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe 6633 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000 6634 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13 6635 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000 6636 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17 6637 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000 6638 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b 6639 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000 6640 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c 6641 + #define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000 6642 + #define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d 6643 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000 6644 + #define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e 6645 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e 6646 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1 6647 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20 6648 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5 6649 + #define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40 6650 + #define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6 6651 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80 6652 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7 6653 + #define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300 6654 + #define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8 6655 + #define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00 6656 + #define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa 6657 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000 6658 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc 6659 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000 6660 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10 6661 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000 6662 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14 6663 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000 6664 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18 6665 + #define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000 6666 + #define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c 6667 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000 6668 + #define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f 6669 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2 6670 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1 6671 + #define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c 6672 + #define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2 6673 + #define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60 6674 + #define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5 6675 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80 6676 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7 6677 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700 6678 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8 6679 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800 6680 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb 6681 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000 6682 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf 6683 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000 6684 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19 6685 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000 6686 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d 6687 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000 6688 + #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f 6689 + #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe 6690 + #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1 6691 + #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0 6692 + #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4 6693 + #define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000 6694 + #define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd 6695 + #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000 6696 + #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf 6697 + #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000 6698 + #define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10 6699 + #define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000 6700 + #define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18 6701 + #define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2 6702 + #define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1 6703 + #define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4 6704 + #define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2 6705 + #define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK 0x6 6706 + #define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT 0x1 6707 + #define PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK 0x18 6708 + #define PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT 0x3 6709 + #define PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK 0x60 6710 + #define PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT 0x5 6711 + #define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK 0x80 6712 + #define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT 0x7 6713 + #define PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK 0x300 6714 + #define PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT 0x8 6715 + #define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK 0x400 6716 + #define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT 0xa 6717 + #define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK 0x1800 6718 + #define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT 0xb 6719 + #define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK 0x1c 6720 + #define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2 6721 + #define PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK 0x60 6722 + #define PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT 0x5 6723 + #define PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK 0x180 6724 + #define PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT 0x7 6725 + #define PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK 0x600 6726 + #define PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT 0x9 6727 + #define PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK 0x1800 6728 + #define PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT 0xb 6729 + #define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK 0x10000000 6730 + #define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT 0x1c 6731 + #define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK 0x20000000 6732 + #define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT 0x1d 6733 + #define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK 0xc0000000 6734 + #define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT 0x1e 6735 + #define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f 6736 + #define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0 6737 + #define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80 6738 + #define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7 6739 + #define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00 6740 + #define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8 6741 + #define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000 6742 + #define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14 6743 + #define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000 6744 + #define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15 6745 + #define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000 6746 + #define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16 6747 + #define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000 6748 + #define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17 6749 + #define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000 6750 + #define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18 6751 + #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff 6752 + #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0 6753 + #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100 6754 + #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8 6755 + #define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000 6756 + #define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10 6757 + #define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000 6758 + #define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11 6759 + #define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000 6760 + #define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14 6761 + #define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff 6762 + #define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0 6763 + #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1 6764 + #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0 6765 + #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e 6766 + #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1 6767 + #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff 6768 + #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0 6769 + #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00 6770 + #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8 6771 + #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000 6772 + #define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10 6773 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1 6774 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0 6775 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2 6776 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1 6777 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4 6778 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2 6779 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8 6780 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3 6781 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10 6782 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4 6783 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20 6784 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5 6785 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40 6786 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6 6787 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80 6788 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7 6789 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100 6790 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8 6791 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200 6792 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9 6793 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400 6794 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa 6795 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800 6796 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb 6797 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000 6798 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc 6799 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000 6800 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd 6801 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000 6802 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe 6803 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK 0x8000 6804 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT 0xf 6805 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK 0x10000 6806 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x10 6807 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK 0x20000 6808 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT 0x11 6809 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK 0x40000 6810 + #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x12 6811 + #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3 6812 + #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0 6813 + #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4 6814 + #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2 6815 + #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8 6816 + #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3 6817 + #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0 6818 + #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4 6819 + #define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800 6820 + #define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb 6821 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff 6822 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 6823 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100 6824 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8 6825 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00 6826 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9 6827 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000 6828 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc 6829 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000 6830 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd 6831 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000 6832 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe 6833 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000 6834 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf 6835 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000 6836 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c 6837 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000 6838 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e 6839 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000 6840 + #define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f 6841 + #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f 6842 + #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0 6843 + #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20 6844 + #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5 6845 + #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0 6846 + #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6 6847 + #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100 6848 + #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8 6849 + #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200 6850 + #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9 6851 + #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400 6852 + #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa 6853 + #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800 6854 + #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb 6855 + #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000 6856 + #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc 6857 + #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000 6858 + #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd 6859 + #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000 6860 + #define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe 6861 + #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000 6862 + #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13 6863 + #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000 6864 + #define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16 6865 + #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 6866 + #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 6867 + #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 6868 + #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 6869 + #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70 6870 + #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4 6871 + #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK 0x300 6872 + #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT 0x8 6873 + #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 6874 + #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 6875 + #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 6876 + #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 6877 + #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70 6878 + #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4 6879 + #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK 0x300 6880 + #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT 0x8 6881 + #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 6882 + #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 6883 + #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 6884 + #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 6885 + #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70 6886 + #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4 6887 + #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK 0x300 6888 + #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT 0x8 6889 + #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 6890 + #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 6891 + #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 6892 + #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 6893 + #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70 6894 + #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4 6895 + #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK 0x300 6896 + #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT 0x8 6897 + #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3 6898 + #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0 6899 + #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4 6900 + #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2 6901 + #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8 6902 + #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3 6903 + #define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10 6904 + #define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4 6905 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7 6906 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 6907 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8 6908 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3 6909 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70 6910 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4 6911 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80 6912 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7 6913 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100 6914 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8 6915 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200 6916 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9 6917 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00 6918 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa 6919 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000 6920 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12 6921 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000 6922 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13 6923 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000 6924 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c 6925 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000 6926 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d 6927 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000 6928 + #define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f 6929 + #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7 6930 + #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0 6931 + #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8 6932 + #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3 6933 + #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10 6934 + #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4 6935 + #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20 6936 + #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5 6937 + #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40 6938 + #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6 6939 + #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80 6940 + #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7 6941 + #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100 6942 + #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8 6943 + #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200 6944 + #define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9 6945 + #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000 6946 + #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe 6947 + #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000 6948 + #define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12 6949 + #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 6950 + #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 6951 + #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70 6952 + #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4 6953 + #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 6954 + #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 6955 + #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70 6956 + #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4 6957 + #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 6958 + #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 6959 + #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70 6960 + #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4 6961 + #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 6962 + #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 6963 + #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70 6964 + #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4 6965 + #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff 6966 + #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0 6967 + #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00 6968 + #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa 6969 + #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000 6970 + #define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14 6971 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf 6972 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0 6973 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0 6974 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4 6975 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00 6976 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8 6977 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000 6978 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc 6979 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000 6980 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10 6981 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000 6982 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14 6983 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000 6984 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18 6985 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000 6986 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19 6987 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000 6988 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a 6989 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000 6990 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b 6991 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000 6992 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c 6993 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000 6994 + #define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d 6995 + #define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000 6996 + #define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e 6997 + #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000 6998 + #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc 6999 + #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000 7000 + #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10 7001 + #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000 7002 + #define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14 7003 + #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000 7004 + #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18 7005 + #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000 7006 + #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a 7007 + #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000 7008 + #define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c 7009 + #define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000 7010 + #define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e 7011 + #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1 7012 + #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0 7013 + #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2 7014 + #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1 7015 + #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4 7016 + #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2 7017 + #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK 0x18 7018 + #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT 0x3 7019 + #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK 0x60 7020 + #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT 0x5 7021 + #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK 0x180 7022 + #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT 0x7 7023 + #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK 0xe00 7024 + #define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT 0x9 7025 + #define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK 0x3000 7026 + #define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT 0xc 7027 + #define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK 0xc000 7028 + #define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT 0xe 7029 + #define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK 0x30000 7030 + #define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT 0x10 7031 + #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000 7032 + #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14 7033 + #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000 7034 + #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18 7035 + #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000 7036 + #define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c 7037 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7 7038 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0 7039 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38 7040 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3 7041 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0 7042 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6 7043 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00 7044 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9 7045 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000 7046 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc 7047 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000 7048 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf 7049 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000 7050 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14 7051 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000 7052 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18 7053 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000 7054 + #define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c 7055 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f 7056 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0 7057 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0 7058 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5 7059 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00 7060 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa 7061 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000 7062 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf 7063 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000 7064 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10 7065 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000 7066 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11 7067 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000 7068 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12 7069 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000 7070 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13 7071 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000 7072 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14 7073 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000 7074 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b 7075 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000 7076 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c 7077 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000 7078 + #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d 7079 + #define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000 7080 + #define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f 7081 + #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf 7082 + #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0 7083 + #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0 7084 + #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4 7085 + #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00 7086 + #define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8 7087 + #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000 7088 + #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc 7089 + #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000 7090 + #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10 7091 + #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000 7092 + #define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14 7093 + #define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000 7094 + #define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18 7095 + #define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000 7096 + #define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a 7097 + #define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000 7098 + #define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b 7099 + #define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000 7100 + #define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c 7101 + #define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK 0x20000000 7102 + #define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT 0x1d 7103 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf 7104 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0 7105 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0 7106 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4 7107 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00 7108 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8 7109 + #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000 7110 + #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc 7111 + #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000 7112 + #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd 7113 + #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK 0x4000 7114 + #define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT 0xe 7115 + #define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK 0x10000 7116 + #define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT 0x10 7117 + #define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK 0x20000 7118 + #define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT 0x11 7119 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000 7120 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12 7121 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000 7122 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15 7123 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000 7124 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18 7125 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000 7126 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b 7127 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000 7128 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c 7129 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000 7130 + #define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d 7131 + #define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3 7132 + #define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0 7133 + #define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc 7134 + #define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2 7135 + #define PB1_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN_MASK 0x10 7136 + #define PB1_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN__SHIFT 0x4 7137 + #define PB1_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY_MASK 0x20 7138 + #define PB1_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY__SHIFT 0x5 7139 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK 0x1 7140 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT 0x0 7141 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK 0x2 7142 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT 0x1 7143 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK 0x4 7144 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT 0x2 7145 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK 0x8 7146 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT 0x3 7147 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK 0x10 7148 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT 0x4 7149 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK 0x20 7150 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT 0x5 7151 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK 0x40 7152 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT 0x6 7153 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK 0x80 7154 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT 0x7 7155 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK 0x100 7156 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT 0x8 7157 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK 0x200 7158 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT 0x9 7159 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK 0x400 7160 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT 0xa 7161 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK 0x800 7162 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT 0xb 7163 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK 0x1000 7164 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT 0xc 7165 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK 0x2000 7166 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT 0xd 7167 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK 0x4000 7168 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT 0xe 7169 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK 0x8000 7170 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT 0xf 7171 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK 0x10000 7172 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT 0x10 7173 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK 0x20000 7174 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT 0x11 7175 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK 0x40000 7176 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT 0x12 7177 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK 0x80000 7178 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT 0x13 7179 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK 0x100000 7180 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT 0x14 7181 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK 0x200000 7182 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT 0x15 7183 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK 0x400000 7184 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT 0x16 7185 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK 0x800000 7186 + #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT 0x17 7187 + #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1 7188 + #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0 7189 + #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2 7190 + #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1 7191 + #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4 7192 + #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2 7193 + #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8 7194 + #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3 7195 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0 7196 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6 7197 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100 7198 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8 7199 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200 7200 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9 7201 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400 7202 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa 7203 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800 7204 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb 7205 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000 7206 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc 7207 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000 7208 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd 7209 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000 7210 + #define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe 7211 + #define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000 7212 + #define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf 7213 + #define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000 7214 + #define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10 7215 + #define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000 7216 + #define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11 7217 + #define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000 7218 + #define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12 7219 + #define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000 7220 + #define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13 7221 + #define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000 7222 + #define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14 7223 + #define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000 7224 + #define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15 7225 + #define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000 7226 + #define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16 7227 + #define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000 7228 + #define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c 7229 + #define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000 7230 + #define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d 7231 + #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000 7232 + #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e 7233 + #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000 7234 + #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f 7235 + #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1 7236 + #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0 7237 + #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2 7238 + #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1 7239 + #define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff 7240 + #define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0 7241 + #define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00 7242 + #define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa 7243 + #define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000 7244 + #define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc 7245 + #define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000 7246 + #define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd 7247 + #define PB1_RX_LANE0_CTRL_REG0__RX_TERM_EN_0_MASK 0x4000 7248 + #define PB1_RX_LANE0_CTRL_REG0__RX_TERM_EN_0__SHIFT 0xe 7249 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7 7250 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0 7251 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8 7252 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3 7253 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK 0x40 7254 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT 0x6 7255 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80 7256 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7 7257 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100 7258 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8 7259 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200 7260 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9 7261 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK 0x3fc00 7262 + #define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT 0xa 7263 + #define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff 7264 + #define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0 7265 + #define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00 7266 + #define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa 7267 + #define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000 7268 + #define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc 7269 + #define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000 7270 + #define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd 7271 + #define PB1_RX_LANE1_CTRL_REG0__RX_TERM_EN_1_MASK 0x4000 7272 + #define PB1_RX_LANE1_CTRL_REG0__RX_TERM_EN_1__SHIFT 0xe 7273 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7 7274 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0 7275 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8 7276 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3 7277 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK 0x40 7278 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT 0x6 7279 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80 7280 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7 7281 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100 7282 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8 7283 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200 7284 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9 7285 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK 0x3fc00 7286 + #define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT 0xa 7287 + #define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff 7288 + #define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0 7289 + #define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00 7290 + #define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa 7291 + #define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000 7292 + #define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc 7293 + #define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000 7294 + #define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd 7295 + #define PB1_RX_LANE2_CTRL_REG0__RX_TERM_EN_2_MASK 0x4000 7296 + #define PB1_RX_LANE2_CTRL_REG0__RX_TERM_EN_2__SHIFT 0xe 7297 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7 7298 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0 7299 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8 7300 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3 7301 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK 0x40 7302 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT 0x6 7303 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80 7304 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7 7305 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100 7306 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8 7307 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200 7308 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9 7309 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK 0x3fc00 7310 + #define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT 0xa 7311 + #define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff 7312 + #define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0 7313 + #define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00 7314 + #define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa 7315 + #define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000 7316 + #define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc 7317 + #define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000 7318 + #define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd 7319 + #define PB1_RX_LANE3_CTRL_REG0__RX_TERM_EN_3_MASK 0x4000 7320 + #define PB1_RX_LANE3_CTRL_REG0__RX_TERM_EN_3__SHIFT 0xe 7321 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7 7322 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0 7323 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8 7324 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3 7325 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK 0x40 7326 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT 0x6 7327 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80 7328 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7 7329 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100 7330 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8 7331 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200 7332 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9 7333 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK 0x3fc00 7334 + #define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT 0xa 7335 + #define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff 7336 + #define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0 7337 + #define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00 7338 + #define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa 7339 + #define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000 7340 + #define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc 7341 + #define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000 7342 + #define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd 7343 + #define PB1_RX_LANE4_CTRL_REG0__RX_TERM_EN_4_MASK 0x4000 7344 + #define PB1_RX_LANE4_CTRL_REG0__RX_TERM_EN_4__SHIFT 0xe 7345 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7 7346 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0 7347 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8 7348 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3 7349 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK 0x40 7350 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT 0x6 7351 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80 7352 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7 7353 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100 7354 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8 7355 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200 7356 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9 7357 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK 0x3fc00 7358 + #define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT 0xa 7359 + #define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff 7360 + #define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0 7361 + #define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00 7362 + #define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa 7363 + #define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000 7364 + #define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc 7365 + #define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000 7366 + #define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd 7367 + #define PB1_RX_LANE5_CTRL_REG0__RX_TERM_EN_5_MASK 0x4000 7368 + #define PB1_RX_LANE5_CTRL_REG0__RX_TERM_EN_5__SHIFT 0xe 7369 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7 7370 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0 7371 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8 7372 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3 7373 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK 0x40 7374 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT 0x6 7375 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80 7376 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7 7377 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100 7378 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8 7379 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200 7380 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9 7381 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK 0x3fc00 7382 + #define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT 0xa 7383 + #define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff 7384 + #define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0 7385 + #define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00 7386 + #define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa 7387 + #define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000 7388 + #define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc 7389 + #define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000 7390 + #define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd 7391 + #define PB1_RX_LANE6_CTRL_REG0__RX_TERM_EN_6_MASK 0x4000 7392 + #define PB1_RX_LANE6_CTRL_REG0__RX_TERM_EN_6__SHIFT 0xe 7393 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7 7394 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0 7395 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8 7396 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3 7397 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK 0x40 7398 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT 0x6 7399 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80 7400 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7 7401 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100 7402 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8 7403 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200 7404 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9 7405 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK 0x3fc00 7406 + #define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT 0xa 7407 + #define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff 7408 + #define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0 7409 + #define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00 7410 + #define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa 7411 + #define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000 7412 + #define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc 7413 + #define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000 7414 + #define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd 7415 + #define PB1_RX_LANE7_CTRL_REG0__RX_TERM_EN_7_MASK 0x4000 7416 + #define PB1_RX_LANE7_CTRL_REG0__RX_TERM_EN_7__SHIFT 0xe 7417 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7 7418 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0 7419 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8 7420 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3 7421 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK 0x40 7422 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT 0x6 7423 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80 7424 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7 7425 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100 7426 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8 7427 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200 7428 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9 7429 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK 0x3fc00 7430 + #define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT 0xa 7431 + #define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff 7432 + #define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0 7433 + #define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00 7434 + #define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa 7435 + #define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000 7436 + #define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc 7437 + #define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000 7438 + #define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd 7439 + #define PB1_RX_LANE8_CTRL_REG0__RX_TERM_EN_8_MASK 0x4000 7440 + #define PB1_RX_LANE8_CTRL_REG0__RX_TERM_EN_8__SHIFT 0xe 7441 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7 7442 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0 7443 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8 7444 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3 7445 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK 0x40 7446 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT 0x6 7447 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80 7448 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7 7449 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100 7450 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8 7451 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200 7452 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9 7453 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK 0x3fc00 7454 + #define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT 0xa 7455 + #define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff 7456 + #define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0 7457 + #define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00 7458 + #define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa 7459 + #define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000 7460 + #define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc 7461 + #define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000 7462 + #define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd 7463 + #define PB1_RX_LANE9_CTRL_REG0__RX_TERM_EN_9_MASK 0x4000 7464 + #define PB1_RX_LANE9_CTRL_REG0__RX_TERM_EN_9__SHIFT 0xe 7465 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7 7466 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0 7467 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8 7468 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3 7469 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK 0x40 7470 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT 0x6 7471 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80 7472 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7 7473 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100 7474 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8 7475 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200 7476 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9 7477 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK 0x3fc00 7478 + #define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT 0xa 7479 + #define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff 7480 + #define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0 7481 + #define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00 7482 + #define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa 7483 + #define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000 7484 + #define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc 7485 + #define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000 7486 + #define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd 7487 + #define PB1_RX_LANE10_CTRL_REG0__RX_TERM_EN_10_MASK 0x4000 7488 + #define PB1_RX_LANE10_CTRL_REG0__RX_TERM_EN_10__SHIFT 0xe 7489 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7 7490 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0 7491 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8 7492 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3 7493 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK 0x40 7494 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT 0x6 7495 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80 7496 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7 7497 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100 7498 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8 7499 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200 7500 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9 7501 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK 0x3fc00 7502 + #define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT 0xa 7503 + #define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff 7504 + #define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0 7505 + #define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00 7506 + #define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa 7507 + #define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000 7508 + #define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc 7509 + #define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000 7510 + #define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd 7511 + #define PB1_RX_LANE11_CTRL_REG0__RX_TERM_EN_11_MASK 0x4000 7512 + #define PB1_RX_LANE11_CTRL_REG0__RX_TERM_EN_11__SHIFT 0xe 7513 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7 7514 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0 7515 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8 7516 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3 7517 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK 0x40 7518 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT 0x6 7519 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80 7520 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7 7521 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100 7522 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8 7523 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200 7524 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9 7525 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK 0x3fc00 7526 + #define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT 0xa 7527 + #define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff 7528 + #define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0 7529 + #define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00 7530 + #define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa 7531 + #define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000 7532 + #define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc 7533 + #define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000 7534 + #define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd 7535 + #define PB1_RX_LANE12_CTRL_REG0__RX_TERM_EN_12_MASK 0x4000 7536 + #define PB1_RX_LANE12_CTRL_REG0__RX_TERM_EN_12__SHIFT 0xe 7537 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7 7538 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0 7539 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8 7540 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3 7541 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK 0x40 7542 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT 0x6 7543 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80 7544 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7 7545 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100 7546 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8 7547 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200 7548 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9 7549 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK 0x3fc00 7550 + #define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT 0xa 7551 + #define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff 7552 + #define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0 7553 + #define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00 7554 + #define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa 7555 + #define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000 7556 + #define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc 7557 + #define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000 7558 + #define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd 7559 + #define PB1_RX_LANE13_CTRL_REG0__RX_TERM_EN_13_MASK 0x4000 7560 + #define PB1_RX_LANE13_CTRL_REG0__RX_TERM_EN_13__SHIFT 0xe 7561 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7 7562 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0 7563 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8 7564 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3 7565 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK 0x40 7566 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT 0x6 7567 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80 7568 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7 7569 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100 7570 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8 7571 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200 7572 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9 7573 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK 0x3fc00 7574 + #define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT 0xa 7575 + #define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff 7576 + #define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0 7577 + #define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00 7578 + #define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa 7579 + #define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000 7580 + #define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc 7581 + #define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000 7582 + #define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd 7583 + #define PB1_RX_LANE14_CTRL_REG0__RX_TERM_EN_14_MASK 0x4000 7584 + #define PB1_RX_LANE14_CTRL_REG0__RX_TERM_EN_14__SHIFT 0xe 7585 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7 7586 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0 7587 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8 7588 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3 7589 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK 0x40 7590 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT 0x6 7591 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80 7592 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7 7593 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100 7594 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8 7595 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200 7596 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9 7597 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK 0x3fc00 7598 + #define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT 0xa 7599 + #define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff 7600 + #define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0 7601 + #define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00 7602 + #define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa 7603 + #define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000 7604 + #define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc 7605 + #define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000 7606 + #define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd 7607 + #define PB1_RX_LANE15_CTRL_REG0__RX_TERM_EN_15_MASK 0x4000 7608 + #define PB1_RX_LANE15_CTRL_REG0__RX_TERM_EN_15__SHIFT 0xe 7609 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7 7610 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0 7611 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8 7612 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3 7613 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK 0x40 7614 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT 0x6 7615 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80 7616 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7 7617 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100 7618 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8 7619 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200 7620 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9 7621 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK 0x3fc00 7622 + #define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT 0xa 7623 + #define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7 7624 + #define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0 7625 + #define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38 7626 + #define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3 7627 + #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700 7628 + #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8 7629 + #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800 7630 + #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb 7631 + #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000 7632 + #define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe 7633 + #define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000 7634 + #define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11 7635 + #define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000 7636 + #define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13 7637 + #define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000 7638 + #define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14 7639 + #define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000 7640 + #define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15 7641 + #define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000 7642 + #define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16 7643 + #define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000 7644 + #define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17 7645 + #define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK 0x1000000 7646 + #define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT 0x18 7647 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1 7648 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0 7649 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2 7650 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1 7651 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4 7652 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2 7653 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8 7654 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3 7655 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10 7656 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4 7657 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20 7658 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5 7659 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40 7660 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6 7661 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80 7662 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7 7663 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100 7664 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8 7665 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200 7666 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9 7667 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400 7668 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa 7669 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800 7670 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb 7671 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000 7672 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc 7673 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000 7674 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd 7675 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000 7676 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe 7677 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000 7678 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf 7679 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000 7680 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10 7681 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000 7682 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11 7683 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000 7684 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12 7685 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000 7686 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13 7687 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000 7688 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14 7689 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000 7690 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15 7691 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000 7692 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16 7693 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000 7694 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17 7695 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000 7696 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18 7697 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000 7698 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19 7699 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000 7700 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a 7701 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000 7702 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b 7703 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000 7704 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c 7705 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000 7706 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d 7707 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000 7708 + #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e 7709 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK 0x1 7710 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT 0x0 7711 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK 0x2 7712 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT 0x1 7713 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK 0x4 7714 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT 0x2 7715 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK 0x8 7716 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT 0x3 7717 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK 0x100 7718 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT 0x8 7719 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK 0x200 7720 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT 0x9 7721 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK 0x400 7722 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT 0xa 7723 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK 0x800 7724 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT 0xb 7725 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK 0x1000 7726 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT 0xc 7727 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK 0x2000 7728 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT 0xd 7729 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK 0x4000 7730 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT 0xe 7731 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK 0x8000 7732 + #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT 0xf 7733 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1 7734 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0 7735 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2 7736 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1 7737 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4 7738 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2 7739 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8 7740 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3 7741 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10 7742 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4 7743 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20 7744 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5 7745 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40 7746 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6 7747 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80 7748 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7 7749 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100 7750 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8 7751 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200 7752 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9 7753 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400 7754 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa 7755 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800 7756 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb 7757 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000 7758 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc 7759 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000 7760 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd 7761 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000 7762 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe 7763 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000 7764 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf 7765 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000 7766 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10 7767 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000 7768 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11 7769 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000 7770 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12 7771 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000 7772 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13 7773 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000 7774 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14 7775 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000 7776 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15 7777 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000 7778 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16 7779 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000 7780 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17 7781 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000 7782 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18 7783 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000 7784 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19 7785 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000 7786 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a 7787 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000 7788 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b 7789 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000 7790 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c 7791 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000 7792 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d 7793 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000 7794 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e 7795 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000 7796 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f 7797 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1 7798 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0 7799 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2 7800 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1 7801 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4 7802 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2 7803 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8 7804 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3 7805 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10 7806 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4 7807 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20 7808 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5 7809 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40 7810 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6 7811 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80 7812 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7 7813 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100 7814 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8 7815 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200 7816 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9 7817 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400 7818 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa 7819 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800 7820 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb 7821 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000 7822 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc 7823 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000 7824 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd 7825 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000 7826 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe 7827 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000 7828 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf 7829 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000 7830 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10 7831 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000 7832 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11 7833 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000 7834 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12 7835 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000 7836 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13 7837 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000 7838 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14 7839 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000 7840 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15 7841 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000 7842 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16 7843 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000 7844 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17 7845 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000 7846 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18 7847 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000 7848 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19 7849 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000 7850 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a 7851 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000 7852 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b 7853 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000 7854 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c 7855 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000 7856 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d 7857 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000 7858 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e 7859 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000 7860 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f 7861 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1 7862 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0 7863 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2 7864 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1 7865 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4 7866 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2 7867 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8 7868 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3 7869 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10 7870 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4 7871 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20 7872 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5 7873 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40 7874 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6 7875 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80 7876 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7 7877 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100 7878 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8 7879 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200 7880 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9 7881 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400 7882 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa 7883 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800 7884 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb 7885 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000 7886 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc 7887 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000 7888 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd 7889 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000 7890 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe 7891 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000 7892 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf 7893 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000 7894 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10 7895 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000 7896 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11 7897 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000 7898 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12 7899 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000 7900 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13 7901 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000 7902 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14 7903 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000 7904 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15 7905 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000 7906 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16 7907 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000 7908 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17 7909 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000 7910 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18 7911 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000 7912 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19 7913 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000 7914 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a 7915 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000 7916 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b 7917 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000 7918 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c 7919 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000 7920 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d 7921 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000 7922 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e 7923 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000 7924 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f 7925 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1 7926 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0 7927 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2 7928 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1 7929 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4 7930 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2 7931 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8 7932 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3 7933 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10 7934 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4 7935 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20 7936 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5 7937 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40 7938 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6 7939 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80 7940 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7 7941 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100 7942 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8 7943 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200 7944 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9 7945 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400 7946 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa 7947 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800 7948 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb 7949 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000 7950 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc 7951 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000 7952 + #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd 7953 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7 7954 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0 7955 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8 7956 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3 7957 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0 7958 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4 7959 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100 7960 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8 7961 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00 7962 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9 7963 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000 7964 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd 7965 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000 7966 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe 7967 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000 7968 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13 7969 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000 7970 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14 7971 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000 7972 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19 7973 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000 7974 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a 7975 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000 7976 + #define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e 7977 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf 7978 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0 7979 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10 7980 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4 7981 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20 7982 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5 7983 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40 7984 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6 7985 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80 7986 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7 7987 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100 7988 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8 7989 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200 7990 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9 7991 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400 7992 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa 7993 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800 7994 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb 7995 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000 7996 + #define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc 7997 + #define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000 7998 + #define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd 7999 + #define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000 8000 + #define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe 8001 + #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000 8002 + #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf 8003 + #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000 8004 + #define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19 8005 + #define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000 8006 + #define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a 8007 + #define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000 8008 + #define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b 8009 + #define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000 8010 + #define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c 8011 + #define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000 8012 + #define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d 8013 + #define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000 8014 + #define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e 8015 + #define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000 8016 + #define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f 8017 + #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1 8018 + #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0 8019 + #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2 8020 + #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1 8021 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4 8022 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2 8023 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8 8024 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3 8025 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10 8026 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4 8027 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20 8028 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5 8029 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40 8030 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6 8031 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80 8032 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7 8033 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100 8034 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8 8035 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200 8036 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9 8037 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400 8038 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa 8039 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800 8040 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb 8041 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000 8042 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc 8043 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000 8044 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10 8045 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000 8046 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14 8047 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000 8048 + #define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19 8049 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf 8050 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0 8051 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0 8052 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4 8053 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100 8054 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8 8055 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200 8056 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9 8057 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00 8058 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa 8059 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000 8060 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe 8061 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000 8062 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12 8063 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000 8064 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17 8065 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000 8066 + #define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c 8067 + #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf 8068 + #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0 8069 + #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10 8070 + #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4 8071 + #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20 8072 + #define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5 8073 + #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1 8074 + #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0 8075 + #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2 8076 + #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1 8077 + #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4 8078 + #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2 8079 + #define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8 8080 + #define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3 8081 + #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1 8082 + #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0 8083 + #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2 8084 + #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1 8085 + #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4 8086 + #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2 8087 + #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8 8088 + #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3 8089 + #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10 8090 + #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4 8091 + #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20 8092 + #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5 8093 + #define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40 8094 + #define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6 8095 + #define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80 8096 + #define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7 8097 + #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7 8098 + #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0 8099 + #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70 8100 + #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4 8101 + #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80 8102 + #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7 8103 + #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300 8104 + #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8 8105 + #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00 8106 + #define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa 8107 + #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1 8108 + #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0 8109 + #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2 8110 + #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1 8111 + #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4 8112 + #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2 8113 + #define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8 8114 + #define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3 8115 + #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1 8116 + #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0 8117 + #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2 8118 + #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1 8119 + #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4 8120 + #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2 8121 + #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8 8122 + #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3 8123 + #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10 8124 + #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4 8125 + #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20 8126 + #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5 8127 + #define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40 8128 + #define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6 8129 + #define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80 8130 + #define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7 8131 + #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7 8132 + #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0 8133 + #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70 8134 + #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4 8135 + #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80 8136 + #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7 8137 + #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300 8138 + #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8 8139 + #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00 8140 + #define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa 8141 + #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1 8142 + #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0 8143 + #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2 8144 + #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1 8145 + #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4 8146 + #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2 8147 + #define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8 8148 + #define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3 8149 + #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1 8150 + #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0 8151 + #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2 8152 + #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1 8153 + #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4 8154 + #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2 8155 + #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8 8156 + #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3 8157 + #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10 8158 + #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4 8159 + #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20 8160 + #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5 8161 + #define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40 8162 + #define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6 8163 + #define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80 8164 + #define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7 8165 + #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7 8166 + #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0 8167 + #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70 8168 + #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4 8169 + #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80 8170 + #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7 8171 + #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300 8172 + #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8 8173 + #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00 8174 + #define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa 8175 + #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1 8176 + #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0 8177 + #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2 8178 + #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1 8179 + #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4 8180 + #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2 8181 + #define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8 8182 + #define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3 8183 + #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1 8184 + #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0 8185 + #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2 8186 + #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1 8187 + #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4 8188 + #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2 8189 + #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8 8190 + #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3 8191 + #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10 8192 + #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4 8193 + #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20 8194 + #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5 8195 + #define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40 8196 + #define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6 8197 + #define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80 8198 + #define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7 8199 + #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7 8200 + #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0 8201 + #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70 8202 + #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4 8203 + #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80 8204 + #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7 8205 + #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300 8206 + #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8 8207 + #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00 8208 + #define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa 8209 + #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1 8210 + #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0 8211 + #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2 8212 + #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1 8213 + #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4 8214 + #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2 8215 + #define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8 8216 + #define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3 8217 + #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1 8218 + #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0 8219 + #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2 8220 + #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1 8221 + #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4 8222 + #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2 8223 + #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8 8224 + #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3 8225 + #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10 8226 + #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4 8227 + #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20 8228 + #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5 8229 + #define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40 8230 + #define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6 8231 + #define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80 8232 + #define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7 8233 + #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7 8234 + #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0 8235 + #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70 8236 + #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4 8237 + #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80 8238 + #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7 8239 + #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300 8240 + #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8 8241 + #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00 8242 + #define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa 8243 + #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1 8244 + #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0 8245 + #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2 8246 + #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1 8247 + #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4 8248 + #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2 8249 + #define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8 8250 + #define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3 8251 + #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1 8252 + #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0 8253 + #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2 8254 + #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1 8255 + #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4 8256 + #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2 8257 + #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8 8258 + #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3 8259 + #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10 8260 + #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4 8261 + #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20 8262 + #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5 8263 + #define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40 8264 + #define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6 8265 + #define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80 8266 + #define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7 8267 + #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7 8268 + #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0 8269 + #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70 8270 + #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4 8271 + #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80 8272 + #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7 8273 + #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300 8274 + #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8 8275 + #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00 8276 + #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa 8277 + #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1 8278 + #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0 8279 + #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2 8280 + #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1 8281 + #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4 8282 + #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2 8283 + #define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8 8284 + #define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3 8285 + #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1 8286 + #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0 8287 + #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2 8288 + #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1 8289 + #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4 8290 + #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2 8291 + #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8 8292 + #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3 8293 + #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10 8294 + #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4 8295 + #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20 8296 + #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5 8297 + #define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40 8298 + #define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6 8299 + #define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80 8300 + #define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7 8301 + #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7 8302 + #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0 8303 + #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70 8304 + #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4 8305 + #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80 8306 + #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7 8307 + #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300 8308 + #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8 8309 + #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00 8310 + #define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa 8311 + #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1 8312 + #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0 8313 + #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2 8314 + #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1 8315 + #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4 8316 + #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2 8317 + #define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8 8318 + #define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3 8319 + #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1 8320 + #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0 8321 + #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2 8322 + #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1 8323 + #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4 8324 + #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2 8325 + #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8 8326 + #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3 8327 + #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10 8328 + #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4 8329 + #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20 8330 + #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5 8331 + #define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40 8332 + #define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6 8333 + #define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80 8334 + #define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7 8335 + #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7 8336 + #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0 8337 + #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70 8338 + #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4 8339 + #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80 8340 + #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7 8341 + #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300 8342 + #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8 8343 + #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00 8344 + #define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa 8345 + #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1 8346 + #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0 8347 + #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2 8348 + #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1 8349 + #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4 8350 + #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2 8351 + #define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8 8352 + #define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3 8353 + #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1 8354 + #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0 8355 + #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2 8356 + #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1 8357 + #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4 8358 + #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2 8359 + #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8 8360 + #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3 8361 + #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10 8362 + #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4 8363 + #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20 8364 + #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5 8365 + #define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40 8366 + #define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6 8367 + #define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80 8368 + #define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7 8369 + #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7 8370 + #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0 8371 + #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70 8372 + #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4 8373 + #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80 8374 + #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7 8375 + #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300 8376 + #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8 8377 + #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00 8378 + #define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa 8379 + #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1 8380 + #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0 8381 + #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2 8382 + #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1 8383 + #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4 8384 + #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2 8385 + #define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8 8386 + #define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3 8387 + #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1 8388 + #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0 8389 + #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2 8390 + #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1 8391 + #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4 8392 + #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2 8393 + #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8 8394 + #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3 8395 + #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10 8396 + #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4 8397 + #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20 8398 + #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5 8399 + #define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40 8400 + #define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6 8401 + #define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80 8402 + #define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7 8403 + #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7 8404 + #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0 8405 + #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70 8406 + #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4 8407 + #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80 8408 + #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7 8409 + #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300 8410 + #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8 8411 + #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00 8412 + #define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa 8413 + #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1 8414 + #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0 8415 + #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2 8416 + #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1 8417 + #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4 8418 + #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2 8419 + #define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8 8420 + #define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3 8421 + #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1 8422 + #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0 8423 + #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2 8424 + #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1 8425 + #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4 8426 + #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2 8427 + #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8 8428 + #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3 8429 + #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10 8430 + #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4 8431 + #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20 8432 + #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5 8433 + #define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40 8434 + #define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6 8435 + #define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80 8436 + #define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7 8437 + #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7 8438 + #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0 8439 + #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70 8440 + #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4 8441 + #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80 8442 + #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7 8443 + #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300 8444 + #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8 8445 + #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00 8446 + #define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa 8447 + #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1 8448 + #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0 8449 + #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2 8450 + #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1 8451 + #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4 8452 + #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2 8453 + #define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8 8454 + #define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3 8455 + #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1 8456 + #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0 8457 + #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2 8458 + #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1 8459 + #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4 8460 + #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2 8461 + #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8 8462 + #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3 8463 + #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10 8464 + #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4 8465 + #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20 8466 + #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5 8467 + #define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40 8468 + #define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6 8469 + #define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80 8470 + #define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7 8471 + #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7 8472 + #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0 8473 + #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70 8474 + #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4 8475 + #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80 8476 + #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7 8477 + #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300 8478 + #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8 8479 + #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00 8480 + #define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa 8481 + #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1 8482 + #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0 8483 + #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2 8484 + #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1 8485 + #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4 8486 + #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2 8487 + #define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8 8488 + #define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3 8489 + #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1 8490 + #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0 8491 + #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2 8492 + #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1 8493 + #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4 8494 + #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2 8495 + #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8 8496 + #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3 8497 + #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10 8498 + #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4 8499 + #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20 8500 + #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5 8501 + #define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40 8502 + #define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6 8503 + #define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80 8504 + #define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7 8505 + #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7 8506 + #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0 8507 + #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70 8508 + #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4 8509 + #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80 8510 + #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7 8511 + #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300 8512 + #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8 8513 + #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00 8514 + #define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa 8515 + #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1 8516 + #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0 8517 + #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2 8518 + #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1 8519 + #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4 8520 + #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2 8521 + #define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8 8522 + #define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3 8523 + #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1 8524 + #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0 8525 + #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2 8526 + #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1 8527 + #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4 8528 + #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2 8529 + #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8 8530 + #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3 8531 + #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10 8532 + #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4 8533 + #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20 8534 + #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5 8535 + #define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40 8536 + #define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6 8537 + #define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80 8538 + #define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7 8539 + #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7 8540 + #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0 8541 + #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70 8542 + #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4 8543 + #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80 8544 + #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7 8545 + #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300 8546 + #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8 8547 + #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00 8548 + #define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa 8549 + #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1 8550 + #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0 8551 + #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2 8552 + #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1 8553 + #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4 8554 + #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2 8555 + #define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8 8556 + #define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3 8557 + #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1 8558 + #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0 8559 + #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2 8560 + #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1 8561 + #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4 8562 + #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2 8563 + #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8 8564 + #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3 8565 + #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10 8566 + #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4 8567 + #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20 8568 + #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5 8569 + #define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40 8570 + #define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6 8571 + #define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80 8572 + #define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7 8573 + #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7 8574 + #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0 8575 + #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70 8576 + #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4 8577 + #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80 8578 + #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7 8579 + #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300 8580 + #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8 8581 + #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00 8582 + #define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa 8583 + #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1 8584 + #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0 8585 + #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2 8586 + #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1 8587 + #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4 8588 + #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2 8589 + #define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8 8590 + #define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3 8591 + #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1 8592 + #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0 8593 + #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2 8594 + #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1 8595 + #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4 8596 + #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2 8597 + #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8 8598 + #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3 8599 + #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10 8600 + #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4 8601 + #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20 8602 + #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5 8603 + #define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40 8604 + #define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6 8605 + #define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80 8606 + #define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7 8607 + #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7 8608 + #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0 8609 + #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70 8610 + #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4 8611 + #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80 8612 + #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7 8613 + #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300 8614 + #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8 8615 + #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00 8616 + #define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa 8617 + #define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff 8618 + #define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0 8619 + #define PB0_PIF_HW_DEBUG__HW_00_DEBUG_MASK 0x1 8620 + #define PB0_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 8621 + #define PB0_PIF_HW_DEBUG__HW_01_DEBUG_MASK 0x2 8622 + #define PB0_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 8623 + #define PB0_PIF_HW_DEBUG__HW_02_DEBUG_MASK 0x4 8624 + #define PB0_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 8625 + #define PB0_PIF_HW_DEBUG__HW_03_DEBUG_MASK 0x8 8626 + #define PB0_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 8627 + #define PB0_PIF_HW_DEBUG__HW_04_DEBUG_MASK 0x10 8628 + #define PB0_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 8629 + #define PB0_PIF_HW_DEBUG__HW_05_DEBUG_MASK 0x20 8630 + #define PB0_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 8631 + #define PB0_PIF_HW_DEBUG__HW_06_DEBUG_MASK 0x40 8632 + #define PB0_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 8633 + #define PB0_PIF_HW_DEBUG__HW_07_DEBUG_MASK 0x80 8634 + #define PB0_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 8635 + #define PB0_PIF_HW_DEBUG__HW_08_DEBUG_MASK 0x100 8636 + #define PB0_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 8637 + #define PB0_PIF_HW_DEBUG__HW_09_DEBUG_MASK 0x200 8638 + #define PB0_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 8639 + #define PB0_PIF_HW_DEBUG__HW_10_DEBUG_MASK 0x400 8640 + #define PB0_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa 8641 + #define PB0_PIF_HW_DEBUG__HW_11_DEBUG_MASK 0x800 8642 + #define PB0_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb 8643 + #define PB0_PIF_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 8644 + #define PB0_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc 8645 + #define PB0_PIF_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 8646 + #define PB0_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd 8647 + #define PB0_PIF_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 8648 + #define PB0_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe 8649 + #define PB0_PIF_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 8650 + #define PB0_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf 8651 + #define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2 8652 + #define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1 8653 + #define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4 8654 + #define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2 8655 + #define PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8 8656 + #define PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3 8657 + #define PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10 8658 + #define PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4 8659 + #define PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20 8660 + #define PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5 8661 + #define PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0 8662 + #define PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6 8663 + #define PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300 8664 + #define PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8 8665 + #define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400 8666 + #define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa 8667 + #define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800 8668 + #define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb 8669 + #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000 8670 + #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc 8671 + #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000 8672 + #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd 8673 + #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000 8674 + #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe 8675 + #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000 8676 + #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf 8677 + #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000 8678 + #define PB0_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10 8679 + #define PB0_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1 8680 + #define PB0_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0 8681 + #define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2 8682 + #define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1 8683 + #define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4 8684 + #define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2 8685 + #define PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8 8686 + #define PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3 8687 + #define PB0_PIF_CTRL__PHY_RST_PWROK_VDD_MASK 0x10 8688 + #define PB0_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4 8689 + #define PB0_PIF_CTRL__PIF_PLL_STATUS_MASK 0xc0 8690 + #define PB0_PIF_CTRL__PIF_PLL_STATUS__SHIFT 0x6 8691 + #define PB0_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100 8692 + #define PB0_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8 8693 + #define PB0_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200 8694 + #define PB0_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9 8695 + #define PB0_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400 8696 + #define PB0_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa 8697 + #define PB0_PIF_CTRL__PIF_PG_EXIT_MODE_MASK 0x800 8698 + #define PB0_PIF_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb 8699 + #define PB0_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000 8700 + #define PB0_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc 8701 + #define PB0_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000 8702 + #define PB0_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd 8703 + #define PB0_PIF_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000 8704 + #define PB0_PIF_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe 8705 + #define PB0_PIF_TX_CTRL__TXPWR_IN_S2_MASK 0x7 8706 + #define PB0_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0 8707 + #define PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38 8708 + #define PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3 8709 + #define PB0_PIF_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0 8710 + #define PB0_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6 8711 + #define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00 8712 + #define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9 8713 + #define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000 8714 + #define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc 8715 + #define PB0_PIF_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000 8716 + #define PB0_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf 8717 + #define PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000 8718 + #define PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12 8719 + #define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000 8720 + #define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15 8721 + #define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000 8722 + #define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16 8723 + #define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000 8724 + #define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17 8725 + #define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000 8726 + #define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18 8727 + #define PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7 8728 + #define PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0 8729 + #define PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38 8730 + #define PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3 8731 + #define PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0 8732 + #define PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6 8733 + #define PB0_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200 8734 + #define PB0_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 8735 + #define PB0_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 8736 + #define PB0_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa 8737 + #define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000 8738 + #define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10 8739 + #define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000 8740 + #define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11 8741 + #define PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000 8742 + #define PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15 8743 + #define PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000 8744 + #define PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16 8745 + #define PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000 8746 + #define PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19 8747 + #define PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000 8748 + #define PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a 8749 + #define PB0_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000 8750 + #define PB0_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d 8751 + #define PB0_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000 8752 + #define PB0_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e 8753 + #define PB0_PIF_RX_CTRL__RXPWR_IN_S2_MASK 0x7 8754 + #define PB0_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0 8755 + #define PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38 8756 + #define PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3 8757 + #define PB0_PIF_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0 8758 + #define PB0_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6 8759 + #define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00 8760 + #define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9 8761 + #define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000 8762 + #define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc 8763 + #define PB0_PIF_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000 8764 + #define PB0_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf 8765 + #define PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000 8766 + #define PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12 8767 + #define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000 8768 + #define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15 8769 + #define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000 8770 + #define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16 8771 + #define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000 8772 + #define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17 8773 + #define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000 8774 + #define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18 8775 + #define PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000 8776 + #define PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19 8777 + #define PB0_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000 8778 + #define PB0_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a 8779 + #define PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7 8780 + #define PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0 8781 + #define PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38 8782 + #define PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3 8783 + #define PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0 8784 + #define PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6 8785 + #define PB0_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200 8786 + #define PB0_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 8787 + #define PB0_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 8788 + #define PB0_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa 8789 + #define PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000 8790 + #define PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10 8791 + #define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000 8792 + #define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11 8793 + #define PB0_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000 8794 + #define PB0_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13 8795 + #define PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000 8796 + #define PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15 8797 + #define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000 8798 + #define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18 8799 + #define PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000 8800 + #define PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19 8801 + #define PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000 8802 + #define PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b 8803 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1 8804 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0 8805 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2 8806 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1 8807 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4 8808 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2 8809 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8 8810 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3 8811 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10 8812 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4 8813 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20 8814 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5 8815 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40 8816 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6 8817 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80 8818 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7 8819 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000 8820 + #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10 8821 + #define PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1 8822 + #define PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0 8823 + #define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2 8824 + #define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1 8825 + #define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4 8826 + #define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2 8827 + #define PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8 8828 + #define PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3 8829 + #define PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10 8830 + #define PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4 8831 + #define PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20 8832 + #define PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5 8833 + #define PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40 8834 + #define PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6 8835 + #define PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80 8836 + #define PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7 8837 + #define PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100 8838 + #define PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8 8839 + #define PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200 8840 + #define PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9 8841 + #define PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400 8842 + #define PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa 8843 + #define PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800 8844 + #define PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb 8845 + #define PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000 8846 + #define PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10 8847 + #define PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000 8848 + #define PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11 8849 + #define PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000 8850 + #define PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14 8851 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1 8852 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0 8853 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2 8854 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1 8855 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4 8856 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2 8857 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8 8858 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3 8859 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10 8860 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4 8861 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20 8862 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5 8863 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40 8864 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6 8865 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80 8866 + #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7 8867 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100 8868 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8 8869 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200 8870 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9 8871 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400 8872 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa 8873 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800 8874 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb 8875 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000 8876 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc 8877 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000 8878 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd 8879 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000 8880 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe 8881 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000 8882 + #define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf 8883 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000 8884 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10 8885 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000 8886 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11 8887 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000 8888 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12 8889 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000 8890 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13 8891 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000 8892 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14 8893 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000 8894 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15 8895 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000 8896 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16 8897 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000 8898 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17 8899 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000 8900 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18 8901 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000 8902 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19 8903 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000 8904 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a 8905 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000 8906 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b 8907 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000 8908 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c 8909 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000 8910 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d 8911 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000 8912 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e 8913 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000 8914 + #define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f 8915 + #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3 8916 + #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0 8917 + #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc 8918 + #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2 8919 + #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10 8920 + #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4 8921 + #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60 8922 + #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5 8923 + #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80 8924 + #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7 8925 + #define PB0_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100 8926 + #define PB0_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8 8927 + #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200 8928 + #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9 8929 + #define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1 8930 + #define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0 8931 + #define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2 8932 + #define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1 8933 + #define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4 8934 + #define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2 8935 + #define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38 8936 + #define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3 8937 + #define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40 8938 + #define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6 8939 + #define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180 8940 + #define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7 8941 + #define PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200 8942 + #define PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9 8943 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000 8944 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10 8945 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000 8946 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11 8947 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000 8948 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12 8949 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000 8950 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13 8951 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000 8952 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14 8953 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000 8954 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15 8955 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000 8956 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16 8957 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000 8958 + #define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17 8959 + #define PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1 8960 + #define PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0 8961 + #define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2 8962 + #define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1 8963 + #define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4 8964 + #define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2 8965 + #define PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8 8966 + #define PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3 8967 + #define PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10 8968 + #define PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4 8969 + #define PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20 8970 + #define PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5 8971 + #define PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40 8972 + #define PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6 8973 + #define PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80 8974 + #define PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7 8975 + #define PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100 8976 + #define PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8 8977 + #define PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200 8978 + #define PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9 8979 + #define PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400 8980 + #define PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa 8981 + #define PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800 8982 + #define PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb 8983 + #define PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000 8984 + #define PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc 8985 + #define PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000 8986 + #define PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd 8987 + #define PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000 8988 + #define PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe 8989 + #define PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000 8990 + #define PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf 8991 + #define PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000 8992 + #define PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10 8993 + #define PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000 8994 + #define PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11 8995 + #define PB0_PIF_LANE0_OVRD2__GANGMODE_0_MASK 0x7 8996 + #define PB0_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0 8997 + #define PB0_PIF_LANE0_OVRD2__FREQDIV_0_MASK 0x18 8998 + #define PB0_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3 8999 + #define PB0_PIF_LANE0_OVRD2__LINKSPEED_0_MASK 0x60 9000 + #define PB0_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5 9001 + #define PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80 9002 + #define PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7 9003 + #define PB0_PIF_LANE0_OVRD2__TXPWR_0_MASK 0x700 9004 + #define PB0_PIF_LANE0_OVRD2__TXPWR_0__SHIFT 0x8 9005 + #define PB0_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800 9006 + #define PB0_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb 9007 + #define PB0_PIF_LANE0_OVRD2__RXPWR_0_MASK 0xe000 9008 + #define PB0_PIF_LANE0_OVRD2__RXPWR_0__SHIFT 0xd 9009 + #define PB0_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000 9010 + #define PB0_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10 9011 + #define PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000 9012 + #define PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12 9013 + #define PB0_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000 9014 + #define PB0_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13 9015 + #define PB0_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000 9016 + #define PB0_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14 9017 + #define PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000 9018 + #define PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15 9019 + #define PB0_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000 9020 + #define PB0_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16 9021 + #define PB0_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000 9022 + #define PB0_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17 9023 + #define PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000 9024 + #define PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18 9025 + #define PB0_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000 9026 + #define PB0_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a 9027 + #define PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1 9028 + #define PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0 9029 + #define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2 9030 + #define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1 9031 + #define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4 9032 + #define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2 9033 + #define PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8 9034 + #define PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3 9035 + #define PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10 9036 + #define PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4 9037 + #define PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20 9038 + #define PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5 9039 + #define PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40 9040 + #define PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6 9041 + #define PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80 9042 + #define PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7 9043 + #define PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100 9044 + #define PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8 9045 + #define PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200 9046 + #define PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9 9047 + #define PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400 9048 + #define PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa 9049 + #define PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800 9050 + #define PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb 9051 + #define PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000 9052 + #define PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc 9053 + #define PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000 9054 + #define PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd 9055 + #define PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000 9056 + #define PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe 9057 + #define PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000 9058 + #define PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf 9059 + #define PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000 9060 + #define PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10 9061 + #define PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000 9062 + #define PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11 9063 + #define PB0_PIF_LANE1_OVRD2__GANGMODE_1_MASK 0x7 9064 + #define PB0_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0 9065 + #define PB0_PIF_LANE1_OVRD2__FREQDIV_1_MASK 0x18 9066 + #define PB0_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3 9067 + #define PB0_PIF_LANE1_OVRD2__LINKSPEED_1_MASK 0x60 9068 + #define PB0_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5 9069 + #define PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80 9070 + #define PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7 9071 + #define PB0_PIF_LANE1_OVRD2__TXPWR_1_MASK 0x700 9072 + #define PB0_PIF_LANE1_OVRD2__TXPWR_1__SHIFT 0x8 9073 + #define PB0_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800 9074 + #define PB0_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb 9075 + #define PB0_PIF_LANE1_OVRD2__RXPWR_1_MASK 0xe000 9076 + #define PB0_PIF_LANE1_OVRD2__RXPWR_1__SHIFT 0xd 9077 + #define PB0_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000 9078 + #define PB0_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10 9079 + #define PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000 9080 + #define PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12 9081 + #define PB0_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000 9082 + #define PB0_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13 9083 + #define PB0_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000 9084 + #define PB0_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14 9085 + #define PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000 9086 + #define PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15 9087 + #define PB0_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000 9088 + #define PB0_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16 9089 + #define PB0_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000 9090 + #define PB0_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17 9091 + #define PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000 9092 + #define PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18 9093 + #define PB0_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000 9094 + #define PB0_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a 9095 + #define PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1 9096 + #define PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0 9097 + #define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2 9098 + #define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1 9099 + #define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4 9100 + #define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2 9101 + #define PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8 9102 + #define PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3 9103 + #define PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10 9104 + #define PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4 9105 + #define PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20 9106 + #define PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5 9107 + #define PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40 9108 + #define PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6 9109 + #define PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80 9110 + #define PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7 9111 + #define PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100 9112 + #define PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8 9113 + #define PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200 9114 + #define PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9 9115 + #define PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400 9116 + #define PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa 9117 + #define PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800 9118 + #define PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb 9119 + #define PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000 9120 + #define PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc 9121 + #define PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000 9122 + #define PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd 9123 + #define PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000 9124 + #define PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe 9125 + #define PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000 9126 + #define PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf 9127 + #define PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000 9128 + #define PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10 9129 + #define PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000 9130 + #define PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11 9131 + #define PB0_PIF_LANE2_OVRD2__GANGMODE_2_MASK 0x7 9132 + #define PB0_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0 9133 + #define PB0_PIF_LANE2_OVRD2__FREQDIV_2_MASK 0x18 9134 + #define PB0_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3 9135 + #define PB0_PIF_LANE2_OVRD2__LINKSPEED_2_MASK 0x60 9136 + #define PB0_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5 9137 + #define PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80 9138 + #define PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7 9139 + #define PB0_PIF_LANE2_OVRD2__TXPWR_2_MASK 0x700 9140 + #define PB0_PIF_LANE2_OVRD2__TXPWR_2__SHIFT 0x8 9141 + #define PB0_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800 9142 + #define PB0_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb 9143 + #define PB0_PIF_LANE2_OVRD2__RXPWR_2_MASK 0xe000 9144 + #define PB0_PIF_LANE2_OVRD2__RXPWR_2__SHIFT 0xd 9145 + #define PB0_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000 9146 + #define PB0_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10 9147 + #define PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000 9148 + #define PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12 9149 + #define PB0_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000 9150 + #define PB0_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13 9151 + #define PB0_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000 9152 + #define PB0_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14 9153 + #define PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000 9154 + #define PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15 9155 + #define PB0_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000 9156 + #define PB0_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16 9157 + #define PB0_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000 9158 + #define PB0_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17 9159 + #define PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000 9160 + #define PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18 9161 + #define PB0_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000 9162 + #define PB0_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a 9163 + #define PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1 9164 + #define PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0 9165 + #define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2 9166 + #define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1 9167 + #define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4 9168 + #define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2 9169 + #define PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8 9170 + #define PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3 9171 + #define PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10 9172 + #define PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4 9173 + #define PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20 9174 + #define PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5 9175 + #define PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40 9176 + #define PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6 9177 + #define PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80 9178 + #define PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7 9179 + #define PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100 9180 + #define PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8 9181 + #define PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200 9182 + #define PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9 9183 + #define PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400 9184 + #define PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa 9185 + #define PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800 9186 + #define PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb 9187 + #define PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000 9188 + #define PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc 9189 + #define PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000 9190 + #define PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd 9191 + #define PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000 9192 + #define PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe 9193 + #define PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000 9194 + #define PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf 9195 + #define PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000 9196 + #define PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10 9197 + #define PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000 9198 + #define PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11 9199 + #define PB0_PIF_LANE3_OVRD2__GANGMODE_3_MASK 0x7 9200 + #define PB0_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0 9201 + #define PB0_PIF_LANE3_OVRD2__FREQDIV_3_MASK 0x18 9202 + #define PB0_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3 9203 + #define PB0_PIF_LANE3_OVRD2__LINKSPEED_3_MASK 0x60 9204 + #define PB0_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5 9205 + #define PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80 9206 + #define PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7 9207 + #define PB0_PIF_LANE3_OVRD2__TXPWR_3_MASK 0x700 9208 + #define PB0_PIF_LANE3_OVRD2__TXPWR_3__SHIFT 0x8 9209 + #define PB0_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800 9210 + #define PB0_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb 9211 + #define PB0_PIF_LANE3_OVRD2__RXPWR_3_MASK 0xe000 9212 + #define PB0_PIF_LANE3_OVRD2__RXPWR_3__SHIFT 0xd 9213 + #define PB0_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000 9214 + #define PB0_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10 9215 + #define PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000 9216 + #define PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12 9217 + #define PB0_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000 9218 + #define PB0_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13 9219 + #define PB0_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000 9220 + #define PB0_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14 9221 + #define PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000 9222 + #define PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15 9223 + #define PB0_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000 9224 + #define PB0_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16 9225 + #define PB0_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000 9226 + #define PB0_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17 9227 + #define PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000 9228 + #define PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18 9229 + #define PB0_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000 9230 + #define PB0_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a 9231 + #define PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1 9232 + #define PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0 9233 + #define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2 9234 + #define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1 9235 + #define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4 9236 + #define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2 9237 + #define PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8 9238 + #define PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3 9239 + #define PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10 9240 + #define PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4 9241 + #define PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20 9242 + #define PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5 9243 + #define PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40 9244 + #define PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6 9245 + #define PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80 9246 + #define PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7 9247 + #define PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100 9248 + #define PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8 9249 + #define PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200 9250 + #define PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9 9251 + #define PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400 9252 + #define PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa 9253 + #define PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800 9254 + #define PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb 9255 + #define PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000 9256 + #define PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc 9257 + #define PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000 9258 + #define PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd 9259 + #define PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000 9260 + #define PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe 9261 + #define PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000 9262 + #define PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf 9263 + #define PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000 9264 + #define PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10 9265 + #define PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000 9266 + #define PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11 9267 + #define PB0_PIF_LANE4_OVRD2__GANGMODE_4_MASK 0x7 9268 + #define PB0_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0 9269 + #define PB0_PIF_LANE4_OVRD2__FREQDIV_4_MASK 0x18 9270 + #define PB0_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3 9271 + #define PB0_PIF_LANE4_OVRD2__LINKSPEED_4_MASK 0x60 9272 + #define PB0_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5 9273 + #define PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80 9274 + #define PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7 9275 + #define PB0_PIF_LANE4_OVRD2__TXPWR_4_MASK 0x700 9276 + #define PB0_PIF_LANE4_OVRD2__TXPWR_4__SHIFT 0x8 9277 + #define PB0_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800 9278 + #define PB0_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb 9279 + #define PB0_PIF_LANE4_OVRD2__RXPWR_4_MASK 0xe000 9280 + #define PB0_PIF_LANE4_OVRD2__RXPWR_4__SHIFT 0xd 9281 + #define PB0_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000 9282 + #define PB0_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10 9283 + #define PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000 9284 + #define PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12 9285 + #define PB0_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000 9286 + #define PB0_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13 9287 + #define PB0_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000 9288 + #define PB0_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14 9289 + #define PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000 9290 + #define PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15 9291 + #define PB0_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000 9292 + #define PB0_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16 9293 + #define PB0_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000 9294 + #define PB0_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17 9295 + #define PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000 9296 + #define PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18 9297 + #define PB0_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000 9298 + #define PB0_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a 9299 + #define PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1 9300 + #define PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0 9301 + #define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2 9302 + #define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1 9303 + #define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4 9304 + #define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2 9305 + #define PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8 9306 + #define PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3 9307 + #define PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10 9308 + #define PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4 9309 + #define PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20 9310 + #define PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5 9311 + #define PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40 9312 + #define PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6 9313 + #define PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80 9314 + #define PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7 9315 + #define PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100 9316 + #define PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8 9317 + #define PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200 9318 + #define PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9 9319 + #define PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400 9320 + #define PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa 9321 + #define PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800 9322 + #define PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb 9323 + #define PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000 9324 + #define PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc 9325 + #define PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000 9326 + #define PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd 9327 + #define PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000 9328 + #define PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe 9329 + #define PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000 9330 + #define PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf 9331 + #define PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000 9332 + #define PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10 9333 + #define PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000 9334 + #define PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11 9335 + #define PB0_PIF_LANE5_OVRD2__GANGMODE_5_MASK 0x7 9336 + #define PB0_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0 9337 + #define PB0_PIF_LANE5_OVRD2__FREQDIV_5_MASK 0x18 9338 + #define PB0_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3 9339 + #define PB0_PIF_LANE5_OVRD2__LINKSPEED_5_MASK 0x60 9340 + #define PB0_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5 9341 + #define PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80 9342 + #define PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7 9343 + #define PB0_PIF_LANE5_OVRD2__TXPWR_5_MASK 0x700 9344 + #define PB0_PIF_LANE5_OVRD2__TXPWR_5__SHIFT 0x8 9345 + #define PB0_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800 9346 + #define PB0_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb 9347 + #define PB0_PIF_LANE5_OVRD2__RXPWR_5_MASK 0xe000 9348 + #define PB0_PIF_LANE5_OVRD2__RXPWR_5__SHIFT 0xd 9349 + #define PB0_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000 9350 + #define PB0_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10 9351 + #define PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000 9352 + #define PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12 9353 + #define PB0_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000 9354 + #define PB0_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13 9355 + #define PB0_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000 9356 + #define PB0_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14 9357 + #define PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000 9358 + #define PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15 9359 + #define PB0_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000 9360 + #define PB0_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16 9361 + #define PB0_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000 9362 + #define PB0_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17 9363 + #define PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000 9364 + #define PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18 9365 + #define PB0_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000 9366 + #define PB0_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a 9367 + #define PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1 9368 + #define PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0 9369 + #define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2 9370 + #define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1 9371 + #define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4 9372 + #define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2 9373 + #define PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8 9374 + #define PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3 9375 + #define PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10 9376 + #define PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4 9377 + #define PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20 9378 + #define PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5 9379 + #define PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40 9380 + #define PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6 9381 + #define PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80 9382 + #define PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7 9383 + #define PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100 9384 + #define PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8 9385 + #define PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200 9386 + #define PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9 9387 + #define PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400 9388 + #define PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa 9389 + #define PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800 9390 + #define PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb 9391 + #define PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000 9392 + #define PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc 9393 + #define PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000 9394 + #define PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd 9395 + #define PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000 9396 + #define PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe 9397 + #define PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000 9398 + #define PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf 9399 + #define PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000 9400 + #define PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10 9401 + #define PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000 9402 + #define PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11 9403 + #define PB0_PIF_LANE6_OVRD2__GANGMODE_6_MASK 0x7 9404 + #define PB0_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0 9405 + #define PB0_PIF_LANE6_OVRD2__FREQDIV_6_MASK 0x18 9406 + #define PB0_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3 9407 + #define PB0_PIF_LANE6_OVRD2__LINKSPEED_6_MASK 0x60 9408 + #define PB0_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5 9409 + #define PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80 9410 + #define PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7 9411 + #define PB0_PIF_LANE6_OVRD2__TXPWR_6_MASK 0x700 9412 + #define PB0_PIF_LANE6_OVRD2__TXPWR_6__SHIFT 0x8 9413 + #define PB0_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800 9414 + #define PB0_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb 9415 + #define PB0_PIF_LANE6_OVRD2__RXPWR_6_MASK 0xe000 9416 + #define PB0_PIF_LANE6_OVRD2__RXPWR_6__SHIFT 0xd 9417 + #define PB0_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000 9418 + #define PB0_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10 9419 + #define PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000 9420 + #define PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12 9421 + #define PB0_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000 9422 + #define PB0_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13 9423 + #define PB0_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000 9424 + #define PB0_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14 9425 + #define PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000 9426 + #define PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15 9427 + #define PB0_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000 9428 + #define PB0_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16 9429 + #define PB0_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000 9430 + #define PB0_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17 9431 + #define PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000 9432 + #define PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18 9433 + #define PB0_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000 9434 + #define PB0_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a 9435 + #define PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1 9436 + #define PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0 9437 + #define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2 9438 + #define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1 9439 + #define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4 9440 + #define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2 9441 + #define PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8 9442 + #define PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3 9443 + #define PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10 9444 + #define PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4 9445 + #define PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20 9446 + #define PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5 9447 + #define PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40 9448 + #define PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6 9449 + #define PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80 9450 + #define PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7 9451 + #define PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100 9452 + #define PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8 9453 + #define PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200 9454 + #define PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9 9455 + #define PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400 9456 + #define PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa 9457 + #define PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800 9458 + #define PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb 9459 + #define PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000 9460 + #define PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc 9461 + #define PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000 9462 + #define PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd 9463 + #define PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000 9464 + #define PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe 9465 + #define PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000 9466 + #define PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf 9467 + #define PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000 9468 + #define PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10 9469 + #define PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000 9470 + #define PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11 9471 + #define PB0_PIF_LANE7_OVRD2__GANGMODE_7_MASK 0x7 9472 + #define PB0_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0 9473 + #define PB0_PIF_LANE7_OVRD2__FREQDIV_7_MASK 0x18 9474 + #define PB0_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3 9475 + #define PB0_PIF_LANE7_OVRD2__LINKSPEED_7_MASK 0x60 9476 + #define PB0_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5 9477 + #define PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80 9478 + #define PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7 9479 + #define PB0_PIF_LANE7_OVRD2__TXPWR_7_MASK 0x700 9480 + #define PB0_PIF_LANE7_OVRD2__TXPWR_7__SHIFT 0x8 9481 + #define PB0_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800 9482 + #define PB0_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb 9483 + #define PB0_PIF_LANE7_OVRD2__RXPWR_7_MASK 0xe000 9484 + #define PB0_PIF_LANE7_OVRD2__RXPWR_7__SHIFT 0xd 9485 + #define PB0_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000 9486 + #define PB0_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10 9487 + #define PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000 9488 + #define PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12 9489 + #define PB0_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000 9490 + #define PB0_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13 9491 + #define PB0_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000 9492 + #define PB0_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14 9493 + #define PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000 9494 + #define PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15 9495 + #define PB0_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000 9496 + #define PB0_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16 9497 + #define PB0_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000 9498 + #define PB0_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17 9499 + #define PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000 9500 + #define PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18 9501 + #define PB0_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000 9502 + #define PB0_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a 9503 + #define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff 9504 + #define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0 9505 + #define PB1_PIF_HW_DEBUG__HW_00_DEBUG_MASK 0x1 9506 + #define PB1_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 9507 + #define PB1_PIF_HW_DEBUG__HW_01_DEBUG_MASK 0x2 9508 + #define PB1_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 9509 + #define PB1_PIF_HW_DEBUG__HW_02_DEBUG_MASK 0x4 9510 + #define PB1_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 9511 + #define PB1_PIF_HW_DEBUG__HW_03_DEBUG_MASK 0x8 9512 + #define PB1_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 9513 + #define PB1_PIF_HW_DEBUG__HW_04_DEBUG_MASK 0x10 9514 + #define PB1_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 9515 + #define PB1_PIF_HW_DEBUG__HW_05_DEBUG_MASK 0x20 9516 + #define PB1_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 9517 + #define PB1_PIF_HW_DEBUG__HW_06_DEBUG_MASK 0x40 9518 + #define PB1_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 9519 + #define PB1_PIF_HW_DEBUG__HW_07_DEBUG_MASK 0x80 9520 + #define PB1_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 9521 + #define PB1_PIF_HW_DEBUG__HW_08_DEBUG_MASK 0x100 9522 + #define PB1_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 9523 + #define PB1_PIF_HW_DEBUG__HW_09_DEBUG_MASK 0x200 9524 + #define PB1_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 9525 + #define PB1_PIF_HW_DEBUG__HW_10_DEBUG_MASK 0x400 9526 + #define PB1_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa 9527 + #define PB1_PIF_HW_DEBUG__HW_11_DEBUG_MASK 0x800 9528 + #define PB1_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb 9529 + #define PB1_PIF_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 9530 + #define PB1_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc 9531 + #define PB1_PIF_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 9532 + #define PB1_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd 9533 + #define PB1_PIF_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 9534 + #define PB1_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe 9535 + #define PB1_PIF_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 9536 + #define PB1_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf 9537 + #define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2 9538 + #define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1 9539 + #define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4 9540 + #define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2 9541 + #define PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8 9542 + #define PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3 9543 + #define PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10 9544 + #define PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4 9545 + #define PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20 9546 + #define PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5 9547 + #define PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0 9548 + #define PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6 9549 + #define PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300 9550 + #define PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8 9551 + #define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400 9552 + #define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa 9553 + #define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800 9554 + #define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb 9555 + #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000 9556 + #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc 9557 + #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000 9558 + #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd 9559 + #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000 9560 + #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe 9561 + #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000 9562 + #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf 9563 + #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000 9564 + #define PB1_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10 9565 + #define PB1_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1 9566 + #define PB1_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0 9567 + #define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2 9568 + #define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1 9569 + #define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4 9570 + #define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2 9571 + #define PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8 9572 + #define PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3 9573 + #define PB1_PIF_CTRL__PHY_RST_PWROK_VDD_MASK 0x10 9574 + #define PB1_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4 9575 + #define PB1_PIF_CTRL__PIF_PLL_STATUS_MASK 0xc0 9576 + #define PB1_PIF_CTRL__PIF_PLL_STATUS__SHIFT 0x6 9577 + #define PB1_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100 9578 + #define PB1_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8 9579 + #define PB1_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200 9580 + #define PB1_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9 9581 + #define PB1_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400 9582 + #define PB1_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa 9583 + #define PB1_PIF_CTRL__PIF_PG_EXIT_MODE_MASK 0x800 9584 + #define PB1_PIF_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb 9585 + #define PB1_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000 9586 + #define PB1_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc 9587 + #define PB1_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000 9588 + #define PB1_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd 9589 + #define PB1_PIF_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000 9590 + #define PB1_PIF_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe 9591 + #define PB1_PIF_TX_CTRL__TXPWR_IN_S2_MASK 0x7 9592 + #define PB1_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0 9593 + #define PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38 9594 + #define PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3 9595 + #define PB1_PIF_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0 9596 + #define PB1_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6 9597 + #define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00 9598 + #define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9 9599 + #define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000 9600 + #define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc 9601 + #define PB1_PIF_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000 9602 + #define PB1_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf 9603 + #define PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000 9604 + #define PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12 9605 + #define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000 9606 + #define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15 9607 + #define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000 9608 + #define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16 9609 + #define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000 9610 + #define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17 9611 + #define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000 9612 + #define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18 9613 + #define PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7 9614 + #define PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0 9615 + #define PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38 9616 + #define PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3 9617 + #define PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0 9618 + #define PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6 9619 + #define PB1_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200 9620 + #define PB1_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 9621 + #define PB1_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 9622 + #define PB1_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa 9623 + #define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000 9624 + #define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10 9625 + #define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000 9626 + #define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11 9627 + #define PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000 9628 + #define PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15 9629 + #define PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000 9630 + #define PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16 9631 + #define PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000 9632 + #define PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19 9633 + #define PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000 9634 + #define PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a 9635 + #define PB1_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000 9636 + #define PB1_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d 9637 + #define PB1_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000 9638 + #define PB1_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e 9639 + #define PB1_PIF_RX_CTRL__RXPWR_IN_S2_MASK 0x7 9640 + #define PB1_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0 9641 + #define PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38 9642 + #define PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3 9643 + #define PB1_PIF_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0 9644 + #define PB1_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6 9645 + #define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00 9646 + #define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9 9647 + #define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000 9648 + #define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc 9649 + #define PB1_PIF_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000 9650 + #define PB1_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf 9651 + #define PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000 9652 + #define PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12 9653 + #define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000 9654 + #define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15 9655 + #define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000 9656 + #define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16 9657 + #define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000 9658 + #define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17 9659 + #define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000 9660 + #define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18 9661 + #define PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000 9662 + #define PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19 9663 + #define PB1_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000 9664 + #define PB1_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a 9665 + #define PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7 9666 + #define PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0 9667 + #define PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38 9668 + #define PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3 9669 + #define PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0 9670 + #define PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6 9671 + #define PB1_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200 9672 + #define PB1_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 9673 + #define PB1_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 9674 + #define PB1_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa 9675 + #define PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000 9676 + #define PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10 9677 + #define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000 9678 + #define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11 9679 + #define PB1_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000 9680 + #define PB1_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13 9681 + #define PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000 9682 + #define PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15 9683 + #define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000 9684 + #define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18 9685 + #define PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000 9686 + #define PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19 9687 + #define PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000 9688 + #define PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b 9689 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1 9690 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0 9691 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2 9692 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1 9693 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4 9694 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2 9695 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8 9696 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3 9697 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10 9698 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4 9699 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20 9700 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5 9701 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40 9702 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6 9703 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80 9704 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7 9705 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000 9706 + #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10 9707 + #define PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1 9708 + #define PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0 9709 + #define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2 9710 + #define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1 9711 + #define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4 9712 + #define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2 9713 + #define PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8 9714 + #define PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3 9715 + #define PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10 9716 + #define PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4 9717 + #define PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20 9718 + #define PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5 9719 + #define PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40 9720 + #define PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6 9721 + #define PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80 9722 + #define PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7 9723 + #define PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100 9724 + #define PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8 9725 + #define PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200 9726 + #define PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9 9727 + #define PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400 9728 + #define PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa 9729 + #define PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800 9730 + #define PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb 9731 + #define PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000 9732 + #define PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10 9733 + #define PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000 9734 + #define PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11 9735 + #define PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000 9736 + #define PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14 9737 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1 9738 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0 9739 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2 9740 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1 9741 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4 9742 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2 9743 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8 9744 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3 9745 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10 9746 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4 9747 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20 9748 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5 9749 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40 9750 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6 9751 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80 9752 + #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7 9753 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100 9754 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8 9755 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200 9756 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9 9757 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400 9758 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa 9759 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800 9760 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb 9761 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000 9762 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc 9763 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000 9764 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd 9765 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000 9766 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe 9767 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000 9768 + #define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf 9769 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000 9770 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10 9771 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000 9772 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11 9773 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000 9774 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12 9775 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000 9776 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13 9777 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000 9778 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14 9779 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000 9780 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15 9781 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000 9782 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16 9783 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000 9784 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17 9785 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000 9786 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18 9787 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000 9788 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19 9789 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000 9790 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a 9791 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000 9792 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b 9793 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000 9794 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c 9795 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000 9796 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d 9797 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000 9798 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e 9799 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000 9800 + #define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f 9801 + #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3 9802 + #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0 9803 + #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc 9804 + #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2 9805 + #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10 9806 + #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4 9807 + #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60 9808 + #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5 9809 + #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80 9810 + #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7 9811 + #define PB1_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100 9812 + #define PB1_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8 9813 + #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200 9814 + #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9 9815 + #define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1 9816 + #define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0 9817 + #define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2 9818 + #define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1 9819 + #define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4 9820 + #define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2 9821 + #define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38 9822 + #define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3 9823 + #define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40 9824 + #define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6 9825 + #define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180 9826 + #define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7 9827 + #define PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200 9828 + #define PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9 9829 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000 9830 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10 9831 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000 9832 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11 9833 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000 9834 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12 9835 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000 9836 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13 9837 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000 9838 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14 9839 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000 9840 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15 9841 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000 9842 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16 9843 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000 9844 + #define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17 9845 + #define PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1 9846 + #define PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0 9847 + #define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2 9848 + #define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1 9849 + #define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4 9850 + #define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2 9851 + #define PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8 9852 + #define PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3 9853 + #define PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10 9854 + #define PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4 9855 + #define PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20 9856 + #define PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5 9857 + #define PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40 9858 + #define PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6 9859 + #define PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80 9860 + #define PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7 9861 + #define PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100 9862 + #define PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8 9863 + #define PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200 9864 + #define PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9 9865 + #define PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400 9866 + #define PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa 9867 + #define PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800 9868 + #define PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb 9869 + #define PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000 9870 + #define PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc 9871 + #define PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000 9872 + #define PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd 9873 + #define PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000 9874 + #define PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe 9875 + #define PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000 9876 + #define PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf 9877 + #define PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000 9878 + #define PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10 9879 + #define PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000 9880 + #define PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11 9881 + #define PB1_PIF_LANE0_OVRD2__GANGMODE_0_MASK 0x7 9882 + #define PB1_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0 9883 + #define PB1_PIF_LANE0_OVRD2__FREQDIV_0_MASK 0x18 9884 + #define PB1_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3 9885 + #define PB1_PIF_LANE0_OVRD2__LINKSPEED_0_MASK 0x60 9886 + #define PB1_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5 9887 + #define PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80 9888 + #define PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7 9889 + #define PB1_PIF_LANE0_OVRD2__TXPWR_0_MASK 0x700 9890 + #define PB1_PIF_LANE0_OVRD2__TXPWR_0__SHIFT 0x8 9891 + #define PB1_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800 9892 + #define PB1_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb 9893 + #define PB1_PIF_LANE0_OVRD2__RXPWR_0_MASK 0xe000 9894 + #define PB1_PIF_LANE0_OVRD2__RXPWR_0__SHIFT 0xd 9895 + #define PB1_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000 9896 + #define PB1_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10 9897 + #define PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000 9898 + #define PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12 9899 + #define PB1_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000 9900 + #define PB1_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13 9901 + #define PB1_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000 9902 + #define PB1_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14 9903 + #define PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000 9904 + #define PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15 9905 + #define PB1_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000 9906 + #define PB1_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16 9907 + #define PB1_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000 9908 + #define PB1_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17 9909 + #define PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000 9910 + #define PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18 9911 + #define PB1_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000 9912 + #define PB1_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a 9913 + #define PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1 9914 + #define PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0 9915 + #define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2 9916 + #define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1 9917 + #define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4 9918 + #define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2 9919 + #define PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8 9920 + #define PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3 9921 + #define PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10 9922 + #define PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4 9923 + #define PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20 9924 + #define PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5 9925 + #define PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40 9926 + #define PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6 9927 + #define PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80 9928 + #define PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7 9929 + #define PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100 9930 + #define PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8 9931 + #define PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200 9932 + #define PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9 9933 + #define PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400 9934 + #define PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa 9935 + #define PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800 9936 + #define PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb 9937 + #define PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000 9938 + #define PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc 9939 + #define PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000 9940 + #define PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd 9941 + #define PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000 9942 + #define PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe 9943 + #define PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000 9944 + #define PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf 9945 + #define PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000 9946 + #define PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10 9947 + #define PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000 9948 + #define PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11 9949 + #define PB1_PIF_LANE1_OVRD2__GANGMODE_1_MASK 0x7 9950 + #define PB1_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0 9951 + #define PB1_PIF_LANE1_OVRD2__FREQDIV_1_MASK 0x18 9952 + #define PB1_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3 9953 + #define PB1_PIF_LANE1_OVRD2__LINKSPEED_1_MASK 0x60 9954 + #define PB1_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5 9955 + #define PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80 9956 + #define PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7 9957 + #define PB1_PIF_LANE1_OVRD2__TXPWR_1_MASK 0x700 9958 + #define PB1_PIF_LANE1_OVRD2__TXPWR_1__SHIFT 0x8 9959 + #define PB1_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800 9960 + #define PB1_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb 9961 + #define PB1_PIF_LANE1_OVRD2__RXPWR_1_MASK 0xe000 9962 + #define PB1_PIF_LANE1_OVRD2__RXPWR_1__SHIFT 0xd 9963 + #define PB1_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000 9964 + #define PB1_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10 9965 + #define PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000 9966 + #define PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12 9967 + #define PB1_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000 9968 + #define PB1_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13 9969 + #define PB1_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000 9970 + #define PB1_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14 9971 + #define PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000 9972 + #define PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15 9973 + #define PB1_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000 9974 + #define PB1_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16 9975 + #define PB1_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000 9976 + #define PB1_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17 9977 + #define PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000 9978 + #define PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18 9979 + #define PB1_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000 9980 + #define PB1_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a 9981 + #define PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1 9982 + #define PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0 9983 + #define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2 9984 + #define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1 9985 + #define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4 9986 + #define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2 9987 + #define PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8 9988 + #define PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3 9989 + #define PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10 9990 + #define PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4 9991 + #define PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20 9992 + #define PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5 9993 + #define PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40 9994 + #define PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6 9995 + #define PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80 9996 + #define PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7 9997 + #define PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100 9998 + #define PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8 9999 + #define PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200 10000 + #define PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9 10001 + #define PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400 10002 + #define PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa 10003 + #define PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800 10004 + #define PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb 10005 + #define PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000 10006 + #define PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc 10007 + #define PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000 10008 + #define PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd 10009 + #define PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000 10010 + #define PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe 10011 + #define PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000 10012 + #define PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf 10013 + #define PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000 10014 + #define PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10 10015 + #define PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000 10016 + #define PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11 10017 + #define PB1_PIF_LANE2_OVRD2__GANGMODE_2_MASK 0x7 10018 + #define PB1_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0 10019 + #define PB1_PIF_LANE2_OVRD2__FREQDIV_2_MASK 0x18 10020 + #define PB1_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3 10021 + #define PB1_PIF_LANE2_OVRD2__LINKSPEED_2_MASK 0x60 10022 + #define PB1_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5 10023 + #define PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80 10024 + #define PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7 10025 + #define PB1_PIF_LANE2_OVRD2__TXPWR_2_MASK 0x700 10026 + #define PB1_PIF_LANE2_OVRD2__TXPWR_2__SHIFT 0x8 10027 + #define PB1_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800 10028 + #define PB1_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb 10029 + #define PB1_PIF_LANE2_OVRD2__RXPWR_2_MASK 0xe000 10030 + #define PB1_PIF_LANE2_OVRD2__RXPWR_2__SHIFT 0xd 10031 + #define PB1_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000 10032 + #define PB1_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10 10033 + #define PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000 10034 + #define PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12 10035 + #define PB1_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000 10036 + #define PB1_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13 10037 + #define PB1_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000 10038 + #define PB1_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14 10039 + #define PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000 10040 + #define PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15 10041 + #define PB1_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000 10042 + #define PB1_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16 10043 + #define PB1_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000 10044 + #define PB1_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17 10045 + #define PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000 10046 + #define PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18 10047 + #define PB1_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000 10048 + #define PB1_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a 10049 + #define PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1 10050 + #define PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0 10051 + #define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2 10052 + #define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1 10053 + #define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4 10054 + #define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2 10055 + #define PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8 10056 + #define PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3 10057 + #define PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10 10058 + #define PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4 10059 + #define PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20 10060 + #define PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5 10061 + #define PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40 10062 + #define PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6 10063 + #define PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80 10064 + #define PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7 10065 + #define PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100 10066 + #define PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8 10067 + #define PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200 10068 + #define PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9 10069 + #define PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400 10070 + #define PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa 10071 + #define PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800 10072 + #define PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb 10073 + #define PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000 10074 + #define PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc 10075 + #define PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000 10076 + #define PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd 10077 + #define PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000 10078 + #define PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe 10079 + #define PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000 10080 + #define PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf 10081 + #define PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000 10082 + #define PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10 10083 + #define PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000 10084 + #define PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11 10085 + #define PB1_PIF_LANE3_OVRD2__GANGMODE_3_MASK 0x7 10086 + #define PB1_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0 10087 + #define PB1_PIF_LANE3_OVRD2__FREQDIV_3_MASK 0x18 10088 + #define PB1_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3 10089 + #define PB1_PIF_LANE3_OVRD2__LINKSPEED_3_MASK 0x60 10090 + #define PB1_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5 10091 + #define PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80 10092 + #define PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7 10093 + #define PB1_PIF_LANE3_OVRD2__TXPWR_3_MASK 0x700 10094 + #define PB1_PIF_LANE3_OVRD2__TXPWR_3__SHIFT 0x8 10095 + #define PB1_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800 10096 + #define PB1_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb 10097 + #define PB1_PIF_LANE3_OVRD2__RXPWR_3_MASK 0xe000 10098 + #define PB1_PIF_LANE3_OVRD2__RXPWR_3__SHIFT 0xd 10099 + #define PB1_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000 10100 + #define PB1_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10 10101 + #define PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000 10102 + #define PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12 10103 + #define PB1_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000 10104 + #define PB1_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13 10105 + #define PB1_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000 10106 + #define PB1_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14 10107 + #define PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000 10108 + #define PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15 10109 + #define PB1_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000 10110 + #define PB1_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16 10111 + #define PB1_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000 10112 + #define PB1_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17 10113 + #define PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000 10114 + #define PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18 10115 + #define PB1_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000 10116 + #define PB1_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a 10117 + #define PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1 10118 + #define PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0 10119 + #define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2 10120 + #define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1 10121 + #define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4 10122 + #define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2 10123 + #define PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8 10124 + #define PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3 10125 + #define PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10 10126 + #define PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4 10127 + #define PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20 10128 + #define PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5 10129 + #define PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40 10130 + #define PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6 10131 + #define PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80 10132 + #define PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7 10133 + #define PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100 10134 + #define PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8 10135 + #define PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200 10136 + #define PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9 10137 + #define PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400 10138 + #define PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa 10139 + #define PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800 10140 + #define PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb 10141 + #define PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000 10142 + #define PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc 10143 + #define PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000 10144 + #define PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd 10145 + #define PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000 10146 + #define PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe 10147 + #define PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000 10148 + #define PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf 10149 + #define PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000 10150 + #define PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10 10151 + #define PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000 10152 + #define PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11 10153 + #define PB1_PIF_LANE4_OVRD2__GANGMODE_4_MASK 0x7 10154 + #define PB1_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0 10155 + #define PB1_PIF_LANE4_OVRD2__FREQDIV_4_MASK 0x18 10156 + #define PB1_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3 10157 + #define PB1_PIF_LANE4_OVRD2__LINKSPEED_4_MASK 0x60 10158 + #define PB1_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5 10159 + #define PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80 10160 + #define PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7 10161 + #define PB1_PIF_LANE4_OVRD2__TXPWR_4_MASK 0x700 10162 + #define PB1_PIF_LANE4_OVRD2__TXPWR_4__SHIFT 0x8 10163 + #define PB1_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800 10164 + #define PB1_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb 10165 + #define PB1_PIF_LANE4_OVRD2__RXPWR_4_MASK 0xe000 10166 + #define PB1_PIF_LANE4_OVRD2__RXPWR_4__SHIFT 0xd 10167 + #define PB1_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000 10168 + #define PB1_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10 10169 + #define PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000 10170 + #define PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12 10171 + #define PB1_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000 10172 + #define PB1_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13 10173 + #define PB1_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000 10174 + #define PB1_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14 10175 + #define PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000 10176 + #define PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15 10177 + #define PB1_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000 10178 + #define PB1_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16 10179 + #define PB1_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000 10180 + #define PB1_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17 10181 + #define PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000 10182 + #define PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18 10183 + #define PB1_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000 10184 + #define PB1_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a 10185 + #define PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1 10186 + #define PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0 10187 + #define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2 10188 + #define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1 10189 + #define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4 10190 + #define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2 10191 + #define PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8 10192 + #define PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3 10193 + #define PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10 10194 + #define PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4 10195 + #define PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20 10196 + #define PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5 10197 + #define PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40 10198 + #define PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6 10199 + #define PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80 10200 + #define PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7 10201 + #define PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100 10202 + #define PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8 10203 + #define PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200 10204 + #define PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9 10205 + #define PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400 10206 + #define PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa 10207 + #define PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800 10208 + #define PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb 10209 + #define PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000 10210 + #define PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc 10211 + #define PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000 10212 + #define PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd 10213 + #define PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000 10214 + #define PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe 10215 + #define PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000 10216 + #define PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf 10217 + #define PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000 10218 + #define PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10 10219 + #define PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000 10220 + #define PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11 10221 + #define PB1_PIF_LANE5_OVRD2__GANGMODE_5_MASK 0x7 10222 + #define PB1_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0 10223 + #define PB1_PIF_LANE5_OVRD2__FREQDIV_5_MASK 0x18 10224 + #define PB1_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3 10225 + #define PB1_PIF_LANE5_OVRD2__LINKSPEED_5_MASK 0x60 10226 + #define PB1_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5 10227 + #define PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80 10228 + #define PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7 10229 + #define PB1_PIF_LANE5_OVRD2__TXPWR_5_MASK 0x700 10230 + #define PB1_PIF_LANE5_OVRD2__TXPWR_5__SHIFT 0x8 10231 + #define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800 10232 + #define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb 10233 + #define PB1_PIF_LANE5_OVRD2__RXPWR_5_MASK 0xe000 10234 + #define PB1_PIF_LANE5_OVRD2__RXPWR_5__SHIFT 0xd 10235 + #define PB1_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000 10236 + #define PB1_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10 10237 + #define PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000 10238 + #define PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12 10239 + #define PB1_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000 10240 + #define PB1_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13 10241 + #define PB1_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000 10242 + #define PB1_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14 10243 + #define PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000 10244 + #define PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15 10245 + #define PB1_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000 10246 + #define PB1_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16 10247 + #define PB1_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000 10248 + #define PB1_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17 10249 + #define PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000 10250 + #define PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18 10251 + #define PB1_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000 10252 + #define PB1_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a 10253 + #define PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1 10254 + #define PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0 10255 + #define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2 10256 + #define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1 10257 + #define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4 10258 + #define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2 10259 + #define PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8 10260 + #define PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3 10261 + #define PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10 10262 + #define PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4 10263 + #define PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20 10264 + #define PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5 10265 + #define PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40 10266 + #define PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6 10267 + #define PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80 10268 + #define PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7 10269 + #define PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100 10270 + #define PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8 10271 + #define PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200 10272 + #define PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9 10273 + #define PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400 10274 + #define PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa 10275 + #define PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800 10276 + #define PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb 10277 + #define PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000 10278 + #define PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc 10279 + #define PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000 10280 + #define PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd 10281 + #define PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000 10282 + #define PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe 10283 + #define PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000 10284 + #define PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf 10285 + #define PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000 10286 + #define PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10 10287 + #define PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000 10288 + #define PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11 10289 + #define PB1_PIF_LANE6_OVRD2__GANGMODE_6_MASK 0x7 10290 + #define PB1_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0 10291 + #define PB1_PIF_LANE6_OVRD2__FREQDIV_6_MASK 0x18 10292 + #define PB1_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3 10293 + #define PB1_PIF_LANE6_OVRD2__LINKSPEED_6_MASK 0x60 10294 + #define PB1_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5 10295 + #define PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80 10296 + #define PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7 10297 + #define PB1_PIF_LANE6_OVRD2__TXPWR_6_MASK 0x700 10298 + #define PB1_PIF_LANE6_OVRD2__TXPWR_6__SHIFT 0x8 10299 + #define PB1_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800 10300 + #define PB1_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb 10301 + #define PB1_PIF_LANE6_OVRD2__RXPWR_6_MASK 0xe000 10302 + #define PB1_PIF_LANE6_OVRD2__RXPWR_6__SHIFT 0xd 10303 + #define PB1_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000 10304 + #define PB1_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10 10305 + #define PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000 10306 + #define PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12 10307 + #define PB1_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000 10308 + #define PB1_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13 10309 + #define PB1_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000 10310 + #define PB1_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14 10311 + #define PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000 10312 + #define PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15 10313 + #define PB1_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000 10314 + #define PB1_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16 10315 + #define PB1_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000 10316 + #define PB1_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17 10317 + #define PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000 10318 + #define PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18 10319 + #define PB1_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000 10320 + #define PB1_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a 10321 + #define PB1_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1 10322 + #define PB1_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0 10323 + #define PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2 10324 + #define PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1 10325 + #define PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4 10326 + #define PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2 10327 + #define PB1_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8 10328 + #define PB1_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3 10329 + #define PB1_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10 10330 + #define PB1_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4 10331 + #define PB1_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20 10332 + #define PB1_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5 10333 + #define PB1_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40 10334 + #define PB1_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6 10335 + #define PB1_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80 10336 + #define PB1_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7 10337 + #define PB1_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100 10338 + #define PB1_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8 10339 + #define PB1_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200 10340 + #define PB1_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9 10341 + #define PB1_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400 10342 + #define PB1_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa 10343 + #define PB1_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800 10344 + #define PB1_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb 10345 + #define PB1_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000 10346 + #define PB1_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc 10347 + #define PB1_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000 10348 + #define PB1_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd 10349 + #define PB1_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000 10350 + #define PB1_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe 10351 + #define PB1_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000 10352 + #define PB1_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf 10353 + #define PB1_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000 10354 + #define PB1_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10 10355 + #define PB1_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000 10356 + #define PB1_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11 10357 + #define PB1_PIF_LANE7_OVRD2__GANGMODE_7_MASK 0x7 10358 + #define PB1_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0 10359 + #define PB1_PIF_LANE7_OVRD2__FREQDIV_7_MASK 0x18 10360 + #define PB1_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3 10361 + #define PB1_PIF_LANE7_OVRD2__LINKSPEED_7_MASK 0x60 10362 + #define PB1_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5 10363 + #define PB1_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80 10364 + #define PB1_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7 10365 + #define PB1_PIF_LANE7_OVRD2__TXPWR_7_MASK 0x700 10366 + #define PB1_PIF_LANE7_OVRD2__TXPWR_7__SHIFT 0x8 10367 + #define PB1_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800 10368 + #define PB1_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb 10369 + #define PB1_PIF_LANE7_OVRD2__RXPWR_7_MASK 0xe000 10370 + #define PB1_PIF_LANE7_OVRD2__RXPWR_7__SHIFT 0xd 10371 + #define PB1_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000 10372 + #define PB1_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10 10373 + #define PB1_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000 10374 + #define PB1_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12 10375 + #define PB1_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000 10376 + #define PB1_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13 10377 + #define PB1_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000 10378 + #define PB1_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14 10379 + #define PB1_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000 10380 + #define PB1_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15 10381 + #define PB1_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000 10382 + #define PB1_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16 10383 + #define PB1_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000 10384 + #define PB1_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17 10385 + #define PB1_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000 10386 + #define PB1_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18 10387 + #define PB1_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000 10388 + #define PB1_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a 10389 + #define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff 10390 + #define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 10391 + #define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff 10392 + #define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 10393 + #define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 10394 + #define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 10395 + #define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 10396 + #define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 10397 + #define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 10398 + #define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 10399 + #define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 10400 + #define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 10401 + #define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 10402 + #define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 10403 + #define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 10404 + #define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 10405 + #define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 10406 + #define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 10407 + #define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 10408 + #define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 10409 + #define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 10410 + #define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 10411 + #define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 10412 + #define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 10413 + #define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 10414 + #define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa 10415 + #define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 10416 + #define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb 10417 + #define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 10418 + #define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc 10419 + #define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 10420 + #define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd 10421 + #define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 10422 + #define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe 10423 + #define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 10424 + #define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf 10425 + #define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 10426 + #define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 10427 + #define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 10428 + #define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 10429 + #define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 10430 + #define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 10431 + #define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 10432 + #define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 10433 + #define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 10434 + #define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 10435 + #define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 10436 + #define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 10437 + #define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 10438 + #define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 10439 + #define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 10440 + #define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 10441 + #define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 10442 + #define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 10443 + #define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 10444 + #define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 10445 + #define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 10446 + #define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa 10447 + #define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 10448 + #define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc 10449 + #define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 10450 + #define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe 10451 + #define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 10452 + #define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf 10453 + #define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 10454 + #define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 10455 + #define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 10456 + #define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 10457 + #define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 10458 + #define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 10459 + #define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 10460 + #define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 10461 + #define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000 10462 + #define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 10463 + #define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000 10464 + #define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 10465 + #define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000 10466 + #define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a 10467 + #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 10468 + #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 10469 + #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 10470 + #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 10471 + #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 10472 + #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 10473 + #define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff 10474 + #define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 10475 + #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 10476 + #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 10477 + #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 10478 + #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e 10479 + #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 10480 + #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f 10481 + #define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff 10482 + #define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 10483 + #define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 10484 + #define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 10485 + #define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 10486 + #define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 10487 + #define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 10488 + #define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf 10489 + #define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 10490 + #define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 10491 + #define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff 10492 + #define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 10493 + #define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 10494 + #define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc 10495 + #define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff 10496 + #define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 10497 + #define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 10498 + #define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 10499 + #define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff 10500 + #define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 10501 + #define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 10502 + #define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 10503 + #define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff 10504 + #define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 10505 + #define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 10506 + #define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 10507 + #define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff 10508 + #define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 10509 + #define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 10510 + #define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 10511 + #define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff 10512 + #define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 10513 + #define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 10514 + #define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 10515 + #define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff 10516 + #define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 10517 + #define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 10518 + #define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 10519 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 10520 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 10521 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 10522 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 10523 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 10524 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 10525 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 10526 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 10527 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 10528 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 10529 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 10530 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 10531 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 10532 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 10533 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 10534 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 10535 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 10536 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 10537 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 10538 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 10539 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 10540 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 10541 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 10542 + #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 10543 + #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 10544 + #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 10545 + #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 10546 + #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 10547 + #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 10548 + #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 10549 + #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 10550 + #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 10551 + #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 10552 + #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 10553 + #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 10554 + #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 10555 + #define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 10556 + #define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 10557 + #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e 10558 + #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 10559 + #define PCIE_FC_P__PD_CREDITS_MASK 0xff 10560 + #define PCIE_FC_P__PD_CREDITS__SHIFT 0x0 10561 + #define PCIE_FC_P__PH_CREDITS_MASK 0xff00 10562 + #define PCIE_FC_P__PH_CREDITS__SHIFT 0x8 10563 + #define PCIE_FC_NP__NPD_CREDITS_MASK 0xff 10564 + #define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 10565 + #define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 10566 + #define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 10567 + #define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff 10568 + #define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 10569 + #define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 10570 + #define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 10571 + #define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 10572 + #define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 10573 + #define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 10574 + #define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 10575 + #define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 10576 + #define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 10577 + #define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 10578 + #define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 10579 + #define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 10580 + #define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 10581 + #define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 10582 + #define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 10583 + #define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 10584 + #define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 10585 + #define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 10586 + #define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 10587 + #define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 10588 + #define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb 10589 + #define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000 10590 + #define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc 10591 + #define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000 10592 + #define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd 10593 + #define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 10594 + #define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe 10595 + #define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 10596 + #define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf 10597 + #define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 10598 + #define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 10599 + #define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 10600 + #define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 10601 + #define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 10602 + #define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 10603 + #define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 10604 + #define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 10605 + #define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 10606 + #define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 10607 + #define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 10608 + #define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 10609 + #define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 10610 + #define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 10611 + #define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 10612 + #define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 10613 + #define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 10614 + #define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 10615 + #define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 10616 + #define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 10617 + #define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 10618 + #define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 10619 + #define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 10620 + #define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 10621 + #define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 10622 + #define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 10623 + #define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 10624 + #define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa 10625 + #define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 10626 + #define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb 10627 + #define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 10628 + #define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc 10629 + #define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 10630 + #define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd 10631 + #define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 10632 + #define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe 10633 + #define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 10634 + #define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf 10635 + #define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 10636 + #define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 10637 + #define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 10638 + #define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 10639 + #define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 10640 + #define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 10641 + #define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 10642 + #define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 10643 + #define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 10644 + #define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 10645 + #define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 10646 + #define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 10647 + #define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 10648 + #define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 10649 + #define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 10650 + #define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 10651 + #define PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 10652 + #define PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a 10653 + #define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 10654 + #define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b 10655 + #define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff 10656 + #define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 10657 + #define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff 10658 + #define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 10659 + #define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 10660 + #define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 10661 + #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 10662 + #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 10663 + #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 10664 + #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 10665 + #define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 10666 + #define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 10667 + #define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 10668 + #define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 10669 + #define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 10670 + #define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 10671 + #define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff 10672 + #define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 10673 + #define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 10674 + #define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 10675 + #define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff 10676 + #define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 10677 + #define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 10678 + #define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 10679 + #define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff 10680 + #define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 10681 + #define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 10682 + #define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 10683 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 10684 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 10685 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc 10686 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 10687 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 10688 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 10689 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 10690 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 10691 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 10692 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 10693 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 10694 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa 10695 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 10696 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc 10697 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 10698 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe 10699 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 10700 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 10701 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 10702 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 10703 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 10704 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 10705 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 10706 + #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 10707 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 10708 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 10709 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc 10710 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 10711 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 10712 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 10713 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 10714 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 10715 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 10716 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 10717 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 10718 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa 10719 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 10720 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc 10721 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 10722 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe 10723 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 10724 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 10725 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 10726 + #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 10727 + #define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE_MASK 0x3 10728 + #define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE__SHIFT 0x0 10729 + #define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0xc 10730 + #define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x2 10731 + #define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 10732 + #define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 10733 + #define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 10734 + #define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 10735 + #define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 10736 + #define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 10737 + #define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 10738 + #define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 10739 + #define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 10740 + #define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 10741 + #define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 10742 + #define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc 10743 + #define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 10744 + #define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 10745 + #define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 10746 + #define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 10747 + #define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 10748 + #define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 10749 + #define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 10750 + #define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 10751 + #define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 10752 + #define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 10753 + #define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 10754 + #define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 10755 + #define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 10756 + #define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 10757 + #define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 10758 + #define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 10759 + #define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 10760 + #define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 10761 + #define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 10762 + #define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b 10763 + #define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 10764 + #define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c 10765 + #define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 10766 + #define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d 10767 + #define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 10768 + #define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e 10769 + #define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 10770 + #define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f 10771 + #define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f 10772 + #define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 10773 + #define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 10774 + #define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 10775 + #define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 10776 + #define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 10777 + #define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 10778 + #define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 10779 + #define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 10780 + #define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 10781 + #define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 10782 + #define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa 10783 + #define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 10784 + #define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb 10785 + #define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 10786 + #define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc 10787 + #define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 10788 + #define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd 10789 + #define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 10790 + #define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe 10791 + #define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 10792 + #define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 10793 + #define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 10794 + #define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 10795 + #define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 10796 + #define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 10797 + #define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 10798 + #define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 10799 + #define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 10800 + #define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 10801 + #define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 10802 + #define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 10803 + #define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 10804 + #define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 10805 + #define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 10806 + #define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 10807 + #define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 10808 + #define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 10809 + #define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 10810 + #define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a 10811 + #define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 10812 + #define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b 10813 + #define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 10814 + #define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c 10815 + #define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 10816 + #define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d 10817 + #define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 10818 + #define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f 10819 + #define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 10820 + #define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 10821 + #define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 10822 + #define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 10823 + #define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 10824 + #define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 10825 + #define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 10826 + #define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 10827 + #define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 10828 + #define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 10829 + #define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 10830 + #define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 10831 + #define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 10832 + #define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 10833 + #define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 10834 + #define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 10835 + #define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 10836 + #define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa 10837 + #define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 10838 + #define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb 10839 + #define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 10840 + #define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc 10841 + #define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 10842 + #define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe 10843 + #define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 10844 + #define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 10845 + #define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 10846 + #define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 10847 + #define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 10848 + #define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 10849 + #define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 10850 + #define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 10851 + #define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 10852 + #define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 10853 + #define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 10854 + #define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 10855 + #define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 10856 + #define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 10857 + #define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 10858 + #define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 10859 + #define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 10860 + #define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a 10861 + #define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 10862 + #define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e 10863 + #define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 10864 + #define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f 10865 + #define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 10866 + #define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 10867 + #define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 10868 + #define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 10869 + #define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 10870 + #define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 10871 + #define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 10872 + #define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 10873 + #define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 10874 + #define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 10875 + #define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 10876 + #define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 10877 + #define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 10878 + #define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 10879 + #define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 10880 + #define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 10881 + #define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 10882 + #define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa 10883 + #define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 10884 + #define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb 10885 + #define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 10886 + #define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc 10887 + #define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 10888 + #define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd 10889 + #define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 10890 + #define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe 10891 + #define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 10892 + #define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf 10893 + #define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 10894 + #define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 10895 + #define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 10896 + #define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 10897 + #define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 10898 + #define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 10899 + #define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 10900 + #define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 10901 + #define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 10902 + #define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 10903 + #define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 10904 + #define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 10905 + #define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 10906 + #define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 10907 + #define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 10908 + #define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a 10909 + #define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f 10910 + #define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 10911 + #define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 10912 + #define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 10913 + #define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 10914 + #define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc 10915 + #define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 10916 + #define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 10917 + #define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 10918 + #define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 10919 + #define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 10920 + #define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 10921 + #define PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 10922 + #define PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 10923 + #define PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 10924 + #define PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 10925 + #define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 10926 + #define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 10927 + #define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 10928 + #define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 10929 + #define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 10930 + #define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 10931 + #define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 10932 + #define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 10933 + #define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 10934 + #define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 10935 + #define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 10936 + #define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 10937 + #define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 10938 + #define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 10939 + #define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 10940 + #define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 10941 + #define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 10942 + #define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 10943 + #define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 10944 + #define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 10945 + #define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 10946 + #define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa 10947 + #define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf 10948 + #define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 10949 + #define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 10950 + #define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 10951 + #define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 10952 + #define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 10953 + #define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 10954 + #define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 10955 + #define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 10956 + #define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 10957 + #define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 10958 + #define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 10959 + #define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 10960 + #define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb 10961 + #define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 10962 + #define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc 10963 + #define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 10964 + #define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd 10965 + #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 10966 + #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe 10967 + #define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 10968 + #define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf 10969 + #define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 10970 + #define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 10971 + #define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 10972 + #define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 10973 + #define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 10974 + #define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 10975 + #define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 10976 + #define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 10977 + #define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 10978 + #define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 10979 + #define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 10980 + #define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 10981 + #define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 10982 + #define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 10983 + #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 10984 + #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 10985 + #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 10986 + #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 10987 + #define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 10988 + #define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a 10989 + #define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 10990 + #define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b 10991 + #define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 10992 + #define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c 10993 + #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 10994 + #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d 10995 + #define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 10996 + #define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e 10997 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 10998 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 10999 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 11000 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 11001 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 11002 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 11003 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 11004 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 11005 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 11006 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 11007 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 11008 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa 11009 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 11010 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb 11011 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 11012 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc 11013 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 11014 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd 11015 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 11016 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe 11017 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 11018 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf 11019 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 11020 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 11021 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 11022 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 11023 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 11024 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 11025 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 11026 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 11027 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 11028 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 11029 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 11030 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 11031 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 11032 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 11033 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 11034 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 11035 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 11036 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 11037 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 11038 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a 11039 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 11040 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b 11041 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 11042 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c 11043 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 11044 + #define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d 11045 + #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff 11046 + #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 11047 + #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 11048 + #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 11049 + #define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 11050 + #define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 11051 + #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 11052 + #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 11053 + #define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 11054 + #define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 11055 + #define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 11056 + #define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 11057 + #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 11058 + #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 11059 + #define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 11060 + #define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 11061 + #define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 11062 + #define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 11063 + #define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 11064 + #define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 11065 + #define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 11066 + #define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 11067 + #define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 11068 + #define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 11069 + #define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 11070 + #define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 11071 + #define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 11072 + #define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 11073 + #define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 11074 + #define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa 11075 + #define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 11076 + #define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc 11077 + #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 11078 + #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd 11079 + #define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 11080 + #define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf 11081 + #define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 11082 + #define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 11083 + #define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 11084 + #define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 11085 + #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 11086 + #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 11087 + #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 11088 + #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 11089 + #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 11090 + #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 11091 + #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 11092 + #define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 11093 + #define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 11094 + #define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 11095 + #define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 11096 + #define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 11097 + #define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 11098 + #define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 11099 + #define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 11100 + #define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a 11101 + #define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 11102 + #define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b 11103 + #define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 11104 + #define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c 11105 + #define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 11106 + #define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d 11107 + #define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 11108 + #define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e 11109 + #define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 11110 + #define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f 11111 + #define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff 11112 + #define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 11113 + #define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 11114 + #define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc 11115 + #define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 11116 + #define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 11117 + #define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff 11118 + #define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 11119 + #define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 11120 + #define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 11121 + #define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 11122 + #define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 11123 + #define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e 11124 + #define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 11125 + #define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 11126 + #define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 11127 + #define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 11128 + #define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd 11129 + #define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 11130 + #define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 11131 + #define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 11132 + #define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 11133 + #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf 11134 + #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 11135 + #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 11136 + #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 11137 + #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 11138 + #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa 11139 + #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 11140 + #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 11141 + #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 11142 + #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 11143 + #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 11144 + #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 11145 + #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e 11146 + #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 11147 + #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 11148 + #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 11149 + #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 11150 + #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd 11151 + #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 11152 + #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 11153 + #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 11154 + #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 11155 + #define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f 11156 + #define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 11157 + #define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 11158 + #define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 11159 + #define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 11160 + #define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 11161 + #define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 11162 + #define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 11163 + #define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f 11164 + #define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 11165 + #define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 11166 + #define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 11167 + #define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 11168 + #define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 11169 + #define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 11170 + #define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 11171 + #define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f 11172 + #define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 11173 + #define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 11174 + #define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 11175 + #define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 11176 + #define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 11177 + #define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 11178 + #define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 11179 + #define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f 11180 + #define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 11181 + #define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 11182 + #define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 11183 + #define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 11184 + #define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 11185 + #define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 11186 + #define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 11187 + #define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f 11188 + #define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 11189 + #define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 11190 + #define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 11191 + #define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 11192 + #define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 11193 + #define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 11194 + #define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 11195 + #define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f 11196 + #define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 11197 + #define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 11198 + #define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 11199 + #define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 11200 + #define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 11201 + #define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 11202 + #define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 11203 + #define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 11204 + #define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 11205 + #define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc 11206 + #define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 11207 + #define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 11208 + #define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 11209 + #define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 11210 + #define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 11211 + #define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 11212 + #define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 11213 + #define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 11214 + #define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb 11215 + #define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 11216 + #define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc 11217 + #define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 11218 + #define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd 11219 + #define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 11220 + #define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe 11221 + #define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 11222 + #define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf 11223 + #define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 11224 + #define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 11225 + #define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 11226 + #define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 11227 + #define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 11228 + #define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 11229 + #define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 11230 + #define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 11231 + #define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 11232 + #define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 11233 + #define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 11234 + #define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 11235 + #define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 11236 + #define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 11237 + #define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 11238 + #define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 11239 + #define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 11240 + #define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 11241 + #define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 11242 + #define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 11243 + #define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 11244 + #define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 11245 + #define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 11246 + #define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 11247 + #define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 11248 + #define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 11249 + #define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 11250 + #define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 11251 + #define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 11252 + #define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 11253 + #define PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 11254 + #define PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 11255 + #define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 11256 + #define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 11257 + #define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 11258 + #define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 11259 + #define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 11260 + #define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa 11261 + #define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 11262 + #define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb 11263 + #define PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 11264 + #define PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf 11265 + #define PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 11266 + #define PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 11267 + #define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc 11268 + #define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 11269 + #define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff 11270 + #define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 11271 + #define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xffffffff 11272 + #define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 11273 + #define PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x1 11274 + #define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 11275 + #define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc 11276 + #define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 11277 + #define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff 11278 + #define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 11279 + #define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xffffffff 11280 + #define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 11281 + #define PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x1 11282 + #define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 11283 + #define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc 11284 + #define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 11285 + #define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff 11286 + #define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 11287 + #define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xffffffff 11288 + #define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 11289 + #define PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x1 11290 + #define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 11291 + #define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc 11292 + #define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 11293 + #define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff 11294 + #define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 11295 + #define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xffffffff 11296 + #define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 11297 + #define PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x1 11298 + #define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 11299 + #define PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xf 11300 + #define PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 11301 + #define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1 11302 + #define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0 11303 + #define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2 11304 + #define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1 11305 + #define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1 11306 + #define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0 11307 + #define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2 11308 + #define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1 11309 + #define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff 11310 + #define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0 11311 + #define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000 11312 + #define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e 11313 + #define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000 11314 + #define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f 11315 + #define BIF_RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1 11316 + #define BIF_RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0 11317 + #define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst_MASK 0x1 11318 + #define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst__SHIFT 0x0 11319 + #define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst_MASK 0x2 11320 + #define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst__SHIFT 0x1 11321 + #define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst_MASK 0x1 11322 + #define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst__SHIFT 0x0 11323 + #define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst_MASK 0x2 11324 + #define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst__SHIFT 0x1 11325 + #define BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst_MASK 0x4 11326 + #define BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst__SHIFT 0x2 11327 + #define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x8 11328 + #define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x3 11329 + #define BIF_PWDN_COMMAND__REG_BU_pw_cmd_MASK 0x1 11330 + #define BIF_PWDN_COMMAND__REG_BU_pw_cmd__SHIFT 0x0 11331 + #define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd_MASK 0x2 11332 + #define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd__SHIFT 0x1 11333 + #define BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd_MASK 0x4 11334 + #define BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd__SHIFT 0x2 11335 + #define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x8 11336 + #define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x3 11337 + #define BIF_PWDN_STATUS__BU_REG_pw_status_MASK 0x1 11338 + #define BIF_PWDN_STATUS__BU_REG_pw_status__SHIFT 0x0 11339 + #define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status_MASK 0x2 11340 + #define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status__SHIFT 0x1 11341 + #define BIF_PWDN_STATUS__SMBUS_REG_pw_status_MASK 0x4 11342 + #define BIF_PWDN_STATUS__SMBUS_REG_pw_status__SHIFT 0x2 11343 + #define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x8 11344 + #define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x3 11345 + #define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer_MASK 0xff 11346 + #define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer__SHIFT 0x0 11347 + #define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer_MASK 0xf00 11348 + #define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer__SHIFT 0x8 11349 + #define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer_MASK 0xff0000 11350 + #define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer__SHIFT 0x10 11351 + #define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout_MASK 0x1000000 11352 + #define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout__SHIFT 0x18 11353 + #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer_MASK 0xff 11354 + #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer__SHIFT 0x0 11355 + #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer_MASK 0xf00 11356 + #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer__SHIFT 0x8 11357 + #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer_MASK 0xff0000 11358 + #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer__SHIFT 0x10 11359 + #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout_MASK 0x1000000 11360 + #define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout__SHIFT 0x18 11361 + #define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkGate_timer_MASK 0xff 11362 + #define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkGate_timer__SHIFT 0x0 11363 + #define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkSetup_timer_MASK 0xf00 11364 + #define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkSetup_timer__SHIFT 0x8 11365 + #define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_timeout_timer_MASK 0xff0000 11366 + #define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_timeout_timer__SHIFT 0x10 11367 + #define BIF_RFE_MST_SMBUS_CMDSTATUS__SMBUS_RFE_mstTimeout_MASK 0x1000000 11368 + #define BIF_RFE_MST_SMBUS_CMDSTATUS__SMBUS_RFE_mstTimeout__SHIFT 0x18 11369 + #define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff 11370 + #define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0 11371 + #define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00 11372 + #define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8 11373 + #define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000 11374 + #define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10 11375 + #define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000 11376 + #define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18 11377 + #define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1 11378 + #define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0 11379 + #define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x1 11380 + #define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x0 11381 + #define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe 11382 + #define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x1 11383 + #define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x10 11384 + #define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x4 11385 + #define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe0 11386 + #define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x5 11387 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_MASK 0x1e 11388 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL__SHIFT 0x1 11389 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN_MASK 0x20 11390 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN__SHIFT 0x5 11391 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD_MASK 0x3c0 11392 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD__SHIFT 0x6 11393 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD_MASK 0x400 11394 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD__SHIFT 0xa 11395 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU_MASK 0x7800 11396 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU__SHIFT 0xb 11397 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU_MASK 0x8000 11398 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU__SHIFT 0xf 11399 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN_MASK 0x10000 11400 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN__SHIFT 0x10 11401 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_IGNORE_QUICKSIM_MASK 0x20000 11402 + #define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_IGNORE_QUICKSIM__SHIFT 0x11 11403 + #define BIF_IMPCTL_SMPLCNTL__FORCE_DONE_MASK 0x1 11404 + #define BIF_IMPCTL_SMPLCNTL__FORCE_DONE__SHIFT 0x0 11405 + #define BIF_IMPCTL_SMPLCNTL__RxPDNB_MASK 0x2 11406 + #define BIF_IMPCTL_SMPLCNTL__RxPDNB__SHIFT 0x1 11407 + #define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd_MASK 0x4 11408 + #define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd__SHIFT 0x2 11409 + #define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu_MASK 0x8 11410 + #define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu__SHIFT 0x3 11411 + #define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD_MASK 0x1f00 11412 + #define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD__SHIFT 0x8 11413 + #define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES_MASK 0x2000 11414 + #define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES__SHIFT 0xd 11415 + #define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE_MASK 0x4000 11416 + #define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE__SHIFT 0xe 11417 + #define BIF_IMPCTL_SMPLCNTL__SETUP_TIME_MASK 0xf8000 11418 + #define BIF_IMPCTL_SMPLCNTL__SETUP_TIME__SHIFT 0xf 11419 + #define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH_MASK 0x3f00000 11420 + #define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH__SHIFT 0x14 11421 + #define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH_MASK 0xfc000000 11422 + #define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH__SHIFT 0x1a 11423 + #define BIF_IMPCTL_RXCNTL__RX_ADJUST_MASK 0x7 11424 + #define BIF_IMPCTL_RXCNTL__RX_ADJUST__SHIFT 0x0 11425 + #define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH_MASK 0x8 11426 + #define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH__SHIFT 0x3 11427 + #define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT_MASK 0x10 11428 + #define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT__SHIFT 0x4 11429 + #define BIF_IMPCTL_RXCNTL__SUSPEND_MASK 0x40 11430 + #define BIF_IMPCTL_RXCNTL__SUSPEND__SHIFT 0x6 11431 + #define BIF_IMPCTL_RXCNTL__FORCE_RST_MASK 0x80 11432 + #define BIF_IMPCTL_RXCNTL__FORCE_RST__SHIFT 0x7 11433 + #define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH_MASK 0xf00 11434 + #define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH__SHIFT 0x8 11435 + #define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_MASK 0x1000 11436 + #define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ__SHIFT 0xc 11437 + #define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH_MASK 0x1e000 11438 + #define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH__SHIFT 0xd 11439 + #define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_MASK 0x20000 11440 + #define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ__SHIFT 0x11 11441 + #define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED_MASK 0x40000 11442 + #define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED__SHIFT 0x12 11443 + #define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL_MASK 0x80000 11444 + #define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL__SHIFT 0x13 11445 + #define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_MASK 0xf00000 11446 + #define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK__SHIFT 0x14 11447 + #define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG_MASK 0x10000000 11448 + #define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG__SHIFT 0x1c 11449 + #define BIF_IMPCTL_RXCNTL__CAL_DONE_MASK 0x20000000 11450 + #define BIF_IMPCTL_RXCNTL__CAL_DONE__SHIFT 0x1d 11451 + #define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd_MASK 0x7 11452 + #define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd__SHIFT 0x0 11453 + #define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd_MASK 0x8 11454 + #define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd__SHIFT 0x3 11455 + #define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd_MASK 0xf00 11456 + #define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd__SHIFT 0x8 11457 + #define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd_MASK 0x1000 11458 + #define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd__SHIFT 0xc 11459 + #define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd_MASK 0x1e000 11460 + #define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd__SHIFT 0xd 11461 + #define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd_MASK 0x20000 11462 + #define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd__SHIFT 0x11 11463 + #define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd_MASK 0x40000 11464 + #define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd__SHIFT 0x12 11465 + #define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd_MASK 0x80000 11466 + #define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd__SHIFT 0x13 11467 + #define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd_MASK 0xf00000 11468 + #define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd__SHIFT 0x14 11469 + #define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd_MASK 0x10000000 11470 + #define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd__SHIFT 0x1c 11471 + #define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu_MASK 0x7 11472 + #define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu__SHIFT 0x0 11473 + #define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu_MASK 0x8 11474 + #define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu__SHIFT 0x3 11475 + #define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu_MASK 0xf00 11476 + #define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu__SHIFT 0x8 11477 + #define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu_MASK 0x1000 11478 + #define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu__SHIFT 0xc 11479 + #define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu_MASK 0x1e000 11480 + #define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu__SHIFT 0xd 11481 + #define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu_MASK 0x20000 11482 + #define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu__SHIFT 0x11 11483 + #define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu_MASK 0x40000 11484 + #define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu__SHIFT 0x12 11485 + #define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu_MASK 0x80000 11486 + #define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu__SHIFT 0x13 11487 + #define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu_MASK 0xf00000 11488 + #define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu__SHIFT 0x14 11489 + #define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu_MASK 0x10000000 11490 + #define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu__SHIFT 0x1c 11491 + #define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD_MASK 0xffffffff 11492 + #define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD__SHIFT 0x0 11493 + 11494 + #endif /* BIF_5_0_SH_MASK_H */