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linux
[MIPS] The irq_chip for TX39/TX49 SoCs
Add generic irq_chip for TX39/TX49 SoCs. This can be replace
jmr3927_irq_irc, tx4927_irq_pic_type and tx4938_irq_pic_type.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
Atsushi Nemoto
and committed by
Ralf Baechle
8420fd00
477f949e
+230
+3
arch/mips/Kconfig
+3
arch/mips/Kconfig
+1
arch/mips/kernel/Makefile
+1
arch/mips/kernel/Makefile
+196
arch/mips/kernel/irq_txx9.c
+196
arch/mips/kernel/irq_txx9.c
···
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/*
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* linux/arch/mips/kernel/irq_txx9.c
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*
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* Based on linux/arch/mips/jmr3927/rbhma3100/irq.c,
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* linux/arch/mips/tx4927/common/tx4927_irq.c,
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* linux/arch/mips/tx4938/common/irq.c
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*
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* Copyright 2001, 2003-2005 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ahennessy@mvista.com
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* source@mvista.com
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <asm/txx9irq.h>
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struct txx9_irc_reg {
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u32 cer;
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u32 cr[2];
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u32 unused0;
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u32 ilr[8];
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u32 unused1[4];
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u32 imr;
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u32 unused2[7];
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u32 scr;
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u32 unused3[7];
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u32 ssr;
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u32 unused4[7];
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u32 csr;
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};
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/* IRCER : Int. Control Enable */
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#define TXx9_IRCER_ICE 0x00000001
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/* IRCR : Int. Control */
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#define TXx9_IRCR_LOW 0x00000000
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#define TXx9_IRCR_HIGH 0x00000001
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#define TXx9_IRCR_DOWN 0x00000002
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#define TXx9_IRCR_UP 0x00000003
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#define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002)
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/* IRSCR : Int. Status Control */
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#define TXx9_IRSCR_EIClrE 0x00000100
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#define TXx9_IRSCR_EIClr_MASK 0x0000000f
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/* IRCSR : Int. Current Status */
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#define TXx9_IRCSR_IF 0x00010000
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#define TXx9_IRCSR_ILV_MASK 0x00000700
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#define TXx9_IRCSR_IVL_MASK 0x0000001f
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#define irc_dlevel 0
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#define irc_elevel 1
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static struct txx9_irc_reg __iomem *txx9_ircptr __read_mostly;
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static struct {
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unsigned char level;
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unsigned char mode;
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} txx9irq[TXx9_MAX_IR] __read_mostly;
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static void txx9_irq_unmask(unsigned int irq)
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{
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unsigned int irq_nr = irq - TXX9_IRQ_BASE;
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u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16 ) / 2];
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int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
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__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
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| (txx9irq[irq_nr].level << ofs),
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ilrp);
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#ifdef CONFIG_CPU_TX39XX
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/* update IRCSR */
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__raw_writel(0, &txx9_ircptr->imr);
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__raw_writel(irc_elevel, &txx9_ircptr->imr);
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#endif
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}
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static inline void txx9_irq_mask(unsigned int irq)
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{
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unsigned int irq_nr = irq - TXX9_IRQ_BASE;
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u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16) / 2];
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int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
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__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
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| (irc_dlevel << ofs),
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ilrp);
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#ifdef CONFIG_CPU_TX39XX
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/* update IRCSR */
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__raw_writel(0, &txx9_ircptr->imr);
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__raw_writel(irc_elevel, &txx9_ircptr->imr);
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/* flush write buffer */
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__raw_readl(&txx9_ircptr->ssr);
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#else
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mmiowb();
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#endif
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}
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static void txx9_irq_mask_ack(unsigned int irq)
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{
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unsigned int irq_nr = irq - TXX9_IRQ_BASE;
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txx9_irq_mask(irq);
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if (TXx9_IRCR_EDGE(txx9irq[irq_nr].mode)) {
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/* clear edge detection */
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u32 cr = __raw_readl(&txx9_ircptr->cr[irq_nr / 8]);
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cr = (cr >> ((irq_nr & (8 - 1)) * 2)) & 3;
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__raw_writel(TXx9_IRSCR_EIClrE | irq_nr,
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&txx9_ircptr->scr);
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}
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}
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static int txx9_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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unsigned int irq_nr = irq - TXX9_IRQ_BASE;
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u32 cr;
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u32 __iomem *crp;
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int ofs;
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int mode;
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if (flow_type & IRQF_TRIGGER_PROBE)
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return 0;
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switch (flow_type & IRQF_TRIGGER_MASK) {
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case IRQF_TRIGGER_RISING: mode = TXx9_IRCR_UP; break;
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case IRQF_TRIGGER_FALLING: mode = TXx9_IRCR_DOWN; break;
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case IRQF_TRIGGER_HIGH: mode = TXx9_IRCR_HIGH; break;
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case IRQF_TRIGGER_LOW: mode = TXx9_IRCR_LOW; break;
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default:
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return -EINVAL;
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}
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crp = &txx9_ircptr->cr[(unsigned int)irq_nr / 8];
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cr = __raw_readl(crp);
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ofs = (irq_nr & (8 - 1)) * 2;
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cr &= ~(0x3 << ofs);
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cr |= (mode & 0x3) << ofs;
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__raw_writel(cr, crp);
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txx9irq[irq_nr].mode = mode;
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return 0;
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}
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static struct irq_chip txx9_irq_chip = {
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.name = "TXX9",
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.ack = txx9_irq_mask_ack,
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.mask = txx9_irq_mask,
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.mask_ack = txx9_irq_mask_ack,
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.unmask = txx9_irq_unmask,
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.set_type = txx9_irq_set_type,
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};
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void __init txx9_irq_init(unsigned long baseaddr)
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{
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int i;
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txx9_ircptr = ioremap(baseaddr, sizeof(struct txx9_irc_reg));
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for (i = 0; i < TXx9_MAX_IR; i++) {
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txx9irq[i].level = 4; /* middle level */
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txx9irq[i].mode = TXx9_IRCR_LOW;
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set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
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&txx9_irq_chip, handle_level_irq);
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}
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/* mask all IRC interrupts */
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__raw_writel(0, &txx9_ircptr->imr);
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for (i = 0; i < 8; i++)
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__raw_writel(0, &txx9_ircptr->ilr[i]);
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/* setup IRC interrupt mode (Low Active) */
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for (i = 0; i < 2; i++)
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__raw_writel(0, &txx9_ircptr->cr[i]);
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/* enable interrupt control */
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__raw_writel(TXx9_IRCER_ICE, &txx9_ircptr->cer);
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__raw_writel(irc_elevel, &txx9_ircptr->imr);
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}
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int __init txx9_irq_set_pri(int irc_irq, int new_pri)
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{
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int old_pri;
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if ((unsigned int)irc_irq >= TXx9_MAX_IR)
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return 0;
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old_pri = txx9irq[irc_irq].level;
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txx9irq[irc_irq].level = new_pri;
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return old_pri;
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}
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int txx9_irq(void)
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{
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u32 csr = __raw_readl(&txx9_ircptr->csr);
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if (likely(!(csr & TXx9_IRCSR_IF)))
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return TXX9_IRQ_BASE + (csr & (TXx9_MAX_IR - 1));
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return -1;
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}
+30
include/asm-mips/txx9irq.h
+30
include/asm-mips/txx9irq.h
···
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/*
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* include/asm-mips/txx9irq.h
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* TX39/TX49 interrupt controller definitions.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_TXX9IRQ_H
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#define __ASM_TXX9IRQ_H
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#include <irq.h>
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#ifdef CONFIG_IRQ_CPU
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#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
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#else
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#define TXX9_IRQ_BASE 0
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#endif
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#ifdef CONFIG_CPU_TX39XX
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#define TXx9_MAX_IR 16
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#else
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#define TXx9_MAX_IR 32
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#endif
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void txx9_irq_init(unsigned long baseaddr);
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int txx9_irq(void);
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int txx9_irq_set_pri(int irc_irq, int new_pri);
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#endif /* __ASM_TXX9IRQ_H */