tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Merge remote branch 'kumar/merge' into merge

Benjamin Herrenschmidt 83ebb3e3 b2a8b4b8

+38 -27
unified split
+6 -6
arch/powerpc/boot/dts/p1020rdb.dts
··· 1 1 /* 2 2 * P1020 RDB Device Tree Source 3 3 * 4 - * Copyright 2009 Freescale Semiconductor Inc. 4 + * Copyright 2009-2011 Freescale Semiconductor Inc. 5 5 * 6 6 * This program is free software; you can redistribute it and/or modify it 7 7 * under the terms of the GNU General Public License as published by the ··· 553 553 reg = <0 0xffe09000 0 0x1000>; 554 554 bus-range = <0 255>; 555 555 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 556 - 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; 556 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 557 557 clock-frequency = <33333333>; 558 558 interrupt-parent = <&mpic>; 559 559 interrupts = <16 2>; ··· 580 580 #address-cells = <3>; 581 581 reg = <0 0xffe0a000 0 0x1000>; 582 582 bus-range = <0 255>; 583 - ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 584 - 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 583 + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 584 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 585 585 clock-frequency = <33333333>; 586 586 interrupt-parent = <&mpic>; 587 587 interrupts = <16 2>; ··· 590 590 #size-cells = <2>; 591 591 #address-cells = <3>; 592 592 device_type = "pci"; 593 - ranges = <0x2000000 0x0 0xc0000000 594 - 0x2000000 0x0 0xc0000000 593 + ranges = <0x2000000 0x0 0x80000000 594 + 0x2000000 0x0 0x80000000 595 595 0x0 0x20000000 596 596 597 597 0x1000000 0x0 0x0
+6 -6
arch/powerpc/boot/dts/p2020rdb.dts
··· 1 1 /* 2 2 * P2020 RDB Device Tree Source 3 3 * 4 - * Copyright 2009 Freescale Semiconductor Inc. 4 + * Copyright 2009-2011 Freescale Semiconductor Inc. 5 5 * 6 6 * This program is free software; you can redistribute it and/or modify it 7 7 * under the terms of the GNU General Public License as published by the ··· 537 537 reg = <0 0xffe09000 0 0x1000>; 538 538 bus-range = <0 255>; 539 539 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 540 - 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; 540 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 541 541 clock-frequency = <33333333>; 542 542 interrupt-parent = <&mpic>; 543 543 interrupts = <25 2>; ··· 564 564 #address-cells = <3>; 565 565 reg = <0 0xffe0a000 0 0x1000>; 566 566 bus-range = <0 255>; 567 - ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 568 - 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 567 + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 568 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 569 569 clock-frequency = <33333333>; 570 570 interrupt-parent = <&mpic>; 571 571 interrupts = <26 2>; ··· 574 574 #size-cells = <2>; 575 575 #address-cells = <3>; 576 576 device_type = "pci"; 577 - ranges = <0x2000000 0x0 0xc0000000 578 - 0x2000000 0x0 0xc0000000 577 + ranges = <0x2000000 0x0 0x80000000 578 + 0x2000000 0x0 0x80000000 579 579 0x0 0x20000000 580 580 581 581 0x1000000 0x0 0x0
+2 -2
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
··· 6 6 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb, 7 7 * eth1, eth2, sdhc, crypto, global-util, pci0. 8 8 * 9 - * Copyright 2009 Freescale Semiconductor Inc. 9 + * Copyright 2009-2011 Freescale Semiconductor Inc. 10 10 * 11 11 * This program is free software; you can redistribute it and/or modify it 12 12 * under the terms of the GNU General Public License as published by the ··· 342 342 reg = <0 0xffe09000 0 0x1000>; 343 343 bus-range = <0 255>; 344 344 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 345 - 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; 345 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 346 346 clock-frequency = <33333333>; 347 347 interrupt-parent = <&mpic>; 348 348 interrupts = <25 2>;
+5 -5
arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
··· 7 7 * 8 8 * Please note to add "-b 1" for core1's dts compiling. 9 9 * 10 - * Copyright 2009 Freescale Semiconductor Inc. 10 + * Copyright 2009-2011 Freescale Semiconductor Inc. 11 11 * 12 12 * This program is free software; you can redistribute it and/or modify it 13 13 * under the terms of the GNU General Public License as published by the ··· 162 162 #address-cells = <3>; 163 163 reg = <0 0xffe0a000 0 0x1000>; 164 164 bus-range = <0 255>; 165 - ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 166 - 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 165 + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 166 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 167 167 clock-frequency = <33333333>; 168 168 interrupt-parent = <&mpic>; 169 169 interrupts = <26 2>; ··· 172 172 #size-cells = <2>; 173 173 #address-cells = <3>; 174 174 device_type = "pci"; 175 - ranges = <0x2000000 0x0 0xc0000000 176 - 0x2000000 0x0 0xc0000000 175 + ranges = <0x2000000 0x0 0x80000000 176 + 0x2000000 0x0 0x80000000 177 177 0x0 0x20000000 178 178 179 179 0x1000000 0x0 0x0
+19 -8
drivers/edac/mpc85xx_edac.c
··· 1147 1147 static void __init mpc85xx_mc_clear_rfxe(void *data) 1148 1148 { 1149 1149 orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1); 1150 - mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000)); 1150 + mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE)); 1151 1151 } 1152 1152 #endif 1153 1153 1154 1154 static int __init mpc85xx_mc_init(void) 1155 1155 { 1156 1156 int res = 0; 1157 + u32 pvr = 0; 1157 1158 1158 1159 printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " 1159 1160 "(C) 2006 Montavista Software\n"); ··· 1184 1183 #endif 1185 1184 1186 1185 #ifdef CONFIG_FSL_SOC_BOOKE 1187 - /* 1188 - * need to clear HID1[RFXE] to disable machine check int 1189 - * so we can catch it 1190 - */ 1191 - if (edac_op_state == EDAC_OPSTATE_INT) 1192 - on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); 1186 + pvr = mfspr(SPRN_PVR); 1187 + 1188 + if ((PVR_VER(pvr) == PVR_VER_E500V1) || 1189 + (PVR_VER(pvr) == PVR_VER_E500V2)) { 1190 + /* 1191 + * need to clear HID1[RFXE] to disable machine check int 1192 + * so we can catch it 1193 + */ 1194 + if (edac_op_state == EDAC_OPSTATE_INT) 1195 + on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); 1196 + } 1193 1197 #endif 1194 1198 1195 1199 return 0; ··· 1212 1206 static void __exit mpc85xx_mc_exit(void) 1213 1207 { 1214 1208 #ifdef CONFIG_FSL_SOC_BOOKE 1215 - on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); 1209 + u32 pvr = mfspr(SPRN_PVR); 1210 + 1211 + if ((PVR_VER(pvr) == PVR_VER_E500V1) || 1212 + (PVR_VER(pvr) == PVR_VER_E500V2)) { 1213 + on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); 1214 + } 1216 1215 #endif 1217 1216 #ifdef CONFIG_PCI 1218 1217 platform_driver_unregister(&mpc85xx_pci_err_driver);