Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

arm64/sysreg: Rename POE_RXW to POE_RWX

It is customary to list R, W, X permissions in that order. In fact
this is already the case for PIE constants (PIE_RWX). Rename POE_RXW
accordingly, as well as POE_XW (currently unused).

While at it also swap the W/X lines in
compute_s1_overlay_permissions() to follow the R, W, X order.

Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
Link: https://lore.kernel.org/r/20250219164029.2309119-3-kevin.brodsky@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

authored by

Kevin Brodsky and committed by
Catalin Marinas
83d78bbf f91a3a60

+10 -10
+3 -3
arch/arm64/include/asm/sysreg.h
··· 1077 1077 #define POE_RX UL(0x3) 1078 1078 #define POE_W UL(0x4) 1079 1079 #define POE_RW UL(0x5) 1080 - #define POE_XW UL(0x6) 1081 - #define POE_RXW UL(0x7) 1080 + #define POE_WX UL(0x6) 1081 + #define POE_RWX UL(0x7) 1082 1082 #define POE_MASK UL(0xf) 1083 1083 1084 1084 #define POR_ELx_BITS_PER_IDX 4 ··· 1087 1087 #define POR_ELx_PERM_PREP(idx, perm) (((perm) & POE_MASK) << POR_ELx_PERM_SHIFT(idx)) 1088 1088 1089 1089 /* Initial value for Permission Overlay Extension for EL0 */ 1090 - #define POR_EL0_INIT POE_RXW 1090 + #define POR_EL0_INIT POE_RWX 1091 1091 1092 1092 /* 1093 1093 * Definitions for Guarded Control Stack
+1 -1
arch/arm64/kernel/signal.c
··· 91 91 u64 por_enable_all = 0; 92 92 93 93 for (int pkey = 0; pkey < arch_max_pkey(); pkey++) 94 - por_enable_all |= POR_ELx_PERM_PREP(pkey, POE_RXW); 94 + por_enable_all |= POR_ELx_PERM_PREP(pkey, POE_RWX); 95 95 96 96 ua_state->por_el0 = read_sysreg_s(SYS_POR_EL0); 97 97 write_sysreg_s(por_enable_all, SYS_POR_EL0);
+4 -4
arch/arm64/kvm/at.c
··· 1090 1090 break; 1091 1091 } 1092 1092 1093 - if (pov_perms & ~POE_RXW) 1093 + if (pov_perms & ~POE_RWX) 1094 1094 pov_perms = POE_NONE; 1095 1095 1096 1096 if (wi->poe && wr->pov) { 1097 1097 wr->pr &= pov_perms & POE_R; 1098 - wr->px &= pov_perms & POE_X; 1099 1098 wr->pw &= pov_perms & POE_W; 1099 + wr->px &= pov_perms & POE_X; 1100 1100 } 1101 1101 1102 - if (uov_perms & ~POE_RXW) 1102 + if (uov_perms & ~POE_RWX) 1103 1103 uov_perms = POE_NONE; 1104 1104 1105 1105 if (wi->e0poe && wr->uov) { 1106 1106 wr->ur &= uov_perms & POE_R; 1107 - wr->ux &= uov_perms & POE_X; 1108 1107 wr->uw &= uov_perms & POE_W; 1108 + wr->ux &= uov_perms & POE_X; 1109 1109 } 1110 1110 } 1111 1111
+2 -2
arch/arm64/mm/mmu.c
··· 1555 1555 #ifdef CONFIG_ARCH_HAS_PKEYS 1556 1556 int arch_set_user_pkey_access(struct task_struct *tsk, int pkey, unsigned long init_val) 1557 1557 { 1558 - u64 new_por = POE_RXW; 1558 + u64 new_por; 1559 1559 u64 old_por; 1560 1560 1561 1561 if (!system_supports_poe()) ··· 1570 1570 return -EINVAL; 1571 1571 1572 1572 /* Set the bits we need in POR: */ 1573 - new_por = POE_RXW; 1573 + new_por = POE_RWX; 1574 1574 if (init_val & PKEY_DISABLE_WRITE) 1575 1575 new_por &= ~POE_W; 1576 1576 if (init_val & PKEY_DISABLE_ACCESS)