tjh.dev / kernel
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PCI: Use PCI_HEADER_TYPE_* instead of literals

Replace literals under drivers/pci/ with PCI_HEADER_TYPE_MASK,
PCI_HEADER_TYPE_NORMAL, and PCI_HEADER_TYPE_MFD.

Also replace !! boolean conversions with FIELD_GET().

Link: https://lore.kernel.org/r/20231003125300.5541-4-ilpo.jarvinen@linux.intel.com
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # for Renesas R-Car

authored by

Ilpo Järvinen and committed by
Bjorn Helgaas 83c08814 bdca03a2

+28 -27
+1 -1
drivers/pci/controller/dwc/pci-layerscape.c
··· 58 58 u32 header_type; 59 59 60 60 header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE); 61 - header_type &= 0x7f; 61 + header_type &= PCI_HEADER_TYPE_MASK; 62 62 63 63 return header_type == PCI_HEADER_TYPE_BRIDGE; 64 64 }
+1 -1
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
··· 539 539 u32 header_type; 540 540 541 541 header_type = mobiveil_csr_readb(pcie, PCI_HEADER_TYPE); 542 - header_type &= 0x7f; 542 + header_type &= PCI_HEADER_TYPE_MASK; 543 543 544 544 return header_type == PCI_HEADER_TYPE_BRIDGE; 545 545 }
+1 -1
drivers/pci/controller/pcie-iproc.c
··· 783 783 784 784 /* make sure we are not in EP mode */ 785 785 iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type); 786 - if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) { 786 + if ((hdr_type & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_BRIDGE) { 787 787 dev_err(dev, "in EP mode, hdr=%#02x\n", hdr_type); 788 788 return -EFAULT; 789 789 }
+1 -1
drivers/pci/controller/pcie-rcar-ep.c
··· 43 43 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); 44 44 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), 45 45 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ENDPOINT << 4); 46 - rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, 46 + rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), PCI_HEADER_TYPE_MASK, 47 47 PCI_HEADER_TYPE_NORMAL); 48 48 49 49 /* Write out the physical slot number = 0 */
+1 -1
drivers/pci/controller/pcie-rcar-host.c
··· 460 460 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); 461 461 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), 462 462 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); 463 - rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, 463 + rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), PCI_HEADER_TYPE_MASK, 464 464 PCI_HEADER_TYPE_BRIDGE); 465 465 466 466 /* Enable data link layer active state reporting */
+1 -1
drivers/pci/controller/vmd.c
··· 527 527 528 528 hdr_type = readb(base + PCI_HEADER_TYPE); 529 529 530 - functions = (hdr_type & 0x80) ? 8 : 1; 530 + functions = (hdr_type & PCI_HEADER_TYPE_MFD) ? 8 : 1; 531 531 for (fn = 0; fn < functions; fn++) { 532 532 base = vmd->cfgbar + PCIE_ECAM_OFFSET(bus, 533 533 PCI_DEVFN(dev, fn), 0);
+3 -3
drivers/pci/hotplug/cpqphp_ctrl.c
··· 2059 2059 return rc; 2060 2060 2061 2061 /* If it's a bridge, check the VGA Enable bit */ 2062 - if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 2062 + if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 2063 2063 rc = pci_bus_read_config_byte(pci_bus, devfn, PCI_BRIDGE_CONTROL, &BCR); 2064 2064 if (rc) 2065 2065 return rc; ··· 2342 2342 if (rc) 2343 2343 return rc; 2344 2344 2345 - if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 2345 + if ((temp_byte & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 2346 2346 /* set Primary bus */ 2347 2347 dbg("set Primary bus = %d\n", func->bus); 2348 2348 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_PRIMARY_BUS, func->bus); ··· 2739 2739 * PCI_BRIDGE_CTL_SERR | 2740 2740 * PCI_BRIDGE_CTL_NO_ISA */ 2741 2741 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command); 2742 - } else if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_NORMAL) { 2742 + } else if ((temp_byte & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_NORMAL) { 2743 2743 /* Standard device */ 2744 2744 rc = pci_bus_read_config_byte(pci_bus, devfn, 0x0B, &class_code); 2745 2745
+11 -11
drivers/pci/hotplug/cpqphp_pci.c
··· 363 363 return rc; 364 364 365 365 /* If multi-function device, set max_functions to 8 */ 366 - if (header_type & 0x80) 366 + if (header_type & PCI_HEADER_TYPE_MFD) 367 367 max_functions = 8; 368 368 else 369 369 max_functions = 1; ··· 372 372 373 373 do { 374 374 DevError = 0; 375 - if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 375 + if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 376 376 /* Recurse the subordinate bus 377 377 * get the subordinate bus number 378 378 */ ··· 487 487 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code); 488 488 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type); 489 489 490 - if (header_type & 0x80) /* Multi-function device */ 490 + if (header_type & PCI_HEADER_TYPE_MFD) 491 491 max_functions = 8; 492 492 else 493 493 max_functions = 1; 494 494 495 495 while (function < max_functions) { 496 - if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 496 + if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 497 497 /* Recurse the subordinate bus */ 498 498 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus); 499 499 ··· 571 571 /* Check for Bridge */ 572 572 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 573 573 574 - if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 574 + if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 575 575 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); 576 576 577 577 sub_bus = (int) secondary_bus; ··· 625 625 626 626 } /* End of base register loop */ 627 627 628 - } else if ((header_type & 0x7F) == 0x00) { 628 + } else if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_NORMAL) { 629 629 /* Figure out IO and memory base lengths */ 630 630 for (cloop = 0x10; cloop <= 0x24; cloop += 4) { 631 631 temp_register = 0xFFFFFFFF; ··· 723 723 /* Check for Bridge */ 724 724 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 725 725 726 - if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 726 + if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 727 727 /* Clear Bridge Control Register */ 728 728 command = 0x00; 729 729 pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command); ··· 858 858 } 859 859 } /* End of base register loop */ 860 860 /* Standard header */ 861 - } else if ((header_type & 0x7F) == 0x00) { 861 + } else if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_NORMAL) { 862 862 /* Figure out IO and memory base lengths */ 863 863 for (cloop = 0x10; cloop <= 0x24; cloop += 4) { 864 864 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base); ··· 975 975 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 976 976 977 977 /* If this is a bridge device, restore subordinate devices */ 978 - if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 978 + if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 979 979 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); 980 980 981 981 sub_bus = (int) secondary_bus; ··· 1067 1067 /* Check for Bridge */ 1068 1068 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 1069 1069 1070 - if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 1070 + if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 1071 1071 /* In order to continue checking, we must program the 1072 1072 * bus registers in the bridge to respond to accesses 1073 1073 * for its subordinate bus(es) ··· 1090 1090 1091 1091 } 1092 1092 /* Check to see if it is a standard config header */ 1093 - else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) { 1093 + else if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_NORMAL) { 1094 1094 /* Check subsystem vendor and ID */ 1095 1095 pci_bus_read_config_dword(pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register); 1096 1096
+3 -2
drivers/pci/hotplug/ibmphp.h
··· 17 17 */ 18 18 19 19 #include <linux/pci_hotplug.h> 20 + #include <linux/pci_regs.h> 20 21 21 22 extern int ibmphp_debug; 22 23 ··· 287 286 288 287 /* pci specific defines */ 289 288 #define PCI_VENDOR_ID_NOTVALID 0xFFFF 290 - #define PCI_HEADER_TYPE_MULTIDEVICE 0x80 291 - #define PCI_HEADER_TYPE_MULTIBRIDGE 0x81 289 + #define PCI_HEADER_TYPE_MULTIDEVICE (PCI_HEADER_TYPE_MFD|PCI_HEADER_TYPE_NORMAL) 290 + #define PCI_HEADER_TYPE_MULTIBRIDGE (PCI_HEADER_TYPE_MFD|PCI_HEADER_TYPE_BRIDGE) 292 291 293 292 #define LATENCY 0x64 294 293 #define CACHE 64
+1 -1
drivers/pci/hotplug/ibmphp_pci.c
··· 1087 1087 pci_bus_read_config_dword(ibmphp_pci_bus, devfn, PCI_CLASS_REVISION, &class); 1088 1088 1089 1089 debug("hdr_type behind the bridge is %x\n", hdr_type); 1090 - if ((hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { 1090 + if ((hdr_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 1091 1091 err("embedded bridges not supported for hot-plugging.\n"); 1092 1092 amount->not_correct = 1; 1093 1093 return amount;
+1 -1
drivers/pci/pci.c
··· 534 534 535 535 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 536 536 537 - pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); 537 + pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & PCI_HEADER_TYPE_MASK); 538 538 if (pos) 539 539 pos = __pci_find_next_cap(bus, devfn, pos, cap); 540 540
+3 -3
drivers/pci/quirks.c
··· 1844 1844 1845 1845 /* Update pdev accordingly */ 1846 1846 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1847 - pdev->hdr_type = hdr & 0x7f; 1848 - pdev->multifunction = !!(hdr & 0x80); 1847 + pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK; 1848 + pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr); 1849 1849 1850 1850 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1851 1851 pdev->class = class >> 8; ··· 5666 5666 5667 5667 /* The GPU becomes a multi-function device when the HDA is enabled */ 5668 5668 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5669 - gpu->multifunction = !!(hdr_type & 0x80); 5669 + gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type); 5670 5670 } 5671 5671 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5672 5672 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);