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ARM: dts: Document the CCI PMU DT bindings

The CCI PMU can profile bus transactions at the master and slave
interfaces of the CCI. The PMU can be used to observe an aggregated
view of the bus traffic between the various components connected to the
CCI.

Introduce a binding for the CCI PMU. The PMU node will be a sub-node of
the CCI node.

Cc: devicetree@vger.kernel.org
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

authored by

Punit Agrawal and committed by
Will Deacon
83bc10a2 fcb20f15

+47 -1
+47 -1
Documentation/devicetree/bindings/arm/cci.txt
··· 85 85 corresponding interface programming 86 86 registers. 87 87 88 + - CCI PMU node 89 + 90 + Parent node must be CCI interconnect node. 91 + 92 + A CCI pmu node must contain the following properties: 93 + 94 + - compatible 95 + Usage: required 96 + Value type: <string> 97 + Definition: must be "arm,cci-400-pmu" 98 + 99 + - reg: 100 + Usage: required 101 + Value type: Integer cells. A register entry, expressed 102 + as a pair of cells, containing base and 103 + size. 104 + Definition: the base address and size of the 105 + corresponding interface programming 106 + registers. 107 + 108 + - interrupts: 109 + Usage: required 110 + Value type: Integer cells. Array of interrupt specifier 111 + entries, as defined in 112 + ../interrupt-controller/interrupts.txt. 113 + Definition: list of counter overflow interrupts, one per 114 + counter. The interrupts must be specified 115 + starting with the cycle counter overflow 116 + interrupt, followed by counter0 overflow 117 + interrupt, counter1 overflow interrupt,... 118 + ,counterN overflow interrupt. 119 + 120 + The CCI PMU has an interrupt signal for each 121 + counter. The number of interrupts must be 122 + equal to the number of counters. 123 + 88 124 * CCI interconnect bus masters 89 125 90 126 Description: masters in the device tree connected to a CCI port ··· 186 150 #address-cells = <1>; 187 151 #size-cells = <1>; 188 152 reg = <0x0 0x2c090000 0 0x1000>; 189 - ranges = <0x0 0x0 0x2c090000 0x6000>; 153 + ranges = <0x0 0x0 0x2c090000 0x10000>; 190 154 191 155 cci_control0: slave-if@1000 { 192 156 compatible = "arm,cci-400-ctrl-if"; ··· 204 168 compatible = "arm,cci-400-ctrl-if"; 205 169 interface-type = "ace"; 206 170 reg = <0x5000 0x1000>; 171 + }; 172 + 173 + pmu@9000 { 174 + compatible = "arm,cci-400-pmu"; 175 + reg = <0x9000 0x5000>; 176 + interrupts = <0 101 4>, 177 + <0 102 4>, 178 + <0 103 4>, 179 + <0 104 4>, 180 + <0 105 4>; 207 181 }; 208 182 }; 209 183