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Merge branch 'Rework-mt762x-GDM-setup-flow'

MarkLee says:

====================
Rework mt762x GDM setup flow

The mt762x GDM block is mainly used to setup the HW internal
rx path from GMAC to RX DMA engine(PDMA) and the packet
switching engine(PSE) is responsed to do the data forward
following the GDM configuration.

This patch set have three goals :

1. Integrate GDM/PSE setup operations into single function "mtk_gdm_config"

2. Refine the timing of GDM/PSE setup, move it from mtk_hw_init
to mtk_open

3. Enable GDM GDMA_DROP_ALL mode to drop all packet during the
stop operation
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

David S. Miller 839554b7 abfb228a

+31 -15
+29 -15
drivers/net/ethernet/mediatek/mtk_eth_soc.c
··· 2180 2180 return 0; 2181 2181 } 2182 2182 2183 + static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 2184 + { 2185 + int i; 2186 + 2187 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2188 + return; 2189 + 2190 + for (i = 0; i < MTK_MAC_COUNT; i++) { 2191 + u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 2192 + 2193 + /* default setup the forward port to send frame to PDMA */ 2194 + val &= ~0xffff; 2195 + 2196 + /* Enable RX checksum */ 2197 + val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2198 + 2199 + val |= config; 2200 + 2201 + mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2202 + } 2203 + /* Reset and enable PSE */ 2204 + mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 2205 + mtk_w32(eth, 0, MTK_RST_GL); 2206 + } 2207 + 2183 2208 static int mtk_open(struct net_device *dev) 2184 2209 { 2185 2210 struct mtk_mac *mac = netdev_priv(dev); ··· 2224 2199 2225 2200 if (err) 2226 2201 return err; 2202 + 2203 + mtk_gdm_config(eth, MTK_GDMA_TO_PDMA); 2227 2204 2228 2205 napi_enable(&eth->tx_napi); 2229 2206 napi_enable(&eth->rx_napi); ··· 2278 2251 /* only shutdown DMA if this is the last user */ 2279 2252 if (!refcount_dec_and_test(&eth->dma_refcnt)) 2280 2253 return 0; 2254 + 2255 + mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 2281 2256 2282 2257 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2283 2258 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); ··· 2404 2375 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 2405 2376 mtk_tx_irq_disable(eth, ~0); 2406 2377 mtk_rx_irq_disable(eth, ~0); 2407 - mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 2408 - mtk_w32(eth, 0, MTK_RST_GL); 2409 2378 2410 2379 /* FE int grouping */ 2411 2380 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); ··· 2411 2384 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 2412 2385 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 2413 2386 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 2414 - 2415 - for (i = 0; i < MTK_MAC_COUNT; i++) { 2416 - u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 2417 - 2418 - /* setup the forward port to send frame to PDMA */ 2419 - val &= ~0xffff; 2420 - 2421 - /* Enable RX checksum */ 2422 - val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2423 - 2424 - /* setup the mac dma */ 2425 - mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2426 - } 2427 2387 2428 2388 return 0; 2429 2389
+2
drivers/net/ethernet/mediatek/mtk_eth_soc.h
··· 84 84 #define MTK_GDMA_ICS_EN BIT(22) 85 85 #define MTK_GDMA_TCS_EN BIT(21) 86 86 #define MTK_GDMA_UCS_EN BIT(20) 87 + #define MTK_GDMA_TO_PDMA 0x0 88 + #define MTK_GDMA_DROP_ALL 0x7777 87 89 88 90 /* Unicast Filter MAC Address Register - Low */ 89 91 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))