drm: Remove the obsolete driver-via · tjh.dev/kernel@8391e00

-7

drivers/gpu/drm/Kconfig

··· 398 398 399 399 if DRM_LEGACY 400 400 401 - config DRM_VIA 402 - tristate "Via unichrome video cards" 403 - depends on DRM && PCI 404 - help 405 - Choose this option if you have a Via unichrome or compatible video 406 - chipset. If M is selected the module will be called via. 407 - 408 401 endif # DRM_LEGACY 409 402 410 403 config DRM_EXPORT_FOR_TESTS

-1

drivers/gpu/drm/Makefile

··· 141 141 obj-$(CONFIG_DRM_V3D) += v3d/ 142 142 obj-$(CONFIG_DRM_VC4) += vc4/ 143 143 obj-$(CONFIG_DRM_VMWGFX)+= vmwgfx/ 144 - obj-$(CONFIG_DRM_VIA) +=via/ 145 144 obj-$(CONFIG_DRM_VGEM) += vgem/ 146 145 obj-$(CONFIG_DRM_VKMS) += vkms/ 147 146 obj-$(CONFIG_DRM_NOUVEAU) +=nouveau/

-8

drivers/gpu/drm/via/Makefile

··· 1 - # SPDX-License-Identifier: GPL-2.0-only 2 - # 3 - # Makefile for the drm device driver. This driver provides support for the 4 - # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. 5 - 6 - via-y := via_dri1.o 7 - 8 - obj-$(CONFIG_DRM_VIA) +=via.o

-1771

drivers/gpu/drm/via/via_3d_reg.h

··· 1 - /* SPDX-License-Identifier: MIT */ 2 - /* 3 - * Copyright 1998-2011 VIA Technologies, Inc. All Rights Reserved. 4 - * Copyright 2001-2011 S3 Graphics, Inc. All Rights Reserved. 5 - */ 6 - 7 - #ifndef VIA_3D_REG_H 8 - #define VIA_3D_REG_H 9 - #define HC_REG_BASE 0x0400 10 - 11 - #define HC_REG_TRANS_SPACE 0x0040 12 - 13 - #define HC_ParaN_MASK 0xffffffff 14 - #define HC_Para_MASK 0x00ffffff 15 - #define HC_SubA_MASK 0xff000000 16 - #define HC_SubA_SHIFT 24 17 - /* Transmission Setting 18 - */ 19 - #define HC_REG_TRANS_SET 0x003c 20 - #define HC_ParaSubType_MASK 0xff000000 21 - #define HC_ParaType_MASK 0x00ff0000 22 - #define HC_ParaOS_MASK 0x0000ff00 23 - #define HC_ParaAdr_MASK 0x000000ff 24 - #define HC_ParaSubType_SHIFT 24 25 - #define HC_ParaType_SHIFT 16 26 - #define HC_ParaOS_SHIFT 8 27 - #define HC_ParaAdr_SHIFT 0 28 - 29 - #define HC_ParaType_CmdVdata 0x0000 30 - #define HC_ParaType_NotTex 0x0001 31 - #define HC_ParaType_Tex 0x0002 32 - #define HC_ParaType_Palette 0x0003 33 - #define HC_ParaType_PreCR 0x0010 34 - #define HC_ParaType_Auto 0x00fe 35 - #define INV_ParaType_Dummy 0x00300000 36 - 37 - /* Transmission Space 38 - */ 39 - #define HC_REG_Hpara0 0x0040 40 - #define HC_REG_HpataAF 0x02fc 41 - 42 - /* Read 43 - */ 44 - #define HC_REG_HREngSt 0x0000 45 - #define HC_REG_HRFIFOempty 0x0004 46 - #define HC_REG_HRFIFOfull 0x0008 47 - #define HC_REG_HRErr 0x000c 48 - #define HC_REG_FIFOstatus 0x0010 49 - /* HC_REG_HREngSt 0x0000 50 - */ 51 - #define HC_HDASZC_MASK 0x00010000 52 - #define HC_HSGEMI_MASK 0x0000f000 53 - #define HC_HLGEMISt_MASK 0x00000f00 54 - #define HC_HCRSt_MASK 0x00000080 55 - #define HC_HSE0St_MASK 0x00000040 56 - #define HC_HSE1St_MASK 0x00000020 57 - #define HC_HPESt_MASK 0x00000010 58 - #define HC_HXESt_MASK 0x00000008 59 - #define HC_HBESt_MASK 0x00000004 60 - #define HC_HE2St_MASK 0x00000002 61 - #define HC_HE3St_MASK 0x00000001 62 - /* HC_REG_HRFIFOempty 0x0004 63 - */ 64 - #define HC_HRZDempty_MASK 0x00000010 65 - #define HC_HRTXAempty_MASK 0x00000008 66 - #define HC_HRTXDempty_MASK 0x00000004 67 - #define HC_HWZDempty_MASK 0x00000002 68 - #define HC_HWCDempty_MASK 0x00000001 69 - /* HC_REG_HRFIFOfull 0x0008 70 - */ 71 - #define HC_HRZDfull_MASK 0x00000010 72 - #define HC_HRTXAfull_MASK 0x00000008 73 - #define HC_HRTXDfull_MASK 0x00000004 74 - #define HC_HWZDfull_MASK 0x00000002 75 - #define HC_HWCDfull_MASK 0x00000001 76 - /* HC_REG_HRErr 0x000c 77 - */ 78 - #define HC_HAGPCMErr_MASK 0x80000000 79 - #define HC_HAGPCMErrC_MASK 0x70000000 80 - /* HC_REG_FIFOstatus 0x0010 81 - */ 82 - #define HC_HRFIFOATall_MASK 0x80000000 83 - #define HC_HRFIFOATbusy_MASK 0x40000000 84 - #define HC_HRATFGMDo_MASK 0x00000100 85 - #define HC_HRATFGMDi_MASK 0x00000080 86 - #define HC_HRATFRZD_MASK 0x00000040 87 - #define HC_HRATFRTXA_MASK 0x00000020 88 - #define HC_HRATFRTXD_MASK 0x00000010 89 - #define HC_HRATFWZD_MASK 0x00000008 90 - #define HC_HRATFWCD_MASK 0x00000004 91 - #define HC_HRATTXTAG_MASK 0x00000002 92 - #define HC_HRATTXCH_MASK 0x00000001 93 - 94 - /* AGP Command Setting 95 - */ 96 - #define HC_SubA_HAGPBstL 0x0060 97 - #define HC_SubA_HAGPBendL 0x0061 98 - #define HC_SubA_HAGPCMNT 0x0062 99 - #define HC_SubA_HAGPBpL 0x0063 100 - #define HC_SubA_HAGPBpH 0x0064 101 - /* HC_SubA_HAGPCMNT 0x0062 102 - */ 103 - #define HC_HAGPCMNT_MASK 0x00800000 104 - #define HC_HCmdErrClr_MASK 0x00400000 105 - #define HC_HAGPBendH_MASK 0x0000ff00 106 - #define HC_HAGPBstH_MASK 0x000000ff 107 - #define HC_HAGPBendH_SHIFT 8 108 - #define HC_HAGPBstH_SHIFT 0 109 - /* HC_SubA_HAGPBpL 0x0063 110 - */ 111 - #define HC_HAGPBpL_MASK 0x00fffffc 112 - #define HC_HAGPBpID_MASK 0x00000003 113 - #define HC_HAGPBpID_PAUSE 0x00000000 114 - #define HC_HAGPBpID_JUMP 0x00000001 115 - #define HC_HAGPBpID_STOP 0x00000002 116 - /* HC_SubA_HAGPBpH 0x0064 117 - */ 118 - #define HC_HAGPBpH_MASK 0x00ffffff 119 - 120 - /* Miscellaneous Settings 121 - */ 122 - #define HC_SubA_HClipTB 0x0070 123 - #define HC_SubA_HClipLR 0x0071 124 - #define HC_SubA_HFPClipTL 0x0072 125 - #define HC_SubA_HFPClipBL 0x0073 126 - #define HC_SubA_HFPClipLL 0x0074 127 - #define HC_SubA_HFPClipRL 0x0075 128 - #define HC_SubA_HFPClipTBH 0x0076 129 - #define HC_SubA_HFPClipLRH 0x0077 130 - #define HC_SubA_HLP 0x0078 131 - #define HC_SubA_HLPRF 0x0079 132 - #define HC_SubA_HSolidCL 0x007a 133 - #define HC_SubA_HPixGC 0x007b 134 - #define HC_SubA_HSPXYOS 0x007c 135 - #define HC_SubA_HVertexCNT 0x007d 136 - 137 - #define HC_HClipT_MASK 0x00fff000 138 - #define HC_HClipT_SHIFT 12 139 - #define HC_HClipB_MASK 0x00000fff 140 - #define HC_HClipB_SHIFT 0 141 - #define HC_HClipL_MASK 0x00fff000 142 - #define HC_HClipL_SHIFT 12 143 - #define HC_HClipR_MASK 0x00000fff 144 - #define HC_HClipR_SHIFT 0 145 - #define HC_HFPClipBH_MASK 0x0000ff00 146 - #define HC_HFPClipBH_SHIFT 8 147 - #define HC_HFPClipTH_MASK 0x000000ff 148 - #define HC_HFPClipTH_SHIFT 0 149 - #define HC_HFPClipRH_MASK 0x0000ff00 150 - #define HC_HFPClipRH_SHIFT 8 151 - #define HC_HFPClipLH_MASK 0x000000ff 152 - #define HC_HFPClipLH_SHIFT 0 153 - #define HC_HSolidCH_MASK 0x000000ff 154 - #define HC_HPixGC_MASK 0x00800000 155 - #define HC_HSPXOS_MASK 0x00fff000 156 - #define HC_HSPXOS_SHIFT 12 157 - #define HC_HSPYOS_MASK 0x00000fff 158 - 159 - /* 160 - * Command A 161 - */ 162 - #define HC_HCmdHeader_MASK 0xfe000000 /*0xffe00000 */ 163 - #define HC_HE3Fire_MASK 0x00100000 164 - #define HC_HPMType_MASK 0x000f0000 165 - #define HC_HEFlag_MASK 0x0000e000 166 - #define HC_HShading_MASK 0x00001c00 167 - #define HC_HPMValidN_MASK 0x00000200 168 - #define HC_HPLEND_MASK 0x00000100 169 - #define HC_HVCycle_MASK 0x000000ff 170 - #define HC_HVCycle_Style_MASK 0x000000c0 171 - #define HC_HVCycle_ChgA_MASK 0x00000030 172 - #define HC_HVCycle_ChgB_MASK 0x0000000c 173 - #define HC_HVCycle_ChgC_MASK 0x00000003 174 - #define HC_HPMType_Point 0x00000000 175 - #define HC_HPMType_Line 0x00010000 176 - #define HC_HPMType_Tri 0x00020000 177 - #define HC_HPMType_TriWF 0x00040000 178 - #define HC_HEFlag_NoAA 0x00000000 179 - #define HC_HEFlag_ab 0x00008000 180 - #define HC_HEFlag_bc 0x00004000 181 - #define HC_HEFlag_ca 0x00002000 182 - #define HC_HShading_Solid 0x00000000 183 - #define HC_HShading_FlatA 0x00000400 184 - #define HC_HShading_FlatB 0x00000800 185 - #define HC_HShading_FlatC 0x00000c00 186 - #define HC_HShading_Gouraud 0x00001000 187 - #define HC_HVCycle_Full 0x00000000 188 - #define HC_HVCycle_AFP 0x00000040 189 - #define HC_HVCycle_One 0x000000c0 190 - #define HC_HVCycle_NewA 0x00000000 191 - #define HC_HVCycle_AA 0x00000010 192 - #define HC_HVCycle_AB 0x00000020 193 - #define HC_HVCycle_AC 0x00000030 194 - #define HC_HVCycle_NewB 0x00000000 195 - #define HC_HVCycle_BA 0x00000004 196 - #define HC_HVCycle_BB 0x00000008 197 - #define HC_HVCycle_BC 0x0000000c 198 - #define HC_HVCycle_NewC 0x00000000 199 - #define HC_HVCycle_CA 0x00000001 200 - #define HC_HVCycle_CB 0x00000002 201 - #define HC_HVCycle_CC 0x00000003 202 - 203 - /* Command B 204 - */ 205 - #define HC_HLPrst_MASK 0x00010000 206 - #define HC_HLLastP_MASK 0x00008000 207 - #define HC_HVPMSK_MASK 0x00007f80 208 - #define HC_HBFace_MASK 0x00000040 209 - #define HC_H2nd1VT_MASK 0x0000003f 210 - #define HC_HVPMSK_X 0x00004000 211 - #define HC_HVPMSK_Y 0x00002000 212 - #define HC_HVPMSK_Z 0x00001000 213 - #define HC_HVPMSK_W 0x00000800 214 - #define HC_HVPMSK_Cd 0x00000400 215 - #define HC_HVPMSK_Cs 0x00000200 216 - #define HC_HVPMSK_S 0x00000100 217 - #define HC_HVPMSK_T 0x00000080 218 - 219 - /* Enable Setting 220 - */ 221 - #define HC_SubA_HEnable 0x0000 222 - #define HC_HenForce1P_MASK 0x00800000 /* [Force 1 Pipe] */ 223 - #define HC_HenZDCheck_MASK 0x00400000 /* [Z dirty bit settings] */ 224 - #define HC_HenTXEnvMap_MASK 0x00200000 225 - #define HC_HenVertexCNT_MASK 0x00100000 226 - #define HC_HenCPUDAZ_MASK 0x00080000 227 - #define HC_HenDASZWC_MASK 0x00040000 228 - #define HC_HenFBCull_MASK 0x00020000 229 - #define HC_HenCW_MASK 0x00010000 230 - #define HC_HenAA_MASK 0x00008000 231 - #define HC_HenST_MASK 0x00004000 232 - #define HC_HenZT_MASK 0x00002000 233 - #define HC_HenZW_MASK 0x00001000 234 - #define HC_HenAT_MASK 0x00000800 235 - #define HC_HenAW_MASK 0x00000400 236 - #define HC_HenSP_MASK 0x00000200 237 - #define HC_HenLP_MASK 0x00000100 238 - #define HC_HenTXCH_MASK 0x00000080 239 - #define HC_HenTXMP_MASK 0x00000040 240 - #define HC_HenTXPP_MASK 0x00000020 241 - #define HC_HenTXTR_MASK 0x00000010 242 - #define HC_HenCS_MASK 0x00000008 243 - #define HC_HenFOG_MASK 0x00000004 244 - #define HC_HenABL_MASK 0x00000002 245 - #define HC_HenDT_MASK 0x00000001 246 - 247 - /* Z Setting 248 - */ 249 - #define HC_SubA_HZWBBasL 0x0010 250 - #define HC_SubA_HZWBBasH 0x0011 251 - #define HC_SubA_HZWBType 0x0012 252 - #define HC_SubA_HZBiasL 0x0013 253 - #define HC_SubA_HZWBend 0x0014 254 - #define HC_SubA_HZWTMD 0x0015 255 - #define HC_SubA_HZWCDL 0x0016 256 - #define HC_SubA_HZWCTAGnum 0x0017 257 - #define HC_SubA_HZCYNum 0x0018 258 - #define HC_SubA_HZWCFire 0x0019 259 - /* HC_SubA_HZWBType 260 - */ 261 - #define HC_HZWBType_MASK 0x00800000 262 - #define HC_HZBiasedWB_MASK 0x00400000 263 - #define HC_HZONEasFF_MASK 0x00200000 264 - #define HC_HZOONEasFF_MASK 0x00100000 265 - #define HC_HZWBFM_MASK 0x00030000 266 - #define HC_HZWBLoc_MASK 0x0000c000 267 - #define HC_HZWBPit_MASK 0x00003fff 268 - #define HC_HZWBFM_16 0x00000000 269 - #define HC_HZWBFM_32 0x00020000 270 - #define HC_HZWBFM_24 0x00030000 271 - #define HC_HZWBLoc_Local 0x00000000 272 - #define HC_HZWBLoc_SyS 0x00004000 273 - /* HC_SubA_HZWBend 274 - */ 275 - #define HC_HZWBend_MASK 0x00ffe000 276 - #define HC_HZBiasH_MASK 0x000000ff 277 - #define HC_HZWBend_SHIFT 10 278 - /* HC_SubA_HZWTMD 279 - */ 280 - #define HC_HZWTMD_MASK 0x00070000 281 - #define HC_HEBEBias_MASK 0x00007f00 282 - #define HC_HZNF_MASK 0x000000ff 283 - #define HC_HZWTMD_NeverPass 0x00000000 284 - #define HC_HZWTMD_LT 0x00010000 285 - #define HC_HZWTMD_EQ 0x00020000 286 - #define HC_HZWTMD_LE 0x00030000 287 - #define HC_HZWTMD_GT 0x00040000 288 - #define HC_HZWTMD_NE 0x00050000 289 - #define HC_HZWTMD_GE 0x00060000 290 - #define HC_HZWTMD_AllPass 0x00070000 291 - #define HC_HEBEBias_SHIFT 8 292 - /* HC_SubA_HZWCDL 0x0016 293 - */ 294 - #define HC_HZWCDL_MASK 0x00ffffff 295 - /* HC_SubA_HZWCTAGnum 0x0017 296 - */ 297 - #define HC_HZWCTAGnum_MASK 0x00ff0000 298 - #define HC_HZWCTAGnum_SHIFT 16 299 - #define HC_HZWCDH_MASK 0x000000ff 300 - #define HC_HZWCDH_SHIFT 0 301 - /* HC_SubA_HZCYNum 0x0018 302 - */ 303 - #define HC_HZCYNum_MASK 0x00030000 304 - #define HC_HZCYNum_SHIFT 16 305 - #define HC_HZWCQWnum_MASK 0x00003fff 306 - #define HC_HZWCQWnum_SHIFT 0 307 - /* HC_SubA_HZWCFire 0x0019 308 - */ 309 - #define HC_ZWCFire_MASK 0x00010000 310 - #define HC_HZWCQWnumLast_MASK 0x00003fff 311 - #define HC_HZWCQWnumLast_SHIFT 0 312 - 313 - /* Stencil Setting 314 - */ 315 - #define HC_SubA_HSTREF 0x0023 316 - #define HC_SubA_HSTMD 0x0024 317 - /* HC_SubA_HSBFM 318 - */ 319 - #define HC_HSBFM_MASK 0x00030000 320 - #define HC_HSBLoc_MASK 0x0000c000 321 - #define HC_HSBPit_MASK 0x00003fff 322 - /* HC_SubA_HSTREF 323 - */ 324 - #define HC_HSTREF_MASK 0x00ff0000 325 - #define HC_HSTOPMSK_MASK 0x0000ff00 326 - #define HC_HSTBMSK_MASK 0x000000ff 327 - #define HC_HSTREF_SHIFT 16 328 - #define HC_HSTOPMSK_SHIFT 8 329 - /* HC_SubA_HSTMD 330 - */ 331 - #define HC_HSTMD_MASK 0x00070000 332 - #define HC_HSTOPSF_MASK 0x000001c0 333 - #define HC_HSTOPSPZF_MASK 0x00000038 334 - #define HC_HSTOPSPZP_MASK 0x00000007 335 - #define HC_HSTMD_NeverPass 0x00000000 336 - #define HC_HSTMD_LT 0x00010000 337 - #define HC_HSTMD_EQ 0x00020000 338 - #define HC_HSTMD_LE 0x00030000 339 - #define HC_HSTMD_GT 0x00040000 340 - #define HC_HSTMD_NE 0x00050000 341 - #define HC_HSTMD_GE 0x00060000 342 - #define HC_HSTMD_AllPass 0x00070000 343 - #define HC_HSTOPSF_KEEP 0x00000000 344 - #define HC_HSTOPSF_ZERO 0x00000040 345 - #define HC_HSTOPSF_REPLACE 0x00000080 346 - #define HC_HSTOPSF_INCRSAT 0x000000c0 347 - #define HC_HSTOPSF_DECRSAT 0x00000100 348 - #define HC_HSTOPSF_INVERT 0x00000140 349 - #define HC_HSTOPSF_INCR 0x00000180 350 - #define HC_HSTOPSF_DECR 0x000001c0 351 - #define HC_HSTOPSPZF_KEEP 0x00000000 352 - #define HC_HSTOPSPZF_ZERO 0x00000008 353 - #define HC_HSTOPSPZF_REPLACE 0x00000010 354 - #define HC_HSTOPSPZF_INCRSAT 0x00000018 355 - #define HC_HSTOPSPZF_DECRSAT 0x00000020 356 - #define HC_HSTOPSPZF_INVERT 0x00000028 357 - #define HC_HSTOPSPZF_INCR 0x00000030 358 - #define HC_HSTOPSPZF_DECR 0x00000038 359 - #define HC_HSTOPSPZP_KEEP 0x00000000 360 - #define HC_HSTOPSPZP_ZERO 0x00000001 361 - #define HC_HSTOPSPZP_REPLACE 0x00000002 362 - #define HC_HSTOPSPZP_INCRSAT 0x00000003 363 - #define HC_HSTOPSPZP_DECRSAT 0x00000004 364 - #define HC_HSTOPSPZP_INVERT 0x00000005 365 - #define HC_HSTOPSPZP_INCR 0x00000006 366 - #define HC_HSTOPSPZP_DECR 0x00000007 367 - 368 - /* Alpha Setting 369 - */ 370 - #define HC_SubA_HABBasL 0x0030 371 - #define HC_SubA_HABBasH 0x0031 372 - #define HC_SubA_HABFM 0x0032 373 - #define HC_SubA_HATMD 0x0033 374 - #define HC_SubA_HABLCsat 0x0034 375 - #define HC_SubA_HABLCop 0x0035 376 - #define HC_SubA_HABLAsat 0x0036 377 - #define HC_SubA_HABLAop 0x0037 378 - #define HC_SubA_HABLRCa 0x0038 379 - #define HC_SubA_HABLRFCa 0x0039 380 - #define HC_SubA_HABLRCbias 0x003a 381 - #define HC_SubA_HABLRCb 0x003b 382 - #define HC_SubA_HABLRFCb 0x003c 383 - #define HC_SubA_HABLRAa 0x003d 384 - #define HC_SubA_HABLRAb 0x003e 385 - /* HC_SubA_HABFM 386 - */ 387 - #define HC_HABFM_MASK 0x00030000 388 - #define HC_HABLoc_MASK 0x0000c000 389 - #define HC_HABPit_MASK 0x000007ff 390 - /* HC_SubA_HATMD 391 - */ 392 - #define HC_HATMD_MASK 0x00000700 393 - #define HC_HATREF_MASK 0x000000ff 394 - #define HC_HATMD_NeverPass 0x00000000 395 - #define HC_HATMD_LT 0x00000100 396 - #define HC_HATMD_EQ 0x00000200 397 - #define HC_HATMD_LE 0x00000300 398 - #define HC_HATMD_GT 0x00000400 399 - #define HC_HATMD_NE 0x00000500 400 - #define HC_HATMD_GE 0x00000600 401 - #define HC_HATMD_AllPass 0x00000700 402 - /* HC_SubA_HABLCsat 403 - */ 404 - #define HC_HABLCsat_MASK 0x00010000 405 - #define HC_HABLCa_MASK 0x0000fc00 406 - #define HC_HABLCa_C_MASK 0x0000c000 407 - #define HC_HABLCa_OPC_MASK 0x00003c00 408 - #define HC_HABLFCa_MASK 0x000003f0 409 - #define HC_HABLFCa_C_MASK 0x00000300 410 - #define HC_HABLFCa_OPC_MASK 0x000000f0 411 - #define HC_HABLCbias_MASK 0x0000000f 412 - #define HC_HABLCbias_C_MASK 0x00000008 413 - #define HC_HABLCbias_OPC_MASK 0x00000007 414 - /*-- Define the input color. 415 - */ 416 - #define HC_XC_Csrc 0x00000000 417 - #define HC_XC_Cdst 0x00000001 418 - #define HC_XC_Asrc 0x00000002 419 - #define HC_XC_Adst 0x00000003 420 - #define HC_XC_Fog 0x00000004 421 - #define HC_XC_HABLRC 0x00000005 422 - #define HC_XC_minSrcDst 0x00000006 423 - #define HC_XC_maxSrcDst 0x00000007 424 - #define HC_XC_mimAsrcInvAdst 0x00000008 425 - #define HC_XC_OPC 0x00000000 426 - #define HC_XC_InvOPC 0x00000010 427 - #define HC_XC_OPCp5 0x00000020 428 - /*-- Define the input Alpha 429 - */ 430 - #define HC_XA_OPA 0x00000000 431 - #define HC_XA_InvOPA 0x00000010 432 - #define HC_XA_OPAp5 0x00000020 433 - #define HC_XA_0 0x00000000 434 - #define HC_XA_Asrc 0x00000001 435 - #define HC_XA_Adst 0x00000002 436 - #define HC_XA_Fog 0x00000003 437 - #define HC_XA_minAsrcFog 0x00000004 438 - #define HC_XA_minAsrcAdst 0x00000005 439 - #define HC_XA_maxAsrcFog 0x00000006 440 - #define HC_XA_maxAsrcAdst 0x00000007 441 - #define HC_XA_HABLRA 0x00000008 442 - #define HC_XA_minAsrcInvAdst 0x00000008 443 - #define HC_XA_HABLFRA 0x00000009 444 - /*-- 445 - */ 446 - #define HC_HABLCa_OPC (HC_XC_OPC << 10) 447 - #define HC_HABLCa_InvOPC (HC_XC_InvOPC << 10) 448 - #define HC_HABLCa_OPCp5 (HC_XC_OPCp5 << 10) 449 - #define HC_HABLCa_Csrc (HC_XC_Csrc << 10) 450 - #define HC_HABLCa_Cdst (HC_XC_Cdst << 10) 451 - #define HC_HABLCa_Asrc (HC_XC_Asrc << 10) 452 - #define HC_HABLCa_Adst (HC_XC_Adst << 10) 453 - #define HC_HABLCa_Fog (HC_XC_Fog << 10) 454 - #define HC_HABLCa_HABLRCa (HC_XC_HABLRC << 10) 455 - #define HC_HABLCa_minSrcDst (HC_XC_minSrcDst << 10) 456 - #define HC_HABLCa_maxSrcDst (HC_XC_maxSrcDst << 10) 457 - #define HC_HABLFCa_OPC (HC_XC_OPC << 4) 458 - #define HC_HABLFCa_InvOPC (HC_XC_InvOPC << 4) 459 - #define HC_HABLFCa_OPCp5 (HC_XC_OPCp5 << 4) 460 - #define HC_HABLFCa_Csrc (HC_XC_Csrc << 4) 461 - #define HC_HABLFCa_Cdst (HC_XC_Cdst << 4) 462 - #define HC_HABLFCa_Asrc (HC_XC_Asrc << 4) 463 - #define HC_HABLFCa_Adst (HC_XC_Adst << 4) 464 - #define HC_HABLFCa_Fog (HC_XC_Fog << 4) 465 - #define HC_HABLFCa_HABLRCa (HC_XC_HABLRC << 4) 466 - #define HC_HABLFCa_minSrcDst (HC_XC_minSrcDst << 4) 467 - #define HC_HABLFCa_maxSrcDst (HC_XC_maxSrcDst << 4) 468 - #define HC_HABLFCa_mimAsrcInvAdst (HC_XC_mimAsrcInvAdst << 4) 469 - #define HC_HABLCbias_HABLRCbias 0x00000000 470 - #define HC_HABLCbias_Asrc 0x00000001 471 - #define HC_HABLCbias_Adst 0x00000002 472 - #define HC_HABLCbias_Fog 0x00000003 473 - #define HC_HABLCbias_Cin 0x00000004 474 - /* HC_SubA_HABLCop 0x0035 475 - */ 476 - #define HC_HABLdot_MASK 0x00010000 477 - #define HC_HABLCop_MASK 0x00004000 478 - #define HC_HABLCb_MASK 0x00003f00 479 - #define HC_HABLCb_C_MASK 0x00003000 480 - #define HC_HABLCb_OPC_MASK 0x00000f00 481 - #define HC_HABLFCb_MASK 0x000000fc 482 - #define HC_HABLFCb_C_MASK 0x000000c0 483 - #define HC_HABLFCb_OPC_MASK 0x0000003c 484 - #define HC_HABLCshift_MASK 0x00000003 485 - #define HC_HABLCb_OPC (HC_XC_OPC << 8) 486 - #define HC_HABLCb_InvOPC (HC_XC_InvOPC << 8) 487 - #define HC_HABLCb_OPCp5 (HC_XC_OPCp5 << 8) 488 - #define HC_HABLCb_Csrc (HC_XC_Csrc << 8) 489 - #define HC_HABLCb_Cdst (HC_XC_Cdst << 8) 490 - #define HC_HABLCb_Asrc (HC_XC_Asrc << 8) 491 - #define HC_HABLCb_Adst (HC_XC_Adst << 8) 492 - #define HC_HABLCb_Fog (HC_XC_Fog << 8) 493 - #define HC_HABLCb_HABLRCa (HC_XC_HABLRC << 8) 494 - #define HC_HABLCb_minSrcDst (HC_XC_minSrcDst << 8) 495 - #define HC_HABLCb_maxSrcDst (HC_XC_maxSrcDst << 8) 496 - #define HC_HABLFCb_OPC (HC_XC_OPC << 2) 497 - #define HC_HABLFCb_InvOPC (HC_XC_InvOPC << 2) 498 - #define HC_HABLFCb_OPCp5 (HC_XC_OPCp5 << 2) 499 - #define HC_HABLFCb_Csrc (HC_XC_Csrc << 2) 500 - #define HC_HABLFCb_Cdst (HC_XC_Cdst << 2) 501 - #define HC_HABLFCb_Asrc (HC_XC_Asrc << 2) 502 - #define HC_HABLFCb_Adst (HC_XC_Adst << 2) 503 - #define HC_HABLFCb_Fog (HC_XC_Fog << 2) 504 - #define HC_HABLFCb_HABLRCb (HC_XC_HABLRC << 2) 505 - #define HC_HABLFCb_minSrcDst (HC_XC_minSrcDst << 2) 506 - #define HC_HABLFCb_maxSrcDst (HC_XC_maxSrcDst << 2) 507 - #define HC_HABLFCb_mimAsrcInvAdst (HC_XC_mimAsrcInvAdst << 2) 508 - /* HC_SubA_HABLAsat 0x0036 509 - */ 510 - #define HC_HABLAsat_MASK 0x00010000 511 - #define HC_HABLAa_MASK 0x0000fc00 512 - #define HC_HABLAa_A_MASK 0x0000c000 513 - #define HC_HABLAa_OPA_MASK 0x00003c00 514 - #define HC_HABLFAa_MASK 0x000003f0 515 - #define HC_HABLFAa_A_MASK 0x00000300 516 - #define HC_HABLFAa_OPA_MASK 0x000000f0 517 - #define HC_HABLAbias_MASK 0x0000000f 518 - #define HC_HABLAbias_A_MASK 0x00000008 519 - #define HC_HABLAbias_OPA_MASK 0x00000007 520 - #define HC_HABLAa_OPA (HC_XA_OPA << 10) 521 - #define HC_HABLAa_InvOPA (HC_XA_InvOPA << 10) 522 - #define HC_HABLAa_OPAp5 (HC_XA_OPAp5 << 10) 523 - #define HC_HABLAa_0 (HC_XA_0 << 10) 524 - #define HC_HABLAa_Asrc (HC_XA_Asrc << 10) 525 - #define HC_HABLAa_Adst (HC_XA_Adst << 10) 526 - #define HC_HABLAa_Fog (HC_XA_Fog << 10) 527 - #define HC_HABLAa_minAsrcFog (HC_XA_minAsrcFog << 10) 528 - #define HC_HABLAa_minAsrcAdst (HC_XA_minAsrcAdst << 10) 529 - #define HC_HABLAa_maxAsrcFog (HC_XA_maxAsrcFog << 10) 530 - #define HC_HABLAa_maxAsrcAdst (HC_XA_maxAsrcAdst << 10) 531 - #define HC_HABLAa_HABLRA (HC_XA_HABLRA << 10) 532 - #define HC_HABLFAa_OPA (HC_XA_OPA << 4) 533 - #define HC_HABLFAa_InvOPA (HC_XA_InvOPA << 4) 534 - #define HC_HABLFAa_OPAp5 (HC_XA_OPAp5 << 4) 535 - #define HC_HABLFAa_0 (HC_XA_0 << 4) 536 - #define HC_HABLFAa_Asrc (HC_XA_Asrc << 4) 537 - #define HC_HABLFAa_Adst (HC_XA_Adst << 4) 538 - #define HC_HABLFAa_Fog (HC_XA_Fog << 4) 539 - #define HC_HABLFAa_minAsrcFog (HC_XA_minAsrcFog << 4) 540 - #define HC_HABLFAa_minAsrcAdst (HC_XA_minAsrcAdst << 4) 541 - #define HC_HABLFAa_maxAsrcFog (HC_XA_maxAsrcFog << 4) 542 - #define HC_HABLFAa_maxAsrcAdst (HC_XA_maxAsrcAdst << 4) 543 - #define HC_HABLFAa_minAsrcInvAdst (HC_XA_minAsrcInvAdst << 4) 544 - #define HC_HABLFAa_HABLFRA (HC_XA_HABLFRA << 4) 545 - #define HC_HABLAbias_HABLRAbias 0x00000000 546 - #define HC_HABLAbias_Asrc 0x00000001 547 - #define HC_HABLAbias_Adst 0x00000002 548 - #define HC_HABLAbias_Fog 0x00000003 549 - #define HC_HABLAbias_Aaa 0x00000004 550 - /* HC_SubA_HABLAop 0x0037 551 - */ 552 - #define HC_HABLAop_MASK 0x00004000 553 - #define HC_HABLAb_MASK 0x00003f00 554 - #define HC_HABLAb_OPA_MASK 0x00000f00 555 - #define HC_HABLFAb_MASK 0x000000fc 556 - #define HC_HABLFAb_OPA_MASK 0x0000003c 557 - #define HC_HABLAshift_MASK 0x00000003 558 - #define HC_HABLAb_OPA (HC_XA_OPA << 8) 559 - #define HC_HABLAb_InvOPA (HC_XA_InvOPA << 8) 560 - #define HC_HABLAb_OPAp5 (HC_XA_OPAp5 << 8) 561 - #define HC_HABLAb_0 (HC_XA_0 << 8) 562 - #define HC_HABLAb_Asrc (HC_XA_Asrc << 8) 563 - #define HC_HABLAb_Adst (HC_XA_Adst << 8) 564 - #define HC_HABLAb_Fog (HC_XA_Fog << 8) 565 - #define HC_HABLAb_minAsrcFog (HC_XA_minAsrcFog << 8) 566 - #define HC_HABLAb_minAsrcAdst (HC_XA_minAsrcAdst << 8) 567 - #define HC_HABLAb_maxAsrcFog (HC_XA_maxAsrcFog << 8) 568 - #define HC_HABLAb_maxAsrcAdst (HC_XA_maxAsrcAdst << 8) 569 - #define HC_HABLAb_HABLRA (HC_XA_HABLRA << 8) 570 - #define HC_HABLFAb_OPA (HC_XA_OPA << 2) 571 - #define HC_HABLFAb_InvOPA (HC_XA_InvOPA << 2) 572 - #define HC_HABLFAb_OPAp5 (HC_XA_OPAp5 << 2) 573 - #define HC_HABLFAb_0 (HC_XA_0 << 2) 574 - #define HC_HABLFAb_Asrc (HC_XA_Asrc << 2) 575 - #define HC_HABLFAb_Adst (HC_XA_Adst << 2) 576 - #define HC_HABLFAb_Fog (HC_XA_Fog << 2) 577 - #define HC_HABLFAb_minAsrcFog (HC_XA_minAsrcFog << 2) 578 - #define HC_HABLFAb_minAsrcAdst (HC_XA_minAsrcAdst << 2) 579 - #define HC_HABLFAb_maxAsrcFog (HC_XA_maxAsrcFog << 2) 580 - #define HC_HABLFAb_maxAsrcAdst (HC_XA_maxAsrcAdst << 2) 581 - #define HC_HABLFAb_minAsrcInvAdst (HC_XA_minAsrcInvAdst << 2) 582 - #define HC_HABLFAb_HABLFRA (HC_XA_HABLFRA << 2) 583 - /* HC_SubA_HABLRAa 0x003d 584 - */ 585 - #define HC_HABLRAa_MASK 0x00ff0000 586 - #define HC_HABLRFAa_MASK 0x0000ff00 587 - #define HC_HABLRAbias_MASK 0x000000ff 588 - #define HC_HABLRAa_SHIFT 16 589 - #define HC_HABLRFAa_SHIFT 8 590 - /* HC_SubA_HABLRAb 0x003e 591 - */ 592 - #define HC_HABLRAb_MASK 0x0000ff00 593 - #define HC_HABLRFAb_MASK 0x000000ff 594 - #define HC_HABLRAb_SHIFT 8 595 - 596 - /* Destination Setting 597 - */ 598 - #define HC_SubA_HDBBasL 0x0040 599 - #define HC_SubA_HDBBasH 0x0041 600 - #define HC_SubA_HDBFM 0x0042 601 - #define HC_SubA_HFBBMSKL 0x0043 602 - #define HC_SubA_HROP 0x0044 603 - /* HC_SubA_HDBFM 0x0042 604 - */ 605 - #define HC_HDBFM_MASK 0x001f0000 606 - #define HC_HDBLoc_MASK 0x0000c000 607 - #define HC_HDBPit_MASK 0x00003fff 608 - #define HC_HDBFM_RGB555 0x00000000 609 - #define HC_HDBFM_RGB565 0x00010000 610 - #define HC_HDBFM_ARGB4444 0x00020000 611 - #define HC_HDBFM_ARGB1555 0x00030000 612 - #define HC_HDBFM_BGR555 0x00040000 613 - #define HC_HDBFM_BGR565 0x00050000 614 - #define HC_HDBFM_ABGR4444 0x00060000 615 - #define HC_HDBFM_ABGR1555 0x00070000 616 - #define HC_HDBFM_ARGB0888 0x00080000 617 - #define HC_HDBFM_ARGB8888 0x00090000 618 - #define HC_HDBFM_ABGR0888 0x000a0000 619 - #define HC_HDBFM_ABGR8888 0x000b0000 620 - #define HC_HDBLoc_Local 0x00000000 621 - #define HC_HDBLoc_Sys 0x00004000 622 - /* HC_SubA_HROP 0x0044 623 - */ 624 - #define HC_HROP_MASK 0x00000f00 625 - #define HC_HFBBMSKH_MASK 0x000000ff 626 - #define HC_HROP_BLACK 0x00000000 627 - #define HC_HROP_DPon 0x00000100 628 - #define HC_HROP_DPna 0x00000200 629 - #define HC_HROP_Pn 0x00000300 630 - #define HC_HROP_PDna 0x00000400 631 - #define HC_HROP_Dn 0x00000500 632 - #define HC_HROP_DPx 0x00000600 633 - #define HC_HROP_DPan 0x00000700 634 - #define HC_HROP_DPa 0x00000800 635 - #define HC_HROP_DPxn 0x00000900 636 - #define HC_HROP_D 0x00000a00 637 - #define HC_HROP_DPno 0x00000b00 638 - #define HC_HROP_P 0x00000c00 639 - #define HC_HROP_PDno 0x00000d00 640 - #define HC_HROP_DPo 0x00000e00 641 - #define HC_HROP_WHITE 0x00000f00 642 - 643 - /* Fog Setting 644 - */ 645 - #define HC_SubA_HFogLF 0x0050 646 - #define HC_SubA_HFogCL 0x0051 647 - #define HC_SubA_HFogCH 0x0052 648 - #define HC_SubA_HFogStL 0x0053 649 - #define HC_SubA_HFogStH 0x0054 650 - #define HC_SubA_HFogOOdMF 0x0055 651 - #define HC_SubA_HFogOOdEF 0x0056 652 - #define HC_SubA_HFogEndL 0x0057 653 - #define HC_SubA_HFogDenst 0x0058 654 - /* HC_SubA_FogLF 0x0050 655 - */ 656 - #define HC_FogLF_MASK 0x00000010 657 - #define HC_FogEq_MASK 0x00000008 658 - #define HC_FogMD_MASK 0x00000007 659 - #define HC_FogMD_LocalFog 0x00000000 660 - #define HC_FogMD_LinearFog 0x00000002 661 - #define HC_FogMD_ExponentialFog 0x00000004 662 - #define HC_FogMD_Exponential2Fog 0x00000005 663 - /* #define HC_FogMD_FogTable 0x00000003 */ 664 - 665 - /* HC_SubA_HFogDenst 0x0058 666 - */ 667 - #define HC_FogDenst_MASK 0x001fff00 668 - #define HC_FogEndL_MASK 0x000000ff 669 - 670 - /* Texture subtype definitions 671 - */ 672 - #define HC_SubType_Samp0 0x00000020 673 - #define HC_SubType_Samp1 0x00000021 674 - 675 - 676 - /* Texture subtype definitions 677 - */ 678 - #define HC_SubType_Tex0 0x00000000 679 - #define HC_SubType_Tex1 0x00000001 680 - #define HC_SubType_TexGeneral 0x000000fe 681 - 682 - /* Attribute of texture n 683 - */ 684 - #define HC_SubA_HTXnL0BasL 0x0000 685 - #define HC_SubA_HTXnL1BasL 0x0001 686 - #define HC_SubA_HTXnL2BasL 0x0002 687 - #define HC_SubA_HTXnL3BasL 0x0003 688 - #define HC_SubA_HTXnL4BasL 0x0004 689 - #define HC_SubA_HTXnL5BasL 0x0005 690 - #define HC_SubA_HTXnL6BasL 0x0006 691 - #define HC_SubA_HTXnL7BasL 0x0007 692 - #define HC_SubA_HTXnL8BasL 0x0008 693 - #define HC_SubA_HTXnL9BasL 0x0009 694 - #define HC_SubA_HTXnLaBasL 0x000a 695 - #define HC_SubA_HTXnLbBasL 0x000b 696 - #define HC_SubA_HTXnLcBasL 0x000c 697 - #define HC_SubA_HTXnLdBasL 0x000d 698 - #define HC_SubA_HTXnLeBasL 0x000e 699 - #define HC_SubA_HTXnLfBasL 0x000f 700 - #define HC_SubA_HTXnL10BasL 0x0010 701 - #define HC_SubA_HTXnL11BasL 0x0011 702 - #define HC_SubA_HTXnL012BasH 0x0020 703 - #define HC_SubA_HTXnL345BasH 0x0021 704 - #define HC_SubA_HTXnL678BasH 0x0022 705 - #define HC_SubA_HTXnL9abBasH 0x0023 706 - #define HC_SubA_HTXnLcdeBasH 0x0024 707 - #define HC_SubA_HTXnLf1011BasH 0x0025 708 - #define HC_SubA_HTXnL0Pit 0x002b 709 - #define HC_SubA_HTXnL1Pit 0x002c 710 - #define HC_SubA_HTXnL2Pit 0x002d 711 - #define HC_SubA_HTXnL3Pit 0x002e 712 - #define HC_SubA_HTXnL4Pit 0x002f 713 - #define HC_SubA_HTXnL5Pit 0x0030 714 - #define HC_SubA_HTXnL6Pit 0x0031 715 - #define HC_SubA_HTXnL7Pit 0x0032 716 - #define HC_SubA_HTXnL8Pit 0x0033 717 - #define HC_SubA_HTXnL9Pit 0x0034 718 - #define HC_SubA_HTXnLaPit 0x0035 719 - #define HC_SubA_HTXnLbPit 0x0036 720 - #define HC_SubA_HTXnLcPit 0x0037 721 - #define HC_SubA_HTXnLdPit 0x0038 722 - #define HC_SubA_HTXnLePit 0x0039 723 - #define HC_SubA_HTXnLfPit 0x003a 724 - #define HC_SubA_HTXnL10Pit 0x003b 725 - #define HC_SubA_HTXnL11Pit 0x003c 726 - #define HC_SubA_HTXnL0_5WE 0x004b 727 - #define HC_SubA_HTXnL6_bWE 0x004c 728 - #define HC_SubA_HTXnLc_11WE 0x004d 729 - #define HC_SubA_HTXnL0_5HE 0x0051 730 - #define HC_SubA_HTXnL6_bHE 0x0052 731 - #define HC_SubA_HTXnLc_11HE 0x0053 732 - #define HC_SubA_HTXnL0OS 0x0077 733 - #define HC_SubA_HTXnTB 0x0078 734 - #define HC_SubA_HTXnMPMD 0x0079 735 - #define HC_SubA_HTXnCLODu 0x007a 736 - #define HC_SubA_HTXnFM 0x007b 737 - #define HC_SubA_HTXnTRCH 0x007c 738 - #define HC_SubA_HTXnTRCL 0x007d 739 - #define HC_SubA_HTXnTBC 0x007e 740 - #define HC_SubA_HTXnTRAH 0x007f 741 - #define HC_SubA_HTXnTBLCsat 0x0080 742 - #define HC_SubA_HTXnTBLCop 0x0081 743 - #define HC_SubA_HTXnTBLMPfog 0x0082 744 - #define HC_SubA_HTXnTBLAsat 0x0083 745 - #define HC_SubA_HTXnTBLRCa 0x0085 746 - #define HC_SubA_HTXnTBLRCb 0x0086 747 - #define HC_SubA_HTXnTBLRCc 0x0087 748 - #define HC_SubA_HTXnTBLRCbias 0x0088 749 - #define HC_SubA_HTXnTBLRAa 0x0089 750 - #define HC_SubA_HTXnTBLRFog 0x008a 751 - #define HC_SubA_HTXnBumpM00 0x0090 752 - #define HC_SubA_HTXnBumpM01 0x0091 753 - #define HC_SubA_HTXnBumpM10 0x0092 754 - #define HC_SubA_HTXnBumpM11 0x0093 755 - #define HC_SubA_HTXnLScale 0x0094 756 - 757 - #define HC_SubA_HTXSMD 0x0000 758 - #define HC_SubA_HTXYUV2RGB1 0x0001 759 - #define HC_SubA_HTXYUV2RGB2 0x0002 760 - #define HC_SubA_HTXYUV2RGB3 0x0003 761 - #define HTXYUV2RGB4BT601 (1<<23) 762 - #define HTXYUV2RGB4BT709 (1<<22) 763 - /* HC_SubA_HTXnL012BasH 0x0020 764 - */ 765 - #define HC_HTXnL0BasH_MASK 0x000000ff 766 - #define HC_HTXnL1BasH_MASK 0x0000ff00 767 - #define HC_HTXnL2BasH_MASK 0x00ff0000 768 - #define HC_HTXnL1BasH_SHIFT 8 769 - #define HC_HTXnL2BasH_SHIFT 16 770 - /* HC_SubA_HTXnL345BasH 0x0021 771 - */ 772 - #define HC_HTXnL3BasH_MASK 0x000000ff 773 - #define HC_HTXnL4BasH_MASK 0x0000ff00 774 - #define HC_HTXnL5BasH_MASK 0x00ff0000 775 - #define HC_HTXnL4BasH_SHIFT 8 776 - #define HC_HTXnL5BasH_SHIFT 16 777 - /* HC_SubA_HTXnL678BasH 0x0022 778 - */ 779 - #define HC_HTXnL6BasH_MASK 0x000000ff 780 - #define HC_HTXnL7BasH_MASK 0x0000ff00 781 - #define HC_HTXnL8BasH_MASK 0x00ff0000 782 - #define HC_HTXnL7BasH_SHIFT 8 783 - #define HC_HTXnL8BasH_SHIFT 16 784 - /* HC_SubA_HTXnL9abBasH 0x0023 785 - */ 786 - #define HC_HTXnL9BasH_MASK 0x000000ff 787 - #define HC_HTXnLaBasH_MASK 0x0000ff00 788 - #define HC_HTXnLbBasH_MASK 0x00ff0000 789 - #define HC_HTXnLaBasH_SHIFT 8 790 - #define HC_HTXnLbBasH_SHIFT 16 791 - /* HC_SubA_HTXnLcdeBasH 0x0024 792 - */ 793 - #define HC_HTXnLcBasH_MASK 0x000000ff 794 - #define HC_HTXnLdBasH_MASK 0x0000ff00 795 - #define HC_HTXnLeBasH_MASK 0x00ff0000 796 - #define HC_HTXnLdBasH_SHIFT 8 797 - #define HC_HTXnLeBasH_SHIFT 16 798 - /* HC_SubA_HTXnLcdeBasH 0x0025 799 - */ 800 - #define HC_HTXnLfBasH_MASK 0x000000ff 801 - #define HC_HTXnL10BasH_MASK 0x0000ff00 802 - #define HC_HTXnL11BasH_MASK 0x00ff0000 803 - #define HC_HTXnL10BasH_SHIFT 8 804 - #define HC_HTXnL11BasH_SHIFT 16 805 - /* HC_SubA_HTXnL0Pit 0x002b 806 - */ 807 - #define HC_HTXnLnPit_MASK 0x00003fff 808 - #define HC_HTXnEnPit_MASK 0x00080000 809 - #define HC_HTXnLnPitE_MASK 0x00f00000 810 - #define HC_HTXnLnPitE_SHIFT 20 811 - /* HC_SubA_HTXnL0_5WE 0x004b 812 - */ 813 - #define HC_HTXnL0WE_MASK 0x0000000f 814 - #define HC_HTXnL1WE_MASK 0x000000f0 815 - #define HC_HTXnL2WE_MASK 0x00000f00 816 - #define HC_HTXnL3WE_MASK 0x0000f000 817 - #define HC_HTXnL4WE_MASK 0x000f0000 818 - #define HC_HTXnL5WE_MASK 0x00f00000 819 - #define HC_HTXnL1WE_SHIFT 4 820 - #define HC_HTXnL2WE_SHIFT 8 821 - #define HC_HTXnL3WE_SHIFT 12 822 - #define HC_HTXnL4WE_SHIFT 16 823 - #define HC_HTXnL5WE_SHIFT 20 824 - /* HC_SubA_HTXnL6_bWE 0x004c 825 - */ 826 - #define HC_HTXnL6WE_MASK 0x0000000f 827 - #define HC_HTXnL7WE_MASK 0x000000f0 828 - #define HC_HTXnL8WE_MASK 0x00000f00 829 - #define HC_HTXnL9WE_MASK 0x0000f000 830 - #define HC_HTXnLaWE_MASK 0x000f0000 831 - #define HC_HTXnLbWE_MASK 0x00f00000 832 - #define HC_HTXnL7WE_SHIFT 4 833 - #define HC_HTXnL8WE_SHIFT 8 834 - #define HC_HTXnL9WE_SHIFT 12 835 - #define HC_HTXnLaWE_SHIFT 16 836 - #define HC_HTXnLbWE_SHIFT 20 837 - /* HC_SubA_HTXnLc_11WE 0x004d 838 - */ 839 - #define HC_HTXnLcWE_MASK 0x0000000f 840 - #define HC_HTXnLdWE_MASK 0x000000f0 841 - #define HC_HTXnLeWE_MASK 0x00000f00 842 - #define HC_HTXnLfWE_MASK 0x0000f000 843 - #define HC_HTXnL10WE_MASK 0x000f0000 844 - #define HC_HTXnL11WE_MASK 0x00f00000 845 - #define HC_HTXnLdWE_SHIFT 4 846 - #define HC_HTXnLeWE_SHIFT 8 847 - #define HC_HTXnLfWE_SHIFT 12 848 - #define HC_HTXnL10WE_SHIFT 16 849 - #define HC_HTXnL11WE_SHIFT 20 850 - /* HC_SubA_HTXnL0_5HE 0x0051 851 - */ 852 - #define HC_HTXnL0HE_MASK 0x0000000f 853 - #define HC_HTXnL1HE_MASK 0x000000f0 854 - #define HC_HTXnL2HE_MASK 0x00000f00 855 - #define HC_HTXnL3HE_MASK 0x0000f000 856 - #define HC_HTXnL4HE_MASK 0x000f0000 857 - #define HC_HTXnL5HE_MASK 0x00f00000 858 - #define HC_HTXnL1HE_SHIFT 4 859 - #define HC_HTXnL2HE_SHIFT 8 860 - #define HC_HTXnL3HE_SHIFT 12 861 - #define HC_HTXnL4HE_SHIFT 16 862 - #define HC_HTXnL5HE_SHIFT 20 863 - /* HC_SubA_HTXnL6_bHE 0x0052 864 - */ 865 - #define HC_HTXnL6HE_MASK 0x0000000f 866 - #define HC_HTXnL7HE_MASK 0x000000f0 867 - #define HC_HTXnL8HE_MASK 0x00000f00 868 - #define HC_HTXnL9HE_MASK 0x0000f000 869 - #define HC_HTXnLaHE_MASK 0x000f0000 870 - #define HC_HTXnLbHE_MASK 0x00f00000 871 - #define HC_HTXnL7HE_SHIFT 4 872 - #define HC_HTXnL8HE_SHIFT 8 873 - #define HC_HTXnL9HE_SHIFT 12 874 - #define HC_HTXnLaHE_SHIFT 16 875 - #define HC_HTXnLbHE_SHIFT 20 876 - /* HC_SubA_HTXnLc_11HE 0x0053 877 - */ 878 - #define HC_HTXnLcHE_MASK 0x0000000f 879 - #define HC_HTXnLdHE_MASK 0x000000f0 880 - #define HC_HTXnLeHE_MASK 0x00000f00 881 - #define HC_HTXnLfHE_MASK 0x0000f000 882 - #define HC_HTXnL10HE_MASK 0x000f0000 883 - #define HC_HTXnL11HE_MASK 0x00f00000 884 - #define HC_HTXnLdHE_SHIFT 4 885 - #define HC_HTXnLeHE_SHIFT 8 886 - #define HC_HTXnLfHE_SHIFT 12 887 - #define HC_HTXnL10HE_SHIFT 16 888 - #define HC_HTXnL11HE_SHIFT 20 889 - /* HC_SubA_HTXnL0OS 0x0077 890 - */ 891 - #define HC_HTXnL0OS_MASK 0x003ff000 892 - #define HC_HTXnLVmax_MASK 0x00000fc0 893 - #define HC_HTXnLVmin_MASK 0x0000003f 894 - #define HC_HTXnL0OS_SHIFT 12 895 - #define HC_HTXnLVmax_SHIFT 6 896 - /* HC_SubA_HTXnTB 0x0078 897 - */ 898 - #define HC_HTXnTB_MASK 0x00f00000 899 - #define HC_HTXnFLSe_MASK 0x0000e000 900 - #define HC_HTXnFLSs_MASK 0x00001c00 901 - #define HC_HTXnFLTe_MASK 0x00000380 902 - #define HC_HTXnFLTs_MASK 0x00000070 903 - #define HC_HTXnFLDs_MASK 0x0000000f 904 - #define HC_HTXnTB_NoTB 0x00000000 905 - #define HC_HTXnTB_TBC_S 0x00100000 906 - #define HC_HTXnTB_TBC_T 0x00200000 907 - #define HC_HTXnTB_TB_S 0x00400000 908 - #define HC_HTXnTB_TB_T 0x00800000 909 - #define HC_HTXnFLSe_Nearest 0x00000000 910 - #define HC_HTXnFLSe_Linear 0x00002000 911 - #define HC_HTXnFLSe_NonLinear 0x00004000 912 - #define HC_HTXnFLSe_Sharp 0x00008000 913 - #define HC_HTXnFLSe_Flat_Gaussian_Cubic 0x0000c000 914 - #define HC_HTXnFLSs_Nearest 0x00000000 915 - #define HC_HTXnFLSs_Linear 0x00000400 916 - #define HC_HTXnFLSs_NonLinear 0x00000800 917 - #define HC_HTXnFLSs_Flat_Gaussian_Cubic 0x00001800 918 - #define HC_HTXnFLTe_Nearest 0x00000000 919 - #define HC_HTXnFLTe_Linear 0x00000080 920 - #define HC_HTXnFLTe_NonLinear 0x00000100 921 - #define HC_HTXnFLTe_Sharp 0x00000180 922 - #define HC_HTXnFLTe_Flat_Gaussian_Cubic 0x00000300 923 - #define HC_HTXnFLTs_Nearest 0x00000000 924 - #define HC_HTXnFLTs_Linear 0x00000010 925 - #define HC_HTXnFLTs_NonLinear 0x00000020 926 - #define HC_HTXnFLTs_Flat_Gaussian_Cubic 0x00000060 927 - #define HC_HTXnFLDs_Tex0 0x00000000 928 - #define HC_HTXnFLDs_Nearest 0x00000001 929 - #define HC_HTXnFLDs_Linear 0x00000002 930 - #define HC_HTXnFLDs_NonLinear 0x00000003 931 - #define HC_HTXnFLDs_Dither 0x00000004 932 - #define HC_HTXnFLDs_ConstLOD 0x00000005 933 - #define HC_HTXnFLDs_Ani 0x00000006 934 - #define HC_HTXnFLDs_AniDither 0x00000007 935 - /* HC_SubA_HTXnMPMD 0x0079 936 - */ 937 - #define HC_HTXnMPMD_SMASK 0x00070000 938 - #define HC_HTXnMPMD_TMASK 0x00380000 939 - #define HC_HTXnLODDTf_MASK 0x00000007 940 - #define HC_HTXnXY2ST_MASK 0x00000008 941 - #define HC_HTXnMPMD_Tsingle 0x00000000 942 - #define HC_HTXnMPMD_Tclamp 0x00080000 943 - #define HC_HTXnMPMD_Trepeat 0x00100000 944 - #define HC_HTXnMPMD_Tmirror 0x00180000 945 - #define HC_HTXnMPMD_Twrap 0x00200000 946 - #define HC_HTXnMPMD_Ssingle 0x00000000 947 - #define HC_HTXnMPMD_Sclamp 0x00010000 948 - #define HC_HTXnMPMD_Srepeat 0x00020000 949 - #define HC_HTXnMPMD_Smirror 0x00030000 950 - #define HC_HTXnMPMD_Swrap 0x00040000 951 - /* HC_SubA_HTXnCLODu 0x007a 952 - */ 953 - #define HC_HTXnCLODu_MASK 0x000ffc00 954 - #define HC_HTXnCLODd_MASK 0x000003ff 955 - #define HC_HTXnCLODu_SHIFT 10 956 - /* HC_SubA_HTXnFM 0x007b 957 - */ 958 - #define HC_HTXnFM_MASK 0x00ff0000 959 - #define HC_HTXnLoc_MASK 0x00000003 960 - #define HC_HTXnFM_INDEX 0x00000000 961 - #define HC_HTXnFM_Intensity 0x00080000 962 - #define HC_HTXnFM_Lum 0x00100000 963 - #define HC_HTXnFM_Alpha 0x00180000 964 - #define HC_HTXnFM_DX 0x00280000 965 - #define HC_HTXnFM_YUV 0x00300000 966 - #define HC_HTXnFM_ARGB16 0x00880000 967 - #define HC_HTXnFM_ARGB32 0x00980000 968 - #define HC_HTXnFM_ABGR16 0x00a80000 969 - #define HC_HTXnFM_ABGR32 0x00b80000 970 - #define HC_HTXnFM_RGBA16 0x00c80000 971 - #define HC_HTXnFM_RGBA32 0x00d80000 972 - #define HC_HTXnFM_BGRA16 0x00e80000 973 - #define HC_HTXnFM_BGRA32 0x00f80000 974 - #define HC_HTXnFM_BUMPMAP 0x00380000 975 - #define HC_HTXnFM_Index1 (HC_HTXnFM_INDEX | 0x00000000) 976 - #define HC_HTXnFM_Index2 (HC_HTXnFM_INDEX | 0x00010000) 977 - #define HC_HTXnFM_Index4 (HC_HTXnFM_INDEX | 0x00020000) 978 - #define HC_HTXnFM_Index8 (HC_HTXnFM_INDEX | 0x00030000) 979 - #define HC_HTXnFM_T1 (HC_HTXnFM_Intensity | 0x00000000) 980 - #define HC_HTXnFM_T2 (HC_HTXnFM_Intensity | 0x00010000) 981 - #define HC_HTXnFM_T4 (HC_HTXnFM_Intensity | 0x00020000) 982 - #define HC_HTXnFM_T8 (HC_HTXnFM_Intensity | 0x00030000) 983 - #define HC_HTXnFM_L1 (HC_HTXnFM_Lum | 0x00000000) 984 - #define HC_HTXnFM_L2 (HC_HTXnFM_Lum | 0x00010000) 985 - #define HC_HTXnFM_L4 (HC_HTXnFM_Lum | 0x00020000) 986 - #define HC_HTXnFM_L8 (HC_HTXnFM_Lum | 0x00030000) 987 - #define HC_HTXnFM_AL44 (HC_HTXnFM_Lum | 0x00040000) 988 - #define HC_HTXnFM_AL88 (HC_HTXnFM_Lum | 0x00050000) 989 - #define HC_HTXnFM_A1 (HC_HTXnFM_Alpha | 0x00000000) 990 - #define HC_HTXnFM_A2 (HC_HTXnFM_Alpha | 0x00010000) 991 - #define HC_HTXnFM_A4 (HC_HTXnFM_Alpha | 0x00020000) 992 - #define HC_HTXnFM_A8 (HC_HTXnFM_Alpha | 0x00030000) 993 - #define HC_HTXnFM_DX1 (HC_HTXnFM_DX | 0x00010000) 994 - #define HC_HTXnFM_DX23 (HC_HTXnFM_DX | 0x00020000) 995 - #define HC_HTXnFM_DX45 (HC_HTXnFM_DX | 0x00030000) 996 - /* YUV package mode */ 997 - #define HC_HTXnFM_YUY2 (HC_HTXnFM_YUV | 0x00000000) 998 - /* YUV planner mode */ 999 - #define HC_HTXnFM_YV12 (HC_HTXnFM_YUV | 0x00040000) 1000 - /* YUV planner mode */ 1001 - #define HC_HTXnFM_IYUV (HC_HTXnFM_YUV | 0x00040000) 1002 - #define HC_HTXnFM_RGB555 (HC_HTXnFM_ARGB16 | 0x00000000) 1003 - #define HC_HTXnFM_RGB565 (HC_HTXnFM_ARGB16 | 0x00010000) 1004 - #define HC_HTXnFM_ARGB1555 (HC_HTXnFM_ARGB16 | 0x00020000) 1005 - #define HC_HTXnFM_ARGB4444 (HC_HTXnFM_ARGB16 | 0x00030000) 1006 - #define HC_HTXnFM_ARGB0888 (HC_HTXnFM_ARGB32 | 0x00000000) 1007 - #define HC_HTXnFM_ARGB8888 (HC_HTXnFM_ARGB32 | 0x00010000) 1008 - #define HC_HTXnFM_BGR555 (HC_HTXnFM_ABGR16 | 0x00000000) 1009 - #define HC_HTXnFM_BGR565 (HC_HTXnFM_ABGR16 | 0x00010000) 1010 - #define HC_HTXnFM_ABGR1555 (HC_HTXnFM_ABGR16 | 0x00020000) 1011 - #define HC_HTXnFM_ABGR4444 (HC_HTXnFM_ABGR16 | 0x00030000) 1012 - #define HC_HTXnFM_ABGR0888 (HC_HTXnFM_ABGR32 | 0x00000000) 1013 - #define HC_HTXnFM_ABGR8888 (HC_HTXnFM_ABGR32 | 0x00010000) 1014 - #define HC_HTXnFM_RGBA5550 (HC_HTXnFM_RGBA16 | 0x00000000) 1015 - #define HC_HTXnFM_RGBA5551 (HC_HTXnFM_RGBA16 | 0x00020000) 1016 - #define HC_HTXnFM_RGBA4444 (HC_HTXnFM_RGBA16 | 0x00030000) 1017 - #define HC_HTXnFM_RGBA8880 (HC_HTXnFM_RGBA32 | 0x00000000) 1018 - #define HC_HTXnFM_RGBA8888 (HC_HTXnFM_RGBA32 | 0x00010000) 1019 - #define HC_HTXnFM_BGRA5550 (HC_HTXnFM_BGRA16 | 0x00000000) 1020 - #define HC_HTXnFM_BGRA5551 (HC_HTXnFM_BGRA16 | 0x00020000) 1021 - #define HC_HTXnFM_BGRA4444 (HC_HTXnFM_BGRA16 | 0x00030000) 1022 - #define HC_HTXnFM_BGRA8880 (HC_HTXnFM_BGRA32 | 0x00000000) 1023 - #define HC_HTXnFM_BGRA8888 (HC_HTXnFM_BGRA32 | 0x00010000) 1024 - #define HC_HTXnFM_VU88 (HC_HTXnFM_BUMPMAP | 0x00000000) 1025 - #define HC_HTXnFM_LVU655 (HC_HTXnFM_BUMPMAP | 0x00010000) 1026 - #define HC_HTXnFM_LVU888 (HC_HTXnFM_BUMPMAP | 0x00020000) 1027 - #define HC_HTXnLoc_Local 0x00000000 1028 - #define HC_HTXnLoc_Sys 0x00000002 1029 - #define HC_HTXnLoc_AGP 0x00000003 1030 - 1031 - /* Video Texture */ 1032 - #define HC_HTXnYUV2RGBMode_RGB 0x00000000 1033 - #define HC_HTXnYUV2RGBMode_SDTV 0x00000001 1034 - #define HC_HTXnYUV2RGBMode_HDTV 0x00000002 1035 - #define HC_HTXnYUV2RGBMode_TABLE 0x00000003 1036 - 1037 - /* HC_SubA_HTXnTRAH 0x007f 1038 - */ 1039 - #define HC_HTXnTRAH_MASK 0x00ff0000 1040 - #define HC_HTXnTRAL_MASK 0x0000ff00 1041 - #define HC_HTXnTBA_MASK 0x000000ff 1042 - #define HC_HTXnTRAH_SHIFT 16 1043 - #define HC_HTXnTRAL_SHIFT 8 1044 - /* HC_SubA_HTXnTBLCsat 0x0080 1045 - *-- Define the input texture. 1046 - */ 1047 - #define HC_XTC_TOPC 0x00000000 1048 - #define HC_XTC_InvTOPC 0x00000010 1049 - #define HC_XTC_TOPCp5 0x00000020 1050 - #define HC_XTC_Cbias 0x00000000 1051 - #define HC_XTC_InvCbias 0x00000010 1052 - #define HC_XTC_0 0x00000000 1053 - #define HC_XTC_Dif 0x00000001 1054 - #define HC_XTC_Spec 0x00000002 1055 - #define HC_XTC_Tex 0x00000003 1056 - #define HC_XTC_Cur 0x00000004 1057 - #define HC_XTC_Adif 0x00000005 1058 - #define HC_XTC_Fog 0x00000006 1059 - #define HC_XTC_Atex 0x00000007 1060 - #define HC_XTC_Acur 0x00000008 1061 - #define HC_XTC_HTXnTBLRC 0x00000009 1062 - #define HC_XTC_Ctexnext 0x0000000a 1063 - /*-- 1064 - */ 1065 - #define HC_HTXnTBLCsat_MASK 0x00800000 1066 - #define HC_HTXnTBLCa_MASK 0x000fc000 1067 - #define HC_HTXnTBLCb_MASK 0x00001f80 1068 - #define HC_HTXnTBLCc_MASK 0x0000003f 1069 - #define HC_HTXnTBLCa_TOPC (HC_XTC_TOPC << 14) 1070 - #define HC_HTXnTBLCa_InvTOPC (HC_XTC_InvTOPC << 14) 1071 - #define HC_HTXnTBLCa_TOPCp5 (HC_XTC_TOPCp5 << 14) 1072 - #define HC_HTXnTBLCa_0 (HC_XTC_0 << 14) 1073 - #define HC_HTXnTBLCa_Dif (HC_XTC_Dif << 14) 1074 - #define HC_HTXnTBLCa_Spec (HC_XTC_Spec << 14) 1075 - #define HC_HTXnTBLCa_Tex (HC_XTC_Tex << 14) 1076 - #define HC_HTXnTBLCa_Cur (HC_XTC_Cur << 14) 1077 - #define HC_HTXnTBLCa_Adif (HC_XTC_Adif << 14) 1078 - #define HC_HTXnTBLCa_Fog (HC_XTC_Fog << 14) 1079 - #define HC_HTXnTBLCa_Atex (HC_XTC_Atex << 14) 1080 - #define HC_HTXnTBLCa_Acur (HC_XTC_Acur << 14) 1081 - #define HC_HTXnTBLCa_HTXnTBLRC (HC_XTC_HTXnTBLRC << 14) 1082 - #define HC_HTXnTBLCa_Ctexnext (HC_XTC_Ctexnext << 14) 1083 - #define HC_HTXnTBLCb_TOPC (HC_XTC_TOPC << 7) 1084 - #define HC_HTXnTBLCb_InvTOPC (HC_XTC_InvTOPC << 7) 1085 - #define HC_HTXnTBLCb_TOPCp5 (HC_XTC_TOPCp5 << 7) 1086 - #define HC_HTXnTBLCb_0 (HC_XTC_0 << 7) 1087 - #define HC_HTXnTBLCb_Dif (HC_XTC_Dif << 7) 1088 - #define HC_HTXnTBLCb_Spec (HC_XTC_Spec << 7) 1089 - #define HC_HTXnTBLCb_Tex (HC_XTC_Tex << 7) 1090 - #define HC_HTXnTBLCb_Cur (HC_XTC_Cur << 7) 1091 - #define HC_HTXnTBLCb_Adif (HC_XTC_Adif << 7) 1092 - #define HC_HTXnTBLCb_Fog (HC_XTC_Fog << 7) 1093 - #define HC_HTXnTBLCb_Atex (HC_XTC_Atex << 7) 1094 - #define HC_HTXnTBLCb_Acur (HC_XTC_Acur << 7) 1095 - #define HC_HTXnTBLCb_HTXnTBLRC (HC_XTC_HTXnTBLRC << 7) 1096 - #define HC_HTXnTBLCb_Ctexnext (HC_XTC_Ctexnext << 7) 1097 - #define HC_HTXnTBLCc_TOPC (HC_XTC_TOPC << 0) 1098 - #define HC_HTXnTBLCc_InvTOPC (HC_XTC_InvTOPC << 0) 1099 - #define HC_HTXnTBLCc_TOPCp5 (HC_XTC_TOPCp5 << 0) 1100 - #define HC_HTXnTBLCc_0 (HC_XTC_0 << 0) 1101 - #define HC_HTXnTBLCc_Dif (HC_XTC_Dif << 0) 1102 - #define HC_HTXnTBLCc_Spec (HC_XTC_Spec << 0) 1103 - #define HC_HTXnTBLCc_Tex (HC_XTC_Tex << 0) 1104 - #define HC_HTXnTBLCc_Cur (HC_XTC_Cur << 0) 1105 - #define HC_HTXnTBLCc_Adif (HC_XTC_Adif << 0) 1106 - #define HC_HTXnTBLCc_Fog (HC_XTC_Fog << 0) 1107 - #define HC_HTXnTBLCc_Atex (HC_XTC_Atex << 0) 1108 - #define HC_HTXnTBLCc_Acur (HC_XTC_Acur << 0) 1109 - #define HC_HTXnTBLCc_HTXnTBLRC (HC_XTC_HTXnTBLRC << 0) 1110 - #define HC_HTXnTBLCc_Ctexnext (HC_XTC_Ctexnext << 0) 1111 - /* HC_SubA_HTXnTBLCop 0x0081 1112 - */ 1113 - #define HC_HTXnTBLdot_MASK 0x00c00000 1114 - #define HC_HTXnTBLCop_MASK 0x00380000 1115 - #define HC_HTXnTBLCbias_MASK 0x0007c000 1116 - #define HC_HTXnTBLCshift_MASK 0x00001800 1117 - #define HC_HTXnTBLAop_MASK 0x00000380 1118 - #define HC_HTXnTBLAbias_MASK 0x00000078 1119 - #define HC_HTXnTBLAshift_MASK 0x00000003 1120 - #define HC_HTXnTBLCop_Add 0x00000000 1121 - #define HC_HTXnTBLCop_Sub 0x00080000 1122 - #define HC_HTXnTBLCop_Min 0x00100000 1123 - #define HC_HTXnTBLCop_Max 0x00180000 1124 - #define HC_HTXnTBLCop_Mask 0x00200000 1125 - #define HC_HTXnTBLCbias_Cbias (HC_XTC_Cbias << 14) 1126 - #define HC_HTXnTBLCbias_InvCbias (HC_XTC_InvCbias << 14) 1127 - #define HC_HTXnTBLCbias_0 (HC_XTC_0 << 14) 1128 - #define HC_HTXnTBLCbias_Dif (HC_XTC_Dif << 14) 1129 - #define HC_HTXnTBLCbias_Spec (HC_XTC_Spec << 14) 1130 - #define HC_HTXnTBLCbias_Tex (HC_XTC_Tex << 14) 1131 - #define HC_HTXnTBLCbias_Cur (HC_XTC_Cur << 14) 1132 - #define HC_HTXnTBLCbias_Adif (HC_XTC_Adif << 14) 1133 - #define HC_HTXnTBLCbias_Fog (HC_XTC_Fog << 14) 1134 - #define HC_HTXnTBLCbias_Atex (HC_XTC_Atex << 14) 1135 - #define HC_HTXnTBLCbias_Acur (HC_XTC_Acur << 14) 1136 - #define HC_HTXnTBLCbias_HTXnTBLRC (HC_XTC_HTXnTBLRC << 14) 1137 - #define HC_HTXnTBLCshift_1 0x00000000 1138 - #define HC_HTXnTBLCshift_2 0x00000800 1139 - #define HC_HTXnTBLCshift_No 0x00001000 1140 - #define HC_HTXnTBLCshift_DotP 0x00001800 1141 - /*=* John Sheng [2003.7.18] texture combine *=*/ 1142 - #define HC_HTXnTBLDOT3 0x00080000 1143 - #define HC_HTXnTBLDOT4 0x000C0000 1144 - 1145 - #define HC_HTXnTBLAop_Add 0x00000000 1146 - #define HC_HTXnTBLAop_Sub 0x00000080 1147 - #define HC_HTXnTBLAop_Min 0x00000100 1148 - #define HC_HTXnTBLAop_Max 0x00000180 1149 - #define HC_HTXnTBLAop_Mask 0x00000200 1150 - #define HC_HTXnTBLAbias_Inv 0x00000040 1151 - #define HC_HTXnTBLAbias_Adif 0x00000000 1152 - #define HC_HTXnTBLAbias_Fog 0x00000008 1153 - #define HC_HTXnTBLAbias_Acur 0x00000010 1154 - #define HC_HTXnTBLAbias_HTXnTBLRAbias 0x00000018 1155 - #define HC_HTXnTBLAbias_Atex 0x00000020 1156 - #define HC_HTXnTBLAshift_1 0x00000000 1157 - #define HC_HTXnTBLAshift_2 0x00000001 1158 - #define HC_HTXnTBLAshift_No 0x00000002 1159 - /* #define HC_HTXnTBLAshift_DotP 0x00000003 */ 1160 - /* HC_SubA_HTXnTBLMPFog 0x0082 1161 - */ 1162 - #define HC_HTXnTBLMPfog_MASK 0x00e00000 1163 - #define HC_HTXnTBLMPfog_0 0x00000000 1164 - #define HC_HTXnTBLMPfog_Adif 0x00200000 1165 - #define HC_HTXnTBLMPfog_Fog 0x00400000 1166 - #define HC_HTXnTBLMPfog_Atex 0x00600000 1167 - #define HC_HTXnTBLMPfog_Acur 0x00800000 1168 - #define HC_HTXnTBLMPfog_GHTXnTBLRFog 0x00a00000 1169 - /* HC_SubA_HTXnTBLAsat 0x0083 1170 - *-- Define the texture alpha input. 1171 - */ 1172 - #define HC_XTA_TOPA 0x00000000 1173 - #define HC_XTA_InvTOPA 0x00000008 1174 - #define HC_XTA_TOPAp5 0x00000010 1175 - #define HC_XTA_Adif 0x00000000 1176 - #define HC_XTA_Fog 0x00000001 1177 - #define HC_XTA_Acur 0x00000002 1178 - #define HC_XTA_HTXnTBLRA 0x00000003 1179 - #define HC_XTA_Atex 0x00000004 1180 - #define HC_XTA_Atexnext 0x00000005 1181 - /*-- 1182 - */ 1183 - #define HC_HTXnTBLAsat_MASK 0x00800000 1184 - #define HC_HTXnTBLAMB_MASK 0x00700000 1185 - #define HC_HTXnTBLAa_MASK 0x0007c000 1186 - #define HC_HTXnTBLAb_MASK 0x00000f80 1187 - #define HC_HTXnTBLAc_MASK 0x0000001f 1188 - #define HC_HTXnTBLAMB_SHIFT 20 1189 - #define HC_HTXnTBLAa_TOPA (HC_XTA_TOPA << 14) 1190 - #define HC_HTXnTBLAa_InvTOPA (HC_XTA_InvTOPA << 14) 1191 - #define HC_HTXnTBLAa_TOPAp5 (HC_XTA_TOPAp5 << 14) 1192 - #define HC_HTXnTBLAa_Adif (HC_XTA_Adif << 14) 1193 - #define HC_HTXnTBLAa_Fog (HC_XTA_Fog << 14) 1194 - #define HC_HTXnTBLAa_Acur (HC_XTA_Acur << 14) 1195 - #define HC_HTXnTBLAa_HTXnTBLRA (HC_XTA_HTXnTBLRA << 14) 1196 - #define HC_HTXnTBLAa_Atex (HC_XTA_Atex << 14) 1197 - #define HC_HTXnTBLAa_Atexnext (HC_XTA_Atexnext << 14) 1198 - #define HC_HTXnTBLAb_TOPA (HC_XTA_TOPA << 7) 1199 - #define HC_HTXnTBLAb_InvTOPA (HC_XTA_InvTOPA << 7) 1200 - #define HC_HTXnTBLAb_TOPAp5 (HC_XTA_TOPAp5 << 7) 1201 - #define HC_HTXnTBLAb_Adif (HC_XTA_Adif << 7) 1202 - #define HC_HTXnTBLAb_Fog (HC_XTA_Fog << 7) 1203 - #define HC_HTXnTBLAb_Acur (HC_XTA_Acur << 7) 1204 - #define HC_HTXnTBLAb_HTXnTBLRA (HC_XTA_HTXnTBLRA << 7) 1205 - #define HC_HTXnTBLAb_Atex (HC_XTA_Atex << 7) 1206 - #define HC_HTXnTBLAb_Atexnext (HC_XTA_Atexnext << 7) 1207 - #define HC_HTXnTBLAc_TOPA (HC_XTA_TOPA << 0) 1208 - #define HC_HTXnTBLAc_InvTOPA (HC_XTA_InvTOPA << 0) 1209 - #define HC_HTXnTBLAc_TOPAp5 (HC_XTA_TOPAp5 << 0) 1210 - #define HC_HTXnTBLAc_Adif (HC_XTA_Adif << 0) 1211 - #define HC_HTXnTBLAc_Fog (HC_XTA_Fog << 0) 1212 - #define HC_HTXnTBLAc_Acur (HC_XTA_Acur << 0) 1213 - #define HC_HTXnTBLAc_HTXnTBLRA (HC_XTA_HTXnTBLRA << 0) 1214 - #define HC_HTXnTBLAc_Atex (HC_XTA_Atex << 0) 1215 - #define HC_HTXnTBLAc_Atexnext (HC_XTA_Atexnext << 0) 1216 - /* HC_SubA_HTXnTBLRAa 0x0089 1217 - */ 1218 - #define HC_HTXnTBLRAa_MASK 0x00ff0000 1219 - #define HC_HTXnTBLRAb_MASK 0x0000ff00 1220 - #define HC_HTXnTBLRAc_MASK 0x000000ff 1221 - #define HC_HTXnTBLRAa_SHIFT 16 1222 - #define HC_HTXnTBLRAb_SHIFT 8 1223 - #define HC_HTXnTBLRAc_SHIFT 0 1224 - /* HC_SubA_HTXnTBLRFog 0x008a 1225 - */ 1226 - #define HC_HTXnTBLRFog_MASK 0x0000ff00 1227 - #define HC_HTXnTBLRAbias_MASK 0x000000ff 1228 - #define HC_HTXnTBLRFog_SHIFT 8 1229 - #define HC_HTXnTBLRAbias_SHIFT 0 1230 - /* HC_SubA_HTXnLScale 0x0094 1231 - */ 1232 - #define HC_HTXnLScale_MASK 0x0007fc00 1233 - #define HC_HTXnLOff_MASK 0x000001ff 1234 - #define HC_HTXnLScale_SHIFT 10 1235 - /* HC_SubA_HTXSMD 0x0000 1236 - */ 1237 - #define HC_HTXSMD_MASK 0x00000080 1238 - #define HC_HTXTMD_MASK 0x00000040 1239 - #define HC_HTXNum_MASK 0x00000038 1240 - #define HC_HTXTRMD_MASK 0x00000006 1241 - #define HC_HTXCHCLR_MASK 0x00000001 1242 - #define HC_HTXNum_SHIFT 3 1243 - 1244 - /* Texture Palette n 1245 - */ 1246 - #define HC_SubType_TexPalette0 0x00000000 1247 - #define HC_SubType_TexPalette1 0x00000001 1248 - #define HC_SubType_FogTable 0x00000010 1249 - #define HC_SubType_Stipple 0x00000014 1250 - /* HC_SubA_TexPalette0 0x0000 1251 - */ 1252 - #define HC_HTPnA_MASK 0xff000000 1253 - #define HC_HTPnR_MASK 0x00ff0000 1254 - #define HC_HTPnG_MASK 0x0000ff00 1255 - #define HC_HTPnB_MASK 0x000000ff 1256 - /* HC_SubA_FogTable 0x0010 1257 - */ 1258 - #define HC_HFPn3_MASK 0xff000000 1259 - #define HC_HFPn2_MASK 0x00ff0000 1260 - #define HC_HFPn1_MASK 0x0000ff00 1261 - #define HC_HFPn_MASK 0x000000ff 1262 - #define HC_HFPn3_SHIFT 24 1263 - #define HC_HFPn2_SHIFT 16 1264 - #define HC_HFPn1_SHIFT 8 1265 - 1266 - /* Auto Testing & Security 1267 - */ 1268 - #define HC_SubA_HenFIFOAT 0x0000 1269 - #define HC_SubA_HFBDrawFirst 0x0004 1270 - #define HC_SubA_HFBBasL 0x0005 1271 - #define HC_SubA_HFBDst 0x0006 1272 - /* HC_SubA_HenFIFOAT 0x0000 1273 - */ 1274 - #define HC_HenFIFOAT_MASK 0x00000020 1275 - #define HC_HenGEMILock_MASK 0x00000010 1276 - #define HC_HenFBASwap_MASK 0x00000008 1277 - #define HC_HenOT_MASK 0x00000004 1278 - #define HC_HenCMDQ_MASK 0x00000002 1279 - #define HC_HenTXCTSU_MASK 0x00000001 1280 - /* HC_SubA_HFBDrawFirst 0x0004 1281 - */ 1282 - #define HC_HFBDrawFirst_MASK 0x00000800 1283 - #define HC_HFBQueue_MASK 0x00000400 1284 - #define HC_HFBLock_MASK 0x00000200 1285 - #define HC_HEOF_MASK 0x00000100 1286 - #define HC_HFBBasH_MASK 0x000000ff 1287 - 1288 - /* GEMI Setting 1289 - */ 1290 - #define HC_SubA_HTArbRCM 0x0008 1291 - #define HC_SubA_HTArbRZ 0x000a 1292 - #define HC_SubA_HTArbWZ 0x000b 1293 - #define HC_SubA_HTArbRTX 0x000c 1294 - #define HC_SubA_HTArbRCW 0x000d 1295 - #define HC_SubA_HTArbE2 0x000e 1296 - #define HC_SubA_HArbRQCM 0x0010 1297 - #define HC_SubA_HArbWQCM 0x0011 1298 - #define HC_SubA_HGEMITout 0x0020 1299 - #define HC_SubA_HFthRTXD 0x0040 1300 - #define HC_SubA_HFthRTXA 0x0044 1301 - #define HC_SubA_HCMDQstL 0x0050 1302 - #define HC_SubA_HCMDQendL 0x0051 1303 - #define HC_SubA_HCMDQLen 0x0052 1304 - /* HC_SubA_HTArbRCM 0x0008 1305 - */ 1306 - #define HC_HTArbRCM_MASK 0x0000ffff 1307 - /* HC_SubA_HTArbRZ 0x000a 1308 - */ 1309 - #define HC_HTArbRZ_MASK 0x0000ffff 1310 - /* HC_SubA_HTArbWZ 0x000b 1311 - */ 1312 - #define HC_HTArbWZ_MASK 0x0000ffff 1313 - /* HC_SubA_HTArbRTX 0x000c 1314 - */ 1315 - #define HC_HTArbRTX_MASK 0x0000ffff 1316 - /* HC_SubA_HTArbRCW 0x000d 1317 - */ 1318 - #define HC_HTArbRCW_MASK 0x0000ffff 1319 - /* HC_SubA_HTArbE2 0x000e 1320 - */ 1321 - #define HC_HTArbE2_MASK 0x0000ffff 1322 - /* HC_SubA_HArbRQCM 0x0010 1323 - */ 1324 - #define HC_HTArbRQCM_MASK 0x0000ffff 1325 - /* HC_SubA_HArbWQCM 0x0011 1326 - */ 1327 - #define HC_HArbWQCM_MASK 0x0000ffff 1328 - /* HC_SubA_HGEMITout 0x0020 1329 - */ 1330 - #define HC_HGEMITout_MASK 0x000f0000 1331 - #define HC_HNPArbZC_MASK 0x0000ffff 1332 - #define HC_HGEMITout_SHIFT 16 1333 - /* HC_SubA_HFthRTXD 0x0040 1334 - */ 1335 - #define HC_HFthRTXD_MASK 0x00ff0000 1336 - #define HC_HFthRZD_MASK 0x0000ff00 1337 - #define HC_HFthWZD_MASK 0x000000ff 1338 - #define HC_HFthRTXD_SHIFT 16 1339 - #define HC_HFthRZD_SHIFT 8 1340 - /* HC_SubA_HFthRTXA 0x0044 1341 - */ 1342 - #define HC_HFthRTXA_MASK 0x000000ff 1343 - 1344 - /**************************************************************************** 1345 - * Define the Halcyon Internal register access constants. For simulator only. 1346 - ***************************************************************************/ 1347 - #define HC_SIMA_HAGPBstL 0x0000 1348 - #define HC_SIMA_HAGPBendL 0x0001 1349 - #define HC_SIMA_HAGPCMNT 0x0002 1350 - #define HC_SIMA_HAGPBpL 0x0003 1351 - #define HC_SIMA_HAGPBpH 0x0004 1352 - #define HC_SIMA_HClipTB 0x0005 1353 - #define HC_SIMA_HClipLR 0x0006 1354 - #define HC_SIMA_HFPClipTL 0x0007 1355 - #define HC_SIMA_HFPClipBL 0x0008 1356 - #define HC_SIMA_HFPClipLL 0x0009 1357 - #define HC_SIMA_HFPClipRL 0x000a 1358 - #define HC_SIMA_HFPClipTBH 0x000b 1359 - #define HC_SIMA_HFPClipLRH 0x000c 1360 - #define HC_SIMA_HLP 0x000d 1361 - #define HC_SIMA_HLPRF 0x000e 1362 - #define HC_SIMA_HSolidCL 0x000f 1363 - #define HC_SIMA_HPixGC 0x0010 1364 - #define HC_SIMA_HSPXYOS 0x0011 1365 - #define HC_SIMA_HCmdA 0x0012 1366 - #define HC_SIMA_HCmdB 0x0013 1367 - #define HC_SIMA_HEnable 0x0014 1368 - #define HC_SIMA_HZWBBasL 0x0015 1369 - #define HC_SIMA_HZWBBasH 0x0016 1370 - #define HC_SIMA_HZWBType 0x0017 1371 - #define HC_SIMA_HZBiasL 0x0018 1372 - #define HC_SIMA_HZWBend 0x0019 1373 - #define HC_SIMA_HZWTMD 0x001a 1374 - #define HC_SIMA_HZWCDL 0x001b 1375 - #define HC_SIMA_HZWCTAGnum 0x001c 1376 - #define HC_SIMA_HZCYNum 0x001d 1377 - #define HC_SIMA_HZWCFire 0x001e 1378 - /* #define HC_SIMA_HSBBasL 0x001d */ 1379 - /* #define HC_SIMA_HSBBasH 0x001e */ 1380 - /* #define HC_SIMA_HSBFM 0x001f */ 1381 - #define HC_SIMA_HSTREF 0x0020 1382 - #define HC_SIMA_HSTMD 0x0021 1383 - #define HC_SIMA_HABBasL 0x0022 1384 - #define HC_SIMA_HABBasH 0x0023 1385 - #define HC_SIMA_HABFM 0x0024 1386 - #define HC_SIMA_HATMD 0x0025 1387 - #define HC_SIMA_HABLCsat 0x0026 1388 - #define HC_SIMA_HABLCop 0x0027 1389 - #define HC_SIMA_HABLAsat 0x0028 1390 - #define HC_SIMA_HABLAop 0x0029 1391 - #define HC_SIMA_HABLRCa 0x002a 1392 - #define HC_SIMA_HABLRFCa 0x002b 1393 - #define HC_SIMA_HABLRCbias 0x002c 1394 - #define HC_SIMA_HABLRCb 0x002d 1395 - #define HC_SIMA_HABLRFCb 0x002e 1396 - #define HC_SIMA_HABLRAa 0x002f 1397 - #define HC_SIMA_HABLRAb 0x0030 1398 - #define HC_SIMA_HDBBasL 0x0031 1399 - #define HC_SIMA_HDBBasH 0x0032 1400 - #define HC_SIMA_HDBFM 0x0033 1401 - #define HC_SIMA_HFBBMSKL 0x0034 1402 - #define HC_SIMA_HROP 0x0035 1403 - #define HC_SIMA_HFogLF 0x0036 1404 - #define HC_SIMA_HFogCL 0x0037 1405 - #define HC_SIMA_HFogCH 0x0038 1406 - #define HC_SIMA_HFogStL 0x0039 1407 - #define HC_SIMA_HFogStH 0x003a 1408 - #define HC_SIMA_HFogOOdMF 0x003b 1409 - #define HC_SIMA_HFogOOdEF 0x003c 1410 - #define HC_SIMA_HFogEndL 0x003d 1411 - #define HC_SIMA_HFogDenst 0x003e 1412 - /*---- start of texture 0 setting ---- 1413 - */ 1414 - #define HC_SIMA_HTX0L0BasL 0x0040 1415 - #define HC_SIMA_HTX0L1BasL 0x0041 1416 - #define HC_SIMA_HTX0L2BasL 0x0042 1417 - #define HC_SIMA_HTX0L3BasL 0x0043 1418 - #define HC_SIMA_HTX0L4BasL 0x0044 1419 - #define HC_SIMA_HTX0L5BasL 0x0045 1420 - #define HC_SIMA_HTX0L6BasL 0x0046 1421 - #define HC_SIMA_HTX0L7BasL 0x0047 1422 - #define HC_SIMA_HTX0L8BasL 0x0048 1423 - #define HC_SIMA_HTX0L9BasL 0x0049 1424 - #define HC_SIMA_HTX0LaBasL 0x004a 1425 - #define HC_SIMA_HTX0LbBasL 0x004b 1426 - #define HC_SIMA_HTX0LcBasL 0x004c 1427 - #define HC_SIMA_HTX0LdBasL 0x004d 1428 - #define HC_SIMA_HTX0LeBasL 0x004e 1429 - #define HC_SIMA_HTX0LfBasL 0x004f 1430 - #define HC_SIMA_HTX0L10BasL 0x0050 1431 - #define HC_SIMA_HTX0L11BasL 0x0051 1432 - #define HC_SIMA_HTX0L012BasH 0x0052 1433 - #define HC_SIMA_HTX0L345BasH 0x0053 1434 - #define HC_SIMA_HTX0L678BasH 0x0054 1435 - #define HC_SIMA_HTX0L9abBasH 0x0055 1436 - #define HC_SIMA_HTX0LcdeBasH 0x0056 1437 - #define HC_SIMA_HTX0Lf1011BasH 0x0057 1438 - #define HC_SIMA_HTX0L0Pit 0x0058 1439 - #define HC_SIMA_HTX0L1Pit 0x0059 1440 - #define HC_SIMA_HTX0L2Pit 0x005a 1441 - #define HC_SIMA_HTX0L3Pit 0x005b 1442 - #define HC_SIMA_HTX0L4Pit 0x005c 1443 - #define HC_SIMA_HTX0L5Pit 0x005d 1444 - #define HC_SIMA_HTX0L6Pit 0x005e 1445 - #define HC_SIMA_HTX0L7Pit 0x005f 1446 - #define HC_SIMA_HTX0L8Pit 0x0060 1447 - #define HC_SIMA_HTX0L9Pit 0x0061 1448 - #define HC_SIMA_HTX0LaPit 0x0062 1449 - #define HC_SIMA_HTX0LbPit 0x0063 1450 - #define HC_SIMA_HTX0LcPit 0x0064 1451 - #define HC_SIMA_HTX0LdPit 0x0065 1452 - #define HC_SIMA_HTX0LePit 0x0066 1453 - #define HC_SIMA_HTX0LfPit 0x0067 1454 - #define HC_SIMA_HTX0L10Pit 0x0068 1455 - #define HC_SIMA_HTX0L11Pit 0x0069 1456 - #define HC_SIMA_HTX0L0_5WE 0x006a 1457 - #define HC_SIMA_HTX0L6_bWE 0x006b 1458 - #define HC_SIMA_HTX0Lc_11WE 0x006c 1459 - #define HC_SIMA_HTX0L0_5HE 0x006d 1460 - #define HC_SIMA_HTX0L6_bHE 0x006e 1461 - #define HC_SIMA_HTX0Lc_11HE 0x006f 1462 - #define HC_SIMA_HTX0L0OS 0x0070 1463 - #define HC_SIMA_HTX0TB 0x0071 1464 - #define HC_SIMA_HTX0MPMD 0x0072 1465 - #define HC_SIMA_HTX0CLODu 0x0073 1466 - #define HC_SIMA_HTX0FM 0x0074 1467 - #define HC_SIMA_HTX0TRCH 0x0075 1468 - #define HC_SIMA_HTX0TRCL 0x0076 1469 - #define HC_SIMA_HTX0TBC 0x0077 1470 - #define HC_SIMA_HTX0TRAH 0x0078 1471 - #define HC_SIMA_HTX0TBLCsat 0x0079 1472 - #define HC_SIMA_HTX0TBLCop 0x007a 1473 - #define HC_SIMA_HTX0TBLMPfog 0x007b 1474 - #define HC_SIMA_HTX0TBLAsat 0x007c 1475 - #define HC_SIMA_HTX0TBLRCa 0x007d 1476 - #define HC_SIMA_HTX0TBLRCb 0x007e 1477 - #define HC_SIMA_HTX0TBLRCc 0x007f 1478 - #define HC_SIMA_HTX0TBLRCbias 0x0080 1479 - #define HC_SIMA_HTX0TBLRAa 0x0081 1480 - #define HC_SIMA_HTX0TBLRFog 0x0082 1481 - #define HC_SIMA_HTX0BumpM00 0x0083 1482 - #define HC_SIMA_HTX0BumpM01 0x0084 1483 - #define HC_SIMA_HTX0BumpM10 0x0085 1484 - #define HC_SIMA_HTX0BumpM11 0x0086 1485 - #define HC_SIMA_HTX0LScale 0x0087 1486 - /*---- end of texture 0 setting ---- 0x008f 1487 - */ 1488 - #define HC_SIMA_TX0TX1_OFF 0x0050 1489 - /*---- start of texture 1 setting ---- 1490 - */ 1491 - #define HC_SIMA_HTX1L0BasL (HC_SIMA_HTX0L0BasL + HC_SIMA_TX0TX1_OFF) 1492 - #define HC_SIMA_HTX1L1BasL (HC_SIMA_HTX0L1BasL + HC_SIMA_TX0TX1_OFF) 1493 - #define HC_SIMA_HTX1L2BasL (HC_SIMA_HTX0L2BasL + HC_SIMA_TX0TX1_OFF) 1494 - #define HC_SIMA_HTX1L3BasL (HC_SIMA_HTX0L3BasL + HC_SIMA_TX0TX1_OFF) 1495 - #define HC_SIMA_HTX1L4BasL (HC_SIMA_HTX0L4BasL + HC_SIMA_TX0TX1_OFF) 1496 - #define HC_SIMA_HTX1L5BasL (HC_SIMA_HTX0L5BasL + HC_SIMA_TX0TX1_OFF) 1497 - #define HC_SIMA_HTX1L6BasL (HC_SIMA_HTX0L6BasL + HC_SIMA_TX0TX1_OFF) 1498 - #define HC_SIMA_HTX1L7BasL (HC_SIMA_HTX0L7BasL + HC_SIMA_TX0TX1_OFF) 1499 - #define HC_SIMA_HTX1L8BasL (HC_SIMA_HTX0L8BasL + HC_SIMA_TX0TX1_OFF) 1500 - #define HC_SIMA_HTX1L9BasL (HC_SIMA_HTX0L9BasL + HC_SIMA_TX0TX1_OFF) 1501 - #define HC_SIMA_HTX1LaBasL (HC_SIMA_HTX0LaBasL + HC_SIMA_TX0TX1_OFF) 1502 - #define HC_SIMA_HTX1LbBasL (HC_SIMA_HTX0LbBasL + HC_SIMA_TX0TX1_OFF) 1503 - #define HC_SIMA_HTX1LcBasL (HC_SIMA_HTX0LcBasL + HC_SIMA_TX0TX1_OFF) 1504 - #define HC_SIMA_HTX1LdBasL (HC_SIMA_HTX0LdBasL + HC_SIMA_TX0TX1_OFF) 1505 - #define HC_SIMA_HTX1LeBasL (HC_SIMA_HTX0LeBasL + HC_SIMA_TX0TX1_OFF) 1506 - #define HC_SIMA_HTX1LfBasL (HC_SIMA_HTX0LfBasL + HC_SIMA_TX0TX1_OFF) 1507 - #define HC_SIMA_HTX1L10BasL (HC_SIMA_HTX0L10BasL + HC_SIMA_TX0TX1_OFF) 1508 - #define HC_SIMA_HTX1L11BasL (HC_SIMA_HTX0L11BasL + HC_SIMA_TX0TX1_OFF) 1509 - #define HC_SIMA_HTX1L012BasH (HC_SIMA_HTX0L012BasH + HC_SIMA_TX0TX1_OFF) 1510 - #define HC_SIMA_HTX1L345BasH (HC_SIMA_HTX0L345BasH + HC_SIMA_TX0TX1_OFF) 1511 - #define HC_SIMA_HTX1L678BasH (HC_SIMA_HTX0L678BasH + HC_SIMA_TX0TX1_OFF) 1512 - #define HC_SIMA_HTX1L9abBasH (HC_SIMA_HTX0L9abBasH + HC_SIMA_TX0TX1_OFF) 1513 - #define HC_SIMA_HTX1LcdeBasH (HC_SIMA_HTX0LcdeBasH + HC_SIMA_TX0TX1_OFF) 1514 - #define HC_SIMA_HTX1Lf1011BasH (HC_SIMA_HTX0Lf1011BasH + HC_SIMA_TX0TX1_OFF) 1515 - #define HC_SIMA_HTX1L0Pit (HC_SIMA_HTX0L0Pit + HC_SIMA_TX0TX1_OFF) 1516 - #define HC_SIMA_HTX1L1Pit (HC_SIMA_HTX0L1Pit + HC_SIMA_TX0TX1_OFF) 1517 - #define HC_SIMA_HTX1L2Pit (HC_SIMA_HTX0L2Pit + HC_SIMA_TX0TX1_OFF) 1518 - #define HC_SIMA_HTX1L3Pit (HC_SIMA_HTX0L3Pit + HC_SIMA_TX0TX1_OFF) 1519 - #define HC_SIMA_HTX1L4Pit (HC_SIMA_HTX0L4Pit + HC_SIMA_TX0TX1_OFF) 1520 - #define HC_SIMA_HTX1L5Pit (HC_SIMA_HTX0L5Pit + HC_SIMA_TX0TX1_OFF) 1521 - #define HC_SIMA_HTX1L6Pit (HC_SIMA_HTX0L6Pit + HC_SIMA_TX0TX1_OFF) 1522 - #define HC_SIMA_HTX1L7Pit (HC_SIMA_HTX0L7Pit + HC_SIMA_TX0TX1_OFF) 1523 - #define HC_SIMA_HTX1L8Pit (HC_SIMA_HTX0L8Pit + HC_SIMA_TX0TX1_OFF) 1524 - #define HC_SIMA_HTX1L9Pit (HC_SIMA_HTX0L9Pit + HC_SIMA_TX0TX1_OFF) 1525 - #define HC_SIMA_HTX1LaPit (HC_SIMA_HTX0LaPit + HC_SIMA_TX0TX1_OFF) 1526 - #define HC_SIMA_HTX1LbPit (HC_SIMA_HTX0LbPit + HC_SIMA_TX0TX1_OFF) 1527 - #define HC_SIMA_HTX1LcPit (HC_SIMA_HTX0LcPit + HC_SIMA_TX0TX1_OFF) 1528 - #define HC_SIMA_HTX1LdPit (HC_SIMA_HTX0LdPit + HC_SIMA_TX0TX1_OFF) 1529 - #define HC_SIMA_HTX1LePit (HC_SIMA_HTX0LePit + HC_SIMA_TX0TX1_OFF) 1530 - #define HC_SIMA_HTX1LfPit (HC_SIMA_HTX0LfPit + HC_SIMA_TX0TX1_OFF) 1531 - #define HC_SIMA_HTX1L10Pit (HC_SIMA_HTX0L10Pit + HC_SIMA_TX0TX1_OFF) 1532 - #define HC_SIMA_HTX1L11Pit (HC_SIMA_HTX0L11Pit + HC_SIMA_TX0TX1_OFF) 1533 - #define HC_SIMA_HTX1L0_5WE (HC_SIMA_HTX0L0_5WE + HC_SIMA_TX0TX1_OFF) 1534 - #define HC_SIMA_HTX1L6_bWE (HC_SIMA_HTX0L6_bWE + HC_SIMA_TX0TX1_OFF) 1535 - #define HC_SIMA_HTX1Lc_11WE (HC_SIMA_HTX0Lc_11WE + HC_SIMA_TX0TX1_OFF) 1536 - #define HC_SIMA_HTX1L0_5HE (HC_SIMA_HTX0L0_5HE + HC_SIMA_TX0TX1_OFF) 1537 - #define HC_SIMA_HTX1L6_bHE (HC_SIMA_HTX0L6_bHE + HC_SIMA_TX0TX1_OFF) 1538 - #define HC_SIMA_HTX1Lc_11HE (HC_SIMA_HTX0Lc_11HE + HC_SIMA_TX0TX1_OFF) 1539 - #define HC_SIMA_HTX1L0OS (HC_SIMA_HTX0L0OS + HC_SIMA_TX0TX1_OFF) 1540 - #define HC_SIMA_HTX1TB (HC_SIMA_HTX0TB + HC_SIMA_TX0TX1_OFF) 1541 - #define HC_SIMA_HTX1MPMD (HC_SIMA_HTX0MPMD + HC_SIMA_TX0TX1_OFF) 1542 - #define HC_SIMA_HTX1CLODu (HC_SIMA_HTX0CLODu + HC_SIMA_TX0TX1_OFF) 1543 - #define HC_SIMA_HTX1FM (HC_SIMA_HTX0FM + HC_SIMA_TX0TX1_OFF) 1544 - #define HC_SIMA_HTX1TRCH (HC_SIMA_HTX0TRCH + HC_SIMA_TX0TX1_OFF) 1545 - #define HC_SIMA_HTX1TRCL (HC_SIMA_HTX0TRCL + HC_SIMA_TX0TX1_OFF) 1546 - #define HC_SIMA_HTX1TBC (HC_SIMA_HTX0TBC + HC_SIMA_TX0TX1_OFF) 1547 - #define HC_SIMA_HTX1TRAH (HC_SIMA_HTX0TRAH + HC_SIMA_TX0TX1_OFF) 1548 - #define HC_SIMA_HTX1LTC (HC_SIMA_HTX0LTC + HC_SIMA_TX0TX1_OFF) 1549 - #define HC_SIMA_HTX1LTA (HC_SIMA_HTX0LTA + HC_SIMA_TX0TX1_OFF) 1550 - #define HC_SIMA_HTX1TBLCsat (HC_SIMA_HTX0TBLCsat + HC_SIMA_TX0TX1_OFF) 1551 - #define HC_SIMA_HTX1TBLCop (HC_SIMA_HTX0TBLCop + HC_SIMA_TX0TX1_OFF) 1552 - #define HC_SIMA_HTX1TBLMPfog (HC_SIMA_HTX0TBLMPfog + HC_SIMA_TX0TX1_OFF) 1553 - #define HC_SIMA_HTX1TBLAsat (HC_SIMA_HTX0TBLAsat + HC_SIMA_TX0TX1_OFF) 1554 - #define HC_SIMA_HTX1TBLRCa (HC_SIMA_HTX0TBLRCa + HC_SIMA_TX0TX1_OFF) 1555 - #define HC_SIMA_HTX1TBLRCb (HC_SIMA_HTX0TBLRCb + HC_SIMA_TX0TX1_OFF) 1556 - #define HC_SIMA_HTX1TBLRCc (HC_SIMA_HTX0TBLRCc + HC_SIMA_TX0TX1_OFF) 1557 - #define HC_SIMA_HTX1TBLRCbias (HC_SIMA_HTX0TBLRCbias + HC_SIMA_TX0TX1_OFF) 1558 - #define HC_SIMA_HTX1TBLRAa (HC_SIMA_HTX0TBLRAa + HC_SIMA_TX0TX1_OFF) 1559 - #define HC_SIMA_HTX1TBLRFog (HC_SIMA_HTX0TBLRFog + HC_SIMA_TX0TX1_OFF) 1560 - #define HC_SIMA_HTX1BumpM00 (HC_SIMA_HTX0BumpM00 + HC_SIMA_TX0TX1_OFF) 1561 - #define HC_SIMA_HTX1BumpM01 (HC_SIMA_HTX0BumpM01 + HC_SIMA_TX0TX1_OFF) 1562 - #define HC_SIMA_HTX1BumpM10 (HC_SIMA_HTX0BumpM10 + HC_SIMA_TX0TX1_OFF) 1563 - #define HC_SIMA_HTX1BumpM11 (HC_SIMA_HTX0BumpM11 + HC_SIMA_TX0TX1_OFF) 1564 - #define HC_SIMA_HTX1LScale (HC_SIMA_HTX0LScale + HC_SIMA_TX0TX1_OFF) 1565 - /*---- end of texture 1 setting ---- 0xaf 1566 - */ 1567 - #define HC_SIMA_HTXSMD 0x00b0 1568 - #define HC_SIMA_HenFIFOAT 0x00b1 1569 - #define HC_SIMA_HFBDrawFirst 0x00b2 1570 - #define HC_SIMA_HFBBasL 0x00b3 1571 - #define HC_SIMA_HTArbRCM 0x00b4 1572 - #define HC_SIMA_HTArbRZ 0x00b5 1573 - #define HC_SIMA_HTArbWZ 0x00b6 1574 - #define HC_SIMA_HTArbRTX 0x00b7 1575 - #define HC_SIMA_HTArbRCW 0x00b8 1576 - #define HC_SIMA_HTArbE2 0x00b9 1577 - #define HC_SIMA_HGEMITout 0x00ba 1578 - #define HC_SIMA_HFthRTXD 0x00bb 1579 - #define HC_SIMA_HFthRTXA 0x00bc 1580 - /* Define the texture palette 0 1581 - */ 1582 - #define HC_SIMA_HTP0 0x0100 1583 - #define HC_SIMA_HTP1 0x0200 1584 - #define HC_SIMA_FOGTABLE 0x0300 1585 - #define HC_SIMA_STIPPLE 0x0400 1586 - #define HC_SIMA_HE3Fire 0x0440 1587 - #define HC_SIMA_TRANS_SET 0x0441 1588 - #define HC_SIMA_HREngSt 0x0442 1589 - #define HC_SIMA_HRFIFOempty 0x0443 1590 - #define HC_SIMA_HRFIFOfull 0x0444 1591 - #define HC_SIMA_HRErr 0x0445 1592 - #define HC_SIMA_FIFOstatus 0x0446 1593 - 1594 - /**************************************************************************** 1595 - * Define the AGP command header. 1596 - ***************************************************************************/ 1597 - #define HC_ACMD_MASK 0xfe000000 1598 - #define HC_ACMD_SUB_MASK 0x0c000000 1599 - #define HC_ACMD_HCmdA 0xee000000 1600 - #define HC_ACMD_HCmdB 0xec000000 1601 - #define HC_ACMD_HCmdC 0xea000000 1602 - #define HC_ACMD_H1 0xf0000000 1603 - #define HC_ACMD_H2 0xf2000000 1604 - #define HC_ACMD_H3 0xf4000000 1605 - #define HC_ACMD_H4 0xf6000000 1606 - 1607 - #define HC_ACMD_H1IO_MASK 0x000001ff 1608 - #define HC_ACMD_H2IO1_MASK 0x001ff000 1609 - #define HC_ACMD_H2IO2_MASK 0x000001ff 1610 - #define HC_ACMD_H2IO1_SHIFT 12 1611 - #define HC_ACMD_H2IO2_SHIFT 0 1612 - #define HC_ACMD_H3IO_MASK 0x000001ff 1613 - #define HC_ACMD_H3COUNT_MASK 0x01fff000 1614 - #define HC_ACMD_H3COUNT_SHIFT 12 1615 - #define HC_ACMD_H4ID_MASK 0x000001ff 1616 - #define HC_ACMD_H4COUNT_MASK 0x01fffe00 1617 - #define HC_ACMD_H4COUNT_SHIFT 9 1618 - 1619 - /***************************************************************************** 1620 - * Define Header 1621 - ****************************************************************************/ 1622 - #define HC_HEADER2 0xF210F110 1623 - 1624 - /***************************************************************************** 1625 - * Define Dummy Value 1626 - ****************************************************************************/ 1627 - #define HC_DUMMY 0xCCCCCCCC 1628 - /***************************************************************************** 1629 - * Define for DMA use 1630 - ****************************************************************************/ 1631 - #define HALCYON_HEADER2 0XF210F110 1632 - #define HALCYON_FIRECMD 0XEE100000 1633 - #define HALCYON_FIREMASK 0XFFF00000 1634 - #define HALCYON_CMDB 0XEC000000 1635 - #define HALCYON_CMDBMASK 0XFFFE0000 1636 - #define HALCYON_SUB_ADDR0 0X00000000 1637 - #define HALCYON_HEADER1MASK 0XFFFFFC00 1638 - #define HALCYON_HEADER1 0XF0000000 1639 - #define HC_SubA_HAGPBstL 0x0060 1640 - #define HC_SubA_HAGPBendL 0x0061 1641 - #define HC_SubA_HAGPCMNT 0x0062 1642 - #define HC_SubA_HAGPBpL 0x0063 1643 - #define HC_SubA_HAGPBpH 0x0064 1644 - #define HC_HAGPCMNT_MASK 0x00800000 1645 - #define HC_HCmdErrClr_MASK 0x00400000 1646 - #define HC_HAGPBendH_MASK 0x0000ff00 1647 - #define HC_HAGPBstH_MASK 0x000000ff 1648 - #define HC_HAGPBendH_SHIFT 8 1649 - #define HC_HAGPBstH_SHIFT 0 1650 - #define HC_HAGPBpL_MASK 0x00fffffc 1651 - #define HC_HAGPBpID_MASK 0x00000003 1652 - #define HC_HAGPBpID_PAUSE 0x00000000 1653 - #define HC_HAGPBpID_JUMP 0x00000001 1654 - #define HC_HAGPBpID_STOP 0x00000002 1655 - #define HC_HAGPBpH_MASK 0x00ffffff 1656 - 1657 - 1658 - #define VIA_VIDEO_HEADER5 0xFE040000 1659 - #define VIA_VIDEO_HEADER6 0xFE050000 1660 - #define VIA_VIDEO_HEADER7 0xFE060000 1661 - #define VIA_VIDEOMASK 0xFFFF0000 1662 - 1663 - /***************************************************************************** 1664 - * Define for H5 DMA use 1665 - ****************************************************************************/ 1666 - #define H5_HC_DUMMY 0xCC000000 1667 - 1668 - /* Command Header Type */ 1669 - #define INV_DUMMY_MASK 0xFF000000 1670 - #define INV_AGPHeader0 0xFE000000 1671 - #define INV_AGPHeader1 0xFE010000 1672 - #define INV_AGPHeader2 0xFE020000 1673 - #define INV_AGPHeader3 0xFE030000 1674 - #define INV_AGPHeader4 0xFE040000 1675 - #define INV_AGPHeader5 0xFE050000 1676 - #define INV_AGPHeader6 0xFE060000 1677 - #define INV_AGPHeader7 0xFE070000 1678 - #define INV_AGPHeader9 0xFE090000 1679 - #define INV_AGPHeaderA 0xFE0A0000 1680 - #define INV_AGPHeader40 0xFE400000 1681 - #define INV_AGPHeader41 0xFE410000 1682 - #define INV_AGPHeader43 0xFE430000 1683 - #define INV_AGPHeader45 0xFE450000 1684 - #define INV_AGPHeader47 0xFE470000 1685 - #define INV_AGPHeader4A 0xFE4A0000 1686 - #define INV_AGPHeader82 0xFE820000 1687 - #define INV_AGPHeader83 0xFE830000 1688 - #define INV_AGPHeader_MASK 0xFFFF0000 1689 - #define INV_AGPHeader2A 0xFE2A0000 1690 - #define INV_AGPHeader25 0xFE250000 1691 - #define INV_AGPHeader20 0xFE200000 1692 - #define INV_AGPHeader23 0xFE230000 1693 - #define INV_AGPHeaderE2 0xFEE20000 1694 - #define INV_AGPHeaderE3 0xFEE30000 1695 - 1696 - /*Transmission IO Space*/ 1697 - #define INV_REG_CR_TRANS 0x041C 1698 - #define INV_REG_CR_BEGIN 0x0420 1699 - #define INV_REG_CR_END 0x0438 1700 - 1701 - #define INV_REG_3D_TRANS 0x043C 1702 - #define INV_REG_3D_BEGIN 0x0440 1703 - #define INV_REG_3D_END 0x06FC 1704 - 1705 - #define INV_ParaType_CmdVdata 0x0000 1706 - 1707 - /* H5 Enable Setting 1708 - */ 1709 - #define INV_HC_SubA_HEnable1 0x00 1710 - 1711 - #define INV_HC_HenAT4ALLRT_MASK 0x00100000 1712 - #define INV_HC_HenATMRT3_MASK 0x00080000 1713 - #define INV_HC_HenATMRT2_MASK 0x00040000 1714 - #define INV_HC_HenATMRT1_MASK 0x00020000 1715 - #define INV_HC_HenATMRT0_MASK 0x00010000 1716 - #define INV_HC_HenSCMRT3_MASK 0x00008000 1717 - #define INV_HC_HenSCMRT2_MASK 0x00004000 1718 - #define INV_HC_HenSCMRT1_MASK 0x00002000 1719 - #define INV_HC_HenSCMRT0_MASK 0x00001000 1720 - #define INV_HC_HenFOGMRT3_MASK 0x00000800 1721 - #define INV_HC_HenFOGMRT2_MASK 0x00000400 1722 - #define INV_HC_HenFOGMRT1_MASK 0x00000200 1723 - #define INV_HC_HenFOGMRT0_MASK 0x00000100 1724 - #define INV_HC_HenABLMRT3_MASK 0x00000080 1725 - #define INV_HC_HenABLMRT2_MASK 0x00000040 1726 - #define INV_HC_HenABLMRT1_MASK 0x00000020 1727 - #define INV_HC_HenABLMRT0_MASK 0x00000010 1728 - #define INV_HC_HenDTMRT3_MASK 0x00000008 1729 - #define INV_HC_HenDTMRT2_MASK 0x00000004 1730 - #define INV_HC_HenDTMRT1_MASK 0x00000002 1731 - #define INV_HC_HenDTMRT0_MASK 0x00000001 1732 - 1733 - #define INV_HC_SubA_HEnable2 0x01 1734 - 1735 - #define INV_HC_HenLUL2DR_MASK 0x00800000 1736 - #define INV_HC_HenLDIAMOND_MASK 0x00400000 1737 - #define INV_HC_HenPSPRITE_MASK 0x00200000 1738 - #define INV_HC_HenC2S_MASK 0x00100000 1739 - #define INV_HC_HenFOGPP_MASK 0x00080000 1740 - #define INV_HC_HenSCPP_MASK 0x00040000 1741 - #define INV_HC_HenCPP_MASK 0x00020000 1742 - #define INV_HC_HenCZ_MASK 0x00002000 1743 - #define INV_HC_HenVC_MASK 0x00001000 1744 - #define INV_HC_HenCL_MASK 0x00000800 1745 - #define INV_HC_HenPS_MASK 0x00000400 1746 - #define INV_HC_HenWCZ_MASK 0x00000200 1747 - #define INV_HC_HenTXCH_MASK 0x00000100 1748 - #define INV_HC_HenBFCULL_MASK 0x00000080 1749 - #define INV_HC_HenCW_MASK 0x00000040 1750 - #define INV_HC_HenAA_MASK 0x00000020 1751 - #define INV_HC_HenST_MASK 0x00000010 1752 - #define INV_HC_HenZT_MASK 0x00000008 1753 - #define INV_HC_HenZW_MASK 0x00000004 1754 - #define INV_HC_HenSP_MASK 0x00000002 1755 - #define INV_HC_HenLP_MASK 0x00000001 1756 - 1757 - /* H5 Miscellaneous Settings 1758 - */ 1759 - #define INV_HC_SubA_HCClipTL 0x0080 1760 - #define INV_HC_SubA_HCClipBL 0x0081 1761 - #define INV_HC_SubA_HSClipTL 0x0082 1762 - #define INV_HC_SubA_HSClipBL 0x0083 1763 - #define INV_HC_SubA_HSolidCL 0x0086 1764 - #define INV_HC_SubA_HSolidCH 0x0087 1765 - #define INV_HC_SubA_HGBClipGL 0x0088 1766 - #define INV_HC_SubA_HGBClipGR 0x0089 1767 - 1768 - 1769 - #define INV_HC_ParaType_Vetex 0x00040000 1770 - 1771 - #endif

-3630

drivers/gpu/drm/via/via_dri1.c

··· 1 - /* 2 - * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. 3 - * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. 4 - * Copyright 2002 Tungsten Graphics, Inc. 5 - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. All Rights Reserved. 6 - * Copyright 2006 Tungsten Graphics Inc., Bismarck, ND., USA. 7 - * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A. All Rights Reserved. 8 - * Copyright 2004 The Unichrome project. All Rights Reserved. 9 - * Copyright 2004 BEAM Ltd. 10 - * Copyright 2005 Thomas Hellstrom. All Rights Reserved. 11 - * 12 - * Permission is hereby granted, free of charge, to any person obtaining a 13 - * copy of this software and associated documentation files (the "Software"), 14 - * to deal in the Software without restriction, including without limitation 15 - * the rights to use, copy, modify, merge, publish, distribute, sub license, 16 - * and/or sell copies of the Software, and to permit persons to whom the 17 - * Software is furnished to do so, subject to the following conditions: 18 - * 19 - * The above copyright notice and this permission notice (including the 20 - * next paragraph) shall be included in all copies or substantial portions 21 - * of the Software. 22 - * 23 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 26 - * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 29 - * DEALINGS IN THE SOFTWARE. 30 - */ 31 - 32 - #include <linux/delay.h> 33 - #include <linux/module.h> 34 - #include <linux/pci.h> 35 - #include <linux/vmalloc.h> 36 - 37 - #include <drm/drm_drv.h> 38 - #include <drm/drm_file.h> 39 - #include <drm/drm_ioctl.h> 40 - #include <drm/drm_legacy.h> 41 - #include <drm/drm_mm.h> 42 - #include <drm/drm_pciids.h> 43 - #include <drm/drm_print.h> 44 - #include <drm/drm_vblank.h> 45 - #include <drm/via_drm.h> 46 - 47 - #include "via_3d_reg.h" 48 - 49 - #define DRIVER_AUTHOR "Various" 50 - 51 - #define DRIVER_NAME "via" 52 - #define DRIVER_DESC "VIA Unichrome / Pro" 53 - #define DRIVER_DATE "20070202" 54 - 55 - #define DRIVER_MAJOR 2 56 - #define DRIVER_MINOR 11 57 - #define DRIVER_PATCHLEVEL 1 58 - 59 - typedef enum { 60 - no_sequence = 0, 61 - z_address, 62 - dest_address, 63 - tex_address 64 - } drm_via_sequence_t; 65 - 66 - typedef struct { 67 - unsigned texture; 68 - uint32_t z_addr; 69 - uint32_t d_addr; 70 - uint32_t t_addr[2][10]; 71 - uint32_t pitch[2][10]; 72 - uint32_t height[2][10]; 73 - uint32_t tex_level_lo[2]; 74 - uint32_t tex_level_hi[2]; 75 - uint32_t tex_palette_size[2]; 76 - uint32_t tex_npot[2]; 77 - drm_via_sequence_t unfinished; 78 - int agp_texture; 79 - int multitex; 80 - struct drm_device *dev; 81 - drm_local_map_t *map_cache; 82 - uint32_t vertex_count; 83 - int agp; 84 - const uint32_t *buf_start; 85 - } drm_via_state_t; 86 - 87 - #define VIA_PCI_BUF_SIZE 60000 88 - #define VIA_FIRE_BUF_SIZE 1024 89 - #define VIA_NUM_IRQS 4 90 - 91 - 92 - #define VIA_NUM_BLIT_ENGINES 2 93 - #define VIA_NUM_BLIT_SLOTS 8 94 - 95 - struct _drm_via_descriptor; 96 - 97 - typedef struct _drm_via_sg_info { 98 - struct page **pages; 99 - unsigned long num_pages; 100 - struct _drm_via_descriptor **desc_pages; 101 - int num_desc_pages; 102 - int num_desc; 103 - enum dma_data_direction direction; 104 - unsigned char *bounce_buffer; 105 - dma_addr_t chain_start; 106 - uint32_t free_on_sequence; 107 - unsigned int descriptors_per_page; 108 - int aborted; 109 - enum { 110 - dr_via_device_mapped, 111 - dr_via_desc_pages_alloc, 112 - dr_via_pages_locked, 113 - dr_via_pages_alloc, 114 - dr_via_sg_init 115 - } state; 116 - } drm_via_sg_info_t; 117 - 118 - typedef struct _drm_via_blitq { 119 - struct drm_device *dev; 120 - uint32_t cur_blit_handle; 121 - uint32_t done_blit_handle; 122 - unsigned serviced; 123 - unsigned head; 124 - unsigned cur; 125 - unsigned num_free; 126 - unsigned num_outstanding; 127 - unsigned long end; 128 - int aborting; 129 - int is_active; 130 - drm_via_sg_info_t *blits[VIA_NUM_BLIT_SLOTS]; 131 - spinlock_t blit_lock; 132 - wait_queue_head_t blit_queue[VIA_NUM_BLIT_SLOTS]; 133 - wait_queue_head_t busy_queue; 134 - struct work_struct wq; 135 - struct timer_list poll_timer; 136 - } drm_via_blitq_t; 137 - 138 - typedef struct drm_via_ring_buffer { 139 - drm_local_map_t map; 140 - char *virtual_start; 141 - } drm_via_ring_buffer_t; 142 - 143 - typedef uint32_t maskarray_t[5]; 144 - 145 - typedef struct drm_via_irq { 146 - atomic_t irq_received; 147 - uint32_t pending_mask; 148 - uint32_t enable_mask; 149 - wait_queue_head_t irq_queue; 150 - } drm_via_irq_t; 151 - 152 - typedef struct drm_via_private { 153 - drm_via_sarea_t *sarea_priv; 154 - drm_local_map_t *sarea; 155 - drm_local_map_t *fb; 156 - drm_local_map_t *mmio; 157 - unsigned long agpAddr; 158 - wait_queue_head_t decoder_queue[VIA_NR_XVMC_LOCKS]; 159 - char *dma_ptr; 160 - unsigned int dma_low; 161 - unsigned int dma_high; 162 - unsigned int dma_offset; 163 - uint32_t dma_wrap; 164 - volatile uint32_t *last_pause_ptr; 165 - volatile uint32_t *hw_addr_ptr; 166 - drm_via_ring_buffer_t ring; 167 - ktime_t last_vblank; 168 - int last_vblank_valid; 169 - ktime_t nsec_per_vblank; 170 - atomic_t vbl_received; 171 - drm_via_state_t hc_state; 172 - char pci_buf[VIA_PCI_BUF_SIZE]; 173 - const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE]; 174 - uint32_t num_fire_offsets; 175 - int chipset; 176 - drm_via_irq_t via_irqs[VIA_NUM_IRQS]; 177 - unsigned num_irqs; 178 - maskarray_t *irq_masks; 179 - uint32_t irq_enable_mask; 180 - uint32_t irq_pending_mask; 181 - int *irq_map; 182 - unsigned int idle_fault; 183 - int vram_initialized; 184 - struct drm_mm vram_mm; 185 - int agp_initialized; 186 - struct drm_mm agp_mm; 187 - /** Mapping of userspace keys to mm objects */ 188 - struct idr object_idr; 189 - unsigned long vram_offset; 190 - unsigned long agp_offset; 191 - drm_via_blitq_t blit_queues[VIA_NUM_BLIT_ENGINES]; 192 - uint32_t dma_diff; 193 - } drm_via_private_t; 194 - 195 - struct via_file_private { 196 - struct list_head obj_list; 197 - }; 198 - 199 - enum via_family { 200 - VIA_OTHER = 0, /* Baseline */ 201 - VIA_PRO_GROUP_A, /* Another video engine and DMA commands */ 202 - VIA_DX9_0 /* Same video as pro_group_a, but 3D is unsupported */ 203 - }; 204 - 205 - /* VIA MMIO register access */ 206 - static inline u32 via_read(struct drm_via_private *dev_priv, u32 reg) 207 - { 208 - return readl((void __iomem *)(dev_priv->mmio->handle + reg)); 209 - } 210 - 211 - static inline void via_write(struct drm_via_private *dev_priv, u32 reg, 212 - u32 val) 213 - { 214 - writel(val, (void __iomem *)(dev_priv->mmio->handle + reg)); 215 - } 216 - 217 - static inline void via_write8(struct drm_via_private *dev_priv, u32 reg, 218 - u32 val) 219 - { 220 - writeb(val, (void __iomem *)(dev_priv->mmio->handle + reg)); 221 - } 222 - 223 - static inline void via_write8_mask(struct drm_via_private *dev_priv, 224 - u32 reg, u32 mask, u32 val) 225 - { 226 - u32 tmp; 227 - 228 - tmp = readb((void __iomem *)(dev_priv->mmio->handle + reg)); 229 - tmp = (tmp & ~mask) | (val & mask); 230 - writeb(tmp, (void __iomem *)(dev_priv->mmio->handle + reg)); 231 - } 232 - 233 - /* 234 - * Poll in a loop waiting for 'contidition' to be true. 235 - * Note: A direct replacement with wait_event_interruptible_timeout() 236 - * will not work unless driver is updated to emit wake_up() 237 - * in relevant places that can impact the 'condition' 238 - * 239 - * Returns: 240 - * ret keeps current value if 'condition' becomes true 241 - * ret = -BUSY if timeout happens 242 - * ret = -EINTR if a signal interrupted the waiting period 243 - */ 244 - #define VIA_WAIT_ON( ret, queue, timeout, condition ) \ 245 - do { \ 246 - DECLARE_WAITQUEUE(entry, current); \ 247 - unsigned long end = jiffies + (timeout); \ 248 - add_wait_queue(&(queue), &entry); \ 249 - \ 250 - for (;;) { \ 251 - __set_current_state(TASK_INTERRUPTIBLE); \ 252 - if (condition) \ 253 - break; \ 254 - if (time_after_eq(jiffies, end)) { \ 255 - ret = -EBUSY; \ 256 - break; \ 257 - } \ 258 - schedule_timeout((HZ/100 > 1) ? HZ/100 : 1); \ 259 - if (signal_pending(current)) { \ 260 - ret = -EINTR; \ 261 - break; \ 262 - } \ 263 - } \ 264 - __set_current_state(TASK_RUNNING); \ 265 - remove_wait_queue(&(queue), &entry); \ 266 - } while (0) 267 - 268 - int via_do_cleanup_map(struct drm_device *dev); 269 - 270 - int via_dma_cleanup(struct drm_device *dev); 271 - int via_driver_dma_quiescent(struct drm_device *dev); 272 - 273 - #define CMDBUF_ALIGNMENT_SIZE (0x100) 274 - #define CMDBUF_ALIGNMENT_MASK (0x0ff) 275 - 276 - /* defines for VIA 3D registers */ 277 - #define VIA_REG_STATUS 0x400 278 - #define VIA_REG_TRANSET 0x43C 279 - #define VIA_REG_TRANSPACE 0x440 280 - 281 - /* VIA_REG_STATUS(0x400): Engine Status */ 282 - #define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ 283 - #define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */ 284 - #define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */ 285 - #define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */ 286 - 287 - #define SetReg2DAGP(nReg, nData) { \ 288 - *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \ 289 - *((uint32_t *)(vb) + 1) = (nData); \ 290 - vb = ((uint32_t *)vb) + 2; \ 291 - dev_priv->dma_low += 8; \ 292 - } 293 - 294 - #define via_flush_write_combine() mb() 295 - 296 - #define VIA_OUT_RING_QW(w1, w2) do { \ 297 - *vb++ = (w1); \ 298 - *vb++ = (w2); \ 299 - dev_priv->dma_low += 8; \ 300 - } while (0) 301 - 302 - #define VIA_MM_ALIGN_SHIFT 4 303 - #define VIA_MM_ALIGN_MASK ((1 << VIA_MM_ALIGN_SHIFT) - 1) 304 - 305 - struct via_memblock { 306 - struct drm_mm_node mm_node; 307 - struct list_head owner_list; 308 - }; 309 - 310 - #define VIA_REG_INTERRUPT 0x200 311 - 312 - /* VIA_REG_INTERRUPT */ 313 - #define VIA_IRQ_GLOBAL (1 << 31) 314 - #define VIA_IRQ_VBLANK_ENABLE (1 << 19) 315 - #define VIA_IRQ_VBLANK_PENDING (1 << 3) 316 - #define VIA_IRQ_HQV0_ENABLE (1 << 11) 317 - #define VIA_IRQ_HQV1_ENABLE (1 << 25) 318 - #define VIA_IRQ_HQV0_PENDING (1 << 9) 319 - #define VIA_IRQ_HQV1_PENDING (1 << 10) 320 - #define VIA_IRQ_DMA0_DD_ENABLE (1 << 20) 321 - #define VIA_IRQ_DMA0_TD_ENABLE (1 << 21) 322 - #define VIA_IRQ_DMA1_DD_ENABLE (1 << 22) 323 - #define VIA_IRQ_DMA1_TD_ENABLE (1 << 23) 324 - #define VIA_IRQ_DMA0_DD_PENDING (1 << 4) 325 - #define VIA_IRQ_DMA0_TD_PENDING (1 << 5) 326 - #define VIA_IRQ_DMA1_DD_PENDING (1 << 6) 327 - #define VIA_IRQ_DMA1_TD_PENDING (1 << 7) 328 - 329 - /* 330 - * PCI DMA Registers 331 - * Channels 2 & 3 don't seem to be implemented in hardware. 332 - */ 333 - 334 - #define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */ 335 - #define VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */ 336 - #define VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */ 337 - #define VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */ 338 - 339 - #define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */ 340 - #define VIA_PCI_DMA_DAR1 0xE54 /* Device Address Register of Channel 1 */ 341 - #define VIA_PCI_DMA_BCR1 0xE58 /* Byte Count Register of Channel 1 */ 342 - #define VIA_PCI_DMA_DPR1 0xE5C /* Descriptor Pointer Register of Channel 1 */ 343 - 344 - #define VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */ 345 - #define VIA_PCI_DMA_DAR2 0xE64 /* Device Address Register of Channel 2 */ 346 - #define VIA_PCI_DMA_BCR2 0xE68 /* Byte Count Register of Channel 2 */ 347 - #define VIA_PCI_DMA_DPR2 0xE6C /* Descriptor Pointer Register of Channel 2 */ 348 - 349 - #define VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */ 350 - #define VIA_PCI_DMA_DAR3 0xE74 /* Device Address Register of Channel 3 */ 351 - #define VIA_PCI_DMA_BCR3 0xE78 /* Byte Count Register of Channel 3 */ 352 - #define VIA_PCI_DMA_DPR3 0xE7C /* Descriptor Pointer Register of Channel 3 */ 353 - 354 - #define VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */ 355 - #define VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */ 356 - #define VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */ 357 - #define VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */ 358 - 359 - #define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */ 360 - #define VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */ 361 - #define VIA_PCI_DMA_CSR2 0xE98 /* Command/Status Register of Channel 2 */ 362 - #define VIA_PCI_DMA_CSR3 0xE9C /* Command/Status Register of Channel 3 */ 363 - 364 - #define VIA_PCI_DMA_PTR 0xEA0 /* Priority Type Register */ 365 - 366 - /* Define for DMA engine */ 367 - /* DPR */ 368 - #define VIA_DMA_DPR_EC (1<<1) /* end of chain */ 369 - #define VIA_DMA_DPR_DDIE (1<<2) /* descriptor done interrupt enable */ 370 - #define VIA_DMA_DPR_DT (1<<3) /* direction of transfer (RO) */ 371 - 372 - /* MR */ 373 - #define VIA_DMA_MR_CM (1<<0) /* chaining mode */ 374 - #define VIA_DMA_MR_TDIE (1<<1) /* transfer done interrupt enable */ 375 - #define VIA_DMA_MR_HENDMACMD (1<<7) /* ? */ 376 - 377 - /* CSR */ 378 - #define VIA_DMA_CSR_DE (1<<0) /* DMA enable */ 379 - #define VIA_DMA_CSR_TS (1<<1) /* transfer start */ 380 - #define VIA_DMA_CSR_TA (1<<2) /* transfer abort */ 381 - #define VIA_DMA_CSR_TD (1<<3) /* transfer done */ 382 - #define VIA_DMA_CSR_DD (1<<4) /* descriptor done */ 383 - #define VIA_DMA_DPR_EC (1<<1) /* end of chain */ 384 - 385 - /* 386 - * Device-specific IRQs go here. This type might need to be extended with 387 - * the register if there are multiple IRQ control registers. 388 - * Currently we activate the HQV interrupts of Unichrome Pro group A. 389 - */ 390 - 391 - static maskarray_t via_pro_group_a_irqs[] = { 392 - {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010, 393 - 0x00000000 }, 394 - {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010, 395 - 0x00000000 }, 396 - {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0, 397 - VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}, 398 - {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1, 399 - VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}, 400 - }; 401 - static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs); 402 - static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3}; 403 - 404 - static maskarray_t via_unichrome_irqs[] = { 405 - {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0, 406 - VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}, 407 - {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1, 408 - VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008} 409 - }; 410 - static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs); 411 - static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1}; 412 - 413 - 414 - /* 415 - * Unmaps the DMA mappings. 416 - * FIXME: Is this a NoOp on x86? Also 417 - * FIXME: What happens if this one is called and a pending blit has previously done 418 - * the same DMA mappings? 419 - */ 420 - #define VIA_PGDN(x) (((unsigned long)(x)) & PAGE_MASK) 421 - #define VIA_PGOFF(x) (((unsigned long)(x)) & ~PAGE_MASK) 422 - #define VIA_PFN(x) ((unsigned long)(x) >> PAGE_SHIFT) 423 - 424 - typedef struct _drm_via_descriptor { 425 - uint32_t mem_addr; 426 - uint32_t dev_addr; 427 - uint32_t size; 428 - uint32_t next; 429 - } drm_via_descriptor_t; 430 - 431 - typedef enum { 432 - state_command, 433 - state_header2, 434 - state_header1, 435 - state_vheader5, 436 - state_vheader6, 437 - state_error 438 - } verifier_state_t; 439 - 440 - typedef enum { 441 - no_check = 0, 442 - check_for_header2, 443 - check_for_header1, 444 - check_for_header2_err, 445 - check_for_header1_err, 446 - check_for_fire, 447 - check_z_buffer_addr0, 448 - check_z_buffer_addr1, 449 - check_z_buffer_addr_mode, 450 - check_destination_addr0, 451 - check_destination_addr1, 452 - check_destination_addr_mode, 453 - check_for_dummy, 454 - check_for_dd, 455 - check_texture_addr0, 456 - check_texture_addr1, 457 - check_texture_addr2, 458 - check_texture_addr3, 459 - check_texture_addr4, 460 - check_texture_addr5, 461 - check_texture_addr6, 462 - check_texture_addr7, 463 - check_texture_addr8, 464 - check_texture_addr_mode, 465 - check_for_vertex_count, 466 - check_number_texunits, 467 - forbidden_command 468 - } hazard_t; 469 - 470 - /* 471 - * Associates each hazard above with a possible multi-command 472 - * sequence. For example an address that is split over multiple 473 - * commands and that needs to be checked at the first command 474 - * that does not include any part of the address. 475 - */ 476 - 477 - static drm_via_sequence_t seqs[] = { 478 - no_sequence, 479 - no_sequence, 480 - no_sequence, 481 - no_sequence, 482 - no_sequence, 483 - no_sequence, 484 - z_address, 485 - z_address, 486 - z_address, 487 - dest_address, 488 - dest_address, 489 - dest_address, 490 - no_sequence, 491 - no_sequence, 492 - tex_address, 493 - tex_address, 494 - tex_address, 495 - tex_address, 496 - tex_address, 497 - tex_address, 498 - tex_address, 499 - tex_address, 500 - tex_address, 501 - tex_address, 502 - no_sequence 503 - }; 504 - 505 - typedef struct { 506 - unsigned int code; 507 - hazard_t hz; 508 - } hz_init_t; 509 - 510 - static hz_init_t init_table1[] = { 511 - {0xf2, check_for_header2_err}, 512 - {0xf0, check_for_header1_err}, 513 - {0xee, check_for_fire}, 514 - {0xcc, check_for_dummy}, 515 - {0xdd, check_for_dd}, 516 - {0x00, no_check}, 517 - {0x10, check_z_buffer_addr0}, 518 - {0x11, check_z_buffer_addr1}, 519 - {0x12, check_z_buffer_addr_mode}, 520 - {0x13, no_check}, 521 - {0x14, no_check}, 522 - {0x15, no_check}, 523 - {0x23, no_check}, 524 - {0x24, no_check}, 525 - {0x33, no_check}, 526 - {0x34, no_check}, 527 - {0x35, no_check}, 528 - {0x36, no_check}, 529 - {0x37, no_check}, 530 - {0x38, no_check}, 531 - {0x39, no_check}, 532 - {0x3A, no_check}, 533 - {0x3B, no_check}, 534 - {0x3C, no_check}, 535 - {0x3D, no_check}, 536 - {0x3E, no_check}, 537 - {0x40, check_destination_addr0}, 538 - {0x41, check_destination_addr1}, 539 - {0x42, check_destination_addr_mode}, 540 - {0x43, no_check}, 541 - {0x44, no_check}, 542 - {0x50, no_check}, 543 - {0x51, no_check}, 544 - {0x52, no_check}, 545 - {0x53, no_check}, 546 - {0x54, no_check}, 547 - {0x55, no_check}, 548 - {0x56, no_check}, 549 - {0x57, no_check}, 550 - {0x58, no_check}, 551 - {0x70, no_check}, 552 - {0x71, no_check}, 553 - {0x78, no_check}, 554 - {0x79, no_check}, 555 - {0x7A, no_check}, 556 - {0x7B, no_check}, 557 - {0x7C, no_check}, 558 - {0x7D, check_for_vertex_count} 559 - }; 560 - 561 - static hz_init_t init_table2[] = { 562 - {0xf2, check_for_header2_err}, 563 - {0xf0, check_for_header1_err}, 564 - {0xee, check_for_fire}, 565 - {0xcc, check_for_dummy}, 566 - {0x00, check_texture_addr0}, 567 - {0x01, check_texture_addr0}, 568 - {0x02, check_texture_addr0}, 569 - {0x03, check_texture_addr0}, 570 - {0x04, check_texture_addr0}, 571 - {0x05, check_texture_addr0}, 572 - {0x06, check_texture_addr0}, 573 - {0x07, check_texture_addr0}, 574 - {0x08, check_texture_addr0}, 575 - {0x09, check_texture_addr0}, 576 - {0x20, check_texture_addr1}, 577 - {0x21, check_texture_addr1}, 578 - {0x22, check_texture_addr1}, 579 - {0x23, check_texture_addr4}, 580 - {0x2B, check_texture_addr3}, 581 - {0x2C, check_texture_addr3}, 582 - {0x2D, check_texture_addr3}, 583 - {0x2E, check_texture_addr3}, 584 - {0x2F, check_texture_addr3}, 585 - {0x30, check_texture_addr3}, 586 - {0x31, check_texture_addr3}, 587 - {0x32, check_texture_addr3}, 588 - {0x33, check_texture_addr3}, 589 - {0x34, check_texture_addr3}, 590 - {0x4B, check_texture_addr5}, 591 - {0x4C, check_texture_addr6}, 592 - {0x51, check_texture_addr7}, 593 - {0x52, check_texture_addr8}, 594 - {0x77, check_texture_addr2}, 595 - {0x78, no_check}, 596 - {0x79, no_check}, 597 - {0x7A, no_check}, 598 - {0x7B, check_texture_addr_mode}, 599 - {0x7C, no_check}, 600 - {0x7D, no_check}, 601 - {0x7E, no_check}, 602 - {0x7F, no_check}, 603 - {0x80, no_check}, 604 - {0x81, no_check}, 605 - {0x82, no_check}, 606 - {0x83, no_check}, 607 - {0x85, no_check}, 608 - {0x86, no_check}, 609 - {0x87, no_check}, 610 - {0x88, no_check}, 611 - {0x89, no_check}, 612 - {0x8A, no_check}, 613 - {0x90, no_check}, 614 - {0x91, no_check}, 615 - {0x92, no_check}, 616 - {0x93, no_check} 617 - }; 618 - 619 - static hz_init_t init_table3[] = { 620 - {0xf2, check_for_header2_err}, 621 - {0xf0, check_for_header1_err}, 622 - {0xcc, check_for_dummy}, 623 - {0x00, check_number_texunits} 624 - }; 625 - 626 - static hazard_t table1[256]; 627 - static hazard_t table2[256]; 628 - static hazard_t table3[256]; 629 - 630 - static __inline__ int 631 - eat_words(const uint32_t **buf, const uint32_t *buf_end, unsigned num_words) 632 - { 633 - if ((buf_end - *buf) >= num_words) { 634 - *buf += num_words; 635 - return 0; 636 - } 637 - DRM_ERROR("Illegal termination of DMA command buffer\n"); 638 - return 1; 639 - } 640 - 641 - /* 642 - * Partially stolen from drm_memory.h 643 - */ 644 - 645 - static __inline__ drm_local_map_t *via_drm_lookup_agp_map(drm_via_state_t *seq, 646 - unsigned long offset, 647 - unsigned long size, 648 - struct drm_device *dev) 649 - { 650 - struct drm_map_list *r_list; 651 - drm_local_map_t *map = seq->map_cache; 652 - 653 - if (map && map->offset <= offset 654 - && (offset + size) <= (map->offset + map->size)) { 655 - return map; 656 - } 657 - 658 - list_for_each_entry(r_list, &dev->maplist, head) { 659 - map = r_list->map; 660 - if (!map) 661 - continue; 662 - if (map->offset <= offset 663 - && (offset + size) <= (map->offset + map->size) 664 - && !(map->flags & _DRM_RESTRICTED) 665 - && (map->type == _DRM_AGP)) { 666 - seq->map_cache = map; 667 - return map; 668 - } 669 - } 670 - return NULL; 671 - } 672 - 673 - /* 674 - * Require that all AGP texture levels reside in the same AGP map which should 675 - * be mappable by the client. This is not a big restriction. 676 - * FIXME: To actually enforce this security policy strictly, drm_rmmap 677 - * would have to wait for dma quiescent before removing an AGP map. 678 - * The via_drm_lookup_agp_map call in reality seems to take 679 - * very little CPU time. 680 - */ 681 - 682 - static __inline__ int finish_current_sequence(drm_via_state_t * cur_seq) 683 - { 684 - switch (cur_seq->unfinished) { 685 - case z_address: 686 - DRM_DEBUG("Z Buffer start address is 0x%x\n", cur_seq->z_addr); 687 - break; 688 - case dest_address: 689 - DRM_DEBUG("Destination start address is 0x%x\n", 690 - cur_seq->d_addr); 691 - break; 692 - case tex_address: 693 - if (cur_seq->agp_texture) { 694 - unsigned start = 695 - cur_seq->tex_level_lo[cur_seq->texture]; 696 - unsigned end = cur_seq->tex_level_hi[cur_seq->texture]; 697 - unsigned long lo = ~0, hi = 0, tmp; 698 - uint32_t *addr, *pitch, *height, tex; 699 - unsigned i; 700 - int npot; 701 - 702 - if (end > 9) 703 - end = 9; 704 - if (start > 9) 705 - start = 9; 706 - 707 - addr = 708 - &(cur_seq->t_addr[tex = cur_seq->texture][start]); 709 - pitch = &(cur_seq->pitch[tex][start]); 710 - height = &(cur_seq->height[tex][start]); 711 - npot = cur_seq->tex_npot[tex]; 712 - for (i = start; i <= end; ++i) { 713 - tmp = *addr++; 714 - if (tmp < lo) 715 - lo = tmp; 716 - if (i == 0 && npot) 717 - tmp += (*height++ * *pitch++); 718 - else 719 - tmp += (*height++ << *pitch++); 720 - if (tmp > hi) 721 - hi = tmp; 722 - } 723 - 724 - if (!via_drm_lookup_agp_map 725 - (cur_seq, lo, hi - lo, cur_seq->dev)) { 726 - DRM_ERROR 727 - ("AGP texture is not in allowed map\n"); 728 - return 2; 729 - } 730 - } 731 - break; 732 - default: 733 - break; 734 - } 735 - cur_seq->unfinished = no_sequence; 736 - return 0; 737 - } 738 - 739 - static __inline__ int 740 - investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq) 741 - { 742 - register uint32_t tmp, *tmp_addr; 743 - 744 - if (cur_seq->unfinished && (cur_seq->unfinished != seqs[hz])) { 745 - int ret; 746 - if ((ret = finish_current_sequence(cur_seq))) 747 - return ret; 748 - } 749 - 750 - switch (hz) { 751 - case check_for_header2: 752 - if (cmd == HALCYON_HEADER2) 753 - return 1; 754 - return 0; 755 - case check_for_header1: 756 - if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) 757 - return 1; 758 - return 0; 759 - case check_for_header2_err: 760 - if (cmd == HALCYON_HEADER2) 761 - return 1; 762 - DRM_ERROR("Illegal DMA HALCYON_HEADER2 command\n"); 763 - break; 764 - case check_for_header1_err: 765 - if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) 766 - return 1; 767 - DRM_ERROR("Illegal DMA HALCYON_HEADER1 command\n"); 768 - break; 769 - case check_for_fire: 770 - if ((cmd & HALCYON_FIREMASK) == HALCYON_FIRECMD) 771 - return 1; 772 - DRM_ERROR("Illegal DMA HALCYON_FIRECMD command\n"); 773 - break; 774 - case check_for_dummy: 775 - if (HC_DUMMY == cmd) 776 - return 0; 777 - DRM_ERROR("Illegal DMA HC_DUMMY command\n"); 778 - break; 779 - case check_for_dd: 780 - if (0xdddddddd == cmd) 781 - return 0; 782 - DRM_ERROR("Illegal DMA 0xdddddddd command\n"); 783 - break; 784 - case check_z_buffer_addr0: 785 - cur_seq->unfinished = z_address; 786 - cur_seq->z_addr = (cur_seq->z_addr & 0xFF000000) | 787 - (cmd & 0x00FFFFFF); 788 - return 0; 789 - case check_z_buffer_addr1: 790 - cur_seq->unfinished = z_address; 791 - cur_seq->z_addr = (cur_seq->z_addr & 0x00FFFFFF) | 792 - ((cmd & 0xFF) << 24); 793 - return 0; 794 - case check_z_buffer_addr_mode: 795 - cur_seq->unfinished = z_address; 796 - if ((cmd & 0x0000C000) == 0) 797 - return 0; 798 - DRM_ERROR("Attempt to place Z buffer in system memory\n"); 799 - return 2; 800 - case check_destination_addr0: 801 - cur_seq->unfinished = dest_address; 802 - cur_seq->d_addr = (cur_seq->d_addr & 0xFF000000) | 803 - (cmd & 0x00FFFFFF); 804 - return 0; 805 - case check_destination_addr1: 806 - cur_seq->unfinished = dest_address; 807 - cur_seq->d_addr = (cur_seq->d_addr & 0x00FFFFFF) | 808 - ((cmd & 0xFF) << 24); 809 - return 0; 810 - case check_destination_addr_mode: 811 - cur_seq->unfinished = dest_address; 812 - if ((cmd & 0x0000C000) == 0) 813 - return 0; 814 - DRM_ERROR 815 - ("Attempt to place 3D drawing buffer in system memory\n"); 816 - return 2; 817 - case check_texture_addr0: 818 - cur_seq->unfinished = tex_address; 819 - tmp = (cmd >> 24); 820 - tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp]; 821 - *tmp_addr = (*tmp_addr & 0xFF000000) | (cmd & 0x00FFFFFF); 822 - return 0; 823 - case check_texture_addr1: 824 - cur_seq->unfinished = tex_address; 825 - tmp = ((cmd >> 24) - 0x20); 826 - tmp += tmp << 1; 827 - tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp]; 828 - *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF) << 24); 829 - tmp_addr++; 830 - *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF00) << 16); 831 - tmp_addr++; 832 - *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF0000) << 8); 833 - return 0; 834 - case check_texture_addr2: 835 - cur_seq->unfinished = tex_address; 836 - cur_seq->tex_level_lo[tmp = cur_seq->texture] = cmd & 0x3F; 837 - cur_seq->tex_level_hi[tmp] = (cmd & 0xFC0) >> 6; 838 - return 0; 839 - case check_texture_addr3: 840 - cur_seq->unfinished = tex_address; 841 - tmp = ((cmd >> 24) - HC_SubA_HTXnL0Pit); 842 - if (tmp == 0 && 843 - (cmd & HC_HTXnEnPit_MASK)) { 844 - cur_seq->pitch[cur_seq->texture][tmp] = 845 - (cmd & HC_HTXnLnPit_MASK); 846 - cur_seq->tex_npot[cur_seq->texture] = 1; 847 - } else { 848 - cur_seq->pitch[cur_seq->texture][tmp] = 849 - (cmd & HC_HTXnLnPitE_MASK) >> HC_HTXnLnPitE_SHIFT; 850 - cur_seq->tex_npot[cur_seq->texture] = 0; 851 - if (cmd & 0x000FFFFF) { 852 - DRM_ERROR 853 - ("Unimplemented texture level 0 pitch mode.\n"); 854 - return 2; 855 - } 856 - } 857 - return 0; 858 - case check_texture_addr4: 859 - cur_seq->unfinished = tex_address; 860 - tmp_addr = &cur_seq->t_addr[cur_seq->texture][9]; 861 - *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF) << 24); 862 - return 0; 863 - case check_texture_addr5: 864 - case check_texture_addr6: 865 - cur_seq->unfinished = tex_address; 866 - /* 867 - * Texture width. We don't care since we have the pitch. 868 - */ 869 - return 0; 870 - case check_texture_addr7: 871 - cur_seq->unfinished = tex_address; 872 - tmp_addr = &(cur_seq->height[cur_seq->texture][0]); 873 - tmp_addr[5] = 1 << ((cmd & 0x00F00000) >> 20); 874 - tmp_addr[4] = 1 << ((cmd & 0x000F0000) >> 16); 875 - tmp_addr[3] = 1 << ((cmd & 0x0000F000) >> 12); 876 - tmp_addr[2] = 1 << ((cmd & 0x00000F00) >> 8); 877 - tmp_addr[1] = 1 << ((cmd & 0x000000F0) >> 4); 878 - tmp_addr[0] = 1 << (cmd & 0x0000000F); 879 - return 0; 880 - case check_texture_addr8: 881 - cur_seq->unfinished = tex_address; 882 - tmp_addr = &(cur_seq->height[cur_seq->texture][0]); 883 - tmp_addr[9] = 1 << ((cmd & 0x0000F000) >> 12); 884 - tmp_addr[8] = 1 << ((cmd & 0x00000F00) >> 8); 885 - tmp_addr[7] = 1 << ((cmd & 0x000000F0) >> 4); 886 - tmp_addr[6] = 1 << (cmd & 0x0000000F); 887 - return 0; 888 - case check_texture_addr_mode: 889 - cur_seq->unfinished = tex_address; 890 - if (2 == (tmp = cmd & 0x00000003)) { 891 - DRM_ERROR 892 - ("Attempt to fetch texture from system memory.\n"); 893 - return 2; 894 - } 895 - cur_seq->agp_texture = (tmp == 3); 896 - cur_seq->tex_palette_size[cur_seq->texture] = 897 - (cmd >> 16) & 0x000000007; 898 - return 0; 899 - case check_for_vertex_count: 900 - cur_seq->vertex_count = cmd & 0x0000FFFF; 901 - return 0; 902 - case check_number_texunits: 903 - cur_seq->multitex = (cmd >> 3) & 1; 904 - return 0; 905 - default: 906 - DRM_ERROR("Illegal DMA data: 0x%x\n", cmd); 907 - return 2; 908 - } 909 - return 2; 910 - } 911 - 912 - static __inline__ int 913 - via_check_prim_list(uint32_t const **buffer, const uint32_t * buf_end, 914 - drm_via_state_t *cur_seq) 915 - { 916 - drm_via_private_t *dev_priv = 917 - (drm_via_private_t *) cur_seq->dev->dev_private; 918 - uint32_t a_fire, bcmd, dw_count; 919 - int ret = 0; 920 - int have_fire; 921 - const uint32_t *buf = *buffer; 922 - 923 - while (buf < buf_end) { 924 - have_fire = 0; 925 - if ((buf_end - buf) < 2) { 926 - DRM_ERROR 927 - ("Unexpected termination of primitive list.\n"); 928 - ret = 1; 929 - break; 930 - } 931 - if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdB) 932 - break; 933 - bcmd = *buf++; 934 - if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdA) { 935 - DRM_ERROR("Expected Vertex List A command, got 0x%x\n", 936 - *buf); 937 - ret = 1; 938 - break; 939 - } 940 - a_fire = 941 - *buf++ | HC_HPLEND_MASK | HC_HPMValidN_MASK | 942 - HC_HE3Fire_MASK; 943 - 944 - /* 945 - * How many dwords per vertex ? 946 - */ 947 - 948 - if (cur_seq->agp && ((bcmd & (0xF << 11)) == 0)) { 949 - DRM_ERROR("Illegal B command vertex data for AGP.\n"); 950 - ret = 1; 951 - break; 952 - } 953 - 954 - dw_count = 0; 955 - if (bcmd & (1 << 7)) 956 - dw_count += (cur_seq->multitex) ? 2 : 1; 957 - if (bcmd & (1 << 8)) 958 - dw_count += (cur_seq->multitex) ? 2 : 1; 959 - if (bcmd & (1 << 9)) 960 - dw_count++; 961 - if (bcmd & (1 << 10)) 962 - dw_count++; 963 - if (bcmd & (1 << 11)) 964 - dw_count++; 965 - if (bcmd & (1 << 12)) 966 - dw_count++; 967 - if (bcmd & (1 << 13)) 968 - dw_count++; 969 - if (bcmd & (1 << 14)) 970 - dw_count++; 971 - 972 - while (buf < buf_end) { 973 - if (*buf == a_fire) { 974 - if (dev_priv->num_fire_offsets >= 975 - VIA_FIRE_BUF_SIZE) { 976 - DRM_ERROR("Fire offset buffer full.\n"); 977 - ret = 1; 978 - break; 979 - } 980 - dev_priv->fire_offsets[dev_priv-> 981 - num_fire_offsets++] = 982 - buf; 983 - have_fire = 1; 984 - buf++; 985 - if (buf < buf_end && *buf == a_fire) 986 - buf++; 987 - break; 988 - } 989 - if ((*buf == HALCYON_HEADER2) || 990 - ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) { 991 - DRM_ERROR("Missing Vertex Fire command, " 992 - "Stray Vertex Fire command or verifier " 993 - "lost sync.\n"); 994 - ret = 1; 995 - break; 996 - } 997 - if ((ret = eat_words(&buf, buf_end, dw_count))) 998 - break; 999 - } 1000 - if (buf >= buf_end && !have_fire) { 1001 - DRM_ERROR("Missing Vertex Fire command or verifier " 1002 - "lost sync.\n"); 1003 - ret = 1; 1004 - break; 1005 - } 1006 - if (cur_seq->agp && ((buf - cur_seq->buf_start) & 0x01)) { 1007 - DRM_ERROR("AGP Primitive list end misaligned.\n"); 1008 - ret = 1; 1009 - break; 1010 - } 1011 - } 1012 - *buffer = buf; 1013 - return ret; 1014 - } 1015 - 1016 - static __inline__ verifier_state_t 1017 - via_check_header2(uint32_t const **buffer, const uint32_t *buf_end, 1018 - drm_via_state_t *hc_state) 1019 - { 1020 - uint32_t cmd; 1021 - int hz_mode; 1022 - hazard_t hz; 1023 - const uint32_t *buf = *buffer; 1024 - const hazard_t *hz_table; 1025 - 1026 - if ((buf_end - buf) < 2) { 1027 - DRM_ERROR 1028 - ("Illegal termination of DMA HALCYON_HEADER2 sequence.\n"); 1029 - return state_error; 1030 - } 1031 - buf++; 1032 - cmd = (*buf++ & 0xFFFF0000) >> 16; 1033 - 1034 - switch (cmd) { 1035 - case HC_ParaType_CmdVdata: 1036 - if (via_check_prim_list(&buf, buf_end, hc_state)) 1037 - return state_error; 1038 - *buffer = buf; 1039 - return state_command; 1040 - case HC_ParaType_NotTex: 1041 - hz_table = table1; 1042 - break; 1043 - case HC_ParaType_Tex: 1044 - hc_state->texture = 0; 1045 - hz_table = table2; 1046 - break; 1047 - case (HC_ParaType_Tex | (HC_SubType_Tex1 << 8)): 1048 - hc_state->texture = 1; 1049 - hz_table = table2; 1050 - break; 1051 - case (HC_ParaType_Tex | (HC_SubType_TexGeneral << 8)): 1052 - hz_table = table3; 1053 - break; 1054 - case HC_ParaType_Auto: 1055 - if (eat_words(&buf, buf_end, 2)) 1056 - return state_error; 1057 - *buffer = buf; 1058 - return state_command; 1059 - case (HC_ParaType_Palette | (HC_SubType_Stipple << 8)): 1060 - if (eat_words(&buf, buf_end, 32)) 1061 - return state_error; 1062 - *buffer = buf; 1063 - return state_command; 1064 - case (HC_ParaType_Palette | (HC_SubType_TexPalette0 << 8)): 1065 - case (HC_ParaType_Palette | (HC_SubType_TexPalette1 << 8)): 1066 - DRM_ERROR("Texture palettes are rejected because of " 1067 - "lack of info how to determine their size.\n"); 1068 - return state_error; 1069 - case (HC_ParaType_Palette | (HC_SubType_FogTable << 8)): 1070 - DRM_ERROR("Fog factor palettes are rejected because of " 1071 - "lack of info how to determine their size.\n"); 1072 - return state_error; 1073 - default: 1074 - 1075 - /* 1076 - * There are some unimplemented HC_ParaTypes here, that 1077 - * need to be implemented if the Mesa driver is extended. 1078 - */ 1079 - 1080 - DRM_ERROR("Invalid or unimplemented HALCYON_HEADER2 " 1081 - "DMA subcommand: 0x%x. Previous dword: 0x%x\n", 1082 - cmd, *(buf - 2)); 1083 - *buffer = buf; 1084 - return state_error; 1085 - } 1086 - 1087 - while (buf < buf_end) { 1088 - cmd = *buf++; 1089 - if ((hz = hz_table[cmd >> 24])) { 1090 - if ((hz_mode = investigate_hazard(cmd, hz, hc_state))) { 1091 - if (hz_mode == 1) { 1092 - buf--; 1093 - break; 1094 - } 1095 - return state_error; 1096 - } 1097 - } else if (hc_state->unfinished && 1098 - finish_current_sequence(hc_state)) { 1099 - return state_error; 1100 - } 1101 - } 1102 - if (hc_state->unfinished && finish_current_sequence(hc_state)) 1103 - return state_error; 1104 - *buffer = buf; 1105 - return state_command; 1106 - } 1107 - 1108 - static __inline__ verifier_state_t 1109 - via_parse_header2(drm_via_private_t *dev_priv, uint32_t const **buffer, 1110 - const uint32_t *buf_end, int *fire_count) 1111 - { 1112 - uint32_t cmd; 1113 - const uint32_t *buf = *buffer; 1114 - const uint32_t *next_fire; 1115 - int burst = 0; 1116 - 1117 - next_fire = dev_priv->fire_offsets[*fire_count]; 1118 - buf++; 1119 - cmd = (*buf & 0xFFFF0000) >> 16; 1120 - via_write(dev_priv, HC_REG_TRANS_SET + HC_REG_BASE, *buf++); 1121 - switch (cmd) { 1122 - case HC_ParaType_CmdVdata: 1123 - while ((buf < buf_end) && 1124 - (*fire_count < dev_priv->num_fire_offsets) && 1125 - (*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB) { 1126 - while (buf <= next_fire) { 1127 - via_write(dev_priv, HC_REG_TRANS_SPACE + HC_REG_BASE + 1128 - (burst & 63), *buf++); 1129 - burst += 4; 1130 - } 1131 - if ((buf < buf_end) 1132 - && ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) 1133 - buf++; 1134 - 1135 - if (++(*fire_count) < dev_priv->num_fire_offsets) 1136 - next_fire = dev_priv->fire_offsets[*fire_count]; 1137 - } 1138 - break; 1139 - default: 1140 - while (buf < buf_end) { 1141 - 1142 - if (*buf == HC_HEADER2 || 1143 - (*buf & HALCYON_HEADER1MASK) == HALCYON_HEADER1 || 1144 - (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5 || 1145 - (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6) 1146 - break; 1147 - 1148 - via_write(dev_priv, HC_REG_TRANS_SPACE + HC_REG_BASE + 1149 - (burst & 63), *buf++); 1150 - burst += 4; 1151 - } 1152 - } 1153 - *buffer = buf; 1154 - return state_command; 1155 - } 1156 - 1157 - static __inline__ int verify_mmio_address(uint32_t address) 1158 - { 1159 - if ((address > 0x3FF) && (address < 0xC00)) { 1160 - DRM_ERROR("Invalid VIDEO DMA command. " 1161 - "Attempt to access 3D- or command burst area.\n"); 1162 - return 1; 1163 - } else if ((address > 0xCFF) && (address < 0x1300)) { 1164 - DRM_ERROR("Invalid VIDEO DMA command. " 1165 - "Attempt to access PCI DMA area.\n"); 1166 - return 1; 1167 - } else if (address > 0x13FF) { 1168 - DRM_ERROR("Invalid VIDEO DMA command. " 1169 - "Attempt to access VGA registers.\n"); 1170 - return 1; 1171 - } 1172 - return 0; 1173 - } 1174 - 1175 - static __inline__ int 1176 - verify_video_tail(uint32_t const **buffer, const uint32_t * buf_end, 1177 - uint32_t dwords) 1178 - { 1179 - const uint32_t *buf = *buffer; 1180 - 1181 - if (buf_end - buf < dwords) { 1182 - DRM_ERROR("Illegal termination of video command.\n"); 1183 - return 1; 1184 - } 1185 - while (dwords--) { 1186 - if (*buf++) { 1187 - DRM_ERROR("Illegal video command tail.\n"); 1188 - return 1; 1189 - } 1190 - } 1191 - *buffer = buf; 1192 - return 0; 1193 - } 1194 - 1195 - static __inline__ verifier_state_t 1196 - via_check_header1(uint32_t const **buffer, const uint32_t * buf_end) 1197 - { 1198 - uint32_t cmd; 1199 - const uint32_t *buf = *buffer; 1200 - verifier_state_t ret = state_command; 1201 - 1202 - while (buf < buf_end) { 1203 - cmd = *buf; 1204 - if ((cmd > ((0x3FF >> 2) | HALCYON_HEADER1)) && 1205 - (cmd < ((0xC00 >> 2) | HALCYON_HEADER1))) { 1206 - if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) 1207 - break; 1208 - DRM_ERROR("Invalid HALCYON_HEADER1 command. " 1209 - "Attempt to access 3D- or command burst area.\n"); 1210 - ret = state_error; 1211 - break; 1212 - } else if (cmd > ((0xCFF >> 2) | HALCYON_HEADER1)) { 1213 - if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) 1214 - break; 1215 - DRM_ERROR("Invalid HALCYON_HEADER1 command. " 1216 - "Attempt to access VGA registers.\n"); 1217 - ret = state_error; 1218 - break; 1219 - } else { 1220 - buf += 2; 1221 - } 1222 - } 1223 - *buffer = buf; 1224 - return ret; 1225 - } 1226 - 1227 - static __inline__ verifier_state_t 1228 - via_parse_header1(drm_via_private_t *dev_priv, uint32_t const **buffer, 1229 - const uint32_t *buf_end) 1230 - { 1231 - register uint32_t cmd; 1232 - const uint32_t *buf = *buffer; 1233 - 1234 - while (buf < buf_end) { 1235 - cmd = *buf; 1236 - if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) 1237 - break; 1238 - via_write(dev_priv, (cmd & ~HALCYON_HEADER1MASK) << 2, *++buf); 1239 - buf++; 1240 - } 1241 - *buffer = buf; 1242 - return state_command; 1243 - } 1244 - 1245 - static __inline__ verifier_state_t 1246 - via_check_vheader5(uint32_t const **buffer, const uint32_t *buf_end) 1247 - { 1248 - uint32_t data; 1249 - const uint32_t *buf = *buffer; 1250 - 1251 - if (buf_end - buf < 4) { 1252 - DRM_ERROR("Illegal termination of video header5 command\n"); 1253 - return state_error; 1254 - } 1255 - 1256 - data = *buf++ & ~VIA_VIDEOMASK; 1257 - if (verify_mmio_address(data)) 1258 - return state_error; 1259 - 1260 - data = *buf++; 1261 - if (*buf++ != 0x00F50000) { 1262 - DRM_ERROR("Illegal header5 header data\n"); 1263 - return state_error; 1264 - } 1265 - if (*buf++ != 0x00000000) { 1266 - DRM_ERROR("Illegal header5 header data\n"); 1267 - return state_error; 1268 - } 1269 - if (eat_words(&buf, buf_end, data)) 1270 - return state_error; 1271 - if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3))) 1272 - return state_error; 1273 - *buffer = buf; 1274 - return state_command; 1275 - 1276 - } 1277 - 1278 - static __inline__ verifier_state_t 1279 - via_parse_vheader5(drm_via_private_t *dev_priv, uint32_t const **buffer, 1280 - const uint32_t *buf_end) 1281 - { 1282 - uint32_t addr, count, i; 1283 - const uint32_t *buf = *buffer; 1284 - 1285 - addr = *buf++ & ~VIA_VIDEOMASK; 1286 - i = count = *buf; 1287 - buf += 3; 1288 - while (i--) 1289 - via_write(dev_priv, addr, *buf++); 1290 - if (count & 3) 1291 - buf += 4 - (count & 3); 1292 - *buffer = buf; 1293 - return state_command; 1294 - } 1295 - 1296 - static __inline__ verifier_state_t 1297 - via_check_vheader6(uint32_t const **buffer, const uint32_t * buf_end) 1298 - { 1299 - uint32_t data; 1300 - const uint32_t *buf = *buffer; 1301 - uint32_t i; 1302 - 1303 - if (buf_end - buf < 4) { 1304 - DRM_ERROR("Illegal termination of video header6 command\n"); 1305 - return state_error; 1306 - } 1307 - buf++; 1308 - data = *buf++; 1309 - if (*buf++ != 0x00F60000) { 1310 - DRM_ERROR("Illegal header6 header data\n"); 1311 - return state_error; 1312 - } 1313 - if (*buf++ != 0x00000000) { 1314 - DRM_ERROR("Illegal header6 header data\n"); 1315 - return state_error; 1316 - } 1317 - if ((buf_end - buf) < (data << 1)) { 1318 - DRM_ERROR("Illegal termination of video header6 command\n"); 1319 - return state_error; 1320 - } 1321 - for (i = 0; i < data; ++i) { 1322 - if (verify_mmio_address(*buf++)) 1323 - return state_error; 1324 - buf++; 1325 - } 1326 - data <<= 1; 1327 - if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3))) 1328 - return state_error; 1329 - *buffer = buf; 1330 - return state_command; 1331 - } 1332 - 1333 - static __inline__ verifier_state_t 1334 - via_parse_vheader6(drm_via_private_t *dev_priv, uint32_t const **buffer, 1335 - const uint32_t *buf_end) 1336 - { 1337 - 1338 - uint32_t addr, count, i; 1339 - const uint32_t *buf = *buffer; 1340 - 1341 - i = count = *++buf; 1342 - buf += 3; 1343 - while (i--) { 1344 - addr = *buf++; 1345 - via_write(dev_priv, addr, *buf++); 1346 - } 1347 - count <<= 1; 1348 - if (count & 3) 1349 - buf += 4 - (count & 3); 1350 - *buffer = buf; 1351 - return state_command; 1352 - } 1353 - 1354 - static int 1355 - via_verify_command_stream(const uint32_t * buf, unsigned int size, 1356 - struct drm_device * dev, int agp) 1357 - { 1358 - 1359 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 1360 - drm_via_state_t *hc_state = &dev_priv->hc_state; 1361 - drm_via_state_t saved_state = *hc_state; 1362 - uint32_t cmd; 1363 - const uint32_t *buf_end = buf + (size >> 2); 1364 - verifier_state_t state = state_command; 1365 - int cme_video; 1366 - int supported_3d; 1367 - 1368 - cme_video = (dev_priv->chipset == VIA_PRO_GROUP_A || 1369 - dev_priv->chipset == VIA_DX9_0); 1370 - 1371 - supported_3d = dev_priv->chipset != VIA_DX9_0; 1372 - 1373 - hc_state->dev = dev; 1374 - hc_state->unfinished = no_sequence; 1375 - hc_state->map_cache = NULL; 1376 - hc_state->agp = agp; 1377 - hc_state->buf_start = buf; 1378 - dev_priv->num_fire_offsets = 0; 1379 - 1380 - while (buf < buf_end) { 1381 - 1382 - switch (state) { 1383 - case state_header2: 1384 - state = via_check_header2(&buf, buf_end, hc_state); 1385 - break; 1386 - case state_header1: 1387 - state = via_check_header1(&buf, buf_end); 1388 - break; 1389 - case state_vheader5: 1390 - state = via_check_vheader5(&buf, buf_end); 1391 - break; 1392 - case state_vheader6: 1393 - state = via_check_vheader6(&buf, buf_end); 1394 - break; 1395 - case state_command: 1396 - cmd = *buf; 1397 - if ((cmd == HALCYON_HEADER2) && supported_3d) 1398 - state = state_header2; 1399 - else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) 1400 - state = state_header1; 1401 - else if (cme_video 1402 - && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5) 1403 - state = state_vheader5; 1404 - else if (cme_video 1405 - && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6) 1406 - state = state_vheader6; 1407 - else if ((cmd == HALCYON_HEADER2) && !supported_3d) { 1408 - DRM_ERROR("Accelerated 3D is not supported on this chipset yet.\n"); 1409 - state = state_error; 1410 - } else { 1411 - DRM_ERROR 1412 - ("Invalid / Unimplemented DMA HEADER command. 0x%x\n", 1413 - cmd); 1414 - state = state_error; 1415 - } 1416 - break; 1417 - case state_error: 1418 - default: 1419 - *hc_state = saved_state; 1420 - return -EINVAL; 1421 - } 1422 - } 1423 - if (state == state_error) { 1424 - *hc_state = saved_state; 1425 - return -EINVAL; 1426 - } 1427 - return 0; 1428 - } 1429 - 1430 - static int 1431 - via_parse_command_stream(struct drm_device *dev, const uint32_t *buf, 1432 - unsigned int size) 1433 - { 1434 - 1435 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 1436 - uint32_t cmd; 1437 - const uint32_t *buf_end = buf + (size >> 2); 1438 - verifier_state_t state = state_command; 1439 - int fire_count = 0; 1440 - 1441 - while (buf < buf_end) { 1442 - 1443 - switch (state) { 1444 - case state_header2: 1445 - state = 1446 - via_parse_header2(dev_priv, &buf, buf_end, 1447 - &fire_count); 1448 - break; 1449 - case state_header1: 1450 - state = via_parse_header1(dev_priv, &buf, buf_end); 1451 - break; 1452 - case state_vheader5: 1453 - state = via_parse_vheader5(dev_priv, &buf, buf_end); 1454 - break; 1455 - case state_vheader6: 1456 - state = via_parse_vheader6(dev_priv, &buf, buf_end); 1457 - break; 1458 - case state_command: 1459 - cmd = *buf; 1460 - if (cmd == HALCYON_HEADER2) 1461 - state = state_header2; 1462 - else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) 1463 - state = state_header1; 1464 - else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5) 1465 - state = state_vheader5; 1466 - else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6) 1467 - state = state_vheader6; 1468 - else { 1469 - DRM_ERROR 1470 - ("Invalid / Unimplemented DMA HEADER command. 0x%x\n", 1471 - cmd); 1472 - state = state_error; 1473 - } 1474 - break; 1475 - case state_error: 1476 - default: 1477 - return -EINVAL; 1478 - } 1479 - } 1480 - if (state == state_error) 1481 - return -EINVAL; 1482 - return 0; 1483 - } 1484 - 1485 - static void 1486 - setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size) 1487 - { 1488 - int i; 1489 - 1490 - for (i = 0; i < 256; ++i) 1491 - table[i] = forbidden_command; 1492 - 1493 - for (i = 0; i < size; ++i) 1494 - table[init_table[i].code] = init_table[i].hz; 1495 - } 1496 - 1497 - static void via_init_command_verifier(void) 1498 - { 1499 - setup_hazard_table(init_table1, table1, ARRAY_SIZE(init_table1)); 1500 - setup_hazard_table(init_table2, table2, ARRAY_SIZE(init_table2)); 1501 - setup_hazard_table(init_table3, table3, ARRAY_SIZE(init_table3)); 1502 - } 1503 - /* 1504 - * Unmap a DMA mapping. 1505 - */ 1506 - static void 1507 - via_unmap_blit_from_device(struct pci_dev *pdev, drm_via_sg_info_t *vsg) 1508 - { 1509 - int num_desc = vsg->num_desc; 1510 - unsigned cur_descriptor_page = num_desc / vsg->descriptors_per_page; 1511 - unsigned descriptor_this_page = num_desc % vsg->descriptors_per_page; 1512 - drm_via_descriptor_t *desc_ptr = vsg->desc_pages[cur_descriptor_page] + 1513 - descriptor_this_page; 1514 - dma_addr_t next = vsg->chain_start; 1515 - 1516 - while (num_desc--) { 1517 - if (descriptor_this_page-- == 0) { 1518 - cur_descriptor_page--; 1519 - descriptor_this_page = vsg->descriptors_per_page - 1; 1520 - desc_ptr = vsg->desc_pages[cur_descriptor_page] + 1521 - descriptor_this_page; 1522 - } 1523 - dma_unmap_single(&pdev->dev, next, sizeof(*desc_ptr), DMA_TO_DEVICE); 1524 - dma_unmap_page(&pdev->dev, desc_ptr->mem_addr, desc_ptr->size, vsg->direction); 1525 - next = (dma_addr_t) desc_ptr->next; 1526 - desc_ptr--; 1527 - } 1528 - } 1529 - 1530 - /* 1531 - * If mode = 0, count how many descriptors are needed. 1532 - * If mode = 1, Map the DMA pages for the device, put together and map also the descriptors. 1533 - * Descriptors are run in reverse order by the hardware because we are not allowed to update the 1534 - * 'next' field without syncing calls when the descriptor is already mapped. 1535 - */ 1536 - static void 1537 - via_map_blit_for_device(struct pci_dev *pdev, 1538 - const drm_via_dmablit_t *xfer, 1539 - drm_via_sg_info_t *vsg, 1540 - int mode) 1541 - { 1542 - unsigned cur_descriptor_page = 0; 1543 - unsigned num_descriptors_this_page = 0; 1544 - unsigned char *mem_addr = xfer->mem_addr; 1545 - unsigned char *cur_mem; 1546 - unsigned char *first_addr = (unsigned char *)VIA_PGDN(mem_addr); 1547 - uint32_t fb_addr = xfer->fb_addr; 1548 - uint32_t cur_fb; 1549 - unsigned long line_len; 1550 - unsigned remaining_len; 1551 - int num_desc = 0; 1552 - int cur_line; 1553 - dma_addr_t next = 0 | VIA_DMA_DPR_EC; 1554 - drm_via_descriptor_t *desc_ptr = NULL; 1555 - 1556 - if (mode == 1) 1557 - desc_ptr = vsg->desc_pages[cur_descriptor_page]; 1558 - 1559 - for (cur_line = 0; cur_line < xfer->num_lines; ++cur_line) { 1560 - 1561 - line_len = xfer->line_length; 1562 - cur_fb = fb_addr; 1563 - cur_mem = mem_addr; 1564 - 1565 - while (line_len > 0) { 1566 - 1567 - remaining_len = min(PAGE_SIZE-VIA_PGOFF(cur_mem), line_len); 1568 - line_len -= remaining_len; 1569 - 1570 - if (mode == 1) { 1571 - desc_ptr->mem_addr = 1572 - dma_map_page(&pdev->dev, 1573 - vsg->pages[VIA_PFN(cur_mem) - 1574 - VIA_PFN(first_addr)], 1575 - VIA_PGOFF(cur_mem), remaining_len, 1576 - vsg->direction); 1577 - desc_ptr->dev_addr = cur_fb; 1578 - 1579 - desc_ptr->size = remaining_len; 1580 - desc_ptr->next = (uint32_t) next; 1581 - next = dma_map_single(&pdev->dev, desc_ptr, sizeof(*desc_ptr), 1582 - DMA_TO_DEVICE); 1583 - desc_ptr++; 1584 - if (++num_descriptors_this_page >= vsg->descriptors_per_page) { 1585 - num_descriptors_this_page = 0; 1586 - desc_ptr = vsg->desc_pages[++cur_descriptor_page]; 1587 - } 1588 - } 1589 - 1590 - num_desc++; 1591 - cur_mem += remaining_len; 1592 - cur_fb += remaining_len; 1593 - } 1594 - 1595 - mem_addr += xfer->mem_stride; 1596 - fb_addr += xfer->fb_stride; 1597 - } 1598 - 1599 - if (mode == 1) { 1600 - vsg->chain_start = next; 1601 - vsg->state = dr_via_device_mapped; 1602 - } 1603 - vsg->num_desc = num_desc; 1604 - } 1605 - 1606 - /* 1607 - * Function that frees up all resources for a blit. It is usable even if the 1608 - * blit info has only been partially built as long as the status enum is consistent 1609 - * with the actual status of the used resources. 1610 - */ 1611 - static void 1612 - via_free_sg_info(struct pci_dev *pdev, drm_via_sg_info_t *vsg) 1613 - { 1614 - int i; 1615 - 1616 - switch (vsg->state) { 1617 - case dr_via_device_mapped: 1618 - via_unmap_blit_from_device(pdev, vsg); 1619 - fallthrough; 1620 - case dr_via_desc_pages_alloc: 1621 - for (i = 0; i < vsg->num_desc_pages; ++i) { 1622 - if (vsg->desc_pages[i] != NULL) 1623 - free_page((unsigned long)vsg->desc_pages[i]); 1624 - } 1625 - kfree(vsg->desc_pages); 1626 - fallthrough; 1627 - case dr_via_pages_locked: 1628 - unpin_user_pages_dirty_lock(vsg->pages, vsg->num_pages, 1629 - (vsg->direction == DMA_FROM_DEVICE)); 1630 - fallthrough; 1631 - case dr_via_pages_alloc: 1632 - vfree(vsg->pages); 1633 - fallthrough; 1634 - default: 1635 - vsg->state = dr_via_sg_init; 1636 - } 1637 - vfree(vsg->bounce_buffer); 1638 - vsg->bounce_buffer = NULL; 1639 - vsg->free_on_sequence = 0; 1640 - } 1641 - 1642 - /* 1643 - * Fire a blit engine. 1644 - */ 1645 - static void 1646 - via_fire_dmablit(struct drm_device *dev, drm_via_sg_info_t *vsg, int engine) 1647 - { 1648 - drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 1649 - 1650 - via_write(dev_priv, VIA_PCI_DMA_MAR0 + engine*0x10, 0); 1651 - via_write(dev_priv, VIA_PCI_DMA_DAR0 + engine*0x10, 0); 1652 - via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD | 1653 - VIA_DMA_CSR_DE); 1654 - via_write(dev_priv, VIA_PCI_DMA_MR0 + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE); 1655 - via_write(dev_priv, VIA_PCI_DMA_BCR0 + engine*0x10, 0); 1656 - via_write(dev_priv, VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start); 1657 - wmb(); 1658 - via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS); 1659 - via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04); 1660 - } 1661 - 1662 - /* 1663 - * Obtain a page pointer array and lock all pages into system memory. A segmentation violation will 1664 - * occur here if the calling user does not have access to the submitted address. 1665 - */ 1666 - static int 1667 - via_lock_all_dma_pages(drm_via_sg_info_t *vsg, drm_via_dmablit_t *xfer) 1668 - { 1669 - int ret; 1670 - unsigned long first_pfn = VIA_PFN(xfer->mem_addr); 1671 - vsg->num_pages = VIA_PFN(xfer->mem_addr + (xfer->num_lines * xfer->mem_stride - 1)) - 1672 - first_pfn + 1; 1673 - 1674 - vsg->pages = vzalloc(array_size(sizeof(struct page *), vsg->num_pages)); 1675 - if (NULL == vsg->pages) 1676 - return -ENOMEM; 1677 - ret = pin_user_pages_fast((unsigned long)xfer->mem_addr, 1678 - vsg->num_pages, 1679 - vsg->direction == DMA_FROM_DEVICE ? FOLL_WRITE : 0, 1680 - vsg->pages); 1681 - if (ret != vsg->num_pages) { 1682 - if (ret < 0) 1683 - return ret; 1684 - vsg->state = dr_via_pages_locked; 1685 - return -EINVAL; 1686 - } 1687 - vsg->state = dr_via_pages_locked; 1688 - DRM_DEBUG("DMA pages locked\n"); 1689 - return 0; 1690 - } 1691 - 1692 - /* 1693 - * Allocate DMA capable memory for the blit descriptor chain, and an array that keeps track of the 1694 - * pages we allocate. We don't want to use kmalloc for the descriptor chain because it may be 1695 - * quite large for some blits, and pages don't need to be contiguous. 1696 - */ 1697 - static int 1698 - via_alloc_desc_pages(drm_via_sg_info_t *vsg) 1699 - { 1700 - int i; 1701 - 1702 - vsg->descriptors_per_page = PAGE_SIZE / sizeof(drm_via_descriptor_t); 1703 - vsg->num_desc_pages = (vsg->num_desc + vsg->descriptors_per_page - 1) / 1704 - vsg->descriptors_per_page; 1705 - 1706 - if (NULL == (vsg->desc_pages = kcalloc(vsg->num_desc_pages, sizeof(void *), GFP_KERNEL))) 1707 - return -ENOMEM; 1708 - 1709 - vsg->state = dr_via_desc_pages_alloc; 1710 - for (i = 0; i < vsg->num_desc_pages; ++i) { 1711 - if (NULL == (vsg->desc_pages[i] = 1712 - (drm_via_descriptor_t *) __get_free_page(GFP_KERNEL))) 1713 - return -ENOMEM; 1714 - } 1715 - DRM_DEBUG("Allocated %d pages for %d descriptors.\n", vsg->num_desc_pages, 1716 - vsg->num_desc); 1717 - return 0; 1718 - } 1719 - 1720 - static void 1721 - via_abort_dmablit(struct drm_device *dev, int engine) 1722 - { 1723 - drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 1724 - 1725 - via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA); 1726 - } 1727 - 1728 - static void 1729 - via_dmablit_engine_off(struct drm_device *dev, int engine) 1730 - { 1731 - drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 1732 - 1733 - via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD); 1734 - } 1735 - 1736 - /* 1737 - * The dmablit part of the IRQ handler. Trying to do only reasonably fast things here. 1738 - * The rest, like unmapping and freeing memory for done blits is done in a separate workqueue 1739 - * task. Basically the task of the interrupt handler is to submit a new blit to the engine, while 1740 - * the workqueue task takes care of processing associated with the old blit. 1741 - */ 1742 - static void 1743 - via_dmablit_handler(struct drm_device *dev, int engine, int from_irq) 1744 - { 1745 - drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 1746 - drm_via_blitq_t *blitq = dev_priv->blit_queues + engine; 1747 - int cur; 1748 - int done_transfer; 1749 - unsigned long irqsave = 0; 1750 - uint32_t status = 0; 1751 - 1752 - DRM_DEBUG("DMA blit handler called. engine = %d, from_irq = %d, blitq = 0x%lx\n", 1753 - engine, from_irq, (unsigned long) blitq); 1754 - 1755 - if (from_irq) 1756 - spin_lock(&blitq->blit_lock); 1757 - else 1758 - spin_lock_irqsave(&blitq->blit_lock, irqsave); 1759 - 1760 - done_transfer = blitq->is_active && 1761 - ((status = via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD); 1762 - done_transfer = done_transfer || (blitq->aborting && !(status & VIA_DMA_CSR_DE)); 1763 - 1764 - cur = blitq->cur; 1765 - if (done_transfer) { 1766 - 1767 - blitq->blits[cur]->aborted = blitq->aborting; 1768 - blitq->done_blit_handle++; 1769 - wake_up(blitq->blit_queue + cur); 1770 - 1771 - cur++; 1772 - if (cur >= VIA_NUM_BLIT_SLOTS) 1773 - cur = 0; 1774 - blitq->cur = cur; 1775 - 1776 - /* 1777 - * Clear transfer done flag. 1778 - */ 1779 - 1780 - via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD); 1781 - 1782 - blitq->is_active = 0; 1783 - blitq->aborting = 0; 1784 - schedule_work(&blitq->wq); 1785 - 1786 - } else if (blitq->is_active && time_after_eq(jiffies, blitq->end)) { 1787 - 1788 - /* 1789 - * Abort transfer after one second. 1790 - */ 1791 - 1792 - via_abort_dmablit(dev, engine); 1793 - blitq->aborting = 1; 1794 - blitq->end = jiffies + HZ; 1795 - } 1796 - 1797 - if (!blitq->is_active) { 1798 - if (blitq->num_outstanding) { 1799 - via_fire_dmablit(dev, blitq->blits[cur], engine); 1800 - blitq->is_active = 1; 1801 - blitq->cur = cur; 1802 - blitq->num_outstanding--; 1803 - blitq->end = jiffies + HZ; 1804 - if (!timer_pending(&blitq->poll_timer)) 1805 - mod_timer(&blitq->poll_timer, jiffies + 1); 1806 - } else { 1807 - if (timer_pending(&blitq->poll_timer)) 1808 - del_timer(&blitq->poll_timer); 1809 - via_dmablit_engine_off(dev, engine); 1810 - } 1811 - } 1812 - 1813 - if (from_irq) 1814 - spin_unlock(&blitq->blit_lock); 1815 - else 1816 - spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 1817 - } 1818 - 1819 - /* 1820 - * Check whether this blit is still active, performing necessary locking. 1821 - */ 1822 - static int 1823 - via_dmablit_active(drm_via_blitq_t *blitq, int engine, uint32_t handle, wait_queue_head_t **queue) 1824 - { 1825 - unsigned long irqsave; 1826 - uint32_t slot; 1827 - int active; 1828 - 1829 - spin_lock_irqsave(&blitq->blit_lock, irqsave); 1830 - 1831 - /* 1832 - * Allow for handle wraparounds. 1833 - */ 1834 - 1835 - active = ((blitq->done_blit_handle - handle) > (1 << 23)) && 1836 - ((blitq->cur_blit_handle - handle) <= (1 << 23)); 1837 - 1838 - if (queue && active) { 1839 - slot = handle - blitq->done_blit_handle + blitq->cur - 1; 1840 - if (slot >= VIA_NUM_BLIT_SLOTS) 1841 - slot -= VIA_NUM_BLIT_SLOTS; 1842 - *queue = blitq->blit_queue + slot; 1843 - } 1844 - 1845 - spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 1846 - 1847 - return active; 1848 - } 1849 - 1850 - /* 1851 - * Sync. Wait for at least three seconds for the blit to be performed. 1852 - */ 1853 - static int 1854 - via_dmablit_sync(struct drm_device *dev, uint32_t handle, int engine) 1855 - { 1856 - 1857 - drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 1858 - drm_via_blitq_t *blitq = dev_priv->blit_queues + engine; 1859 - wait_queue_head_t *queue; 1860 - int ret = 0; 1861 - 1862 - if (via_dmablit_active(blitq, engine, handle, &queue)) { 1863 - VIA_WAIT_ON(ret, *queue, 3 * HZ, 1864 - !via_dmablit_active(blitq, engine, handle, NULL)); 1865 - } 1866 - DRM_DEBUG("DMA blit sync handle 0x%x engine %d returned %d\n", 1867 - handle, engine, ret); 1868 - 1869 - return ret; 1870 - } 1871 - 1872 - /* 1873 - * A timer that regularly polls the blit engine in cases where we don't have interrupts: 1874 - * a) Broken hardware (typically those that don't have any video capture facility). 1875 - * b) Blit abort. The hardware doesn't send an interrupt when a blit is aborted. 1876 - * The timer and hardware IRQ's can and do work in parallel. If the hardware has 1877 - * irqs, it will shorten the latency somewhat. 1878 - */ 1879 - static void 1880 - via_dmablit_timer(struct timer_list *t) 1881 - { 1882 - drm_via_blitq_t *blitq = from_timer(blitq, t, poll_timer); 1883 - struct drm_device *dev = blitq->dev; 1884 - int engine = (int) 1885 - (blitq - ((drm_via_private_t *)dev->dev_private)->blit_queues); 1886 - 1887 - DRM_DEBUG("Polling timer called for engine %d, jiffies %lu\n", engine, 1888 - (unsigned long) jiffies); 1889 - 1890 - via_dmablit_handler(dev, engine, 0); 1891 - 1892 - if (!timer_pending(&blitq->poll_timer)) { 1893 - mod_timer(&blitq->poll_timer, jiffies + 1); 1894 - 1895 - /* 1896 - * Rerun handler to delete timer if engines are off, and 1897 - * to shorten abort latency. This is a little nasty. 1898 - */ 1899 - 1900 - via_dmablit_handler(dev, engine, 0); 1901 - 1902 - } 1903 - } 1904 - 1905 - /* 1906 - * Workqueue task that frees data and mappings associated with a blit. 1907 - * Also wakes up waiting processes. Each of these tasks handles one 1908 - * blit engine only and may not be called on each interrupt. 1909 - */ 1910 - static void 1911 - via_dmablit_workqueue(struct work_struct *work) 1912 - { 1913 - drm_via_blitq_t *blitq = container_of(work, drm_via_blitq_t, wq); 1914 - struct drm_device *dev = blitq->dev; 1915 - struct pci_dev *pdev = to_pci_dev(dev->dev); 1916 - unsigned long irqsave; 1917 - drm_via_sg_info_t *cur_sg; 1918 - int cur_released; 1919 - 1920 - 1921 - DRM_DEBUG("Workqueue task called for blit engine %ld\n", (unsigned long) 1922 - (blitq - ((drm_via_private_t *)dev->dev_private)->blit_queues)); 1923 - 1924 - spin_lock_irqsave(&blitq->blit_lock, irqsave); 1925 - 1926 - while (blitq->serviced != blitq->cur) { 1927 - 1928 - cur_released = blitq->serviced++; 1929 - 1930 - DRM_DEBUG("Releasing blit slot %d\n", cur_released); 1931 - 1932 - if (blitq->serviced >= VIA_NUM_BLIT_SLOTS) 1933 - blitq->serviced = 0; 1934 - 1935 - cur_sg = blitq->blits[cur_released]; 1936 - blitq->num_free++; 1937 - 1938 - spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 1939 - 1940 - wake_up(&blitq->busy_queue); 1941 - 1942 - via_free_sg_info(pdev, cur_sg); 1943 - kfree(cur_sg); 1944 - 1945 - spin_lock_irqsave(&blitq->blit_lock, irqsave); 1946 - } 1947 - 1948 - spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 1949 - } 1950 - 1951 - /* 1952 - * Init all blit engines. Currently we use two, but some hardware have 4. 1953 - */ 1954 - static void 1955 - via_init_dmablit(struct drm_device *dev) 1956 - { 1957 - int i, j; 1958 - drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 1959 - struct pci_dev *pdev = to_pci_dev(dev->dev); 1960 - drm_via_blitq_t *blitq; 1961 - 1962 - pci_set_master(pdev); 1963 - 1964 - for (i = 0; i < VIA_NUM_BLIT_ENGINES; ++i) { 1965 - blitq = dev_priv->blit_queues + i; 1966 - blitq->dev = dev; 1967 - blitq->cur_blit_handle = 0; 1968 - blitq->done_blit_handle = 0; 1969 - blitq->head = 0; 1970 - blitq->cur = 0; 1971 - blitq->serviced = 0; 1972 - blitq->num_free = VIA_NUM_BLIT_SLOTS - 1; 1973 - blitq->num_outstanding = 0; 1974 - blitq->is_active = 0; 1975 - blitq->aborting = 0; 1976 - spin_lock_init(&blitq->blit_lock); 1977 - for (j = 0; j < VIA_NUM_BLIT_SLOTS; ++j) 1978 - init_waitqueue_head(blitq->blit_queue + j); 1979 - init_waitqueue_head(&blitq->busy_queue); 1980 - INIT_WORK(&blitq->wq, via_dmablit_workqueue); 1981 - timer_setup(&blitq->poll_timer, via_dmablit_timer, 0); 1982 - } 1983 - } 1984 - 1985 - /* 1986 - * Build all info and do all mappings required for a blit. 1987 - */ 1988 - static int 1989 - via_build_sg_info(struct drm_device *dev, drm_via_sg_info_t *vsg, drm_via_dmablit_t *xfer) 1990 - { 1991 - struct pci_dev *pdev = to_pci_dev(dev->dev); 1992 - int draw = xfer->to_fb; 1993 - int ret = 0; 1994 - 1995 - vsg->direction = (draw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 1996 - vsg->bounce_buffer = NULL; 1997 - 1998 - vsg->state = dr_via_sg_init; 1999 - 2000 - if (xfer->num_lines <= 0 || xfer->line_length <= 0) { 2001 - DRM_ERROR("Zero size bitblt.\n"); 2002 - return -EINVAL; 2003 - } 2004 - 2005 - /* 2006 - * Below check is a driver limitation, not a hardware one. We 2007 - * don't want to lock unused pages, and don't want to incoporate the 2008 - * extra logic of avoiding them. Make sure there are no. 2009 - * (Not a big limitation anyway.) 2010 - */ 2011 - 2012 - if ((xfer->mem_stride - xfer->line_length) > 2*PAGE_SIZE) { 2013 - DRM_ERROR("Too large system memory stride. Stride: %d, " 2014 - "Length: %d\n", xfer->mem_stride, xfer->line_length); 2015 - return -EINVAL; 2016 - } 2017 - 2018 - if ((xfer->mem_stride == xfer->line_length) && 2019 - (xfer->fb_stride == xfer->line_length)) { 2020 - xfer->mem_stride *= xfer->num_lines; 2021 - xfer->line_length = xfer->mem_stride; 2022 - xfer->fb_stride = xfer->mem_stride; 2023 - xfer->num_lines = 1; 2024 - } 2025 - 2026 - /* 2027 - * Don't lock an arbitrary large number of pages, since that causes a 2028 - * DOS security hole. 2029 - */ 2030 - 2031 - if (xfer->num_lines > 2048 || (xfer->num_lines*xfer->mem_stride > (2048*2048*4))) { 2032 - DRM_ERROR("Too large PCI DMA bitblt.\n"); 2033 - return -EINVAL; 2034 - } 2035 - 2036 - /* 2037 - * we allow a negative fb stride to allow flipping of images in 2038 - * transfer. 2039 - */ 2040 - 2041 - if (xfer->mem_stride < xfer->line_length || 2042 - abs(xfer->fb_stride) < xfer->line_length) { 2043 - DRM_ERROR("Invalid frame-buffer / memory stride.\n"); 2044 - return -EINVAL; 2045 - } 2046 - 2047 - /* 2048 - * A hardware bug seems to be worked around if system memory addresses start on 2049 - * 16 byte boundaries. This seems a bit restrictive however. VIA is contacted 2050 - * about this. Meanwhile, impose the following restrictions: 2051 - */ 2052 - 2053 - #ifdef VIA_BUGFREE 2054 - if ((((unsigned long)xfer->mem_addr & 3) != ((unsigned long)xfer->fb_addr & 3)) || 2055 - ((xfer->num_lines > 1) && ((xfer->mem_stride & 3) != (xfer->fb_stride & 3)))) { 2056 - DRM_ERROR("Invalid DRM bitblt alignment.\n"); 2057 - return -EINVAL; 2058 - } 2059 - #else 2060 - if ((((unsigned long)xfer->mem_addr & 15) || 2061 - ((unsigned long)xfer->fb_addr & 3)) || 2062 - ((xfer->num_lines > 1) && 2063 - ((xfer->mem_stride & 15) || (xfer->fb_stride & 3)))) { 2064 - DRM_ERROR("Invalid DRM bitblt alignment.\n"); 2065 - return -EINVAL; 2066 - } 2067 - #endif 2068 - 2069 - if (0 != (ret = via_lock_all_dma_pages(vsg, xfer))) { 2070 - DRM_ERROR("Could not lock DMA pages.\n"); 2071 - via_free_sg_info(pdev, vsg); 2072 - return ret; 2073 - } 2074 - 2075 - via_map_blit_for_device(pdev, xfer, vsg, 0); 2076 - if (0 != (ret = via_alloc_desc_pages(vsg))) { 2077 - DRM_ERROR("Could not allocate DMA descriptor pages.\n"); 2078 - via_free_sg_info(pdev, vsg); 2079 - return ret; 2080 - } 2081 - via_map_blit_for_device(pdev, xfer, vsg, 1); 2082 - 2083 - return 0; 2084 - } 2085 - 2086 - /* 2087 - * Reserve one free slot in the blit queue. Will wait for one second for one 2088 - * to become available. Otherwise -EBUSY is returned. 2089 - */ 2090 - static int 2091 - via_dmablit_grab_slot(drm_via_blitq_t *blitq, int engine) 2092 - { 2093 - int ret = 0; 2094 - unsigned long irqsave; 2095 - 2096 - DRM_DEBUG("Num free is %d\n", blitq->num_free); 2097 - spin_lock_irqsave(&blitq->blit_lock, irqsave); 2098 - while (blitq->num_free == 0) { 2099 - spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 2100 - 2101 - VIA_WAIT_ON(ret, blitq->busy_queue, HZ, blitq->num_free > 0); 2102 - if (ret) 2103 - return (-EINTR == ret) ? -EAGAIN : ret; 2104 - 2105 - spin_lock_irqsave(&blitq->blit_lock, irqsave); 2106 - } 2107 - 2108 - blitq->num_free--; 2109 - spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 2110 - 2111 - return 0; 2112 - } 2113 - 2114 - /* 2115 - * Hand back a free slot if we changed our mind. 2116 - */ 2117 - static void 2118 - via_dmablit_release_slot(drm_via_blitq_t *blitq) 2119 - { 2120 - unsigned long irqsave; 2121 - 2122 - spin_lock_irqsave(&blitq->blit_lock, irqsave); 2123 - blitq->num_free++; 2124 - spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 2125 - wake_up(&blitq->busy_queue); 2126 - } 2127 - 2128 - /* 2129 - * Grab a free slot. Build blit info and queue a blit. 2130 - */ 2131 - static int 2132 - via_dmablit(struct drm_device *dev, drm_via_dmablit_t *xfer) 2133 - { 2134 - drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; 2135 - drm_via_sg_info_t *vsg; 2136 - drm_via_blitq_t *blitq; 2137 - int ret; 2138 - int engine; 2139 - unsigned long irqsave; 2140 - 2141 - if (dev_priv == NULL) { 2142 - DRM_ERROR("Called without initialization.\n"); 2143 - return -EINVAL; 2144 - } 2145 - 2146 - engine = (xfer->to_fb) ? 0 : 1; 2147 - blitq = dev_priv->blit_queues + engine; 2148 - if (0 != (ret = via_dmablit_grab_slot(blitq, engine))) 2149 - return ret; 2150 - if (NULL == (vsg = kmalloc(sizeof(*vsg), GFP_KERNEL))) { 2151 - via_dmablit_release_slot(blitq); 2152 - return -ENOMEM; 2153 - } 2154 - if (0 != (ret = via_build_sg_info(dev, vsg, xfer))) { 2155 - via_dmablit_release_slot(blitq); 2156 - kfree(vsg); 2157 - return ret; 2158 - } 2159 - spin_lock_irqsave(&blitq->blit_lock, irqsave); 2160 - 2161 - blitq->blits[blitq->head++] = vsg; 2162 - if (blitq->head >= VIA_NUM_BLIT_SLOTS) 2163 - blitq->head = 0; 2164 - blitq->num_outstanding++; 2165 - xfer->sync.sync_handle = ++blitq->cur_blit_handle; 2166 - 2167 - spin_unlock_irqrestore(&blitq->blit_lock, irqsave); 2168 - xfer->sync.engine = engine; 2169 - 2170 - via_dmablit_handler(dev, engine, 0); 2171 - 2172 - return 0; 2173 - } 2174 - 2175 - /* 2176 - * Sync on a previously submitted blit. Note that the X server use signals extensively, and 2177 - * that there is a very big probability that this IOCTL will be interrupted by a signal. In that 2178 - * case it returns with -EAGAIN for the signal to be delivered. 2179 - * The caller should then reissue the IOCTL. This is similar to what is being done for drmGetLock(). 2180 - */ 2181 - static int 2182 - via_dma_blit_sync(struct drm_device *dev, void *data, struct drm_file *file_priv) 2183 - { 2184 - drm_via_blitsync_t *sync = data; 2185 - int err; 2186 - 2187 - if (sync->engine >= VIA_NUM_BLIT_ENGINES) 2188 - return -EINVAL; 2189 - 2190 - err = via_dmablit_sync(dev, sync->sync_handle, sync->engine); 2191 - 2192 - if (-EINTR == err) 2193 - err = -EAGAIN; 2194 - 2195 - return err; 2196 - } 2197 - 2198 - /* 2199 - * Queue a blit and hand back a handle to be used for sync. This IOCTL may be interrupted by a signal 2200 - * while waiting for a free slot in the blit queue. In that case it returns with -EAGAIN and should 2201 - * be reissued. See the above IOCTL code. 2202 - */ 2203 - static int 2204 - via_dma_blit(struct drm_device *dev, void *data, struct drm_file *file_priv) 2205 - { 2206 - drm_via_dmablit_t *xfer = data; 2207 - int err; 2208 - 2209 - err = via_dmablit(dev, xfer); 2210 - 2211 - return err; 2212 - } 2213 - 2214 - static u32 via_get_vblank_counter(struct drm_device *dev, unsigned int pipe) 2215 - { 2216 - drm_via_private_t *dev_priv = dev->dev_private; 2217 - 2218 - if (pipe != 0) 2219 - return 0; 2220 - 2221 - return atomic_read(&dev_priv->vbl_received); 2222 - } 2223 - 2224 - static irqreturn_t via_driver_irq_handler(int irq, void *arg) 2225 - { 2226 - struct drm_device *dev = (struct drm_device *) arg; 2227 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 2228 - u32 status; 2229 - int handled = 0; 2230 - ktime_t cur_vblank; 2231 - drm_via_irq_t *cur_irq = dev_priv->via_irqs; 2232 - int i; 2233 - 2234 - status = via_read(dev_priv, VIA_REG_INTERRUPT); 2235 - if (status & VIA_IRQ_VBLANK_PENDING) { 2236 - atomic_inc(&dev_priv->vbl_received); 2237 - if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) { 2238 - cur_vblank = ktime_get(); 2239 - if (dev_priv->last_vblank_valid) { 2240 - dev_priv->nsec_per_vblank = 2241 - ktime_sub(cur_vblank, 2242 - dev_priv->last_vblank) >> 4; 2243 - } 2244 - dev_priv->last_vblank = cur_vblank; 2245 - dev_priv->last_vblank_valid = 1; 2246 - } 2247 - if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) { 2248 - DRM_DEBUG("nsec per vblank is: %llu\n", 2249 - ktime_to_ns(dev_priv->nsec_per_vblank)); 2250 - } 2251 - drm_handle_vblank(dev, 0); 2252 - handled = 1; 2253 - } 2254 - 2255 - for (i = 0; i < dev_priv->num_irqs; ++i) { 2256 - if (status & cur_irq->pending_mask) { 2257 - atomic_inc(&cur_irq->irq_received); 2258 - wake_up(&cur_irq->irq_queue); 2259 - handled = 1; 2260 - if (dev_priv->irq_map[drm_via_irq_dma0_td] == i) 2261 - via_dmablit_handler(dev, 0, 1); 2262 - else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i) 2263 - via_dmablit_handler(dev, 1, 1); 2264 - } 2265 - cur_irq++; 2266 - } 2267 - 2268 - /* Acknowledge interrupts */ 2269 - via_write(dev_priv, VIA_REG_INTERRUPT, status); 2270 - 2271 - 2272 - if (handled) 2273 - return IRQ_HANDLED; 2274 - else 2275 - return IRQ_NONE; 2276 - } 2277 - 2278 - static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t *dev_priv) 2279 - { 2280 - u32 status; 2281 - 2282 - if (dev_priv) { 2283 - /* Acknowledge interrupts */ 2284 - status = via_read(dev_priv, VIA_REG_INTERRUPT); 2285 - via_write(dev_priv, VIA_REG_INTERRUPT, status | 2286 - dev_priv->irq_pending_mask); 2287 - } 2288 - } 2289 - 2290 - static int via_enable_vblank(struct drm_device *dev, unsigned int pipe) 2291 - { 2292 - drm_via_private_t *dev_priv = dev->dev_private; 2293 - u32 status; 2294 - 2295 - if (pipe != 0) { 2296 - DRM_ERROR("%s: bad crtc %u\n", __func__, pipe); 2297 - return -EINVAL; 2298 - } 2299 - 2300 - status = via_read(dev_priv, VIA_REG_INTERRUPT); 2301 - via_write(dev_priv, VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE); 2302 - 2303 - via_write8(dev_priv, 0x83d4, 0x11); 2304 - via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30); 2305 - 2306 - return 0; 2307 - } 2308 - 2309 - static void via_disable_vblank(struct drm_device *dev, unsigned int pipe) 2310 - { 2311 - drm_via_private_t *dev_priv = dev->dev_private; 2312 - u32 status; 2313 - 2314 - status = via_read(dev_priv, VIA_REG_INTERRUPT); 2315 - via_write(dev_priv, VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE); 2316 - 2317 - via_write8(dev_priv, 0x83d4, 0x11); 2318 - via_write8_mask(dev_priv, 0x83d5, 0x30, 0); 2319 - 2320 - if (pipe != 0) 2321 - DRM_ERROR("%s: bad crtc %u\n", __func__, pipe); 2322 - } 2323 - 2324 - static int 2325 - via_driver_irq_wait(struct drm_device *dev, unsigned int irq, int force_sequence, 2326 - unsigned int *sequence) 2327 - { 2328 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 2329 - unsigned int cur_irq_sequence; 2330 - drm_via_irq_t *cur_irq; 2331 - int ret = 0; 2332 - maskarray_t *masks; 2333 - int real_irq; 2334 - 2335 - DRM_DEBUG("\n"); 2336 - 2337 - if (!dev_priv) { 2338 - DRM_ERROR("called with no initialization\n"); 2339 - return -EINVAL; 2340 - } 2341 - 2342 - if (irq >= drm_via_irq_num) { 2343 - DRM_ERROR("Trying to wait on unknown irq %d\n", irq); 2344 - return -EINVAL; 2345 - } 2346 - 2347 - real_irq = dev_priv->irq_map[irq]; 2348 - 2349 - if (real_irq < 0) { 2350 - DRM_ERROR("Video IRQ %d not available on this hardware.\n", 2351 - irq); 2352 - return -EINVAL; 2353 - } 2354 - 2355 - masks = dev_priv->irq_masks; 2356 - cur_irq = dev_priv->via_irqs + real_irq; 2357 - 2358 - if (masks[real_irq][2] && !force_sequence) { 2359 - VIA_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ, 2360 - ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) == 2361 - masks[irq][4])); 2362 - cur_irq_sequence = atomic_read(&cur_irq->irq_received); 2363 - } else { 2364 - VIA_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ, 2365 - (((cur_irq_sequence = 2366 - atomic_read(&cur_irq->irq_received)) - 2367 - *sequence) <= (1 << 23))); 2368 - } 2369 - *sequence = cur_irq_sequence; 2370 - return ret; 2371 - } 2372 - 2373 - 2374 - /* 2375 - * drm_dma.h hooks 2376 - */ 2377 - 2378 - static void via_driver_irq_preinstall(struct drm_device *dev) 2379 - { 2380 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 2381 - u32 status; 2382 - drm_via_irq_t *cur_irq; 2383 - int i; 2384 - 2385 - DRM_DEBUG("dev_priv: %p\n", dev_priv); 2386 - if (dev_priv) { 2387 - cur_irq = dev_priv->via_irqs; 2388 - 2389 - dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE; 2390 - dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING; 2391 - 2392 - if (dev_priv->chipset == VIA_PRO_GROUP_A || 2393 - dev_priv->chipset == VIA_DX9_0) { 2394 - dev_priv->irq_masks = via_pro_group_a_irqs; 2395 - dev_priv->num_irqs = via_num_pro_group_a; 2396 - dev_priv->irq_map = via_irqmap_pro_group_a; 2397 - } else { 2398 - dev_priv->irq_masks = via_unichrome_irqs; 2399 - dev_priv->num_irqs = via_num_unichrome; 2400 - dev_priv->irq_map = via_irqmap_unichrome; 2401 - } 2402 - 2403 - for (i = 0; i < dev_priv->num_irqs; ++i) { 2404 - atomic_set(&cur_irq->irq_received, 0); 2405 - cur_irq->enable_mask = dev_priv->irq_masks[i][0]; 2406 - cur_irq->pending_mask = dev_priv->irq_masks[i][1]; 2407 - init_waitqueue_head(&cur_irq->irq_queue); 2408 - dev_priv->irq_enable_mask |= cur_irq->enable_mask; 2409 - dev_priv->irq_pending_mask |= cur_irq->pending_mask; 2410 - cur_irq++; 2411 - 2412 - DRM_DEBUG("Initializing IRQ %d\n", i); 2413 - } 2414 - 2415 - dev_priv->last_vblank_valid = 0; 2416 - 2417 - /* Clear VSync interrupt regs */ 2418 - status = via_read(dev_priv, VIA_REG_INTERRUPT); 2419 - via_write(dev_priv, VIA_REG_INTERRUPT, status & 2420 - ~(dev_priv->irq_enable_mask)); 2421 - 2422 - /* Clear bits if they're already high */ 2423 - viadrv_acknowledge_irqs(dev_priv); 2424 - } 2425 - } 2426 - 2427 - static int via_driver_irq_postinstall(struct drm_device *dev) 2428 - { 2429 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 2430 - u32 status; 2431 - 2432 - DRM_DEBUG("fun: %s\n", __func__); 2433 - if (!dev_priv) 2434 - return -EINVAL; 2435 - 2436 - status = via_read(dev_priv, VIA_REG_INTERRUPT); 2437 - via_write(dev_priv, VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL 2438 - | dev_priv->irq_enable_mask); 2439 - 2440 - /* Some magic, oh for some data sheets ! */ 2441 - via_write8(dev_priv, 0x83d4, 0x11); 2442 - via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30); 2443 - 2444 - return 0; 2445 - } 2446 - 2447 - static void via_driver_irq_uninstall(struct drm_device *dev) 2448 - { 2449 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 2450 - u32 status; 2451 - 2452 - DRM_DEBUG("\n"); 2453 - if (dev_priv) { 2454 - 2455 - /* Some more magic, oh for some data sheets ! */ 2456 - 2457 - via_write8(dev_priv, 0x83d4, 0x11); 2458 - via_write8_mask(dev_priv, 0x83d5, 0x30, 0); 2459 - 2460 - status = via_read(dev_priv, VIA_REG_INTERRUPT); 2461 - via_write(dev_priv, VIA_REG_INTERRUPT, status & 2462 - ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask)); 2463 - } 2464 - } 2465 - 2466 - static int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv) 2467 - { 2468 - drm_via_irqwait_t *irqwait = data; 2469 - struct timespec64 now; 2470 - int ret = 0; 2471 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 2472 - drm_via_irq_t *cur_irq = dev_priv->via_irqs; 2473 - int force_sequence; 2474 - 2475 - if (irqwait->request.irq >= dev_priv->num_irqs) { 2476 - DRM_ERROR("Trying to wait on unknown irq %d\n", 2477 - irqwait->request.irq); 2478 - return -EINVAL; 2479 - } 2480 - 2481 - cur_irq += irqwait->request.irq; 2482 - 2483 - switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) { 2484 - case VIA_IRQ_RELATIVE: 2485 - irqwait->request.sequence += 2486 - atomic_read(&cur_irq->irq_received); 2487 - irqwait->request.type &= ~_DRM_VBLANK_RELATIVE; 2488 - break; 2489 - case VIA_IRQ_ABSOLUTE: 2490 - break; 2491 - default: 2492 - return -EINVAL; 2493 - } 2494 - 2495 - if (irqwait->request.type & VIA_IRQ_SIGNAL) { 2496 - DRM_ERROR("Signals on Via IRQs not implemented yet.\n"); 2497 - return -EINVAL; 2498 - } 2499 - 2500 - force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE); 2501 - 2502 - ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence, 2503 - &irqwait->request.sequence); 2504 - ktime_get_ts64(&now); 2505 - irqwait->reply.tval_sec = now.tv_sec; 2506 - irqwait->reply.tval_usec = now.tv_nsec / NSEC_PER_USEC; 2507 - 2508 - return ret; 2509 - } 2510 - 2511 - static void via_init_futex(drm_via_private_t *dev_priv) 2512 - { 2513 - unsigned int i; 2514 - 2515 - DRM_DEBUG("\n"); 2516 - 2517 - for (i = 0; i < VIA_NR_XVMC_LOCKS; ++i) { 2518 - init_waitqueue_head(&(dev_priv->decoder_queue[i])); 2519 - XVMCLOCKPTR(dev_priv->sarea_priv, i)->lock = 0; 2520 - } 2521 - } 2522 - 2523 - static void via_cleanup_futex(drm_via_private_t *dev_priv) 2524 - { 2525 - } 2526 - 2527 - static void via_release_futex(drm_via_private_t *dev_priv, int context) 2528 - { 2529 - unsigned int i; 2530 - volatile int *lock; 2531 - 2532 - if (!dev_priv->sarea_priv) 2533 - return; 2534 - 2535 - for (i = 0; i < VIA_NR_XVMC_LOCKS; ++i) { 2536 - lock = (volatile int *)XVMCLOCKPTR(dev_priv->sarea_priv, i); 2537 - if ((_DRM_LOCKING_CONTEXT(*lock) == context)) { 2538 - if (_DRM_LOCK_IS_HELD(*lock) 2539 - && (*lock & _DRM_LOCK_CONT)) { 2540 - wake_up(&(dev_priv->decoder_queue[i])); 2541 - } 2542 - *lock = 0; 2543 - } 2544 - } 2545 - } 2546 - 2547 - static int via_decoder_futex(struct drm_device *dev, void *data, struct drm_file *file_priv) 2548 - { 2549 - drm_via_futex_t *fx = data; 2550 - volatile int *lock; 2551 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 2552 - drm_via_sarea_t *sAPriv = dev_priv->sarea_priv; 2553 - int ret = 0; 2554 - 2555 - DRM_DEBUG("\n"); 2556 - 2557 - if (fx->lock >= VIA_NR_XVMC_LOCKS) 2558 - return -EFAULT; 2559 - 2560 - lock = (volatile int *)XVMCLOCKPTR(sAPriv, fx->lock); 2561 - 2562 - switch (fx->func) { 2563 - case VIA_FUTEX_WAIT: 2564 - VIA_WAIT_ON(ret, dev_priv->decoder_queue[fx->lock], 2565 - (fx->ms / 10) * (HZ / 100), *lock != fx->val); 2566 - return ret; 2567 - case VIA_FUTEX_WAKE: 2568 - wake_up(&(dev_priv->decoder_queue[fx->lock])); 2569 - return 0; 2570 - } 2571 - return 0; 2572 - } 2573 - 2574 - static int via_agp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 2575 - { 2576 - drm_via_agp_t *agp = data; 2577 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 2578 - 2579 - mutex_lock(&dev->struct_mutex); 2580 - drm_mm_init(&dev_priv->agp_mm, 0, agp->size >> VIA_MM_ALIGN_SHIFT); 2581 - 2582 - dev_priv->agp_initialized = 1; 2583 - dev_priv->agp_offset = agp->offset; 2584 - mutex_unlock(&dev->struct_mutex); 2585 - 2586 - DRM_DEBUG("offset = %u, size = %u\n", agp->offset, agp->size); 2587 - return 0; 2588 - } 2589 - 2590 - static int via_fb_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 2591 - { 2592 - drm_via_fb_t *fb = data; 2593 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 2594 - 2595 - mutex_lock(&dev->struct_mutex); 2596 - drm_mm_init(&dev_priv->vram_mm, 0, fb->size >> VIA_MM_ALIGN_SHIFT); 2597 - 2598 - dev_priv->vram_initialized = 1; 2599 - dev_priv->vram_offset = fb->offset; 2600 - 2601 - mutex_unlock(&dev->struct_mutex); 2602 - DRM_DEBUG("offset = %u, size = %u\n", fb->offset, fb->size); 2603 - 2604 - return 0; 2605 - 2606 - } 2607 - 2608 - static int via_final_context(struct drm_device *dev, int context) 2609 - { 2610 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 2611 - 2612 - via_release_futex(dev_priv, context); 2613 - 2614 - /* Linux specific until context tracking code gets ported to BSD */ 2615 - /* Last context, perform cleanup */ 2616 - if (list_is_singular(&dev->ctxlist)) { 2617 - DRM_DEBUG("Last Context\n"); 2618 - drm_legacy_irq_uninstall(dev); 2619 - via_cleanup_futex(dev_priv); 2620 - via_do_cleanup_map(dev); 2621 - } 2622 - return 1; 2623 - } 2624 - 2625 - static void via_lastclose(struct drm_device *dev) 2626 - { 2627 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 2628 - 2629 - if (!dev_priv) 2630 - return; 2631 - 2632 - mutex_lock(&dev->struct_mutex); 2633 - if (dev_priv->vram_initialized) { 2634 - drm_mm_takedown(&dev_priv->vram_mm); 2635 - dev_priv->vram_initialized = 0; 2636 - } 2637 - if (dev_priv->agp_initialized) { 2638 - drm_mm_takedown(&dev_priv->agp_mm); 2639 - dev_priv->agp_initialized = 0; 2640 - } 2641 - mutex_unlock(&dev->struct_mutex); 2642 - } 2643 - 2644 - static int via_mem_alloc(struct drm_device *dev, void *data, 2645 - struct drm_file *file) 2646 - { 2647 - drm_via_mem_t *mem = data; 2648 - int retval = 0, user_key; 2649 - struct via_memblock *item; 2650 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 2651 - struct via_file_private *file_priv = file->driver_priv; 2652 - unsigned long tmpSize; 2653 - 2654 - if (mem->type > VIA_MEM_AGP) { 2655 - DRM_ERROR("Unknown memory type allocation\n"); 2656 - return -EINVAL; 2657 - } 2658 - mutex_lock(&dev->struct_mutex); 2659 - if (0 == ((mem->type == VIA_MEM_VIDEO) ? dev_priv->vram_initialized : 2660 - dev_priv->agp_initialized)) { 2661 - mutex_unlock(&dev->struct_mutex); 2662 - DRM_ERROR 2663 - ("Attempt to allocate from uninitialized memory manager.\n"); 2664 - return -EINVAL; 2665 - } 2666 - 2667 - item = kzalloc(sizeof(*item), GFP_KERNEL); 2668 - if (!item) { 2669 - retval = -ENOMEM; 2670 - goto fail_alloc; 2671 - } 2672 - 2673 - tmpSize = (mem->size + VIA_MM_ALIGN_MASK) >> VIA_MM_ALIGN_SHIFT; 2674 - if (mem->type == VIA_MEM_AGP) 2675 - retval = drm_mm_insert_node(&dev_priv->agp_mm, 2676 - &item->mm_node, 2677 - tmpSize); 2678 - else 2679 - retval = drm_mm_insert_node(&dev_priv->vram_mm, 2680 - &item->mm_node, 2681 - tmpSize); 2682 - if (retval) 2683 - goto fail_alloc; 2684 - 2685 - retval = idr_alloc(&dev_priv->object_idr, item, 1, 0, GFP_KERNEL); 2686 - if (retval < 0) 2687 - goto fail_idr; 2688 - user_key = retval; 2689 - 2690 - list_add(&item->owner_list, &file_priv->obj_list); 2691 - mutex_unlock(&dev->struct_mutex); 2692 - 2693 - mem->offset = ((mem->type == VIA_MEM_VIDEO) ? 2694 - dev_priv->vram_offset : dev_priv->agp_offset) + 2695 - ((item->mm_node.start) << VIA_MM_ALIGN_SHIFT); 2696 - mem->index = user_key; 2697 - 2698 - return 0; 2699 - 2700 - fail_idr: 2701 - drm_mm_remove_node(&item->mm_node); 2702 - fail_alloc: 2703 - kfree(item); 2704 - mutex_unlock(&dev->struct_mutex); 2705 - 2706 - mem->offset = 0; 2707 - mem->size = 0; 2708 - mem->index = 0; 2709 - DRM_DEBUG("Video memory allocation failed\n"); 2710 - 2711 - return retval; 2712 - } 2713 - 2714 - static int via_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv) 2715 - { 2716 - drm_via_private_t *dev_priv = dev->dev_private; 2717 - drm_via_mem_t *mem = data; 2718 - struct via_memblock *obj; 2719 - 2720 - mutex_lock(&dev->struct_mutex); 2721 - obj = idr_find(&dev_priv->object_idr, mem->index); 2722 - if (obj == NULL) { 2723 - mutex_unlock(&dev->struct_mutex); 2724 - return -EINVAL; 2725 - } 2726 - 2727 - idr_remove(&dev_priv->object_idr, mem->index); 2728 - list_del(&obj->owner_list); 2729 - drm_mm_remove_node(&obj->mm_node); 2730 - kfree(obj); 2731 - mutex_unlock(&dev->struct_mutex); 2732 - 2733 - DRM_DEBUG("free = 0x%lx\n", mem->index); 2734 - 2735 - return 0; 2736 - } 2737 - 2738 - 2739 - static void via_reclaim_buffers_locked(struct drm_device *dev, 2740 - struct drm_file *file) 2741 - { 2742 - struct via_file_private *file_priv = file->driver_priv; 2743 - struct via_memblock *entry, *next; 2744 - 2745 - if (!(dev->master && file->master->lock.hw_lock)) 2746 - return; 2747 - 2748 - drm_legacy_idlelock_take(&file->master->lock); 2749 - 2750 - mutex_lock(&dev->struct_mutex); 2751 - if (list_empty(&file_priv->obj_list)) { 2752 - mutex_unlock(&dev->struct_mutex); 2753 - drm_legacy_idlelock_release(&file->master->lock); 2754 - 2755 - return; 2756 - } 2757 - 2758 - via_driver_dma_quiescent(dev); 2759 - 2760 - list_for_each_entry_safe(entry, next, &file_priv->obj_list, 2761 - owner_list) { 2762 - list_del(&entry->owner_list); 2763 - drm_mm_remove_node(&entry->mm_node); 2764 - kfree(entry); 2765 - } 2766 - mutex_unlock(&dev->struct_mutex); 2767 - 2768 - drm_legacy_idlelock_release(&file->master->lock); 2769 - 2770 - return; 2771 - } 2772 - 2773 - static int via_do_init_map(struct drm_device *dev, drm_via_init_t *init) 2774 - { 2775 - drm_via_private_t *dev_priv = dev->dev_private; 2776 - 2777 - DRM_DEBUG("\n"); 2778 - 2779 - dev_priv->sarea = drm_legacy_getsarea(dev); 2780 - if (!dev_priv->sarea) { 2781 - DRM_ERROR("could not find sarea!\n"); 2782 - dev->dev_private = (void *)dev_priv; 2783 - via_do_cleanup_map(dev); 2784 - return -EINVAL; 2785 - } 2786 - 2787 - dev_priv->fb = drm_legacy_findmap(dev, init->fb_offset); 2788 - if (!dev_priv->fb) { 2789 - DRM_ERROR("could not find framebuffer!\n"); 2790 - dev->dev_private = (void *)dev_priv; 2791 - via_do_cleanup_map(dev); 2792 - return -EINVAL; 2793 - } 2794 - dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset); 2795 - if (!dev_priv->mmio) { 2796 - DRM_ERROR("could not find mmio region!\n"); 2797 - dev->dev_private = (void *)dev_priv; 2798 - via_do_cleanup_map(dev); 2799 - return -EINVAL; 2800 - } 2801 - 2802 - dev_priv->sarea_priv = 2803 - (drm_via_sarea_t *) ((u8 *) dev_priv->sarea->handle + 2804 - init->sarea_priv_offset); 2805 - 2806 - dev_priv->agpAddr = init->agpAddr; 2807 - 2808 - via_init_futex(dev_priv); 2809 - 2810 - via_init_dmablit(dev); 2811 - 2812 - dev->dev_private = (void *)dev_priv; 2813 - return 0; 2814 - } 2815 - 2816 - int via_do_cleanup_map(struct drm_device *dev) 2817 - { 2818 - via_dma_cleanup(dev); 2819 - 2820 - return 0; 2821 - } 2822 - 2823 - static int via_map_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 2824 - { 2825 - drm_via_init_t *init = data; 2826 - 2827 - DRM_DEBUG("\n"); 2828 - 2829 - switch (init->func) { 2830 - case VIA_INIT_MAP: 2831 - return via_do_init_map(dev, init); 2832 - case VIA_CLEANUP_MAP: 2833 - return via_do_cleanup_map(dev); 2834 - } 2835 - 2836 - return -EINVAL; 2837 - } 2838 - 2839 - static int via_driver_load(struct drm_device *dev, unsigned long chipset) 2840 - { 2841 - struct pci_dev *pdev = to_pci_dev(dev->dev); 2842 - drm_via_private_t *dev_priv; 2843 - int ret = 0; 2844 - 2845 - dev_priv = kzalloc(sizeof(drm_via_private_t), GFP_KERNEL); 2846 - if (dev_priv == NULL) 2847 - return -ENOMEM; 2848 - 2849 - idr_init_base(&dev_priv->object_idr, 1); 2850 - dev->dev_private = (void *)dev_priv; 2851 - 2852 - dev_priv->chipset = chipset; 2853 - 2854 - pci_set_master(pdev); 2855 - 2856 - ret = drm_vblank_init(dev, 1); 2857 - if (ret) { 2858 - kfree(dev_priv); 2859 - return ret; 2860 - } 2861 - 2862 - return 0; 2863 - } 2864 - 2865 - static void via_driver_unload(struct drm_device *dev) 2866 - { 2867 - drm_via_private_t *dev_priv = dev->dev_private; 2868 - 2869 - idr_destroy(&dev_priv->object_idr); 2870 - 2871 - kfree(dev_priv); 2872 - } 2873 - 2874 - static void via_cmdbuf_start(drm_via_private_t *dev_priv); 2875 - static void via_cmdbuf_pause(drm_via_private_t *dev_priv); 2876 - static void via_cmdbuf_reset(drm_via_private_t *dev_priv); 2877 - static void via_cmdbuf_rewind(drm_via_private_t *dev_priv); 2878 - static int via_wait_idle(drm_via_private_t *dev_priv); 2879 - static void via_pad_cache(drm_via_private_t *dev_priv, int qwords); 2880 - 2881 - /* 2882 - * Free space in command buffer. 2883 - */ 2884 - 2885 - static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv) 2886 - { 2887 - uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; 2888 - uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; 2889 - 2890 - return ((hw_addr <= dev_priv->dma_low) ? 2891 - (dev_priv->dma_high + hw_addr - dev_priv->dma_low) : 2892 - (hw_addr - dev_priv->dma_low)); 2893 - } 2894 - 2895 - /* 2896 - * How much does the command regulator lag behind? 2897 - */ 2898 - 2899 - static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv) 2900 - { 2901 - uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; 2902 - uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; 2903 - 2904 - return ((hw_addr <= dev_priv->dma_low) ? 2905 - (dev_priv->dma_low - hw_addr) : 2906 - (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr)); 2907 - } 2908 - 2909 - /* 2910 - * Check that the given size fits in the buffer, otherwise wait. 2911 - */ 2912 - 2913 - static inline int 2914 - via_cmdbuf_wait(drm_via_private_t *dev_priv, unsigned int size) 2915 - { 2916 - uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; 2917 - uint32_t cur_addr, hw_addr, next_addr; 2918 - volatile uint32_t *hw_addr_ptr; 2919 - uint32_t count; 2920 - hw_addr_ptr = dev_priv->hw_addr_ptr; 2921 - cur_addr = dev_priv->dma_low; 2922 - next_addr = cur_addr + size + 512 * 1024; 2923 - count = 1000000; 2924 - do { 2925 - hw_addr = *hw_addr_ptr - agp_base; 2926 - if (count-- == 0) { 2927 - DRM_ERROR 2928 - ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n", 2929 - hw_addr, cur_addr, next_addr); 2930 - return -1; 2931 - } 2932 - if ((cur_addr < hw_addr) && (next_addr >= hw_addr)) 2933 - msleep(1); 2934 - } while ((cur_addr < hw_addr) && (next_addr >= hw_addr)); 2935 - return 0; 2936 - } 2937 - 2938 - /* 2939 - * Checks whether buffer head has reach the end. Rewind the ring buffer 2940 - * when necessary. 2941 - * 2942 - * Returns virtual pointer to ring buffer. 2943 - */ 2944 - 2945 - static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv, 2946 - unsigned int size) 2947 - { 2948 - if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) > 2949 - dev_priv->dma_high) { 2950 - via_cmdbuf_rewind(dev_priv); 2951 - } 2952 - if (via_cmdbuf_wait(dev_priv, size) != 0) 2953 - return NULL; 2954 - 2955 - return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); 2956 - } 2957 - 2958 - int via_dma_cleanup(struct drm_device *dev) 2959 - { 2960 - if (dev->dev_private) { 2961 - drm_via_private_t *dev_priv = 2962 - (drm_via_private_t *) dev->dev_private; 2963 - 2964 - if (dev_priv->ring.virtual_start && dev_priv->mmio) { 2965 - via_cmdbuf_reset(dev_priv); 2966 - 2967 - drm_legacy_ioremapfree(&dev_priv->ring.map, dev); 2968 - dev_priv->ring.virtual_start = NULL; 2969 - } 2970 - 2971 - } 2972 - 2973 - return 0; 2974 - } 2975 - 2976 - static int via_initialize(struct drm_device *dev, 2977 - drm_via_private_t *dev_priv, 2978 - drm_via_dma_init_t *init) 2979 - { 2980 - if (!dev_priv || !dev_priv->mmio) { 2981 - DRM_ERROR("via_dma_init called before via_map_init\n"); 2982 - return -EFAULT; 2983 - } 2984 - 2985 - if (dev_priv->ring.virtual_start != NULL) { 2986 - DRM_ERROR("called again without calling cleanup\n"); 2987 - return -EFAULT; 2988 - } 2989 - 2990 - if (!dev->agp || !dev->agp->base) { 2991 - DRM_ERROR("called with no agp memory available\n"); 2992 - return -EFAULT; 2993 - } 2994 - 2995 - if (dev_priv->chipset == VIA_DX9_0) { 2996 - DRM_ERROR("AGP DMA is not supported on this chip\n"); 2997 - return -EINVAL; 2998 - } 2999 - 3000 - dev_priv->ring.map.offset = dev->agp->base + init->offset; 3001 - dev_priv->ring.map.size = init->size; 3002 - dev_priv->ring.map.type = 0; 3003 - dev_priv->ring.map.flags = 0; 3004 - dev_priv->ring.map.mtrr = 0; 3005 - 3006 - drm_legacy_ioremap(&dev_priv->ring.map, dev); 3007 - 3008 - if (dev_priv->ring.map.handle == NULL) { 3009 - via_dma_cleanup(dev); 3010 - DRM_ERROR("can not ioremap virtual address for" 3011 - " ring buffer\n"); 3012 - return -ENOMEM; 3013 - } 3014 - 3015 - dev_priv->ring.virtual_start = dev_priv->ring.map.handle; 3016 - 3017 - dev_priv->dma_ptr = dev_priv->ring.virtual_start; 3018 - dev_priv->dma_low = 0; 3019 - dev_priv->dma_high = init->size; 3020 - dev_priv->dma_wrap = init->size; 3021 - dev_priv->dma_offset = init->offset; 3022 - dev_priv->last_pause_ptr = NULL; 3023 - dev_priv->hw_addr_ptr = 3024 - (volatile uint32_t *)((char *)dev_priv->mmio->handle + 3025 - init->reg_pause_addr); 3026 - 3027 - via_cmdbuf_start(dev_priv); 3028 - 3029 - return 0; 3030 - } 3031 - 3032 - static int via_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 3033 - { 3034 - drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 3035 - drm_via_dma_init_t *init = data; 3036 - int retcode = 0; 3037 - 3038 - switch (init->func) { 3039 - case VIA_INIT_DMA: 3040 - if (!capable(CAP_SYS_ADMIN)) 3041 - retcode = -EPERM; 3042 - else 3043 - retcode = via_initialize(dev, dev_priv, init); 3044 - break; 3045 - case VIA_CLEANUP_DMA: 3046 - if (!capable(CAP_SYS_ADMIN)) 3047 - retcode = -EPERM; 3048 - else 3049 - retcode = via_dma_cleanup(dev); 3050 - break; 3051 - case VIA_DMA_INITIALIZED: 3052 - retcode = (dev_priv->ring.virtual_start != NULL) ? 3053 - 0 : -EFAULT; 3054 - break; 3055 - default: 3056 - retcode = -EINVAL; 3057 - break; 3058 - } 3059 - 3060 - return retcode; 3061 - } 3062 - 3063 - static int via_dispatch_cmdbuffer(struct drm_device *dev, drm_via_cmdbuffer_t *cmd) 3064 - { 3065 - drm_via_private_t *dev_priv; 3066 - uint32_t *vb; 3067 - int ret; 3068 - 3069 - dev_priv = (drm_via_private_t *) dev->dev_private; 3070 - 3071 - if (dev_priv->ring.virtual_start == NULL) { 3072 - DRM_ERROR("called without initializing AGP ring buffer.\n"); 3073 - return -EFAULT; 3074 - } 3075 - 3076 - if (cmd->size > VIA_PCI_BUF_SIZE) 3077 - return -ENOMEM; 3078 - 3079 - if (copy_from_user(dev_priv->pci_buf, cmd->buf, cmd->size)) 3080 - return -EFAULT; 3081 - 3082 - /* 3083 - * Running this function on AGP memory is dead slow. Therefore 3084 - * we run it on a temporary cacheable system memory buffer and 3085 - * copy it to AGP memory when ready. 3086 - */ 3087 - 3088 - if ((ret = 3089 - via_verify_command_stream((uint32_t *) dev_priv->pci_buf, 3090 - cmd->size, dev, 1))) { 3091 - return ret; 3092 - } 3093 - 3094 - vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size); 3095 - if (vb == NULL) 3096 - return -EAGAIN; 3097 - 3098 - memcpy(vb, dev_priv->pci_buf, cmd->size); 3099 - 3100 - dev_priv->dma_low += cmd->size; 3101 - 3102 - /* 3103 - * Small submissions somehow stalls the CPU. (AGP cache effects?) 3104 - * pad to greater size. 3105 - */ 3106 - 3107 - if (cmd->size < 0x100) 3108 - via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3); 3109 - via_cmdbuf_pause(dev_priv); 3110 - 3111 - return 0; 3112 - } 3113 - 3114 - int via_driver_dma_quiescent(struct drm_device *dev) 3115 - { 3116 - drm_via_private_t *dev_priv = dev->dev_private; 3117 - 3118 - if (!via_wait_idle(dev_priv)) 3119 - return -EBUSY; 3120 - return 0; 3121 - } 3122 - 3123 - static int via_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) 3124 - { 3125 - 3126 - LOCK_TEST_WITH_RETURN(dev, file_priv); 3127 - 3128 - return via_driver_dma_quiescent(dev); 3129 - } 3130 - 3131 - static int via_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv) 3132 - { 3133 - drm_via_cmdbuffer_t *cmdbuf = data; 3134 - int ret; 3135 - 3136 - LOCK_TEST_WITH_RETURN(dev, file_priv); 3137 - 3138 - DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size); 3139 - 3140 - ret = via_dispatch_cmdbuffer(dev, cmdbuf); 3141 - return ret; 3142 - } 3143 - 3144 - static int via_dispatch_pci_cmdbuffer(struct drm_device *dev, 3145 - drm_via_cmdbuffer_t *cmd) 3146 - { 3147 - drm_via_private_t *dev_priv = dev->dev_private; 3148 - int ret; 3149 - 3150 - if (cmd->size > VIA_PCI_BUF_SIZE) 3151 - return -ENOMEM; 3152 - if (copy_from_user(dev_priv->pci_buf, cmd->buf, cmd->size)) 3153 - return -EFAULT; 3154 - 3155 - if ((ret = 3156 - via_verify_command_stream((uint32_t *) dev_priv->pci_buf, 3157 - cmd->size, dev, 0))) { 3158 - return ret; 3159 - } 3160 - 3161 - ret = 3162 - via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf, 3163 - cmd->size); 3164 - return ret; 3165 - } 3166 - 3167 - static int via_pci_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv) 3168 - { 3169 - drm_via_cmdbuffer_t *cmdbuf = data; 3170 - int ret; 3171 - 3172 - LOCK_TEST_WITH_RETURN(dev, file_priv); 3173 - 3174 - DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size); 3175 - 3176 - ret = via_dispatch_pci_cmdbuffer(dev, cmdbuf); 3177 - return ret; 3178 - } 3179 - 3180 - static inline uint32_t *via_align_buffer(drm_via_private_t *dev_priv, 3181 - uint32_t * vb, int qw_count) 3182 - { 3183 - for (; qw_count > 0; --qw_count) 3184 - VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY); 3185 - return vb; 3186 - } 3187 - 3188 - /* 3189 - * This function is used internally by ring buffer management code. 3190 - * 3191 - * Returns virtual pointer to ring buffer. 3192 - */ 3193 - static inline uint32_t *via_get_dma(drm_via_private_t *dev_priv) 3194 - { 3195 - return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); 3196 - } 3197 - 3198 - /* 3199 - * Hooks a segment of data into the tail of the ring-buffer by 3200 - * modifying the pause address stored in the buffer itself. If 3201 - * the regulator has already paused, restart it. 3202 - */ 3203 - static int via_hook_segment(drm_via_private_t *dev_priv, 3204 - uint32_t pause_addr_hi, uint32_t pause_addr_lo, 3205 - int no_pci_fire) 3206 - { 3207 - int paused, count; 3208 - volatile uint32_t *paused_at = dev_priv->last_pause_ptr; 3209 - uint32_t reader, ptr; 3210 - uint32_t diff; 3211 - 3212 - paused = 0; 3213 - via_flush_write_combine(); 3214 - (void) *(volatile uint32_t *)(via_get_dma(dev_priv) - 1); 3215 - 3216 - *paused_at = pause_addr_lo; 3217 - via_flush_write_combine(); 3218 - (void) *paused_at; 3219 - 3220 - reader = *(dev_priv->hw_addr_ptr); 3221 - ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) + 3222 - dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; 3223 - 3224 - dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1; 3225 - 3226 - /* 3227 - * If there is a possibility that the command reader will 3228 - * miss the new pause address and pause on the old one, 3229 - * In that case we need to program the new start address 3230 - * using PCI. 3231 - */ 3232 - 3233 - diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff; 3234 - count = 10000000; 3235 - while (diff == 0 && count--) { 3236 - paused = (via_read(dev_priv, 0x41c) & 0x80000000); 3237 - if (paused) 3238 - break; 3239 - reader = *(dev_priv->hw_addr_ptr); 3240 - diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff; 3241 - } 3242 - 3243 - paused = via_read(dev_priv, 0x41c) & 0x80000000; 3244 - 3245 - if (paused && !no_pci_fire) { 3246 - reader = *(dev_priv->hw_addr_ptr); 3247 - diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff; 3248 - diff &= (dev_priv->dma_high - 1); 3249 - if (diff != 0 && diff < (dev_priv->dma_high >> 1)) { 3250 - DRM_ERROR("Paused at incorrect address. " 3251 - "0x%08x, 0x%08x 0x%08x\n", 3252 - ptr, reader, dev_priv->dma_diff); 3253 - } else if (diff == 0) { 3254 - /* 3255 - * There is a concern that these writes may stall the PCI bus 3256 - * if the GPU is not idle. However, idling the GPU first 3257 - * doesn't make a difference. 3258 - */ 3259 - 3260 - via_write(dev_priv, VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); 3261 - via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_hi); 3262 - via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_lo); 3263 - via_read(dev_priv, VIA_REG_TRANSPACE); 3264 - } 3265 - } 3266 - return paused; 3267 - } 3268 - 3269 - static int via_wait_idle(drm_via_private_t *dev_priv) 3270 - { 3271 - int count = 10000000; 3272 - 3273 - while (!(via_read(dev_priv, VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && --count) 3274 - ; 3275 - 3276 - while (count && (via_read(dev_priv, VIA_REG_STATUS) & 3277 - (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | 3278 - VIA_3D_ENG_BUSY))) 3279 - --count; 3280 - return count; 3281 - } 3282 - 3283 - static uint32_t *via_align_cmd(drm_via_private_t *dev_priv, uint32_t cmd_type, 3284 - uint32_t addr, uint32_t *cmd_addr_hi, 3285 - uint32_t *cmd_addr_lo, int skip_wait) 3286 - { 3287 - uint32_t agp_base; 3288 - uint32_t cmd_addr, addr_lo, addr_hi; 3289 - uint32_t *vb; 3290 - uint32_t qw_pad_count; 3291 - 3292 - if (!skip_wait) 3293 - via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE); 3294 - 3295 - vb = via_get_dma(dev_priv); 3296 - VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) | 3297 - (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16); 3298 - agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; 3299 - qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) - 3300 - ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3); 3301 - 3302 - cmd_addr = (addr) ? addr : 3303 - agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3); 3304 - addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) | 3305 - (cmd_addr & HC_HAGPBpL_MASK)); 3306 - addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24)); 3307 - 3308 - vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1); 3309 - VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo); 3310 - return vb; 3311 - } 3312 - 3313 - static void via_cmdbuf_start(drm_via_private_t *dev_priv) 3314 - { 3315 - uint32_t pause_addr_lo, pause_addr_hi; 3316 - uint32_t start_addr, start_addr_lo; 3317 - uint32_t end_addr, end_addr_lo; 3318 - uint32_t command; 3319 - uint32_t agp_base; 3320 - uint32_t ptr; 3321 - uint32_t reader; 3322 - int count; 3323 - 3324 - dev_priv->dma_low = 0; 3325 - 3326 - agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; 3327 - start_addr = agp_base; 3328 - end_addr = agp_base + dev_priv->dma_high; 3329 - 3330 - start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF)); 3331 - end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF)); 3332 - command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) | 3333 - ((end_addr & 0xff000000) >> 16)); 3334 - 3335 - dev_priv->last_pause_ptr = 3336 - via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, 3337 - &pause_addr_hi, &pause_addr_lo, 1) - 1; 3338 - 3339 - via_flush_write_combine(); 3340 - (void) *(volatile uint32_t *)dev_priv->last_pause_ptr; 3341 - 3342 - via_write(dev_priv, VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); 3343 - via_write(dev_priv, VIA_REG_TRANSPACE, command); 3344 - via_write(dev_priv, VIA_REG_TRANSPACE, start_addr_lo); 3345 - via_write(dev_priv, VIA_REG_TRANSPACE, end_addr_lo); 3346 - 3347 - via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_hi); 3348 - via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_lo); 3349 - wmb(); 3350 - via_write(dev_priv, VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK); 3351 - via_read(dev_priv, VIA_REG_TRANSPACE); 3352 - 3353 - dev_priv->dma_diff = 0; 3354 - 3355 - count = 10000000; 3356 - while (!(via_read(dev_priv, 0x41c) & 0x80000000) && count--); 3357 - 3358 - reader = *(dev_priv->hw_addr_ptr); 3359 - ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) + 3360 - dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; 3361 - 3362 - /* 3363 - * This is the difference between where we tell the 3364 - * command reader to pause and where it actually pauses. 3365 - * This differs between hw implementation so we need to 3366 - * detect it. 3367 - */ 3368 - 3369 - dev_priv->dma_diff = ptr - reader; 3370 - } 3371 - 3372 - static void via_pad_cache(drm_via_private_t *dev_priv, int qwords) 3373 - { 3374 - uint32_t *vb; 3375 - 3376 - via_cmdbuf_wait(dev_priv, qwords + 2); 3377 - vb = via_get_dma(dev_priv); 3378 - VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16); 3379 - via_align_buffer(dev_priv, vb, qwords); 3380 - } 3381 - 3382 - static inline void via_dummy_bitblt(drm_via_private_t *dev_priv) 3383 - { 3384 - uint32_t *vb = via_get_dma(dev_priv); 3385 - SetReg2DAGP(0x0C, (0 | (0 << 16))); 3386 - SetReg2DAGP(0x10, 0 | (0 << 16)); 3387 - SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000); 3388 - } 3389 - 3390 - static void via_cmdbuf_jump(drm_via_private_t *dev_priv) 3391 - { 3392 - uint32_t pause_addr_lo, pause_addr_hi; 3393 - uint32_t jump_addr_lo, jump_addr_hi; 3394 - volatile uint32_t *last_pause_ptr; 3395 - uint32_t dma_low_save1, dma_low_save2; 3396 - 3397 - via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi, 3398 - &jump_addr_lo, 0); 3399 - 3400 - dev_priv->dma_wrap = dev_priv->dma_low; 3401 - 3402 - /* 3403 - * Wrap command buffer to the beginning. 3404 - */ 3405 - 3406 - dev_priv->dma_low = 0; 3407 - if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) 3408 - DRM_ERROR("via_cmdbuf_jump failed\n"); 3409 - 3410 - via_dummy_bitblt(dev_priv); 3411 - via_dummy_bitblt(dev_priv); 3412 - 3413 - last_pause_ptr = 3414 - via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, 3415 - &pause_addr_lo, 0) - 1; 3416 - via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, 3417 - &pause_addr_lo, 0); 3418 - 3419 - *last_pause_ptr = pause_addr_lo; 3420 - dma_low_save1 = dev_priv->dma_low; 3421 - 3422 - /* 3423 - * Now, set a trap that will pause the regulator if it tries to rerun the old 3424 - * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause 3425 - * and reissues the jump command over PCI, while the regulator has already taken the jump 3426 - * and actually paused at the current buffer end). 3427 - * There appears to be no other way to detect this condition, since the hw_addr_pointer 3428 - * does not seem to get updated immediately when a jump occurs. 3429 - */ 3430 - 3431 - last_pause_ptr = 3432 - via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, 3433 - &pause_addr_lo, 0) - 1; 3434 - via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, 3435 - &pause_addr_lo, 0); 3436 - *last_pause_ptr = pause_addr_lo; 3437 - 3438 - dma_low_save2 = dev_priv->dma_low; 3439 - dev_priv->dma_low = dma_low_save1; 3440 - via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0); 3441 - dev_priv->dma_low = dma_low_save2; 3442 - via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0); 3443 - } 3444 - 3445 - 3446 - static void via_cmdbuf_rewind(drm_via_private_t *dev_priv) 3447 - { 3448 - via_cmdbuf_jump(dev_priv); 3449 - } 3450 - 3451 - static void via_cmdbuf_flush(drm_via_private_t *dev_priv, uint32_t cmd_type) 3452 - { 3453 - uint32_t pause_addr_lo, pause_addr_hi; 3454 - 3455 - via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0); 3456 - via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0); 3457 - } 3458 - 3459 - static void via_cmdbuf_pause(drm_via_private_t *dev_priv) 3460 - { 3461 - via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE); 3462 - } 3463 - 3464 - static void via_cmdbuf_reset(drm_via_private_t *dev_priv) 3465 - { 3466 - via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP); 3467 - via_wait_idle(dev_priv); 3468 - } 3469 - 3470 - /* 3471 - * User interface to the space and lag functions. 3472 - */ 3473 - 3474 - static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *file_priv) 3475 - { 3476 - drm_via_cmdbuf_size_t *d_siz = data; 3477 - int ret = 0; 3478 - uint32_t tmp_size, count; 3479 - drm_via_private_t *dev_priv; 3480 - 3481 - DRM_DEBUG("\n"); 3482 - LOCK_TEST_WITH_RETURN(dev, file_priv); 3483 - 3484 - dev_priv = (drm_via_private_t *) dev->dev_private; 3485 - 3486 - if (dev_priv->ring.virtual_start == NULL) { 3487 - DRM_ERROR("called without initializing AGP ring buffer.\n"); 3488 - return -EFAULT; 3489 - } 3490 - 3491 - count = 1000000; 3492 - tmp_size = d_siz->size; 3493 - switch (d_siz->func) { 3494 - case VIA_CMDBUF_SPACE: 3495 - while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size) 3496 - && --count) { 3497 - if (!d_siz->wait) 3498 - break; 3499 - } 3500 - if (!count) { 3501 - DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n"); 3502 - ret = -EAGAIN; 3503 - } 3504 - break; 3505 - case VIA_CMDBUF_LAG: 3506 - while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz->size) 3507 - && --count) { 3508 - if (!d_siz->wait) 3509 - break; 3510 - } 3511 - if (!count) { 3512 - DRM_ERROR("VIA_CMDBUF_LAG timed out.\n"); 3513 - ret = -EAGAIN; 3514 - } 3515 - break; 3516 - default: 3517 - ret = -EFAULT; 3518 - } 3519 - d_siz->size = tmp_size; 3520 - 3521 - return ret; 3522 - } 3523 - 3524 - static const struct drm_ioctl_desc via_ioctls[] = { 3525 - DRM_IOCTL_DEF_DRV(VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH), 3526 - DRM_IOCTL_DEF_DRV(VIA_FREEMEM, via_mem_free, DRM_AUTH), 3527 - DRM_IOCTL_DEF_DRV(VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER), 3528 - DRM_IOCTL_DEF_DRV(VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER), 3529 - DRM_IOCTL_DEF_DRV(VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER), 3530 - DRM_IOCTL_DEF_DRV(VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH), 3531 - DRM_IOCTL_DEF_DRV(VIA_DMA_INIT, via_dma_init, DRM_AUTH), 3532 - DRM_IOCTL_DEF_DRV(VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH), 3533 - DRM_IOCTL_DEF_DRV(VIA_FLUSH, via_flush_ioctl, DRM_AUTH), 3534 - DRM_IOCTL_DEF_DRV(VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH), 3535 - DRM_IOCTL_DEF_DRV(VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH), 3536 - DRM_IOCTL_DEF_DRV(VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH), 3537 - DRM_IOCTL_DEF_DRV(VIA_DMA_BLIT, via_dma_blit, DRM_AUTH), 3538 - DRM_IOCTL_DEF_DRV(VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH) 3539 - }; 3540 - 3541 - static int via_max_ioctl = ARRAY_SIZE(via_ioctls); 3542 - static int via_driver_open(struct drm_device *dev, struct drm_file *file) 3543 - { 3544 - struct via_file_private *file_priv; 3545 - 3546 - DRM_DEBUG_DRIVER("\n"); 3547 - file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL); 3548 - if (!file_priv) 3549 - return -ENOMEM; 3550 - 3551 - file->driver_priv = file_priv; 3552 - 3553 - INIT_LIST_HEAD(&file_priv->obj_list); 3554 - 3555 - return 0; 3556 - } 3557 - 3558 - static void via_driver_postclose(struct drm_device *dev, struct drm_file *file) 3559 - { 3560 - struct via_file_private *file_priv = file->driver_priv; 3561 - 3562 - kfree(file_priv); 3563 - } 3564 - 3565 - static struct pci_device_id pciidlist[] = { 3566 - viadrv_PCI_IDS 3567 - }; 3568 - 3569 - static const struct file_operations via_driver_fops = { 3570 - .owner = THIS_MODULE, 3571 - .open = drm_open, 3572 - .release = drm_release, 3573 - .unlocked_ioctl = drm_ioctl, 3574 - .mmap = drm_legacy_mmap, 3575 - .poll = drm_poll, 3576 - .compat_ioctl = drm_compat_ioctl, 3577 - .llseek = noop_llseek, 3578 - }; 3579 - 3580 - static struct drm_driver driver = { 3581 - .driver_features = 3582 - DRIVER_USE_AGP | DRIVER_HAVE_IRQ | DRIVER_LEGACY, 3583 - .load = via_driver_load, 3584 - .unload = via_driver_unload, 3585 - .open = via_driver_open, 3586 - .preclose = via_reclaim_buffers_locked, 3587 - .postclose = via_driver_postclose, 3588 - .context_dtor = via_final_context, 3589 - .get_vblank_counter = via_get_vblank_counter, 3590 - .enable_vblank = via_enable_vblank, 3591 - .disable_vblank = via_disable_vblank, 3592 - .irq_preinstall = via_driver_irq_preinstall, 3593 - .irq_postinstall = via_driver_irq_postinstall, 3594 - .irq_uninstall = via_driver_irq_uninstall, 3595 - .irq_handler = via_driver_irq_handler, 3596 - .dma_quiescent = via_driver_dma_quiescent, 3597 - .lastclose = via_lastclose, 3598 - .ioctls = via_ioctls, 3599 - .fops = &via_driver_fops, 3600 - .name = DRIVER_NAME, 3601 - .desc = DRIVER_DESC, 3602 - .date = DRIVER_DATE, 3603 - .major = DRIVER_MAJOR, 3604 - .minor = DRIVER_MINOR, 3605 - .patchlevel = DRIVER_PATCHLEVEL, 3606 - }; 3607 - 3608 - static struct pci_driver via_pci_driver = { 3609 - .name = DRIVER_NAME, 3610 - .id_table = pciidlist, 3611 - }; 3612 - 3613 - static int __init via_init(void) 3614 - { 3615 - driver.num_ioctls = via_max_ioctl; 3616 - via_init_command_verifier(); 3617 - return drm_legacy_pci_init(&driver, &via_pci_driver); 3618 - } 3619 - 3620 - static void __exit via_exit(void) 3621 - { 3622 - drm_legacy_pci_exit(&driver, &via_pci_driver); 3623 - } 3624 - 3625 - module_init(via_init); 3626 - module_exit(via_exit); 3627 - 3628 - MODULE_AUTHOR(DRIVER_AUTHOR); 3629 - MODULE_DESCRIPTION(DRIVER_DESC); 3630 - MODULE_LICENSE("GPL and additional rights");

-282

include/uapi/drm/via_drm.h

··· 1 - /* 2 - * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. 3 - * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. 4 - * 5 - * Permission is hereby granted, free of charge, to any person obtaining a 6 - * copy of this software and associated documentation files (the "Software"), 7 - * to deal in the Software without restriction, including without limitation 8 - * the rights to use, copy, modify, merge, publish, distribute, sub license, 9 - * and/or sell copies of the Software, and to permit persons to whom the 10 - * Software is furnished to do so, subject to the following conditions: 11 - * 12 - * The above copyright notice and this permission notice (including the 13 - * next paragraph) shall be included in all copies or substantial portions 14 - * of the Software. 15 - * 16 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 - * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 - * DEALINGS IN THE SOFTWARE. 23 - */ 24 - #ifndef _VIA_DRM_H_ 25 - #define _VIA_DRM_H_ 26 - 27 - #include "drm.h" 28 - 29 - #if defined(__cplusplus) 30 - extern "C" { 31 - #endif 32 - 33 - /* WARNING: These defines must be the same as what the Xserver uses. 34 - * if you change them, you must change the defines in the Xserver. 35 - */ 36 - 37 - #ifndef _VIA_DEFINES_ 38 - #define _VIA_DEFINES_ 39 - 40 - 41 - #define VIA_NR_SAREA_CLIPRECTS 8 42 - #define VIA_NR_XVMC_PORTS 10 43 - #define VIA_NR_XVMC_LOCKS 5 44 - #define VIA_MAX_CACHELINE_SIZE 64 45 - #define XVMCLOCKPTR(saPriv,lockNo) \ 46 - ((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \ 47 - (VIA_MAX_CACHELINE_SIZE - 1)) & \ 48 - ~(VIA_MAX_CACHELINE_SIZE - 1)) + \ 49 - VIA_MAX_CACHELINE_SIZE*(lockNo))) 50 - 51 - /* Each region is a minimum of 64k, and there are at most 64 of them. 52 - */ 53 - #define VIA_NR_TEX_REGIONS 64 54 - #define VIA_LOG_MIN_TEX_REGION_SIZE 16 55 - #endif 56 - 57 - #define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ 58 - #define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ 59 - #define VIA_UPLOAD_CTX 0x4 60 - #define VIA_UPLOAD_BUFFERS 0x8 61 - #define VIA_UPLOAD_TEX0 0x10 62 - #define VIA_UPLOAD_TEX1 0x20 63 - #define VIA_UPLOAD_CLIPRECTS 0x40 64 - #define VIA_UPLOAD_ALL 0xff 65 - 66 - /* VIA specific ioctls */ 67 - #define DRM_VIA_ALLOCMEM 0x00 68 - #define DRM_VIA_FREEMEM 0x01 69 - #define DRM_VIA_AGP_INIT 0x02 70 - #define DRM_VIA_FB_INIT 0x03 71 - #define DRM_VIA_MAP_INIT 0x04 72 - #define DRM_VIA_DEC_FUTEX 0x05 73 - #define NOT_USED 74 - #define DRM_VIA_DMA_INIT 0x07 75 - #define DRM_VIA_CMDBUFFER 0x08 76 - #define DRM_VIA_FLUSH 0x09 77 - #define DRM_VIA_PCICMD 0x0a 78 - #define DRM_VIA_CMDBUF_SIZE 0x0b 79 - #define NOT_USED 80 - #define DRM_VIA_WAIT_IRQ 0x0d 81 - #define DRM_VIA_DMA_BLIT 0x0e 82 - #define DRM_VIA_BLIT_SYNC 0x0f 83 - 84 - #define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t) 85 - #define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t) 86 - #define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t) 87 - #define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t) 88 - #define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t) 89 - #define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t) 90 - #define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t) 91 - #define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t) 92 - #define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH) 93 - #define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t) 94 - #define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \ 95 - drm_via_cmdbuf_size_t) 96 - #define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t) 97 - #define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t) 98 - #define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t) 99 - 100 - /* Indices into buf.Setup where various bits of state are mirrored per 101 - * context and per buffer. These can be fired at the card as a unit, 102 - * or in a piecewise fashion as required. 103 - */ 104 - 105 - #define VIA_TEX_SETUP_SIZE 8 106 - 107 - /* Flags for clear ioctl 108 - */ 109 - #define VIA_FRONT 0x1 110 - #define VIA_BACK 0x2 111 - #define VIA_DEPTH 0x4 112 - #define VIA_STENCIL 0x8 113 - #define VIA_MEM_VIDEO 0 /* matches drm constant */ 114 - #define VIA_MEM_AGP 1 /* matches drm constant */ 115 - #define VIA_MEM_SYSTEM 2 116 - #define VIA_MEM_MIXED 3 117 - #define VIA_MEM_UNKNOWN 4 118 - 119 - typedef struct { 120 - __u32 offset; 121 - __u32 size; 122 - } drm_via_agp_t; 123 - 124 - typedef struct { 125 - __u32 offset; 126 - __u32 size; 127 - } drm_via_fb_t; 128 - 129 - typedef struct { 130 - __u32 context; 131 - __u32 type; 132 - __u32 size; 133 - unsigned long index; 134 - unsigned long offset; 135 - } drm_via_mem_t; 136 - 137 - typedef struct _drm_via_init { 138 - enum { 139 - VIA_INIT_MAP = 0x01, 140 - VIA_CLEANUP_MAP = 0x02 141 - } func; 142 - 143 - unsigned long sarea_priv_offset; 144 - unsigned long fb_offset; 145 - unsigned long mmio_offset; 146 - unsigned long agpAddr; 147 - } drm_via_init_t; 148 - 149 - typedef struct _drm_via_futex { 150 - enum { 151 - VIA_FUTEX_WAIT = 0x00, 152 - VIA_FUTEX_WAKE = 0X01 153 - } func; 154 - __u32 ms; 155 - __u32 lock; 156 - __u32 val; 157 - } drm_via_futex_t; 158 - 159 - typedef struct _drm_via_dma_init { 160 - enum { 161 - VIA_INIT_DMA = 0x01, 162 - VIA_CLEANUP_DMA = 0x02, 163 - VIA_DMA_INITIALIZED = 0x03 164 - } func; 165 - 166 - unsigned long offset; 167 - unsigned long size; 168 - unsigned long reg_pause_addr; 169 - } drm_via_dma_init_t; 170 - 171 - typedef struct _drm_via_cmdbuffer { 172 - char __user *buf; 173 - unsigned long size; 174 - } drm_via_cmdbuffer_t; 175 - 176 - /* Warning: If you change the SAREA structure you must change the Xserver 177 - * structure as well */ 178 - 179 - typedef struct _drm_via_tex_region { 180 - unsigned char next, prev; /* indices to form a circular LRU */ 181 - unsigned char inUse; /* owned by a client, or free? */ 182 - int age; /* tracked by clients to update local LRU's */ 183 - } drm_via_tex_region_t; 184 - 185 - typedef struct _drm_via_sarea { 186 - unsigned int dirty; 187 - unsigned int nbox; 188 - struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS]; 189 - drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; 190 - int texAge; /* last time texture was uploaded */ 191 - int ctxOwner; /* last context to upload state */ 192 - int vertexPrim; 193 - 194 - /* 195 - * Below is for XvMC. 196 - * We want the lock integers alone on, and aligned to, a cache line. 197 - * Therefore this somewhat strange construct. 198 - */ 199 - 200 - char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)]; 201 - 202 - unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS]; 203 - unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS]; 204 - unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */ 205 - 206 - /* Used by the 3d driver only at this point, for pageflipping: 207 - */ 208 - unsigned int pfCurrentOffset; 209 - } drm_via_sarea_t; 210 - 211 - typedef struct _drm_via_cmdbuf_size { 212 - enum { 213 - VIA_CMDBUF_SPACE = 0x01, 214 - VIA_CMDBUF_LAG = 0x02 215 - } func; 216 - int wait; 217 - __u32 size; 218 - } drm_via_cmdbuf_size_t; 219 - 220 - typedef enum { 221 - VIA_IRQ_ABSOLUTE = 0x0, 222 - VIA_IRQ_RELATIVE = 0x1, 223 - VIA_IRQ_SIGNAL = 0x10000000, 224 - VIA_IRQ_FORCE_SEQUENCE = 0x20000000 225 - } via_irq_seq_type_t; 226 - 227 - #define VIA_IRQ_FLAGS_MASK 0xF0000000 228 - 229 - enum drm_via_irqs { 230 - drm_via_irq_hqv0 = 0, 231 - drm_via_irq_hqv1, 232 - drm_via_irq_dma0_dd, 233 - drm_via_irq_dma0_td, 234 - drm_via_irq_dma1_dd, 235 - drm_via_irq_dma1_td, 236 - drm_via_irq_num 237 - }; 238 - 239 - struct drm_via_wait_irq_request { 240 - unsigned irq; 241 - via_irq_seq_type_t type; 242 - __u32 sequence; 243 - __u32 signal; 244 - }; 245 - 246 - typedef union drm_via_irqwait { 247 - struct drm_via_wait_irq_request request; 248 - struct drm_wait_vblank_reply reply; 249 - } drm_via_irqwait_t; 250 - 251 - typedef struct drm_via_blitsync { 252 - __u32 sync_handle; 253 - unsigned engine; 254 - } drm_via_blitsync_t; 255 - 256 - /* - * Below,"flags" is currently unused but will be used for possible future 257 - * extensions like kernel space bounce buffers for bad alignments and 258 - * blit engine busy-wait polling for better latency in the absence of 259 - * interrupts. 260 - */ 261 - 262 - typedef struct drm_via_dmablit { 263 - __u32 num_lines; 264 - __u32 line_length; 265 - 266 - __u32 fb_addr; 267 - __u32 fb_stride; 268 - 269 - unsigned char *mem_addr; 270 - __u32 mem_stride; 271 - 272 - __u32 flags; 273 - int to_fb; 274 - 275 - drm_via_blitsync_t sync; 276 - } drm_via_dmablit_t; 277 - 278 - #if defined(__cplusplus) 279 - } 280 - #endif 281 - 282 - #endif /* _VIA_DRM_H_ */