Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

perf arch: Support register names from all archs

When reading a perf.data file with register values, there is a mismatch
between the names and the values of the registers because the tool is
built using only the register names from the local architecture.

Reading a perf.data file that was recorded on ARM64, gives the following
erroneous output on an X86 machine:

# perf report -i perf_arm64.data -D
[...]
24661932634451 0x698 [0x21d0]: PERF_RECORD_SAMPLE(IP, 0x1): 43239/43239: 0xffffc5be8f100f98 period: 1 addr: 0
... user regs: mask 0x1ffffffff ABI 64-bit
.... AX 0x0000ffffd1515817
.... BX 0x0000ffffd1515480
.... CX 0x0000aaaadabf6c80
.... DX 0x000000000000002e
.... SI 0x0000000040100401
.... DI 0x0040600200000080
.... BP 0x0000ffffd1510e10
.... SP 0x0000000000000000
.... IP 0x00000000000000dd
.... FLAGS 0x0000ffffd1510cd0
.... CS 0x0000000000000000
.... SS 0x0000000000000030
.... DS 0x0000ffffa569a208
.... ES 0x0000000000000000
.... FS 0x0000000000000000
.... GS 0x0000000000000000
.... R8 0x0000aaaad3de9650
.... R9 0x0000ffffa57397f0
.... R10 0x0000000000000001
.... R11 0x0000ffffa57fd000
.... R12 0x0000ffffd1515817
.... R13 0x0000ffffd1515480
.... R14 0x0000aaaadabf6c80
.... R15 0x0000000000000000
.... unknown 0x0000000000000001
.... unknown 0x0000000000000000
.... unknown 0x0000000000000000
.... unknown 0x0000000000000000
.... unknown 0x0000000000000000
.... unknown 0x0000ffffd1510d90
.... unknown 0x0000ffffa5739b90
.... unknown 0x0000ffffd1510d80
.... XMM0 0x0000ffffa57392c8
... thread: perf-exec:43239
...... dso: [kernel.kallsyms]

As can be seen, the register names correspond to X86 registers, even
though the perf.data file was recorded on an ARM64 system. After this
patch, the output of the command displays the correct register names:

# perf report -i perf_arm64.data -D
[...]
24661932634451 0x698 [0x21d0]: PERF_RECORD_SAMPLE(IP, 0x1): 43239/43239: 0xffffc5be8f100f98 period: 1 addr: 0
... user regs: mask 0x1ffffffff ABI 64-bit
.... x0 0x0000ffffd1515817
.... x1 0x0000ffffd1515480
.... x2 0x0000aaaadabf6c80
.... x3 0x000000000000002e
.... x4 0x0000000040100401
.... x5 0x0040600200000080
.... x6 0x0000ffffd1510e10
.... x7 0x0000000000000000
.... x8 0x00000000000000dd
.... x9 0x0000ffffd1510cd0
.... x10 0x0000000000000000
.... x11 0x0000000000000030
.... x12 0x0000ffffa569a208
.... x13 0x0000000000000000
.... x14 0x0000000000000000
.... x15 0x0000000000000000
.... x16 0x0000aaaad3de9650
.... x17 0x0000ffffa57397f0
.... x18 0x0000000000000001
.... x19 0x0000ffffa57fd000
.... x20 0x0000ffffd1515817
.... x21 0x0000ffffd1515480
.... x22 0x0000aaaadabf6c80
.... x23 0x0000000000000000
.... x24 0x0000000000000001
.... x25 0x0000000000000000
.... x26 0x0000000000000000
.... x27 0x0000000000000000
.... x28 0x0000000000000000
.... x29 0x0000ffffd1510d90
.... lr 0x0000ffffa5739b90
.... sp 0x0000ffffd1510d80
.... pc 0x0000ffffa57392c8
... thread: perf-exec:43239
...... dso: [kernel.kallsyms]

Tester comments:

Athira reports:

"Looks good to me. Tested this patchset in powerpc by capturing regs in
powerpc and doing perf report to read the data from x86."

Reported-by: Alexandre Truong <alexandre.truong@arm.com>
Reviewed-by: Athira Jajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: German Gomez <german.gomez@arm.com>
Tested-by: Athira Jajeev <atrajeev@linux.vnet.ibm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: John Garry <john.garry@huawei.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-csky@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Link: https://lore.kernel.org/r/20211207180653.1147374-4-german.gomez@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

authored by

German Gomez and committed by
Arnaldo Carvalho de Melo
83869019 d3b58af9

+697 -601
-42
tools/perf/arch/arm/include/perf_regs.h
··· 15 15 #define PERF_REG_IP PERF_REG_ARM_PC 16 16 #define PERF_REG_SP PERF_REG_ARM_SP 17 17 18 - static inline const char *__perf_reg_name(int id) 19 - { 20 - switch (id) { 21 - case PERF_REG_ARM_R0: 22 - return "r0"; 23 - case PERF_REG_ARM_R1: 24 - return "r1"; 25 - case PERF_REG_ARM_R2: 26 - return "r2"; 27 - case PERF_REG_ARM_R3: 28 - return "r3"; 29 - case PERF_REG_ARM_R4: 30 - return "r4"; 31 - case PERF_REG_ARM_R5: 32 - return "r5"; 33 - case PERF_REG_ARM_R6: 34 - return "r6"; 35 - case PERF_REG_ARM_R7: 36 - return "r7"; 37 - case PERF_REG_ARM_R8: 38 - return "r8"; 39 - case PERF_REG_ARM_R9: 40 - return "r9"; 41 - case PERF_REG_ARM_R10: 42 - return "r10"; 43 - case PERF_REG_ARM_FP: 44 - return "fp"; 45 - case PERF_REG_ARM_IP: 46 - return "ip"; 47 - case PERF_REG_ARM_SP: 48 - return "sp"; 49 - case PERF_REG_ARM_LR: 50 - return "lr"; 51 - case PERF_REG_ARM_PC: 52 - return "pc"; 53 - default: 54 - return NULL; 55 - } 56 - 57 - return NULL; 58 - } 59 - 60 18 #endif /* ARCH_PERF_REGS_H */
-76
tools/perf/arch/arm64/include/perf_regs.h
··· 17 17 #define PERF_REG_IP PERF_REG_ARM64_PC 18 18 #define PERF_REG_SP PERF_REG_ARM64_SP 19 19 20 - static inline const char *__perf_reg_name(int id) 21 - { 22 - switch (id) { 23 - case PERF_REG_ARM64_X0: 24 - return "x0"; 25 - case PERF_REG_ARM64_X1: 26 - return "x1"; 27 - case PERF_REG_ARM64_X2: 28 - return "x2"; 29 - case PERF_REG_ARM64_X3: 30 - return "x3"; 31 - case PERF_REG_ARM64_X4: 32 - return "x4"; 33 - case PERF_REG_ARM64_X5: 34 - return "x5"; 35 - case PERF_REG_ARM64_X6: 36 - return "x6"; 37 - case PERF_REG_ARM64_X7: 38 - return "x7"; 39 - case PERF_REG_ARM64_X8: 40 - return "x8"; 41 - case PERF_REG_ARM64_X9: 42 - return "x9"; 43 - case PERF_REG_ARM64_X10: 44 - return "x10"; 45 - case PERF_REG_ARM64_X11: 46 - return "x11"; 47 - case PERF_REG_ARM64_X12: 48 - return "x12"; 49 - case PERF_REG_ARM64_X13: 50 - return "x13"; 51 - case PERF_REG_ARM64_X14: 52 - return "x14"; 53 - case PERF_REG_ARM64_X15: 54 - return "x15"; 55 - case PERF_REG_ARM64_X16: 56 - return "x16"; 57 - case PERF_REG_ARM64_X17: 58 - return "x17"; 59 - case PERF_REG_ARM64_X18: 60 - return "x18"; 61 - case PERF_REG_ARM64_X19: 62 - return "x19"; 63 - case PERF_REG_ARM64_X20: 64 - return "x20"; 65 - case PERF_REG_ARM64_X21: 66 - return "x21"; 67 - case PERF_REG_ARM64_X22: 68 - return "x22"; 69 - case PERF_REG_ARM64_X23: 70 - return "x23"; 71 - case PERF_REG_ARM64_X24: 72 - return "x24"; 73 - case PERF_REG_ARM64_X25: 74 - return "x25"; 75 - case PERF_REG_ARM64_X26: 76 - return "x26"; 77 - case PERF_REG_ARM64_X27: 78 - return "x27"; 79 - case PERF_REG_ARM64_X28: 80 - return "x28"; 81 - case PERF_REG_ARM64_X29: 82 - return "x29"; 83 - case PERF_REG_ARM64_SP: 84 - return "sp"; 85 - case PERF_REG_ARM64_LR: 86 - return "lr"; 87 - case PERF_REG_ARM64_PC: 88 - return "pc"; 89 - default: 90 - return NULL; 91 - } 92 - 93 - return NULL; 94 - } 95 - 96 20 #endif /* ARCH_PERF_REGS_H */
-82
tools/perf/arch/csky/include/perf_regs.h
··· 15 15 #define PERF_REG_IP PERF_REG_CSKY_PC 16 16 #define PERF_REG_SP PERF_REG_CSKY_SP 17 17 18 - static inline const char *__perf_reg_name(int id) 19 - { 20 - switch (id) { 21 - case PERF_REG_CSKY_A0: 22 - return "a0"; 23 - case PERF_REG_CSKY_A1: 24 - return "a1"; 25 - case PERF_REG_CSKY_A2: 26 - return "a2"; 27 - case PERF_REG_CSKY_A3: 28 - return "a3"; 29 - case PERF_REG_CSKY_REGS0: 30 - return "regs0"; 31 - case PERF_REG_CSKY_REGS1: 32 - return "regs1"; 33 - case PERF_REG_CSKY_REGS2: 34 - return "regs2"; 35 - case PERF_REG_CSKY_REGS3: 36 - return "regs3"; 37 - case PERF_REG_CSKY_REGS4: 38 - return "regs4"; 39 - case PERF_REG_CSKY_REGS5: 40 - return "regs5"; 41 - case PERF_REG_CSKY_REGS6: 42 - return "regs6"; 43 - case PERF_REG_CSKY_REGS7: 44 - return "regs7"; 45 - case PERF_REG_CSKY_REGS8: 46 - return "regs8"; 47 - case PERF_REG_CSKY_REGS9: 48 - return "regs9"; 49 - case PERF_REG_CSKY_SP: 50 - return "sp"; 51 - case PERF_REG_CSKY_LR: 52 - return "lr"; 53 - case PERF_REG_CSKY_PC: 54 - return "pc"; 55 - #if defined(__CSKYABIV2__) 56 - case PERF_REG_CSKY_EXREGS0: 57 - return "exregs0"; 58 - case PERF_REG_CSKY_EXREGS1: 59 - return "exregs1"; 60 - case PERF_REG_CSKY_EXREGS2: 61 - return "exregs2"; 62 - case PERF_REG_CSKY_EXREGS3: 63 - return "exregs3"; 64 - case PERF_REG_CSKY_EXREGS4: 65 - return "exregs4"; 66 - case PERF_REG_CSKY_EXREGS5: 67 - return "exregs5"; 68 - case PERF_REG_CSKY_EXREGS6: 69 - return "exregs6"; 70 - case PERF_REG_CSKY_EXREGS7: 71 - return "exregs7"; 72 - case PERF_REG_CSKY_EXREGS8: 73 - return "exregs8"; 74 - case PERF_REG_CSKY_EXREGS9: 75 - return "exregs9"; 76 - case PERF_REG_CSKY_EXREGS10: 77 - return "exregs10"; 78 - case PERF_REG_CSKY_EXREGS11: 79 - return "exregs11"; 80 - case PERF_REG_CSKY_EXREGS12: 81 - return "exregs12"; 82 - case PERF_REG_CSKY_EXREGS13: 83 - return "exregs13"; 84 - case PERF_REG_CSKY_EXREGS14: 85 - return "exregs14"; 86 - case PERF_REG_CSKY_TLS: 87 - return "tls"; 88 - case PERF_REG_CSKY_HI: 89 - return "hi"; 90 - case PERF_REG_CSKY_LO: 91 - return "lo"; 92 - #endif 93 - default: 94 - return NULL; 95 - } 96 - 97 - return NULL; 98 - } 99 - 100 18 #endif /* ARCH_PERF_REGS_H */
-69
tools/perf/arch/mips/include/perf_regs.h
··· 12 12 13 13 #define PERF_REGS_MASK ((1ULL << PERF_REG_MIPS_MAX) - 1) 14 14 15 - static inline const char *__perf_reg_name(int id) 16 - { 17 - switch (id) { 18 - case PERF_REG_MIPS_PC: 19 - return "PC"; 20 - case PERF_REG_MIPS_R1: 21 - return "$1"; 22 - case PERF_REG_MIPS_R2: 23 - return "$2"; 24 - case PERF_REG_MIPS_R3: 25 - return "$3"; 26 - case PERF_REG_MIPS_R4: 27 - return "$4"; 28 - case PERF_REG_MIPS_R5: 29 - return "$5"; 30 - case PERF_REG_MIPS_R6: 31 - return "$6"; 32 - case PERF_REG_MIPS_R7: 33 - return "$7"; 34 - case PERF_REG_MIPS_R8: 35 - return "$8"; 36 - case PERF_REG_MIPS_R9: 37 - return "$9"; 38 - case PERF_REG_MIPS_R10: 39 - return "$10"; 40 - case PERF_REG_MIPS_R11: 41 - return "$11"; 42 - case PERF_REG_MIPS_R12: 43 - return "$12"; 44 - case PERF_REG_MIPS_R13: 45 - return "$13"; 46 - case PERF_REG_MIPS_R14: 47 - return "$14"; 48 - case PERF_REG_MIPS_R15: 49 - return "$15"; 50 - case PERF_REG_MIPS_R16: 51 - return "$16"; 52 - case PERF_REG_MIPS_R17: 53 - return "$17"; 54 - case PERF_REG_MIPS_R18: 55 - return "$18"; 56 - case PERF_REG_MIPS_R19: 57 - return "$19"; 58 - case PERF_REG_MIPS_R20: 59 - return "$20"; 60 - case PERF_REG_MIPS_R21: 61 - return "$21"; 62 - case PERF_REG_MIPS_R22: 63 - return "$22"; 64 - case PERF_REG_MIPS_R23: 65 - return "$23"; 66 - case PERF_REG_MIPS_R24: 67 - return "$24"; 68 - case PERF_REG_MIPS_R25: 69 - return "$25"; 70 - case PERF_REG_MIPS_R28: 71 - return "$28"; 72 - case PERF_REG_MIPS_R29: 73 - return "$29"; 74 - case PERF_REG_MIPS_R30: 75 - return "$30"; 76 - case PERF_REG_MIPS_R31: 77 - return "$31"; 78 - default: 79 - break; 80 - } 81 - return NULL; 82 - } 83 - 84 15 #endif /* ARCH_PERF_REGS_H */
-66
tools/perf/arch/powerpc/include/perf_regs.h
··· 19 19 #define PERF_REG_IP PERF_REG_POWERPC_NIP 20 20 #define PERF_REG_SP PERF_REG_POWERPC_R1 21 21 22 - static const char *reg_names[] = { 23 - [PERF_REG_POWERPC_R0] = "r0", 24 - [PERF_REG_POWERPC_R1] = "r1", 25 - [PERF_REG_POWERPC_R2] = "r2", 26 - [PERF_REG_POWERPC_R3] = "r3", 27 - [PERF_REG_POWERPC_R4] = "r4", 28 - [PERF_REG_POWERPC_R5] = "r5", 29 - [PERF_REG_POWERPC_R6] = "r6", 30 - [PERF_REG_POWERPC_R7] = "r7", 31 - [PERF_REG_POWERPC_R8] = "r8", 32 - [PERF_REG_POWERPC_R9] = "r9", 33 - [PERF_REG_POWERPC_R10] = "r10", 34 - [PERF_REG_POWERPC_R11] = "r11", 35 - [PERF_REG_POWERPC_R12] = "r12", 36 - [PERF_REG_POWERPC_R13] = "r13", 37 - [PERF_REG_POWERPC_R14] = "r14", 38 - [PERF_REG_POWERPC_R15] = "r15", 39 - [PERF_REG_POWERPC_R16] = "r16", 40 - [PERF_REG_POWERPC_R17] = "r17", 41 - [PERF_REG_POWERPC_R18] = "r18", 42 - [PERF_REG_POWERPC_R19] = "r19", 43 - [PERF_REG_POWERPC_R20] = "r20", 44 - [PERF_REG_POWERPC_R21] = "r21", 45 - [PERF_REG_POWERPC_R22] = "r22", 46 - [PERF_REG_POWERPC_R23] = "r23", 47 - [PERF_REG_POWERPC_R24] = "r24", 48 - [PERF_REG_POWERPC_R25] = "r25", 49 - [PERF_REG_POWERPC_R26] = "r26", 50 - [PERF_REG_POWERPC_R27] = "r27", 51 - [PERF_REG_POWERPC_R28] = "r28", 52 - [PERF_REG_POWERPC_R29] = "r29", 53 - [PERF_REG_POWERPC_R30] = "r30", 54 - [PERF_REG_POWERPC_R31] = "r31", 55 - [PERF_REG_POWERPC_NIP] = "nip", 56 - [PERF_REG_POWERPC_MSR] = "msr", 57 - [PERF_REG_POWERPC_ORIG_R3] = "orig_r3", 58 - [PERF_REG_POWERPC_CTR] = "ctr", 59 - [PERF_REG_POWERPC_LINK] = "link", 60 - [PERF_REG_POWERPC_XER] = "xer", 61 - [PERF_REG_POWERPC_CCR] = "ccr", 62 - [PERF_REG_POWERPC_SOFTE] = "softe", 63 - [PERF_REG_POWERPC_TRAP] = "trap", 64 - [PERF_REG_POWERPC_DAR] = "dar", 65 - [PERF_REG_POWERPC_DSISR] = "dsisr", 66 - [PERF_REG_POWERPC_SIER] = "sier", 67 - [PERF_REG_POWERPC_MMCRA] = "mmcra", 68 - [PERF_REG_POWERPC_MMCR0] = "mmcr0", 69 - [PERF_REG_POWERPC_MMCR1] = "mmcr1", 70 - [PERF_REG_POWERPC_MMCR2] = "mmcr2", 71 - [PERF_REG_POWERPC_MMCR3] = "mmcr3", 72 - [PERF_REG_POWERPC_SIER2] = "sier2", 73 - [PERF_REG_POWERPC_SIER3] = "sier3", 74 - [PERF_REG_POWERPC_PMC1] = "pmc1", 75 - [PERF_REG_POWERPC_PMC2] = "pmc2", 76 - [PERF_REG_POWERPC_PMC3] = "pmc3", 77 - [PERF_REG_POWERPC_PMC4] = "pmc4", 78 - [PERF_REG_POWERPC_PMC5] = "pmc5", 79 - [PERF_REG_POWERPC_PMC6] = "pmc6", 80 - [PERF_REG_POWERPC_SDAR] = "sdar", 81 - [PERF_REG_POWERPC_SIAR] = "siar", 82 - }; 83 - 84 - static inline const char *__perf_reg_name(int id) 85 - { 86 - return reg_names[id]; 87 - } 88 22 #endif /* ARCH_PERF_REGS_H */
-74
tools/perf/arch/riscv/include/perf_regs.h
··· 19 19 #define PERF_REG_IP PERF_REG_RISCV_PC 20 20 #define PERF_REG_SP PERF_REG_RISCV_SP 21 21 22 - static inline const char *__perf_reg_name(int id) 23 - { 24 - switch (id) { 25 - case PERF_REG_RISCV_PC: 26 - return "pc"; 27 - case PERF_REG_RISCV_RA: 28 - return "ra"; 29 - case PERF_REG_RISCV_SP: 30 - return "sp"; 31 - case PERF_REG_RISCV_GP: 32 - return "gp"; 33 - case PERF_REG_RISCV_TP: 34 - return "tp"; 35 - case PERF_REG_RISCV_T0: 36 - return "t0"; 37 - case PERF_REG_RISCV_T1: 38 - return "t1"; 39 - case PERF_REG_RISCV_T2: 40 - return "t2"; 41 - case PERF_REG_RISCV_S0: 42 - return "s0"; 43 - case PERF_REG_RISCV_S1: 44 - return "s1"; 45 - case PERF_REG_RISCV_A0: 46 - return "a0"; 47 - case PERF_REG_RISCV_A1: 48 - return "a1"; 49 - case PERF_REG_RISCV_A2: 50 - return "a2"; 51 - case PERF_REG_RISCV_A3: 52 - return "a3"; 53 - case PERF_REG_RISCV_A4: 54 - return "a4"; 55 - case PERF_REG_RISCV_A5: 56 - return "a5"; 57 - case PERF_REG_RISCV_A6: 58 - return "a6"; 59 - case PERF_REG_RISCV_A7: 60 - return "a7"; 61 - case PERF_REG_RISCV_S2: 62 - return "s2"; 63 - case PERF_REG_RISCV_S3: 64 - return "s3"; 65 - case PERF_REG_RISCV_S4: 66 - return "s4"; 67 - case PERF_REG_RISCV_S5: 68 - return "s5"; 69 - case PERF_REG_RISCV_S6: 70 - return "s6"; 71 - case PERF_REG_RISCV_S7: 72 - return "s7"; 73 - case PERF_REG_RISCV_S8: 74 - return "s8"; 75 - case PERF_REG_RISCV_S9: 76 - return "s9"; 77 - case PERF_REG_RISCV_S10: 78 - return "s10"; 79 - case PERF_REG_RISCV_S11: 80 - return "s11"; 81 - case PERF_REG_RISCV_T3: 82 - return "t3"; 83 - case PERF_REG_RISCV_T4: 84 - return "t4"; 85 - case PERF_REG_RISCV_T5: 86 - return "t5"; 87 - case PERF_REG_RISCV_T6: 88 - return "t6"; 89 - default: 90 - return NULL; 91 - } 92 - 93 - return NULL; 94 - } 95 - 96 22 #endif /* ARCH_PERF_REGS_H */
-78
tools/perf/arch/s390/include/perf_regs.h
··· 14 14 #define PERF_REG_IP PERF_REG_S390_PC 15 15 #define PERF_REG_SP PERF_REG_S390_R15 16 16 17 - static inline const char *__perf_reg_name(int id) 18 - { 19 - switch (id) { 20 - case PERF_REG_S390_R0: 21 - return "R0"; 22 - case PERF_REG_S390_R1: 23 - return "R1"; 24 - case PERF_REG_S390_R2: 25 - return "R2"; 26 - case PERF_REG_S390_R3: 27 - return "R3"; 28 - case PERF_REG_S390_R4: 29 - return "R4"; 30 - case PERF_REG_S390_R5: 31 - return "R5"; 32 - case PERF_REG_S390_R6: 33 - return "R6"; 34 - case PERF_REG_S390_R7: 35 - return "R7"; 36 - case PERF_REG_S390_R8: 37 - return "R8"; 38 - case PERF_REG_S390_R9: 39 - return "R9"; 40 - case PERF_REG_S390_R10: 41 - return "R10"; 42 - case PERF_REG_S390_R11: 43 - return "R11"; 44 - case PERF_REG_S390_R12: 45 - return "R12"; 46 - case PERF_REG_S390_R13: 47 - return "R13"; 48 - case PERF_REG_S390_R14: 49 - return "R14"; 50 - case PERF_REG_S390_R15: 51 - return "R15"; 52 - case PERF_REG_S390_FP0: 53 - return "FP0"; 54 - case PERF_REG_S390_FP1: 55 - return "FP1"; 56 - case PERF_REG_S390_FP2: 57 - return "FP2"; 58 - case PERF_REG_S390_FP3: 59 - return "FP3"; 60 - case PERF_REG_S390_FP4: 61 - return "FP4"; 62 - case PERF_REG_S390_FP5: 63 - return "FP5"; 64 - case PERF_REG_S390_FP6: 65 - return "FP6"; 66 - case PERF_REG_S390_FP7: 67 - return "FP7"; 68 - case PERF_REG_S390_FP8: 69 - return "FP8"; 70 - case PERF_REG_S390_FP9: 71 - return "FP9"; 72 - case PERF_REG_S390_FP10: 73 - return "FP10"; 74 - case PERF_REG_S390_FP11: 75 - return "FP11"; 76 - case PERF_REG_S390_FP12: 77 - return "FP12"; 78 - case PERF_REG_S390_FP13: 79 - return "FP13"; 80 - case PERF_REG_S390_FP14: 81 - return "FP14"; 82 - case PERF_REG_S390_FP15: 83 - return "FP15"; 84 - case PERF_REG_S390_MASK: 85 - return "MASK"; 86 - case PERF_REG_S390_PC: 87 - return "PC"; 88 - default: 89 - return NULL; 90 - } 91 - 92 - return NULL; 93 - } 94 - 95 17 #endif /* ARCH_PERF_REGS_H */
-82
tools/perf/arch/x86/include/perf_regs.h
··· 23 23 #define PERF_REG_IP PERF_REG_X86_IP 24 24 #define PERF_REG_SP PERF_REG_X86_SP 25 25 26 - static inline const char *__perf_reg_name(int id) 27 - { 28 - switch (id) { 29 - case PERF_REG_X86_AX: 30 - return "AX"; 31 - case PERF_REG_X86_BX: 32 - return "BX"; 33 - case PERF_REG_X86_CX: 34 - return "CX"; 35 - case PERF_REG_X86_DX: 36 - return "DX"; 37 - case PERF_REG_X86_SI: 38 - return "SI"; 39 - case PERF_REG_X86_DI: 40 - return "DI"; 41 - case PERF_REG_X86_BP: 42 - return "BP"; 43 - case PERF_REG_X86_SP: 44 - return "SP"; 45 - case PERF_REG_X86_IP: 46 - return "IP"; 47 - case PERF_REG_X86_FLAGS: 48 - return "FLAGS"; 49 - case PERF_REG_X86_CS: 50 - return "CS"; 51 - case PERF_REG_X86_SS: 52 - return "SS"; 53 - case PERF_REG_X86_DS: 54 - return "DS"; 55 - case PERF_REG_X86_ES: 56 - return "ES"; 57 - case PERF_REG_X86_FS: 58 - return "FS"; 59 - case PERF_REG_X86_GS: 60 - return "GS"; 61 - #ifdef HAVE_ARCH_X86_64_SUPPORT 62 - case PERF_REG_X86_R8: 63 - return "R8"; 64 - case PERF_REG_X86_R9: 65 - return "R9"; 66 - case PERF_REG_X86_R10: 67 - return "R10"; 68 - case PERF_REG_X86_R11: 69 - return "R11"; 70 - case PERF_REG_X86_R12: 71 - return "R12"; 72 - case PERF_REG_X86_R13: 73 - return "R13"; 74 - case PERF_REG_X86_R14: 75 - return "R14"; 76 - case PERF_REG_X86_R15: 77 - return "R15"; 78 - #endif /* HAVE_ARCH_X86_64_SUPPORT */ 79 - 80 - #define XMM(x) \ 81 - case PERF_REG_X86_XMM ## x: \ 82 - case PERF_REG_X86_XMM ## x + 1: \ 83 - return "XMM" #x; 84 - XMM(0) 85 - XMM(1) 86 - XMM(2) 87 - XMM(3) 88 - XMM(4) 89 - XMM(5) 90 - XMM(6) 91 - XMM(7) 92 - XMM(8) 93 - XMM(9) 94 - XMM(10) 95 - XMM(11) 96 - XMM(12) 97 - XMM(13) 98 - XMM(14) 99 - XMM(15) 100 - #undef XMM 101 - default: 102 - return NULL; 103 - } 104 - 105 - return NULL; 106 - } 107 - 108 26 #endif /* ARCH_PERF_REGS_H */
+10 -8
tools/perf/builtin-script.c
··· 15 15 #include "util/symbol.h" 16 16 #include "util/thread.h" 17 17 #include "util/trace-event.h" 18 + #include "util/env.h" 18 19 #include "util/evlist.h" 19 20 #include "util/evsel.h" 20 21 #include "util/evsel_fprintf.h" ··· 649 648 return 0; 650 649 } 651 650 652 - static int perf_sample__fprintf_regs(struct regs_dump *regs, uint64_t mask, 651 + static int perf_sample__fprintf_regs(struct regs_dump *regs, uint64_t mask, const char *arch, 653 652 FILE *fp) 654 653 { 655 654 unsigned i = 0, r; ··· 662 661 663 662 for_each_set_bit(r, (unsigned long *) &mask, sizeof(mask) * 8) { 664 663 u64 val = regs->regs[i++]; 665 - printed += fprintf(fp, "%5s:0x%"PRIx64" ", perf_reg_name(r), val); 664 + printed += fprintf(fp, "%5s:0x%"PRIx64" ", perf_reg_name(r, arch), val); 666 665 } 667 666 668 667 return printed; ··· 719 718 } 720 719 721 720 static int perf_sample__fprintf_iregs(struct perf_sample *sample, 722 - struct perf_event_attr *attr, FILE *fp) 721 + struct perf_event_attr *attr, const char *arch, FILE *fp) 723 722 { 724 723 return perf_sample__fprintf_regs(&sample->intr_regs, 725 - attr->sample_regs_intr, fp); 724 + attr->sample_regs_intr, arch, fp); 726 725 } 727 726 728 727 static int perf_sample__fprintf_uregs(struct perf_sample *sample, 729 - struct perf_event_attr *attr, FILE *fp) 728 + struct perf_event_attr *attr, const char *arch, FILE *fp) 730 729 { 731 730 return perf_sample__fprintf_regs(&sample->user_regs, 732 - attr->sample_regs_user, fp); 731 + attr->sample_regs_user, arch, fp); 733 732 } 734 733 735 734 static int perf_sample__fprintf_start(struct perf_script *script, ··· 2001 2000 struct evsel_script *es = evsel->priv; 2002 2001 FILE *fp = es->fp; 2003 2002 char str[PAGE_SIZE_NAME_LEN]; 2003 + const char *arch = perf_env__arch(machine->env); 2004 2004 2005 2005 if (output[type].fields == 0) 2006 2006 return; ··· 2068 2066 } 2069 2067 2070 2068 if (PRINT_FIELD(IREGS)) 2071 - perf_sample__fprintf_iregs(sample, attr, fp); 2069 + perf_sample__fprintf_iregs(sample, attr, arch, fp); 2072 2070 2073 2071 if (PRINT_FIELD(UREGS)) 2074 - perf_sample__fprintf_uregs(sample, attr, fp); 2072 + perf_sample__fprintf_uregs(sample, attr, arch, fp); 2075 2073 2076 2074 if (PRINT_FIELD(BRSTACK)) 2077 2075 perf_sample__fprintf_brstack(sample, thread, attr, fp);
+666
tools/perf/util/perf_regs.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 #include <errno.h> 3 + #include <string.h> 3 4 #include "perf_regs.h" 4 5 #include "event.h" 5 6 ··· 21 20 } 22 21 23 22 #ifdef HAVE_PERF_REGS_SUPPORT 23 + 24 + #define perf_event_arm_regs perf_event_arm64_regs 25 + #include "../../arch/arm64/include/uapi/asm/perf_regs.h" 26 + #undef perf_event_arm_regs 27 + 28 + #include "../../arch/arm/include/uapi/asm/perf_regs.h" 29 + #include "../../arch/csky/include/uapi/asm/perf_regs.h" 30 + #include "../../arch/mips/include/uapi/asm/perf_regs.h" 31 + #include "../../arch/powerpc/include/uapi/asm/perf_regs.h" 32 + #include "../../arch/riscv/include/uapi/asm/perf_regs.h" 33 + #include "../../arch/s390/include/uapi/asm/perf_regs.h" 34 + #include "../../arch/x86/include/uapi/asm/perf_regs.h" 35 + 36 + static const char *__perf_reg_name_arm64(int id) 37 + { 38 + switch (id) { 39 + case PERF_REG_ARM64_X0: 40 + return "x0"; 41 + case PERF_REG_ARM64_X1: 42 + return "x1"; 43 + case PERF_REG_ARM64_X2: 44 + return "x2"; 45 + case PERF_REG_ARM64_X3: 46 + return "x3"; 47 + case PERF_REG_ARM64_X4: 48 + return "x4"; 49 + case PERF_REG_ARM64_X5: 50 + return "x5"; 51 + case PERF_REG_ARM64_X6: 52 + return "x6"; 53 + case PERF_REG_ARM64_X7: 54 + return "x7"; 55 + case PERF_REG_ARM64_X8: 56 + return "x8"; 57 + case PERF_REG_ARM64_X9: 58 + return "x9"; 59 + case PERF_REG_ARM64_X10: 60 + return "x10"; 61 + case PERF_REG_ARM64_X11: 62 + return "x11"; 63 + case PERF_REG_ARM64_X12: 64 + return "x12"; 65 + case PERF_REG_ARM64_X13: 66 + return "x13"; 67 + case PERF_REG_ARM64_X14: 68 + return "x14"; 69 + case PERF_REG_ARM64_X15: 70 + return "x15"; 71 + case PERF_REG_ARM64_X16: 72 + return "x16"; 73 + case PERF_REG_ARM64_X17: 74 + return "x17"; 75 + case PERF_REG_ARM64_X18: 76 + return "x18"; 77 + case PERF_REG_ARM64_X19: 78 + return "x19"; 79 + case PERF_REG_ARM64_X20: 80 + return "x20"; 81 + case PERF_REG_ARM64_X21: 82 + return "x21"; 83 + case PERF_REG_ARM64_X22: 84 + return "x22"; 85 + case PERF_REG_ARM64_X23: 86 + return "x23"; 87 + case PERF_REG_ARM64_X24: 88 + return "x24"; 89 + case PERF_REG_ARM64_X25: 90 + return "x25"; 91 + case PERF_REG_ARM64_X26: 92 + return "x26"; 93 + case PERF_REG_ARM64_X27: 94 + return "x27"; 95 + case PERF_REG_ARM64_X28: 96 + return "x28"; 97 + case PERF_REG_ARM64_X29: 98 + return "x29"; 99 + case PERF_REG_ARM64_SP: 100 + return "sp"; 101 + case PERF_REG_ARM64_LR: 102 + return "lr"; 103 + case PERF_REG_ARM64_PC: 104 + return "pc"; 105 + default: 106 + return NULL; 107 + } 108 + 109 + return NULL; 110 + } 111 + 112 + static const char *__perf_reg_name_arm(int id) 113 + { 114 + switch (id) { 115 + case PERF_REG_ARM_R0: 116 + return "r0"; 117 + case PERF_REG_ARM_R1: 118 + return "r1"; 119 + case PERF_REG_ARM_R2: 120 + return "r2"; 121 + case PERF_REG_ARM_R3: 122 + return "r3"; 123 + case PERF_REG_ARM_R4: 124 + return "r4"; 125 + case PERF_REG_ARM_R5: 126 + return "r5"; 127 + case PERF_REG_ARM_R6: 128 + return "r6"; 129 + case PERF_REG_ARM_R7: 130 + return "r7"; 131 + case PERF_REG_ARM_R8: 132 + return "r8"; 133 + case PERF_REG_ARM_R9: 134 + return "r9"; 135 + case PERF_REG_ARM_R10: 136 + return "r10"; 137 + case PERF_REG_ARM_FP: 138 + return "fp"; 139 + case PERF_REG_ARM_IP: 140 + return "ip"; 141 + case PERF_REG_ARM_SP: 142 + return "sp"; 143 + case PERF_REG_ARM_LR: 144 + return "lr"; 145 + case PERF_REG_ARM_PC: 146 + return "pc"; 147 + default: 148 + return NULL; 149 + } 150 + 151 + return NULL; 152 + } 153 + 154 + static const char *__perf_reg_name_csky(int id) 155 + { 156 + switch (id) { 157 + case PERF_REG_CSKY_A0: 158 + return "a0"; 159 + case PERF_REG_CSKY_A1: 160 + return "a1"; 161 + case PERF_REG_CSKY_A2: 162 + return "a2"; 163 + case PERF_REG_CSKY_A3: 164 + return "a3"; 165 + case PERF_REG_CSKY_REGS0: 166 + return "regs0"; 167 + case PERF_REG_CSKY_REGS1: 168 + return "regs1"; 169 + case PERF_REG_CSKY_REGS2: 170 + return "regs2"; 171 + case PERF_REG_CSKY_REGS3: 172 + return "regs3"; 173 + case PERF_REG_CSKY_REGS4: 174 + return "regs4"; 175 + case PERF_REG_CSKY_REGS5: 176 + return "regs5"; 177 + case PERF_REG_CSKY_REGS6: 178 + return "regs6"; 179 + case PERF_REG_CSKY_REGS7: 180 + return "regs7"; 181 + case PERF_REG_CSKY_REGS8: 182 + return "regs8"; 183 + case PERF_REG_CSKY_REGS9: 184 + return "regs9"; 185 + case PERF_REG_CSKY_SP: 186 + return "sp"; 187 + case PERF_REG_CSKY_LR: 188 + return "lr"; 189 + case PERF_REG_CSKY_PC: 190 + return "pc"; 191 + #if defined(__CSKYABIV2__) 192 + case PERF_REG_CSKY_EXREGS0: 193 + return "exregs0"; 194 + case PERF_REG_CSKY_EXREGS1: 195 + return "exregs1"; 196 + case PERF_REG_CSKY_EXREGS2: 197 + return "exregs2"; 198 + case PERF_REG_CSKY_EXREGS3: 199 + return "exregs3"; 200 + case PERF_REG_CSKY_EXREGS4: 201 + return "exregs4"; 202 + case PERF_REG_CSKY_EXREGS5: 203 + return "exregs5"; 204 + case PERF_REG_CSKY_EXREGS6: 205 + return "exregs6"; 206 + case PERF_REG_CSKY_EXREGS7: 207 + return "exregs7"; 208 + case PERF_REG_CSKY_EXREGS8: 209 + return "exregs8"; 210 + case PERF_REG_CSKY_EXREGS9: 211 + return "exregs9"; 212 + case PERF_REG_CSKY_EXREGS10: 213 + return "exregs10"; 214 + case PERF_REG_CSKY_EXREGS11: 215 + return "exregs11"; 216 + case PERF_REG_CSKY_EXREGS12: 217 + return "exregs12"; 218 + case PERF_REG_CSKY_EXREGS13: 219 + return "exregs13"; 220 + case PERF_REG_CSKY_EXREGS14: 221 + return "exregs14"; 222 + case PERF_REG_CSKY_TLS: 223 + return "tls"; 224 + case PERF_REG_CSKY_HI: 225 + return "hi"; 226 + case PERF_REG_CSKY_LO: 227 + return "lo"; 228 + #endif 229 + default: 230 + return NULL; 231 + } 232 + 233 + return NULL; 234 + } 235 + 236 + static const char *__perf_reg_name_mips(int id) 237 + { 238 + switch (id) { 239 + case PERF_REG_MIPS_PC: 240 + return "PC"; 241 + case PERF_REG_MIPS_R1: 242 + return "$1"; 243 + case PERF_REG_MIPS_R2: 244 + return "$2"; 245 + case PERF_REG_MIPS_R3: 246 + return "$3"; 247 + case PERF_REG_MIPS_R4: 248 + return "$4"; 249 + case PERF_REG_MIPS_R5: 250 + return "$5"; 251 + case PERF_REG_MIPS_R6: 252 + return "$6"; 253 + case PERF_REG_MIPS_R7: 254 + return "$7"; 255 + case PERF_REG_MIPS_R8: 256 + return "$8"; 257 + case PERF_REG_MIPS_R9: 258 + return "$9"; 259 + case PERF_REG_MIPS_R10: 260 + return "$10"; 261 + case PERF_REG_MIPS_R11: 262 + return "$11"; 263 + case PERF_REG_MIPS_R12: 264 + return "$12"; 265 + case PERF_REG_MIPS_R13: 266 + return "$13"; 267 + case PERF_REG_MIPS_R14: 268 + return "$14"; 269 + case PERF_REG_MIPS_R15: 270 + return "$15"; 271 + case PERF_REG_MIPS_R16: 272 + return "$16"; 273 + case PERF_REG_MIPS_R17: 274 + return "$17"; 275 + case PERF_REG_MIPS_R18: 276 + return "$18"; 277 + case PERF_REG_MIPS_R19: 278 + return "$19"; 279 + case PERF_REG_MIPS_R20: 280 + return "$20"; 281 + case PERF_REG_MIPS_R21: 282 + return "$21"; 283 + case PERF_REG_MIPS_R22: 284 + return "$22"; 285 + case PERF_REG_MIPS_R23: 286 + return "$23"; 287 + case PERF_REG_MIPS_R24: 288 + return "$24"; 289 + case PERF_REG_MIPS_R25: 290 + return "$25"; 291 + case PERF_REG_MIPS_R28: 292 + return "$28"; 293 + case PERF_REG_MIPS_R29: 294 + return "$29"; 295 + case PERF_REG_MIPS_R30: 296 + return "$30"; 297 + case PERF_REG_MIPS_R31: 298 + return "$31"; 299 + default: 300 + break; 301 + } 302 + return NULL; 303 + } 304 + 305 + static const char *__perf_reg_name_powerpc(int id) 306 + { 307 + switch (id) { 308 + case PERF_REG_POWERPC_R0: 309 + return "r0"; 310 + case PERF_REG_POWERPC_R1: 311 + return "r1"; 312 + case PERF_REG_POWERPC_R2: 313 + return "r2"; 314 + case PERF_REG_POWERPC_R3: 315 + return "r3"; 316 + case PERF_REG_POWERPC_R4: 317 + return "r4"; 318 + case PERF_REG_POWERPC_R5: 319 + return "r5"; 320 + case PERF_REG_POWERPC_R6: 321 + return "r6"; 322 + case PERF_REG_POWERPC_R7: 323 + return "r7"; 324 + case PERF_REG_POWERPC_R8: 325 + return "r8"; 326 + case PERF_REG_POWERPC_R9: 327 + return "r9"; 328 + case PERF_REG_POWERPC_R10: 329 + return "r10"; 330 + case PERF_REG_POWERPC_R11: 331 + return "r11"; 332 + case PERF_REG_POWERPC_R12: 333 + return "r12"; 334 + case PERF_REG_POWERPC_R13: 335 + return "r13"; 336 + case PERF_REG_POWERPC_R14: 337 + return "r14"; 338 + case PERF_REG_POWERPC_R15: 339 + return "r15"; 340 + case PERF_REG_POWERPC_R16: 341 + return "r16"; 342 + case PERF_REG_POWERPC_R17: 343 + return "r17"; 344 + case PERF_REG_POWERPC_R18: 345 + return "r18"; 346 + case PERF_REG_POWERPC_R19: 347 + return "r19"; 348 + case PERF_REG_POWERPC_R20: 349 + return "r20"; 350 + case PERF_REG_POWERPC_R21: 351 + return "r21"; 352 + case PERF_REG_POWERPC_R22: 353 + return "r22"; 354 + case PERF_REG_POWERPC_R23: 355 + return "r23"; 356 + case PERF_REG_POWERPC_R24: 357 + return "r24"; 358 + case PERF_REG_POWERPC_R25: 359 + return "r25"; 360 + case PERF_REG_POWERPC_R26: 361 + return "r26"; 362 + case PERF_REG_POWERPC_R27: 363 + return "r27"; 364 + case PERF_REG_POWERPC_R28: 365 + return "r28"; 366 + case PERF_REG_POWERPC_R29: 367 + return "r29"; 368 + case PERF_REG_POWERPC_R30: 369 + return "r30"; 370 + case PERF_REG_POWERPC_R31: 371 + return "r31"; 372 + case PERF_REG_POWERPC_NIP: 373 + return "nip"; 374 + case PERF_REG_POWERPC_MSR: 375 + return "msr"; 376 + case PERF_REG_POWERPC_ORIG_R3: 377 + return "orig_r3"; 378 + case PERF_REG_POWERPC_CTR: 379 + return "ctr"; 380 + case PERF_REG_POWERPC_LINK: 381 + return "link"; 382 + case PERF_REG_POWERPC_XER: 383 + return "xer"; 384 + case PERF_REG_POWERPC_CCR: 385 + return "ccr"; 386 + case PERF_REG_POWERPC_SOFTE: 387 + return "softe"; 388 + case PERF_REG_POWERPC_TRAP: 389 + return "trap"; 390 + case PERF_REG_POWERPC_DAR: 391 + return "dar"; 392 + case PERF_REG_POWERPC_DSISR: 393 + return "dsisr"; 394 + case PERF_REG_POWERPC_SIER: 395 + return "sier"; 396 + case PERF_REG_POWERPC_MMCRA: 397 + return "mmcra"; 398 + case PERF_REG_POWERPC_MMCR0: 399 + return "mmcr0"; 400 + case PERF_REG_POWERPC_MMCR1: 401 + return "mmcr1"; 402 + case PERF_REG_POWERPC_MMCR2: 403 + return "mmcr2"; 404 + case PERF_REG_POWERPC_MMCR3: 405 + return "mmcr3"; 406 + case PERF_REG_POWERPC_SIER2: 407 + return "sier2"; 408 + case PERF_REG_POWERPC_SIER3: 409 + return "sier3"; 410 + case PERF_REG_POWERPC_PMC1: 411 + return "pmc1"; 412 + case PERF_REG_POWERPC_PMC2: 413 + return "pmc2"; 414 + case PERF_REG_POWERPC_PMC3: 415 + return "pmc3"; 416 + case PERF_REG_POWERPC_PMC4: 417 + return "pmc4"; 418 + case PERF_REG_POWERPC_PMC5: 419 + return "pmc5"; 420 + case PERF_REG_POWERPC_PMC6: 421 + return "pmc6"; 422 + case PERF_REG_POWERPC_SDAR: 423 + return "sdar"; 424 + case PERF_REG_POWERPC_SIAR: 425 + return "siar"; 426 + default: 427 + break; 428 + } 429 + return NULL; 430 + } 431 + 432 + static const char *__perf_reg_name_riscv(int id) 433 + { 434 + switch (id) { 435 + case PERF_REG_RISCV_PC: 436 + return "pc"; 437 + case PERF_REG_RISCV_RA: 438 + return "ra"; 439 + case PERF_REG_RISCV_SP: 440 + return "sp"; 441 + case PERF_REG_RISCV_GP: 442 + return "gp"; 443 + case PERF_REG_RISCV_TP: 444 + return "tp"; 445 + case PERF_REG_RISCV_T0: 446 + return "t0"; 447 + case PERF_REG_RISCV_T1: 448 + return "t1"; 449 + case PERF_REG_RISCV_T2: 450 + return "t2"; 451 + case PERF_REG_RISCV_S0: 452 + return "s0"; 453 + case PERF_REG_RISCV_S1: 454 + return "s1"; 455 + case PERF_REG_RISCV_A0: 456 + return "a0"; 457 + case PERF_REG_RISCV_A1: 458 + return "a1"; 459 + case PERF_REG_RISCV_A2: 460 + return "a2"; 461 + case PERF_REG_RISCV_A3: 462 + return "a3"; 463 + case PERF_REG_RISCV_A4: 464 + return "a4"; 465 + case PERF_REG_RISCV_A5: 466 + return "a5"; 467 + case PERF_REG_RISCV_A6: 468 + return "a6"; 469 + case PERF_REG_RISCV_A7: 470 + return "a7"; 471 + case PERF_REG_RISCV_S2: 472 + return "s2"; 473 + case PERF_REG_RISCV_S3: 474 + return "s3"; 475 + case PERF_REG_RISCV_S4: 476 + return "s4"; 477 + case PERF_REG_RISCV_S5: 478 + return "s5"; 479 + case PERF_REG_RISCV_S6: 480 + return "s6"; 481 + case PERF_REG_RISCV_S7: 482 + return "s7"; 483 + case PERF_REG_RISCV_S8: 484 + return "s8"; 485 + case PERF_REG_RISCV_S9: 486 + return "s9"; 487 + case PERF_REG_RISCV_S10: 488 + return "s10"; 489 + case PERF_REG_RISCV_S11: 490 + return "s11"; 491 + case PERF_REG_RISCV_T3: 492 + return "t3"; 493 + case PERF_REG_RISCV_T4: 494 + return "t4"; 495 + case PERF_REG_RISCV_T5: 496 + return "t5"; 497 + case PERF_REG_RISCV_T6: 498 + return "t6"; 499 + default: 500 + return NULL; 501 + } 502 + 503 + return NULL; 504 + } 505 + 506 + static const char *__perf_reg_name_s390(int id) 507 + { 508 + switch (id) { 509 + case PERF_REG_S390_R0: 510 + return "R0"; 511 + case PERF_REG_S390_R1: 512 + return "R1"; 513 + case PERF_REG_S390_R2: 514 + return "R2"; 515 + case PERF_REG_S390_R3: 516 + return "R3"; 517 + case PERF_REG_S390_R4: 518 + return "R4"; 519 + case PERF_REG_S390_R5: 520 + return "R5"; 521 + case PERF_REG_S390_R6: 522 + return "R6"; 523 + case PERF_REG_S390_R7: 524 + return "R7"; 525 + case PERF_REG_S390_R8: 526 + return "R8"; 527 + case PERF_REG_S390_R9: 528 + return "R9"; 529 + case PERF_REG_S390_R10: 530 + return "R10"; 531 + case PERF_REG_S390_R11: 532 + return "R11"; 533 + case PERF_REG_S390_R12: 534 + return "R12"; 535 + case PERF_REG_S390_R13: 536 + return "R13"; 537 + case PERF_REG_S390_R14: 538 + return "R14"; 539 + case PERF_REG_S390_R15: 540 + return "R15"; 541 + case PERF_REG_S390_FP0: 542 + return "FP0"; 543 + case PERF_REG_S390_FP1: 544 + return "FP1"; 545 + case PERF_REG_S390_FP2: 546 + return "FP2"; 547 + case PERF_REG_S390_FP3: 548 + return "FP3"; 549 + case PERF_REG_S390_FP4: 550 + return "FP4"; 551 + case PERF_REG_S390_FP5: 552 + return "FP5"; 553 + case PERF_REG_S390_FP6: 554 + return "FP6"; 555 + case PERF_REG_S390_FP7: 556 + return "FP7"; 557 + case PERF_REG_S390_FP8: 558 + return "FP8"; 559 + case PERF_REG_S390_FP9: 560 + return "FP9"; 561 + case PERF_REG_S390_FP10: 562 + return "FP10"; 563 + case PERF_REG_S390_FP11: 564 + return "FP11"; 565 + case PERF_REG_S390_FP12: 566 + return "FP12"; 567 + case PERF_REG_S390_FP13: 568 + return "FP13"; 569 + case PERF_REG_S390_FP14: 570 + return "FP14"; 571 + case PERF_REG_S390_FP15: 572 + return "FP15"; 573 + case PERF_REG_S390_MASK: 574 + return "MASK"; 575 + case PERF_REG_S390_PC: 576 + return "PC"; 577 + default: 578 + return NULL; 579 + } 580 + 581 + return NULL; 582 + } 583 + 584 + static const char *__perf_reg_name_x86(int id) 585 + { 586 + switch (id) { 587 + case PERF_REG_X86_AX: 588 + return "AX"; 589 + case PERF_REG_X86_BX: 590 + return "BX"; 591 + case PERF_REG_X86_CX: 592 + return "CX"; 593 + case PERF_REG_X86_DX: 594 + return "DX"; 595 + case PERF_REG_X86_SI: 596 + return "SI"; 597 + case PERF_REG_X86_DI: 598 + return "DI"; 599 + case PERF_REG_X86_BP: 600 + return "BP"; 601 + case PERF_REG_X86_SP: 602 + return "SP"; 603 + case PERF_REG_X86_IP: 604 + return "IP"; 605 + case PERF_REG_X86_FLAGS: 606 + return "FLAGS"; 607 + case PERF_REG_X86_CS: 608 + return "CS"; 609 + case PERF_REG_X86_SS: 610 + return "SS"; 611 + case PERF_REG_X86_DS: 612 + return "DS"; 613 + case PERF_REG_X86_ES: 614 + return "ES"; 615 + case PERF_REG_X86_FS: 616 + return "FS"; 617 + case PERF_REG_X86_GS: 618 + return "GS"; 619 + case PERF_REG_X86_R8: 620 + return "R8"; 621 + case PERF_REG_X86_R9: 622 + return "R9"; 623 + case PERF_REG_X86_R10: 624 + return "R10"; 625 + case PERF_REG_X86_R11: 626 + return "R11"; 627 + case PERF_REG_X86_R12: 628 + return "R12"; 629 + case PERF_REG_X86_R13: 630 + return "R13"; 631 + case PERF_REG_X86_R14: 632 + return "R14"; 633 + case PERF_REG_X86_R15: 634 + return "R15"; 635 + 636 + #define XMM(x) \ 637 + case PERF_REG_X86_XMM ## x: \ 638 + case PERF_REG_X86_XMM ## x + 1: \ 639 + return "XMM" #x; 640 + XMM(0) 641 + XMM(1) 642 + XMM(2) 643 + XMM(3) 644 + XMM(4) 645 + XMM(5) 646 + XMM(6) 647 + XMM(7) 648 + XMM(8) 649 + XMM(9) 650 + XMM(10) 651 + XMM(11) 652 + XMM(12) 653 + XMM(13) 654 + XMM(14) 655 + XMM(15) 656 + #undef XMM 657 + default: 658 + return NULL; 659 + } 660 + 661 + return NULL; 662 + } 663 + 664 + const char *perf_reg_name(int id, const char *arch) 665 + { 666 + const char *reg_name = NULL; 667 + 668 + if (!strcmp(arch, "csky")) 669 + reg_name = __perf_reg_name_csky(id); 670 + else if (!strcmp(arch, "mips")) 671 + reg_name = __perf_reg_name_mips(id); 672 + else if (!strcmp(arch, "powerpc")) 673 + reg_name = __perf_reg_name_powerpc(id); 674 + else if (!strcmp(arch, "riscv")) 675 + reg_name = __perf_reg_name_riscv(id); 676 + else if (!strcmp(arch, "s390")) 677 + reg_name = __perf_reg_name_s390(id); 678 + else if (!strcmp(arch, "x86")) 679 + reg_name = __perf_reg_name_x86(id); 680 + else if (!strcmp(arch, "arm")) 681 + reg_name = __perf_reg_name_arm(id); 682 + else if (!strcmp(arch, "arm64")) 683 + reg_name = __perf_reg_name_arm64(id); 684 + 685 + return reg_name ?: "unknown"; 686 + } 687 + 24 688 int perf_reg_value(u64 *valp, struct regs_dump *regs, int id) 25 689 { 26 690 int i, idx = 0;
+2 -8
tools/perf/util/perf_regs.h
··· 31 31 32 32 #define DWARF_MINIMAL_REGS ((1ULL << PERF_REG_IP) | (1ULL << PERF_REG_SP)) 33 33 34 + const char *perf_reg_name(int id, const char *arch); 34 35 int perf_reg_value(u64 *valp, struct regs_dump *regs, int id); 35 - 36 - static inline const char *perf_reg_name(int id) 37 - { 38 - const char *reg_name = __perf_reg_name(id); 39 - 40 - return reg_name ?: "unknown"; 41 - } 42 36 43 37 #else 44 38 #define PERF_REGS_MASK 0 ··· 40 46 41 47 #define DWARF_MINIMAL_REGS PERF_REGS_MASK 42 48 43 - static inline const char *perf_reg_name(int id __maybe_unused) 49 + static inline const char *perf_reg_name(int id __maybe_unused, const char *arch __maybe_unused) 44 50 { 45 51 return "unknown"; 46 52 }
+6 -4
tools/perf/util/scripting-engines/trace-event-python.c
··· 36 36 #include "../debug.h" 37 37 #include "../dso.h" 38 38 #include "../callchain.h" 39 + #include "../env.h" 39 40 #include "../evsel.h" 40 41 #include "../event.h" 41 42 #include "../thread.h" ··· 688 687 _PyUnicode_FromString(decode)); 689 688 } 690 689 691 - static void regs_map(struct regs_dump *regs, uint64_t mask, char *bf, int size) 690 + static void regs_map(struct regs_dump *regs, uint64_t mask, const char *arch, char *bf, int size) 692 691 { 693 692 unsigned int i = 0, r; 694 693 int printed = 0; ··· 703 702 704 703 printed += scnprintf(bf + printed, size - printed, 705 704 "%5s:0x%" PRIx64 " ", 706 - perf_reg_name(r), val); 705 + perf_reg_name(r, arch), val); 707 706 } 708 707 } 709 708 ··· 712 711 struct evsel *evsel) 713 712 { 714 713 struct perf_event_attr *attr = &evsel->core.attr; 714 + const char *arch = perf_env__arch(evsel__env(evsel)); 715 715 716 716 /* 717 717 * Here value 28 is a constant size which can be used to print ··· 724 722 int size = __sw_hweight64(attr->sample_regs_intr) * 28; 725 723 char bf[size]; 726 724 727 - regs_map(&sample->intr_regs, attr->sample_regs_intr, bf, sizeof(bf)); 725 + regs_map(&sample->intr_regs, attr->sample_regs_intr, arch, bf, sizeof(bf)); 728 726 729 727 pydict_set_item_string_decref(dict, "iregs", 730 728 _PyUnicode_FromString(bf)); 731 729 732 - regs_map(&sample->user_regs, attr->sample_regs_user, bf, sizeof(bf)); 730 + regs_map(&sample->user_regs, attr->sample_regs_user, arch, bf, sizeof(bf)); 733 731 734 732 pydict_set_item_string_decref(dict, "uregs", 735 733 _PyUnicode_FromString(bf));
+13 -12
tools/perf/util/session.c
··· 15 15 #include "map_symbol.h" 16 16 #include "branch.h" 17 17 #include "debug.h" 18 + #include "env.h" 18 19 #include "evlist.h" 19 20 #include "evsel.h" 20 21 #include "memswap.h" ··· 1169 1168 } 1170 1169 } 1171 1170 1172 - static void regs_dump__printf(u64 mask, u64 *regs) 1171 + static void regs_dump__printf(u64 mask, u64 *regs, const char *arch) 1173 1172 { 1174 1173 unsigned rid, i = 0; 1175 1174 ··· 1177 1176 u64 val = regs[i++]; 1178 1177 1179 1178 printf(".... %-5s 0x%016" PRIx64 "\n", 1180 - perf_reg_name(rid), val); 1179 + perf_reg_name(rid, arch), val); 1181 1180 } 1182 1181 } 1183 1182 ··· 1195 1194 return regs_abi[d->abi]; 1196 1195 } 1197 1196 1198 - static void regs__printf(const char *type, struct regs_dump *regs) 1197 + static void regs__printf(const char *type, struct regs_dump *regs, const char *arch) 1199 1198 { 1200 1199 u64 mask = regs->mask; 1201 1200 ··· 1204 1203 mask, 1205 1204 regs_dump_abi(regs)); 1206 1205 1207 - regs_dump__printf(mask, regs->regs); 1206 + regs_dump__printf(mask, regs->regs, arch); 1208 1207 } 1209 1208 1210 - static void regs_user__printf(struct perf_sample *sample) 1209 + static void regs_user__printf(struct perf_sample *sample, const char *arch) 1211 1210 { 1212 1211 struct regs_dump *user_regs = &sample->user_regs; 1213 1212 1214 1213 if (user_regs->regs) 1215 - regs__printf("user", user_regs); 1214 + regs__printf("user", user_regs, arch); 1216 1215 } 1217 1216 1218 - static void regs_intr__printf(struct perf_sample *sample) 1217 + static void regs_intr__printf(struct perf_sample *sample, const char *arch) 1219 1218 { 1220 1219 struct regs_dump *intr_regs = &sample->intr_regs; 1221 1220 1222 1221 if (intr_regs->regs) 1223 - regs__printf("intr", intr_regs); 1222 + regs__printf("intr", intr_regs, arch); 1224 1223 } 1225 1224 1226 1225 static void stack_user__printf(struct stack_dump *dump) ··· 1305 1304 } 1306 1305 1307 1306 static void dump_sample(struct evsel *evsel, union perf_event *event, 1308 - struct perf_sample *sample) 1307 + struct perf_sample *sample, const char *arch) 1309 1308 { 1310 1309 u64 sample_type; 1311 1310 char str[PAGE_SIZE_NAME_LEN]; ··· 1326 1325 branch_stack__printf(sample, evsel__has_branch_callstack(evsel)); 1327 1326 1328 1327 if (sample_type & PERF_SAMPLE_REGS_USER) 1329 - regs_user__printf(sample); 1328 + regs_user__printf(sample, arch); 1330 1329 1331 1330 if (sample_type & PERF_SAMPLE_REGS_INTR) 1332 - regs_intr__printf(sample); 1331 + regs_intr__printf(sample, arch); 1333 1332 1334 1333 if (sample_type & PERF_SAMPLE_STACK_USER) 1335 1334 stack_user__printf(&sample->user_stack); ··· 1503 1502 ++evlist->stats.nr_unknown_id; 1504 1503 return 0; 1505 1504 } 1506 - dump_sample(evsel, event, sample); 1505 + dump_sample(evsel, event, sample, perf_env__arch(machine->env)); 1507 1506 if (machine == NULL) { 1508 1507 ++evlist->stats.nr_unprocessable_samples; 1509 1508 return 0;