clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)

tjh.dev / kernel

fork atom

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

fork atom

clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)

Use the provider based method to get a clock's name so that we
can get rid of the clk member in struct clk_hw one day. Mostly
converted with the following coccinelle script.

@@
struct clk_hw *E;
@@

-__clk_get_name(E->clk)
+clk_hw_get_name(E)

Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Kevin Cernekee <cernekee@chromium.org>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

authored by

Stephen Boyd and committed by

Michael Turquette 10 years ago 836ee0f7 e7df6f6e

+70 -70

18 changed files

expand all collapse all

drivers

clk

berlin

berlin2-pll.c

clk-xgene.c

pistachio

clk-pll.c

qcom

clk-branch.c

rockchip

clk-inverter.c

clk-mmc-phase.c

samsung

clk-pll.c

shmobile

clk-div6.c

clk-flexgen.c

clkgen-fsyn.c

clkgen-mux.c

clkgen-pll.c

tegra

clk-pll.c

apll.c

clkt_dflt.c

clockdomain.c

ux500

clk-prcmu.c

clk-sysctrl.c

+2 -2

drivers/clk/berlin/berlin2-pll.c

reviewed

··· 61 61 fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK; 62 62 rfdiv = (val >> map->rfdiv_shift) & RFDIV_MASK; 63 63 if (rfdiv == 0) { 64 64 - pr_warn("%s has zero rfdiv\n", __clk_get_name(hw->clk)); 64 64 + pr_warn("%s has zero rfdiv\n", clk_hw_get_name(hw)); 65 65 rfdiv = 1; 66 66 } 67 67 ··· 70 70 vcodiv = map->vcodiv[vcodivsel]; 71 71 if (vcodiv == 0) { 72 72 pr_warn("%s has zero vcodiv (index %d)\n", 73 73 - __clk_get_name(hw->clk), vcodivsel); 73 73 + clk_hw_get_name(hw), vcodivsel); 74 74 vcodiv = 1; 75 75 } 76 76

+11 -11

drivers/clk/clk-xgene.c

reviewed

··· 74 74 u32 data; 75 75 76 76 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); 77 77 - pr_debug("%s pll %s\n", __clk_get_name(hw->clk), 77 77 + pr_debug("%s pll %s\n", clk_hw_get_name(hw), 78 78 data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled"); 79 79 80 80 return data & REGSPEC_RESET_F1_MASK ? 0 : 1; ··· 112 112 fref = parent_rate / nref; 113 113 fvco = fref * nfb; 114 114 } 115 115 - pr_debug("%s pll recalc rate %ld parent %ld\n", __clk_get_name(hw->clk), 115 115 + pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw), 116 116 fvco / nout, parent_rate); 117 117 118 118 return fvco / nout; ··· 225 225 spin_lock_irqsave(pclk->lock, flags); 226 226 227 227 if (pclk->param.csr_reg != NULL) { 228 228 - pr_debug("%s clock enabled\n", __clk_get_name(hw->clk)); 228 228 + pr_debug("%s clock enabled\n", clk_hw_get_name(hw)); 229 229 reg = __pa(pclk->param.csr_reg); 230 230 /* First enable the clock */ 231 231 data = xgene_clk_read(pclk->param.csr_reg + ··· 234 234 xgene_clk_write(data, pclk->param.csr_reg + 235 235 pclk->param.reg_clk_offset); 236 236 pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n", 237 237 - __clk_get_name(hw->clk), &reg, 237 237 + clk_hw_get_name(hw), &reg, 238 238 pclk->param.reg_clk_offset, pclk->param.reg_clk_mask, 239 239 data); 240 240 ··· 245 245 xgene_clk_write(data, pclk->param.csr_reg + 246 246 pclk->param.reg_csr_offset); 247 247 pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n", 248 248 - __clk_get_name(hw->clk), &reg, 248 248 + clk_hw_get_name(hw), &reg, 249 249 pclk->param.reg_csr_offset, pclk->param.reg_csr_mask, 250 250 data); 251 251 } ··· 266 266 spin_lock_irqsave(pclk->lock, flags); 267 267 268 268 if (pclk->param.csr_reg != NULL) { 269 269 - pr_debug("%s clock disabled\n", __clk_get_name(hw->clk)); 269 269 + pr_debug("%s clock disabled\n", clk_hw_get_name(hw)); 270 270 /* First put the CSR in reset */ 271 271 data = xgene_clk_read(pclk->param.csr_reg + 272 272 pclk->param.reg_csr_offset); ··· 292 292 u32 data = 0; 293 293 294 294 if (pclk->param.csr_reg != NULL) { 295 295 - pr_debug("%s clock checking\n", __clk_get_name(hw->clk)); 295 295 + pr_debug("%s clock checking\n", clk_hw_get_name(hw)); 296 296 data = xgene_clk_read(pclk->param.csr_reg + 297 297 pclk->param.reg_clk_offset); 298 298 - pr_debug("%s clock is %s\n", __clk_get_name(hw->clk), 298 298 + pr_debug("%s clock is %s\n", clk_hw_get_name(hw), 299 299 data & pclk->param.reg_clk_mask ? "enabled" : 300 300 "disabled"); 301 301 } ··· 318 318 data &= (1 << pclk->param.reg_divider_width) - 1; 319 319 320 320 pr_debug("%s clock recalc rate %ld parent %ld\n", 321 321 - __clk_get_name(hw->clk), 321 321 + clk_hw_get_name(hw), 322 322 parent_rate / data, parent_rate); 323 323 324 324 return parent_rate / data; 325 325 } else { 326 326 pr_debug("%s clock recalc rate %ld parent %ld\n", 327 327 - __clk_get_name(hw->clk), parent_rate, parent_rate); 327 327 + clk_hw_get_name(hw), parent_rate, parent_rate); 328 328 return parent_rate; 329 329 } 330 330 } ··· 356 356 data |= divider; 357 357 xgene_clk_write(data, pclk->param.divider_reg + 358 358 pclk->param.reg_divider_offset); 359 359 - pr_debug("%s clock set rate %ld\n", __clk_get_name(hw->clk), 359 359 + pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw), 360 360 parent_rate / divider_save); 361 361 } else { 362 362 divider_save = 1;

+2 -2

drivers/clk/pistachio/clk-pll.c

reviewed

··· 174 174 struct pistachio_pll_rate_table *params; 175 175 int enabled = pll_gf40lp_frac_is_enabled(hw); 176 176 u32 val, vco, old_postdiv1, old_postdiv2; 177 177 - const char *name = __clk_get_name(hw->clk); 177 177 + const char *name = clk_hw_get_name(hw); 178 178 179 179 if (rate < MIN_OUTPUT_FRAC || rate > MAX_OUTPUT_FRAC) 180 180 return -EINVAL; ··· 316 316 struct pistachio_pll_rate_table *params; 317 317 int enabled = pll_gf40lp_laint_is_enabled(hw); 318 318 u32 val, vco, old_postdiv1, old_postdiv2; 319 319 - const char *name = __clk_get_name(hw->clk); 319 319 + const char *name = clk_hw_get_name(hw); 320 320 321 321 if (rate < MIN_OUTPUT_LA || rate > MAX_OUTPUT_LA) 322 322 return -EINVAL;

+1 -1

drivers/clk/qcom/clk-branch.c

reviewed

··· 75 75 bool (check_halt)(const struct clk_branch *, bool)) 76 76 { 77 77 bool voted = br->halt_check & BRANCH_VOTED; 78 78 - const char *name = __clk_get_name(br->clkr.hw.clk); 78 78 + const char *name = clk_hw_get_name(&br->clkr.hw); 79 79 80 80 /* Skip checking halt bit if the clock is in hardware gated mode */ 81 81 if (clk_branch_in_hwcg_mode(br))

+1 -1

drivers/clk/rockchip/clk-inverter.c

reviewed

··· 50 50 val = !!degrees; 51 51 } else { 52 52 pr_err("%s: unsupported phase %d for %s\n", 53 53 - __func__, degrees, __clk_get_name(hw->clk)); 53 53 + __func__, degrees, clk_hw_get_name(hw)); 54 54 return -EINVAL; 55 55 } 56 56

+1 -1

drivers/clk/rockchip/clk-mmc-phase.c

reviewed

··· 108 108 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), mmc_clock->reg); 109 109 110 110 pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n", 111 111 - __clk_get_name(hw->clk), degrees, delay_num, 111 111 + clk_hw_get_name(hw), degrees, delay_num, 112 112 mmc_clock->reg, raw_value>>(mmc_clock->shift), 113 113 rockchip_mmc_get_phase(hw) 114 114 );

+9 -9

drivers/clk/samsung/clk-pll.c

reviewed

··· 182 182 rate = samsung_get_pll_settings(pll, drate); 183 183 if (!rate) { 184 184 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 185 185 - drate, __clk_get_name(hw->clk)); 185 185 + drate, clk_hw_get_name(hw)); 186 186 return -EINVAL; 187 187 } 188 188 ··· 290 290 rate = samsung_get_pll_settings(pll, drate); 291 291 if (!rate) { 292 292 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 293 293 - drate, __clk_get_name(hw->clk)); 293 293 + drate, clk_hw_get_name(hw)); 294 294 return -EINVAL; 295 295 } 296 296 ··· 405 405 rate = samsung_get_pll_settings(pll, drate); 406 406 if (!rate) { 407 407 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 408 408 - drate, __clk_get_name(hw->clk)); 408 408 + drate, clk_hw_get_name(hw)); 409 409 return -EINVAL; 410 410 } 411 411 ··· 457 457 458 458 if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) { 459 459 pr_err("%s: could not lock PLL %s\n", 460 460 - __func__, __clk_get_name(hw->clk)); 460 460 + __func__, clk_hw_get_name(hw)); 461 461 return -EFAULT; 462 462 } 463 463 ··· 556 556 rate = samsung_get_pll_settings(pll, drate); 557 557 if (!rate) { 558 558 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 559 559 - drate, __clk_get_name(hw->clk)); 559 559 + drate, clk_hw_get_name(hw)); 560 560 return -EINVAL; 561 561 } 562 562 ··· 616 616 617 617 if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) { 618 618 pr_err("%s: could not lock PLL %s\n", 619 619 - __func__, __clk_get_name(hw->clk)); 619 619 + __func__, clk_hw_get_name(hw)); 620 620 return -EFAULT; 621 621 } 622 622 ··· 774 774 rate = samsung_get_pll_settings(pll, drate); 775 775 if (!rate) { 776 776 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 777 777 - drate, __clk_get_name(hw->clk)); 777 777 + drate, clk_hw_get_name(hw)); 778 778 return -EINVAL; 779 779 } 780 780 ··· 1015 1015 rate = samsung_get_pll_settings(pll, drate); 1016 1016 if (!rate) { 1017 1017 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 1018 1018 - drate, __clk_get_name(hw->clk)); 1018 1018 + drate, clk_hw_get_name(hw)); 1019 1019 return -EINVAL; 1020 1020 } 1021 1021 ··· 1113 1113 rate = samsung_get_pll_settings(pll, drate); 1114 1114 if (!rate) { 1115 1115 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 1116 1116 - drate, __clk_get_name(hw->clk)); 1116 1116 + drate, clk_hw_get_name(hw)); 1117 1117 return -EINVAL; 1118 1118 } 1119 1119

+1 -1

drivers/clk/shmobile/clk-div6.c

reviewed

··· 139 139 } 140 140 141 141 pr_err("%s: %s DIV6 clock set to invalid parent %u\n", 142 142 - __func__, __clk_get_name(hw->clk), hw_index); 142 142 + __func__, clk_hw_get_name(hw), hw_index); 143 143 return 0; 144 144 } 145 145

+2 -2

drivers/clk/st/clk-flexgen.c

reviewed

··· 45 45 46 46 clk_gate_ops.enable(fgate_hw); 47 47 48 48 - pr_debug("%s: flexgen output enabled\n", __clk_get_name(hw->clk)); 48 48 + pr_debug("%s: flexgen output enabled\n", clk_hw_get_name(hw)); 49 49 return 0; 50 50 } 51 51 ··· 59 59 60 60 clk_gate_ops.disable(fgate_hw); 61 61 62 62 - pr_debug("%s: flexgen output disabled\n", __clk_get_name(hw->clk)); 62 62 + pr_debug("%s: flexgen output disabled\n", clk_hw_get_name(hw)); 63 63 } 64 64 65 65 static int flexgen_is_enabled(struct clk_hw *hw)

+9 -9

drivers/clk/st/clkgen-fsyn.c

reviewed

··· 513 513 params.ndiv = CLKGEN_READ(pll, ndiv); 514 514 if (clk_fs660c32_vco_get_rate(parent_rate, &params, &rate)) 515 515 pr_err("%s:%s error calculating rate\n", 516 516 - __clk_get_name(hw->clk), __func__); 516 516 + clk_hw_get_name(hw), __func__); 517 517 518 518 pll->ndiv = params.ndiv; 519 519 ··· 558 558 clk_fs660c32_vco_get_rate(*prate, &params, &rate); 559 559 560 560 pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n", 561 561 - __func__, __clk_get_name(hw->clk), 561 561 + __func__, clk_hw_get_name(hw), 562 562 rate, (unsigned int)params.sdiv, 563 563 (unsigned int)params.mdiv, 564 564 (unsigned int)params.pe, (unsigned int)params.nsdiv); ··· 581 581 clk_fs660c32_vco_get_rate(parent_rate, &params, &hwrate); 582 582 583 583 pr_debug("%s: %s new rate %ld [ndiv=0x%x]\n", 584 584 - __func__, __clk_get_name(hw->clk), 584 584 + __func__, clk_hw_get_name(hw), 585 585 hwrate, (unsigned int)params.ndiv); 586 586 587 587 if (!hwrate) ··· 745 745 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw); 746 746 unsigned long flags = 0; 747 747 748 748 - pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk)); 748 748 + pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); 749 749 750 750 quadfs_fsynth_program_rate(fs); 751 751 ··· 770 770 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw); 771 771 unsigned long flags = 0; 772 772 773 773 - pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk)); 773 773 + pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); 774 774 775 775 if (fs->lock) 776 776 spin_lock_irqsave(fs->lock, flags); ··· 787 787 u32 nsb = CLKGEN_READ(fs, nsb[fs->chan]); 788 788 789 789 pr_debug("%s: %s enable bit = 0x%x\n", 790 790 - __func__, __clk_get_name(hw->clk), nsb); 790 790 + __func__, clk_hw_get_name(hw), nsb); 791 791 792 792 return fs->data->standby_polarity ? !nsb : !!nsb; 793 793 } ··· 946 946 947 947 if (clk_fs_get_rate(parent_rate, &params, &rate)) { 948 948 pr_err("%s:%s error calculating rate\n", 949 949 - __clk_get_name(hw->clk), __func__); 949 949 + clk_hw_get_name(hw), __func__); 950 950 } 951 951 952 952 - pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); 952 952 + pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); 953 953 954 954 return rate; 955 955 } ··· 962 962 rate = quadfs_find_best_rate(hw, rate, *prate, &params); 963 963 964 964 pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n", 965 965 - __func__, __clk_get_name(hw->clk), 965 965 + __func__, clk_hw_get_name(hw), 966 966 rate, (unsigned int)params.sdiv, (unsigned int)params.mdiv, 967 967 (unsigned int)params.pe, (unsigned int)params.nsdiv); 968 968

+1 -1

drivers/clk/st/clkgen-mux.c

reviewed

··· 139 139 genamux->muxsel = clk_mux_ops.get_parent(mux_hw); 140 140 if ((s8)genamux->muxsel < 0) { 141 141 pr_debug("%s: %s: Invalid parent, setting to default.\n", 142 142 - __func__, __clk_get_name(hw->clk)); 142 142 + __func__, clk_hw_get_name(hw)); 143 143 genamux->muxsel = 0; 144 144 } 145 145

+4 -4

drivers/clk/st/clkgen-pll.c

reviewed

··· 292 292 res = (uint64_t)2 * (uint64_t)parent_rate * (uint64_t)ndiv; 293 293 rate = (unsigned long)div64_u64(res, mdiv * (1 << pdiv)); 294 294 295 295 - pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); 295 295 + pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); 296 296 297 297 return rate; 298 298 ··· 317 317 /* Note: input is divided by 1000 to avoid overflow */ 318 318 rate = ((2 * (parent_rate / 1000) * ndiv) / mdiv) * 1000; 319 319 320 320 - pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); 320 320 + pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); 321 321 322 322 return rate; 323 323 } ··· 339 339 /* Note: input is divided to avoid overflow */ 340 340 rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000; 341 341 342 342 - pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); 342 342 + pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); 343 343 344 344 return rate; 345 345 } ··· 366 366 /* Note: input is divided by 1000 to avoid overflow */ 367 367 rate = (((parent_rate / 1000) * ldf) / (odf * idf)) * 1000; 368 368 369 369 - pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); 369 369 + pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); 370 370 371 371 return rate; 372 372 }

+4 -4

drivers/clk/tegra/clk-pll.c

reviewed

··· 264 264 } 265 265 266 266 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, 267 267 - __clk_get_name(pll->hw.clk)); 267 267 + clk_hw_get_name(&pll->hw)); 268 268 269 269 return -1; 270 270 } ··· 595 595 if (pll->params->flags & TEGRA_PLL_FIXED) { 596 596 if (rate != pll->params->fixed_rate) { 597 597 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 598 598 - __func__, __clk_get_name(hw->clk), 598 598 + __func__, clk_hw_get_name(hw), 599 599 pll->params->fixed_rate, rate); 600 600 return -EINVAL; 601 601 } ··· 605 605 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 606 606 _calc_rate(hw, &cfg, rate, parent_rate)) { 607 607 pr_err("%s: Failed to set %s rate %lu\n", __func__, 608 608 - __clk_get_name(hw->clk), rate); 608 608 + clk_hw_get_name(hw), rate); 609 609 WARN_ON(1); 610 610 return -EINVAL; 611 611 } ··· 663 663 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, 664 664 parent_rate)) { 665 665 pr_err("Clock %s has unknown fixed frequency\n", 666 666 - __clk_get_name(hw->clk)); 666 666 + clk_hw_get_name(hw)); 667 667 BUG(); 668 668 } 669 669 return pll->params->fixed_rate;

+2 -2

drivers/clk/ti/apll.c

reviewed

··· 50 50 if (!ad) 51 51 return -EINVAL; 52 52 53 53 - clk_name = __clk_get_name(clk->hw.clk); 53 53 + clk_name = clk_hw_get_name(&clk->hw); 54 54 55 55 state <<= __ffs(ad->idlest_mask); 56 56 ··· 273 273 274 274 if (i == MAX_APLL_WAIT_TRIES) { 275 275 pr_warn("%s failed to transition to locked\n", 276 276 - __clk_get_name(clk->hw.clk)); 276 276 + clk_hw_get_name(&clk->hw)); 277 277 return -EBUSY; 278 278 } 279 279

+4 -4

drivers/clk/ti/clkt_dflt.c

reviewed

··· 110 110 if (r) { 111 111 /* IDLEST register not in the CM module */ 112 112 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), 113 113 - idlest_val, __clk_get_name(clk->hw.clk)); 113 113 + idlest_val, clk_hw_get_name(&clk->hw)); 114 114 } else { 115 115 ti_clk_ll_ops->cm_wait_module_ready(0, prcm_mod, idlest_reg_id, 116 116 idlest_bit); ··· 216 216 if (ret) { 217 217 WARN(1, 218 218 "%s: could not enable %s's clockdomain %s: %d\n", 219 219 - __func__, __clk_get_name(hw->clk), 219 219 + __func__, clk_hw_get_name(hw), 220 220 clk->clkdm_name, ret); 221 221 return ret; 222 222 } ··· 224 224 225 225 if (unlikely(!clk->enable_reg)) { 226 226 pr_err("%s: %s missing enable_reg\n", __func__, 227 227 - __clk_get_name(hw->clk)); 227 227 + clk_hw_get_name(hw)); 228 228 ret = -EINVAL; 229 229 goto err; 230 230 } ··· 270 270 * controlled by its parent. 271 271 */ 272 272 pr_err("%s: independent clock %s has no enable_reg\n", 273 273 - __func__, __clk_get_name(hw->clk)); 273 273 + __func__, clk_hw_get_name(hw)); 274 274 return; 275 275 } 276 276

+7 -7

drivers/clk/ti/clockdomain.c

reviewed

··· 48 48 49 49 if (unlikely(!clk->clkdm)) { 50 50 pr_err("%s: %s: no clkdm set ?!\n", __func__, 51 51 - __clk_get_name(hw->clk)); 51 51 + clk_hw_get_name(hw)); 52 52 return -EINVAL; 53 53 } 54 54 55 55 if (unlikely(clk->enable_reg)) 56 56 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, 57 57 - __clk_get_name(hw->clk)); 57 57 + clk_hw_get_name(hw)); 58 58 59 59 if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) { 60 60 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 61 61 - __func__, __clk_get_name(hw->clk)); 61 61 + __func__, clk_hw_get_name(hw)); 62 62 return 0; 63 63 } 64 64 65 65 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); 66 66 WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", 67 67 - __func__, __clk_get_name(hw->clk), clk->clkdm_name, ret); 67 67 + __func__, clk_hw_get_name(hw), clk->clkdm_name, ret); 68 68 69 69 return ret; 70 70 } ··· 86 86 87 87 if (unlikely(!clk->clkdm)) { 88 88 pr_err("%s: %s: no clkdm set ?!\n", __func__, 89 89 - __clk_get_name(hw->clk)); 89 89 + clk_hw_get_name(hw)); 90 90 return; 91 91 } 92 92 93 93 if (unlikely(clk->enable_reg)) 94 94 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, 95 95 - __clk_get_name(hw->clk)); 95 95 + clk_hw_get_name(hw)); 96 96 97 97 if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) { 98 98 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 99 99 - __func__, __clk_get_name(hw->clk)); 99 99 + __func__, clk_hw_get_name(hw)); 100 100 return; 101 101 } 102 102

+8 -8

drivers/clk/ux500/clk-prcmu.c

reviewed

··· 43 43 struct clk_prcmu *clk = to_clk_prcmu(hw); 44 44 if (prcmu_request_clock(clk->cg_sel, false)) 45 45 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__, 46 46 - __clk_get_name(hw->clk)); 46 46 + clk_hw_get_name(hw)); 47 47 else 48 48 clk->is_prepared = 0; 49 49 } ··· 101 101 102 102 if (!clk->opp_requested) { 103 103 err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP, 104 104 - (char *)__clk_get_name(hw->clk), 104 104 + (char *)clk_hw_get_name(hw), 105 105 100); 106 106 if (err) { 107 107 pr_err("clk_prcmu: %s fail req APE OPP for %s.\n", 108 108 - __func__, __clk_get_name(hw->clk)); 108 108 + __func__, clk_hw_get_name(hw)); 109 109 return err; 110 110 } 111 111 clk->opp_requested = 1; ··· 114 114 err = prcmu_request_clock(clk->cg_sel, true); 115 115 if (err) { 116 116 prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP, 117 117 - (char *)__clk_get_name(hw->clk)); 117 117 + (char *)clk_hw_get_name(hw)); 118 118 clk->opp_requested = 0; 119 119 return err; 120 120 } ··· 129 129 130 130 if (prcmu_request_clock(clk->cg_sel, false)) { 131 131 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__, 132 132 - __clk_get_name(hw->clk)); 132 132 + clk_hw_get_name(hw)); 133 133 return; 134 134 } 135 135 136 136 if (clk->opp_requested) { 137 137 prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP, 138 138 - (char *)__clk_get_name(hw->clk)); 138 138 + (char *)clk_hw_get_name(hw)); 139 139 clk->opp_requested = 0; 140 140 } 141 141 ··· 151 151 err = prcmu_request_ape_opp_100_voltage(true); 152 152 if (err) { 153 153 pr_err("clk_prcmu: %s fail req APE OPP VOLT for %s.\n", 154 154 - __func__, __clk_get_name(hw->clk)); 154 154 + __func__, clk_hw_get_name(hw)); 155 155 return err; 156 156 } 157 157 clk->opp_requested = 1; ··· 174 174 175 175 if (prcmu_request_clock(clk->cg_sel, false)) { 176 176 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__, 177 177 - __clk_get_name(hw->clk)); 177 177 + clk_hw_get_name(hw)); 178 178 return; 179 179 } 180 180

+1 -1

drivers/clk/ux500/clk-sysctrl.c

reviewed

··· 52 52 struct clk_sysctrl *clk = to_clk_sysctrl(hw); 53 53 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0])) 54 54 dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n", 55 55 - __func__, __clk_get_name(hw->clk)); 55 55 + __func__, clk_hw_get_name(hw)); 56 56 } 57 57 58 58 static unsigned long clk_sysctrl_recalc_rate(struct clk_hw *hw,