+9
-14
virt/kvm/arm/mmu.c
+9
-14
virt/kvm/arm/mmu.c
···
102
102
* @addr: IPA
103
103
* @pmd: pmd pointer for IPA
104
104
*
105
-
* Function clears a PMD entry, flushes addr 1st and 2nd stage TLBs. Marks all
106
-
* pages in the range dirty.
105
+
* Function clears a PMD entry, flushes addr 1st and 2nd stage TLBs.
107
106
*/
108
107
static void stage2_dissolve_pmd(struct kvm *kvm, phys_addr_t addr, pmd_t *pmd)
109
108
{
···
120
121
* @addr: IPA
121
122
* @pud: pud pointer for IPA
122
123
*
123
-
* Function clears a PUD entry, flushes addr 1st and 2nd stage TLBs. Marks all
124
-
* pages in the range dirty.
124
+
* Function clears a PUD entry, flushes addr 1st and 2nd stage TLBs.
125
125
*/
126
126
static void stage2_dissolve_pud(struct kvm *kvm, phys_addr_t addr, pud_t *pudp)
127
127
{
···
897
899
* kvm_alloc_stage2_pgd - allocate level-1 table for stage-2 translation.
898
900
* @kvm: The KVM struct pointer for the VM.
899
901
*
900
-
* Allocates only the stage-2 HW PGD level table(s) (can support either full
901
-
* 40-bit input addresses or limited to 32-bit input addresses). Clears the
902
-
* allocated pages.
902
+
* Allocates only the stage-2 HW PGD level table(s) of size defined by
903
+
* stage2_pgd_size(kvm).
903
904
*
904
905
* Note we don't need locking here as this is only called when the VM is
905
906
* created, which can only be done once.
···
1475
1478
}
1476
1479
1477
1480
/**
1478
-
* stage2_wp_puds - write protect PGD range
1479
-
* @pgd: pointer to pgd entry
1480
-
* @addr: range start address
1481
-
* @end: range end address
1482
-
*
1483
-
* Process PUD entries, for a huge PUD we cause a panic.
1484
-
*/
1481
+
* stage2_wp_puds - write protect PGD range
1482
+
* @pgd: pointer to pgd entry
1483
+
* @addr: range start address
1484
+
* @end: range end address
1485
+
*/
1485
1486
static void stage2_wp_puds(struct kvm *kvm, pgd_t *pgd,
1486
1487
phys_addr_t addr, phys_addr_t end)
1487
1488
{