tjh.dev / kernel
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drm/i915/dsi: convert platform checks to display->platform.<platform> style

These are stragglers from a time the display->platform mechanism didn't
exist. Finish the conversion.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/493e4c550f9c515e2e82df1afd8a74a24156e76e.1739378096.git.jani.nikula@intel.com

Jani Nikula 82fafa7d 010d150a

+4 -7
+4 -7
drivers/gpu/drm/i915/display/icl_dsi.c
··· 345 345 const struct intel_crtc_state *crtc_state) 346 346 { 347 347 struct intel_display *display = to_intel_display(encoder); 348 - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 349 348 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 350 349 enum port port; 351 350 int afe_clk_khz; ··· 353 354 354 355 afe_clk_khz = afe_clk(encoder, crtc_state); 355 356 356 - if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 357 + if (display->platform.alderlake_s || display->platform.alderlake_p) { 357 358 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 358 359 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 359 360 esc_clk_div_m = act_word_clk * 8; ··· 374 375 intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port)); 375 376 } 376 377 377 - if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 378 + if (display->platform.alderlake_s || display->platform.alderlake_p) { 378 379 for_each_dsi_port(port, intel_dsi->ports) { 379 380 intel_de_write(display, ADL_MIPIO_DW(port, 8), 380 381 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); ··· 425 426 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 426 427 { 427 428 struct intel_display *display = to_intel_display(encoder); 428 - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 429 429 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 430 430 enum phy phy; 431 431 u32 tmp; ··· 449 451 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); 450 452 451 453 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 452 - if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) || 454 + if (display->platform.jasperlake || display->platform.elkhartlake || 453 455 (DISPLAY_VER(display) >= 12)) { 454 456 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), 455 457 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0)); ··· 531 533 const struct intel_crtc_state *crtc_state) 532 534 { 533 535 struct intel_display *display = to_intel_display(encoder); 534 - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 535 536 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 536 537 enum port port; 537 538 enum phy phy; ··· 560 563 } 561 564 } 562 565 563 - if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 566 + if (display->platform.jasperlake || display->platform.elkhartlake) { 564 567 for_each_dsi_phy(phy, intel_dsi->phys) 565 568 intel_de_rmw(display, ICL_DPHY_CHKN(phy), 566 569 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);