tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branches 'clk-qcom' and 'clk-microchip' into clk-next
* clk-qcom: (63 commits)
clk: qcom: gcc-sc8280xp: Add runtime PM
clk: qcom: gpucc-sc8280xp: Add runtime PM
clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags
clk: qcom: gpucc-sm6375: Enable runtime pm
dt-bindings: clock: sm6375-gpucc: Add VDD_GX
clk: qcom: gcc-sm6115: Add missing PLL config properties
clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
clk: qcom: gcc-ipq6018: remove duplicate initializers
clk: qcom: gcc-ipq9574: Enable crypto clocks
dt-bindings: clock: Add crypto clock and reset definitions
clk: qcom: Add lpass audio clock controller driver for SC8280XP
clk: qcom: Add lpass clock controller driver for SC8280XP
dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP
dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP
dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226
clk: qcom: gpucc-sm8550: Add support for graphics clock controller
clk: qcom: Add support for SM8450 GPUCC
clk: qcom: gcc-sm8450: Enable hw_clk_ctrl
clk: qcom: rcg2: Make hw_clk_ctrl toggleable
dt-bindings: clock: qcom: Add SM8550 graphics clock controller
...
* clk-microchip:
clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id
clk: at91: sama7g5: switch to parent_hw and parent_data
clk: at91: sckc: switch to parent_data/parent_hw
clk: at91: clk-sam9x60-pll: add support for parent_hw
clk: at91: clk-utmi: add support for parent_hw
clk: at91: clk-system: add support for parent_hw
clk: at91: clk-programmable: add support for parent_hw
clk: at91: clk-peripheral: add support for parent_hw
clk: at91: clk-master: add support for parent_hw
clk: at91: clk-generated: add support for parent_hw
clk: at91: clk-main: add support for parent_data/parent_hw
+8255
-865
+1
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
+1
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
+73
Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
+73
Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Global Clock & Reset Controller on MSM8953
8
+
9
+
maintainers:
10
+
- Adam Skladowski <a_skl39@protonmail.com>
11
+
- Sireesh Kodali <sireeshkodali@protonmail.com>
12
+
13
+
description: |
14
+
Qualcomm global clock control module provides the clocks, resets and power
15
+
domains on MSM8953.
16
+
17
+
See also: include/dt-bindings/clock/qcom,gcc-msm8953.h
18
+
19
+
properties:
20
+
compatible:
21
+
const: qcom,gcc-msm8953
22
+
23
+
clocks:
24
+
items:
25
+
- description: Board XO source
26
+
- description: Sleep clock source
27
+
- description: Byte clock from DSI PHY0
28
+
- description: Pixel clock from DSI PHY0
29
+
- description: Byte clock from DSI PHY1
30
+
- description: Pixel clock from DSI PHY1
31
+
32
+
clock-names:
33
+
items:
34
+
- const: xo
35
+
- const: sleep
36
+
- const: dsi0pll
37
+
- const: dsi0pllbyte
38
+
- const: dsi1pll
39
+
- const: dsi1pllbyte
40
+
41
+
required:
42
+
- compatible
43
+
- clocks
44
+
- clock-names
45
+
46
+
allOf:
47
+
- $ref: qcom,gcc.yaml#
48
+
49
+
unevaluatedProperties: false
50
+
51
+
examples:
52
+
- |
53
+
#include <dt-bindings/clock/qcom,rpmcc.h>
54
+
55
+
clock-controller@1800000 {
56
+
compatible = "qcom,gcc-msm8953";
57
+
reg = <0x01800000 0x80000>;
58
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
59
+
<&sleep_clk>,
60
+
<&dsi0_phy 1>,
61
+
<&dsi0_phy 0>,
62
+
<&dsi1_phy 1>,
63
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<&dsi1_phy 0>;
64
+
clock-names = "xo",
65
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"sleep",
66
+
"dsi0pll",
67
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"dsi0pllbyte",
68
+
"dsi1pll",
69
+
"dsi1pllbyte";
70
+
#clock-cells = <1>;
71
+
#reset-cells = <1>;
72
+
#power-domain-cells = <1>;
73
+
};
-1
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
-1
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
+7
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
+7
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
···
32
32
- const: bi_tcxo_ao
33
33
- const: sleep_clk
34
34
35
+
power-domains:
36
+
items:
37
+
- description: CX domain
38
+
35
39
required:
36
40
- compatible
37
41
- clocks
···
49
45
examples:
50
46
- |
51
47
#include <dt-bindings/clock/qcom,rpmh.h>
48
+
#include <dt-bindings/power/qcom-rpmpd.h>
49
+
52
50
clock-controller@100000 {
53
51
compatible = "qcom,gcc-sc7180";
54
52
reg = <0x00100000 0x1f0000>;
···
58
52
<&rpmhcc RPMH_CXO_CLK_A>,
59
53
<&sleep_clk>;
60
54
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
55
+
power-domains = <&rpmhpd SC7180_CX>;
61
56
#clock-cells = <1>;
62
57
#reset-cells = <1>;
63
58
#power-domain-cells = <1>;
+7
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
+7
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
···
43
43
- const: ufs_phy_tx_symbol_0_clk
44
44
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
45
45
46
+
power-domains:
47
+
items:
48
+
- description: CX domain
49
+
46
50
required:
47
51
- compatible
48
52
- clocks
···
60
56
examples:
61
57
- |
62
58
#include <dt-bindings/clock/qcom,rpmh.h>
59
+
#include <dt-bindings/power/qcom-rpmpd.h>
60
+
63
61
clock-controller@100000 {
64
62
compatible = "qcom,gcc-sc7280";
65
63
reg = <0x00100000 0x1f0000>;
···
77
71
"pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
78
72
"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
79
73
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
74
+
power-domains = <&rpmhpd SC7280_CX>;
80
75
#clock-cells = <1>;
81
76
#reset-cells = <1>;
82
77
#power-domain-cells = <1>;
+4
-1
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
+4
-1
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
···
23
23
clocks:
24
24
items:
25
25
- description: Board XO source
26
+
- description: Board active XO source
26
27
- description: Sleep clock source
27
28
28
29
clock-names:
29
30
items:
30
31
- const: bi_tcxo
32
+
- const: bi_tcxo_ao
31
33
- const: sleep_clk
32
34
33
35
required:
···
49
47
compatible = "qcom,gcc-sm8250";
50
48
reg = <0x00100000 0x1f0000>;
51
49
clocks = <&rpmhcc RPMH_CXO_CLK>,
50
+
<&rpmhcc RPMH_CXO_CLK_A>,
52
51
<&sleep_clk>;
53
-
clock-names = "bi_tcxo", "sleep_clk";
52
+
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
54
53
#clock-cells = <1>;
55
54
#reset-cells = <1>;
56
55
#power-domain-cells = <1>;
+3
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+3
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+1
Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
+1
Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
+30
-2
Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
+30
-2
Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
···
31
31
- qcom,mmcc-sdm660
32
32
33
33
clocks:
34
-
minItems: 8
34
+
minItems: 7
35
35
maxItems: 13
36
36
37
37
clock-names:
38
-
minItems: 8
38
+
minItems: 7
39
39
maxItems: 13
40
40
41
41
'#clock-cells':
···
98
98
- const: dsi2pll
99
99
- const: dsi2pllbyte
100
100
- const: hdmipll
101
+
102
+
- if:
103
+
properties:
104
+
compatible:
105
+
contains:
106
+
enum:
107
+
- qcom,mmcc-msm8226
108
+
then:
109
+
properties:
110
+
clocks:
111
+
items:
112
+
- description: Board XO source
113
+
- description: MMSS GPLL0 voted clock
114
+
- description: GPLL0 voted clock
115
+
- description: GPLL1 voted clock
116
+
- description: GFX3D clock source
117
+
- description: DSI phy instance 0 dsi clock
118
+
- description: DSI phy instance 0 byte clock
119
+
120
+
clock-names:
121
+
items:
122
+
- const: xo
123
+
- const: mmss_gpll0_vote
124
+
- const: gpll0_vote
125
+
- const: gpll1_vote
126
+
- const: gfx3d_clk_src
127
+
- const: dsi0pll
128
+
- const: dsi0pllbyte
101
129
102
130
- if:
103
131
properties:
+1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+60
Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
+60
Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP
8
+
9
+
maintainers:
10
+
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11
+
12
+
description: |
13
+
Qualcomm LPASS core and audio clock control module provides the clocks,
14
+
and reset on SC8280XP.
15
+
16
+
See also::
17
+
include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- qcom,sc8280xp-lpassaudiocc
23
+
- qcom,sc8280xp-lpasscc
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
'#clock-cells':
29
+
const: 1
30
+
31
+
'#reset-cells':
32
+
const: 1
33
+
34
+
required:
35
+
- compatible
36
+
- reg
37
+
- '#clock-cells'
38
+
- '#reset-cells'
39
+
40
+
additionalProperties: false
41
+
42
+
examples:
43
+
- |
44
+
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
45
+
lpass_audiocc: clock-controller@32a9000 {
46
+
compatible = "qcom,sc8280xp-lpassaudiocc";
47
+
reg = <0x032a9000 0x1000>;
48
+
#clock-cells = <1>;
49
+
#reset-cells = <1>;
50
+
};
51
+
52
+
- |
53
+
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
54
+
lpasscc: clock-controller@33e0000 {
55
+
compatible = "qcom,sc8280xp-lpasscc";
56
+
reg = <0x033e0000 0x12000>;
57
+
#clock-cells = <1>;
58
+
#reset-cells = <1>;
59
+
};
60
+
...
+65
Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml
+65
Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Global Clock & Reset Controller on SDX75
8
+
9
+
maintainers:
10
+
- Imran Shaik <quic_imrashai@quicinc.com>
11
+
- Taniya Das <quic_tdas@quicinc.com>
12
+
13
+
description: |
14
+
Qualcomm global clock control module provides the clocks, resets and power
15
+
domains on SDX75
16
+
17
+
See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h
18
+
19
+
properties:
20
+
compatible:
21
+
const: qcom,sdx75-gcc
22
+
23
+
clocks:
24
+
items:
25
+
- description: Board XO source
26
+
- description: Sleep clock source
27
+
- description: EMAC0 sgmiiphy mac rclk source
28
+
- description: EMAC0 sgmiiphy mac tclk source
29
+
- description: EMAC0 sgmiiphy rclk source
30
+
- description: EMAC0 sgmiiphy tclk source
31
+
- description: EMAC1 sgmiiphy mac rclk source
32
+
- description: EMAC1 sgmiiphy mac tclk source
33
+
- description: EMAC1 sgmiiphy rclk source
34
+
- description: EMAC1 sgmiiphy tclk source
35
+
- description: PCIE20 phy aux clock source
36
+
- description: PCIE_1 Pipe clock source
37
+
- description: PCIE_2 Pipe clock source
38
+
- description: PCIE Pipe clock source
39
+
- description: USB3 phy wrapper pipe clock source
40
+
41
+
required:
42
+
- compatible
43
+
- clocks
44
+
45
+
allOf:
46
+
- $ref: qcom,gcc.yaml#
47
+
48
+
unevaluatedProperties: false
49
+
50
+
examples:
51
+
- |
52
+
#include <dt-bindings/clock/qcom,rpmh.h>
53
+
clock-controller@80000 {
54
+
compatible = "qcom,sdx75-gcc";
55
+
reg = <0x80000 0x1f7400>;
56
+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>,
57
+
<&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>,
58
+
<&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>,
59
+
<&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>,
60
+
<&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
61
+
#clock-cells = <1>;
62
+
#reset-cells = <1>;
63
+
#power-domain-cells = <1>;
64
+
};
65
+
...
+15
Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml
+15
Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml
···
27
27
- description: GPLL0 div branch source
28
28
- description: SNoC DVM GFX source
29
29
30
+
power-domains:
31
+
description:
32
+
A phandle and PM domain specifier for the VDD_GX power rail
33
+
maxItems: 1
34
+
35
+
required-opps:
36
+
description:
37
+
A phandle to an OPP node describing required VDD_GX performance point.
38
+
maxItems: 1
39
+
30
40
required:
31
41
- compatible
32
42
- clocks
43
+
- power-domains
44
+
- required-opps
33
45
34
46
allOf:
35
47
- $ref: qcom,gcc.yaml#
···
52
40
- |
53
41
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
54
42
#include <dt-bindings/clock/qcom,rpmcc.h>
43
+
#include <dt-bindings/power/qcom-rpmpd.h>
55
44
56
45
soc {
57
46
#address-cells = <2>;
···
65
52
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
66
53
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
67
54
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
55
+
power-domains = <&rpmpd SM6375_VDDGX>;
56
+
required-opps = <&rpmpd_opp_low_svs>;
68
57
#clock-cells = <1>;
69
58
#reset-cells = <1>;
70
59
#power-domain-cells = <1>;
+68
Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml
+68
Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SM8350 Video Clock & Reset Controller
8
+
9
+
maintainers:
10
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
11
+
12
+
description: |
13
+
Qualcomm video clock control module provides the clocks, resets and power
14
+
domains on Qualcomm SoCs.
15
+
16
+
See also::
17
+
include/dt-bindings/clock/qcom,videocc-sm8350.h
18
+
include/dt-bindings/reset/qcom,videocc-sm8350.h
19
+
20
+
properties:
21
+
compatible:
22
+
const: qcom,sm8350-videocc
23
+
24
+
clocks:
25
+
items:
26
+
- description: Board XO source
27
+
- description: Board active XO source
28
+
- description: Board sleep clock
29
+
30
+
power-domains:
31
+
description:
32
+
A phandle and PM domain specifier for the MMCX power domain.
33
+
maxItems: 1
34
+
35
+
required-opps:
36
+
description:
37
+
A phandle to an OPP node describing required MMCX performance point.
38
+
maxItems: 1
39
+
40
+
required:
41
+
- compatible
42
+
- clocks
43
+
- power-domains
44
+
- required-opps
45
+
46
+
allOf:
47
+
- $ref: qcom,gcc.yaml#
48
+
49
+
unevaluatedProperties: false
50
+
51
+
examples:
52
+
- |
53
+
#include <dt-bindings/clock/qcom,rpmh.h>
54
+
#include <dt-bindings/power/qcom-rpmpd.h>
55
+
56
+
clock-controller@abf0000 {
57
+
compatible = "qcom,sm8350-videocc";
58
+
reg = <0x0abf0000 0x10000>;
59
+
clocks = <&rpmhcc RPMH_CXO_CLK>,
60
+
<&rpmhcc RPMH_CXO_CLK_A>,
61
+
<&sleep_clk>;
62
+
power-domains = <&rpmhpd SM8350_MMCX>;
63
+
required-opps = <&rpmhpd_opp_low_svs>;
64
+
#clock-cells = <1>;
65
+
#reset-cells = <1>;
66
+
#power-domain-cells = <1>;
67
+
};
68
+
...
+75
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
+75
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Graphics Clock & Reset Controller on SM8450
8
+
9
+
maintainers:
10
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
11
+
12
+
description: |
13
+
Qualcomm graphics clock control module provides the clocks, resets and power
14
+
domains on Qualcomm SoCs.
15
+
16
+
See also::
17
+
include/dt-bindings/clock/qcom,sm8450-gpucc.h
18
+
include/dt-bindings/clock/qcom,sm8550-gpucc.h
19
+
include/dt-bindings/reset/qcom,sm8450-gpucc.h
20
+
21
+
properties:
22
+
compatible:
23
+
enum:
24
+
- qcom,sm8450-gpucc
25
+
- qcom,sm8550-gpucc
26
+
27
+
clocks:
28
+
items:
29
+
- description: Board XO source
30
+
- description: GPLL0 main branch source
31
+
- description: GPLL0 div branch source
32
+
33
+
'#clock-cells':
34
+
const: 1
35
+
36
+
'#reset-cells':
37
+
const: 1
38
+
39
+
'#power-domain-cells':
40
+
const: 1
41
+
42
+
reg:
43
+
maxItems: 1
44
+
45
+
required:
46
+
- compatible
47
+
- reg
48
+
- clocks
49
+
- '#clock-cells'
50
+
- '#reset-cells'
51
+
- '#power-domain-cells'
52
+
53
+
additionalProperties: false
54
+
55
+
examples:
56
+
- |
57
+
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
58
+
#include <dt-bindings/clock/qcom,rpmh.h>
59
+
60
+
soc {
61
+
#address-cells = <2>;
62
+
#size-cells = <2>;
63
+
64
+
clock-controller@3d90000 {
65
+
compatible = "qcom,sm8450-gpucc";
66
+
reg = <0 0x03d90000 0 0xa000>;
67
+
clocks = <&rpmhcc RPMH_CXO_CLK>,
68
+
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
69
+
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
70
+
#clock-cells = <1>;
71
+
#reset-cells = <1>;
72
+
#power-domain-cells = <1>;
73
+
};
74
+
};
75
+
...
+79
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
+79
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Video Clock & Reset Controller on SM8450
8
+
9
+
maintainers:
10
+
- Taniya Das <quic_tdas@quicinc.com>
11
+
12
+
description: |
13
+
Qualcomm video clock control module provides the clocks, resets and power
14
+
domains on SM8450.
15
+
16
+
See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- qcom,sm8450-videocc
22
+
- qcom,sm8550-videocc
23
+
24
+
reg:
25
+
maxItems: 1
26
+
27
+
clocks:
28
+
items:
29
+
- description: Board XO source
30
+
- description: Video AHB clock from GCC
31
+
32
+
power-domains:
33
+
maxItems: 1
34
+
description:
35
+
MMCX power domain.
36
+
37
+
required-opps:
38
+
maxItems: 1
39
+
description:
40
+
A phandle to an OPP node describing required MMCX performance point.
41
+
42
+
'#clock-cells':
43
+
const: 1
44
+
45
+
'#reset-cells':
46
+
const: 1
47
+
48
+
'#power-domain-cells':
49
+
const: 1
50
+
51
+
required:
52
+
- compatible
53
+
- reg
54
+
- clocks
55
+
- power-domains
56
+
- required-opps
57
+
- '#clock-cells'
58
+
- '#reset-cells'
59
+
- '#power-domain-cells'
60
+
61
+
additionalProperties: false
62
+
63
+
examples:
64
+
- |
65
+
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
66
+
#include <dt-bindings/clock/qcom,rpmh.h>
67
+
#include <dt-bindings/power/qcom-rpmpd.h>
68
+
videocc: clock-controller@aaf0000 {
69
+
compatible = "qcom,sm8450-videocc";
70
+
reg = <0x0aaf0000 0x10000>;
71
+
clocks = <&rpmhcc RPMH_CXO_CLK>,
72
+
<&gcc GCC_VIDEO_AHB_CLK>;
73
+
power-domains = <&rpmhpd SM8450_MMCX>;
74
+
required-opps = <&rpmhpd_opp_low_svs>;
75
+
#clock-cells = <1>;
76
+
#reset-cells = <1>;
77
+
#power-domain-cells = <1>;
78
+
};
79
+
...
+7
-7
drivers/clk/at91/at91rm9200.c
+7
-7
drivers/clk/at91/at91rm9200.c
···
108
108
109
109
bypass = of_property_read_bool(np, "atmel,osc-bypass");
110
110
111
-
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
111
+
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
112
112
bypass);
113
113
if (IS_ERR(hw))
114
114
goto err_free;
115
115
116
-
hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
116
+
hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL);
117
117
if (IS_ERR(hw))
118
118
goto err_free;
119
119
···
140
140
parent_names[2] = "pllack";
141
141
parent_names[3] = "pllbck";
142
142
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
143
-
parent_names,
143
+
parent_names, NULL,
144
144
&at91rm9200_master_layout,
145
145
&rm9200_mck_characteristics,
146
146
&rm9200_mck_lock);
···
148
148
goto err_free;
149
149
150
150
hw = at91_clk_register_master_div(regmap, "masterck_div",
151
-
"masterck_pres",
151
+
"masterck_pres", NULL,
152
152
&at91rm9200_master_layout,
153
153
&rm9200_mck_characteristics,
154
154
&rm9200_mck_lock, CLK_SET_RATE_GATE, 0);
···
171
171
snprintf(name, sizeof(name), "prog%d", i);
172
172
173
173
hw = at91_clk_register_programmable(regmap, name,
174
-
parent_names, 4, i,
174
+
parent_names, NULL, 4, i,
175
175
&at91rm9200_programmable_layout,
176
176
NULL);
177
177
if (IS_ERR(hw))
···
182
182
183
183
for (i = 0; i < ARRAY_SIZE(at91rm9200_systemck); i++) {
184
184
hw = at91_clk_register_system(regmap, at91rm9200_systemck[i].n,
185
-
at91rm9200_systemck[i].p,
185
+
at91rm9200_systemck[i].p, NULL,
186
186
at91rm9200_systemck[i].id, 0);
187
187
if (IS_ERR(hw))
188
188
goto err_free;
···
193
193
for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) {
194
194
hw = at91_clk_register_peripheral(regmap,
195
195
at91rm9200_periphck[i].n,
196
-
"masterck_div",
196
+
"masterck_div", NULL,
197
197
at91rm9200_periphck[i].id);
198
198
if (IS_ERR(hw))
199
199
goto err_free;
+7
-7
drivers/clk/at91/at91sam9260.c
+7
-7
drivers/clk/at91/at91sam9260.c
···
363
363
364
364
bypass = of_property_read_bool(np, "atmel,osc-bypass");
365
365
366
-
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
366
+
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
367
367
bypass);
368
368
if (IS_ERR(hw))
369
369
goto err_free;
370
370
371
-
hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
371
+
hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL);
372
372
if (IS_ERR(hw))
373
373
goto err_free;
374
374
···
416
416
parent_names[2] = "pllack";
417
417
parent_names[3] = "pllbck";
418
418
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
419
-
parent_names,
419
+
parent_names, NULL,
420
420
&at91rm9200_master_layout,
421
421
data->mck_characteristics,
422
422
&at91sam9260_mck_lock);
···
424
424
goto err_free;
425
425
426
426
hw = at91_clk_register_master_div(regmap, "masterck_div",
427
-
"masterck_pres",
427
+
"masterck_pres", NULL,
428
428
&at91rm9200_master_layout,
429
429
data->mck_characteristics,
430
430
&at91sam9260_mck_lock,
···
448
448
snprintf(name, sizeof(name), "prog%d", i);
449
449
450
450
hw = at91_clk_register_programmable(regmap, name,
451
-
parent_names, 4, i,
451
+
parent_names, NULL, 4, i,
452
452
&at91rm9200_programmable_layout,
453
453
NULL);
454
454
if (IS_ERR(hw))
···
459
459
460
460
for (i = 0; i < data->num_sck; i++) {
461
461
hw = at91_clk_register_system(regmap, data->sck[i].n,
462
-
data->sck[i].p,
462
+
data->sck[i].p, NULL,
463
463
data->sck[i].id, 0);
464
464
if (IS_ERR(hw))
465
465
goto err_free;
···
470
470
for (i = 0; i < data->num_pck; i++) {
471
471
hw = at91_clk_register_peripheral(regmap,
472
472
data->pck[i].n,
473
-
"masterck_div",
473
+
"masterck_div", NULL,
474
474
data->pck[i].id);
475
475
if (IS_ERR(hw))
476
476
goto err_free;
+8
-8
drivers/clk/at91/at91sam9g45.c
+8
-8
drivers/clk/at91/at91sam9g45.c
···
123
123
124
124
bypass = of_property_read_bool(np, "atmel,osc-bypass");
125
125
126
-
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
126
+
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
127
127
bypass);
128
128
if (IS_ERR(hw))
129
129
goto err_free;
130
130
131
-
hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
131
+
hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL);
132
132
if (IS_ERR(hw))
133
133
goto err_free;
134
134
···
145
145
146
146
at91sam9g45_pmc->chws[PMC_PLLACK] = hw;
147
147
148
-
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
148
+
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
149
149
if (IS_ERR(hw))
150
150
goto err_free;
151
151
···
156
156
parent_names[2] = "plladivck";
157
157
parent_names[3] = "utmick";
158
158
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
159
-
parent_names,
159
+
parent_names, NULL,
160
160
&at91rm9200_master_layout,
161
161
&mck_characteristics,
162
162
&at91sam9g45_mck_lock);
···
164
164
goto err_free;
165
165
166
166
hw = at91_clk_register_master_div(regmap, "masterck_div",
167
-
"masterck_pres",
167
+
"masterck_pres", NULL,
168
168
&at91rm9200_master_layout,
169
169
&mck_characteristics,
170
170
&at91sam9g45_mck_lock,
···
191
191
snprintf(name, sizeof(name), "prog%d", i);
192
192
193
193
hw = at91_clk_register_programmable(regmap, name,
194
-
parent_names, 5, i,
194
+
parent_names, NULL, 5, i,
195
195
&at91sam9g45_programmable_layout,
196
196
NULL);
197
197
if (IS_ERR(hw))
···
202
202
203
203
for (i = 0; i < ARRAY_SIZE(at91sam9g45_systemck); i++) {
204
204
hw = at91_clk_register_system(regmap, at91sam9g45_systemck[i].n,
205
-
at91sam9g45_systemck[i].p,
205
+
at91sam9g45_systemck[i].p, NULL,
206
206
at91sam9g45_systemck[i].id,
207
207
at91sam9g45_systemck[i].flags);
208
208
if (IS_ERR(hw))
···
214
214
for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) {
215
215
hw = at91_clk_register_peripheral(regmap,
216
216
at91sam9g45_periphck[i].n,
217
-
"masterck_div",
217
+
"masterck_div", NULL,
218
218
at91sam9g45_periphck[i].id);
219
219
if (IS_ERR(hw))
220
220
goto err_free;
+7
-7
drivers/clk/at91/at91sam9n12.c
+7
-7
drivers/clk/at91/at91sam9n12.c
···
147
147
148
148
bypass = of_property_read_bool(np, "atmel,osc-bypass");
149
149
150
-
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
150
+
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
151
151
bypass);
152
152
if (IS_ERR(hw))
153
153
goto err_free;
154
154
155
155
parent_names[0] = "main_rc_osc";
156
156
parent_names[1] = "main_osc";
157
-
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
157
+
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
158
158
if (IS_ERR(hw))
159
159
goto err_free;
160
160
···
183
183
parent_names[2] = "plladivck";
184
184
parent_names[3] = "pllbck";
185
185
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
186
-
parent_names,
186
+
parent_names, NULL,
187
187
&at91sam9x5_master_layout,
188
188
&mck_characteristics,
189
189
&at91sam9n12_mck_lock);
···
191
191
goto err_free;
192
192
193
193
hw = at91_clk_register_master_div(regmap, "masterck_div",
194
-
"masterck_pres",
194
+
"masterck_pres", NULL,
195
195
&at91sam9x5_master_layout,
196
196
&mck_characteristics,
197
197
&at91sam9n12_mck_lock,
···
216
216
snprintf(name, sizeof(name), "prog%d", i);
217
217
218
218
hw = at91_clk_register_programmable(regmap, name,
219
-
parent_names, 5, i,
219
+
parent_names, NULL, 5, i,
220
220
&at91sam9x5_programmable_layout,
221
221
NULL);
222
222
if (IS_ERR(hw))
···
227
227
228
228
for (i = 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) {
229
229
hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n,
230
-
at91sam9n12_systemck[i].p,
230
+
at91sam9n12_systemck[i].p, NULL,
231
231
at91sam9n12_systemck[i].id,
232
232
at91sam9n12_systemck[i].flags);
233
233
if (IS_ERR(hw))
···
240
240
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
241
241
&at91sam9n12_pcr_layout,
242
242
at91sam9n12_periphck[i].n,
243
-
"masterck_div",
243
+
"masterck_div", NULL,
244
244
at91sam9n12_periphck[i].id,
245
245
&range, INT_MIN, 0);
246
246
if (IS_ERR(hw))
+7
-7
drivers/clk/at91/at91sam9rl.c
+7
-7
drivers/clk/at91/at91sam9rl.c
···
95
95
if (!at91sam9rl_pmc)
96
96
return;
97
97
98
-
hw = at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name);
98
+
hw = at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name, NULL);
99
99
if (IS_ERR(hw))
100
100
goto err_free;
101
101
···
109
109
110
110
at91sam9rl_pmc->chws[PMC_PLLACK] = hw;
111
111
112
-
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
112
+
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
113
113
if (IS_ERR(hw))
114
114
goto err_free;
115
115
···
120
120
parent_names[2] = "pllack";
121
121
parent_names[3] = "utmick";
122
122
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
123
-
parent_names,
123
+
parent_names, NULL,
124
124
&at91rm9200_master_layout,
125
125
&sam9rl_mck_characteristics,
126
126
&sam9rl_mck_lock);
···
128
128
goto err_free;
129
129
130
130
hw = at91_clk_register_master_div(regmap, "masterck_div",
131
-
"masterck_pres",
131
+
"masterck_pres", NULL,
132
132
&at91rm9200_master_layout,
133
133
&sam9rl_mck_characteristics,
134
134
&sam9rl_mck_lock, CLK_SET_RATE_GATE, 0);
···
148
148
snprintf(name, sizeof(name), "prog%d", i);
149
149
150
150
hw = at91_clk_register_programmable(regmap, name,
151
-
parent_names, 5, i,
151
+
parent_names, NULL, 5, i,
152
152
&at91rm9200_programmable_layout,
153
153
NULL);
154
154
if (IS_ERR(hw))
···
159
159
160
160
for (i = 0; i < ARRAY_SIZE(at91sam9rl_systemck); i++) {
161
161
hw = at91_clk_register_system(regmap, at91sam9rl_systemck[i].n,
162
-
at91sam9rl_systemck[i].p,
162
+
at91sam9rl_systemck[i].p, NULL,
163
163
at91sam9rl_systemck[i].id, 0);
164
164
if (IS_ERR(hw))
165
165
goto err_free;
···
170
170
for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) {
171
171
hw = at91_clk_register_peripheral(regmap,
172
172
at91sam9rl_periphck[i].n,
173
-
"masterck_div",
173
+
"masterck_div", NULL,
174
174
at91sam9rl_periphck[i].id);
175
175
if (IS_ERR(hw))
176
176
goto err_free;
+10
-10
drivers/clk/at91/at91sam9x5.c
+10
-10
drivers/clk/at91/at91sam9x5.c
···
169
169
170
170
bypass = of_property_read_bool(np, "atmel,osc-bypass");
171
171
172
-
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
172
+
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
173
173
bypass);
174
174
if (IS_ERR(hw))
175
175
goto err_free;
176
176
177
177
parent_names[0] = "main_rc_osc";
178
178
parent_names[1] = "main_osc";
179
-
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
179
+
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
180
180
if (IS_ERR(hw))
181
181
goto err_free;
182
182
···
193
193
194
194
at91sam9x5_pmc->chws[PMC_PLLACK] = hw;
195
195
196
-
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
196
+
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
197
197
if (IS_ERR(hw))
198
198
goto err_free;
199
199
···
204
204
parent_names[2] = "plladivck";
205
205
parent_names[3] = "utmick";
206
206
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
207
-
parent_names,
207
+
parent_names, NULL,
208
208
&at91sam9x5_master_layout,
209
209
&mck_characteristics, &mck_lock);
210
210
if (IS_ERR(hw))
211
211
goto err_free;
212
212
213
213
hw = at91_clk_register_master_div(regmap, "masterck_div",
214
-
"masterck_pres",
214
+
"masterck_pres", NULL,
215
215
&at91sam9x5_master_layout,
216
216
&mck_characteristics, &mck_lock,
217
217
CLK_SET_RATE_GATE, 0);
···
241
241
snprintf(name, sizeof(name), "prog%d", i);
242
242
243
243
hw = at91_clk_register_programmable(regmap, name,
244
-
parent_names, 5, i,
244
+
parent_names, NULL, 5, i,
245
245
&at91sam9x5_programmable_layout,
246
246
NULL);
247
247
if (IS_ERR(hw))
···
252
252
253
253
for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
254
254
hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
255
-
at91sam9x5_systemck[i].p,
255
+
at91sam9x5_systemck[i].p, NULL,
256
256
at91sam9x5_systemck[i].id,
257
257
at91sam9x5_systemck[i].flags);
258
258
if (IS_ERR(hw))
···
263
263
264
264
if (has_lcdck) {
265
265
hw = at91_clk_register_system(regmap, "lcdck", "masterck_div",
266
-
3, 0);
266
+
NULL, 3, 0);
267
267
if (IS_ERR(hw))
268
268
goto err_free;
269
269
···
274
274
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
275
275
&at91sam9x5_pcr_layout,
276
276
at91sam9x5_periphck[i].n,
277
-
"masterck_div",
277
+
"masterck_div", NULL,
278
278
at91sam9x5_periphck[i].id,
279
279
&range, INT_MIN, 0);
280
280
if (IS_ERR(hw))
···
287
287
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
288
288
&at91sam9x5_pcr_layout,
289
289
extra_pcks[i].n,
290
-
"masterck_div",
290
+
"masterck_div", NULL,
291
291
extra_pcks[i].id,
292
292
&range, INT_MIN, 0);
293
293
if (IS_ERR(hw))
+9
-2
drivers/clk/at91/clk-generated.c
+9
-2
drivers/clk/at91/clk-generated.c
···
319
319
at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
320
320
const struct clk_pcr_layout *layout,
321
321
const char *name, const char **parent_names,
322
+
struct clk_hw **parent_hws,
322
323
u32 *mux_table, u8 num_parents, u8 id,
323
324
const struct clk_range *range,
324
325
int chg_pid)
325
326
{
326
327
struct clk_generated *gck;
327
-
struct clk_init_data init;
328
+
struct clk_init_data init = {};
328
329
struct clk_hw *hw;
329
330
int ret;
331
+
332
+
if (!(parent_names || parent_hws))
333
+
return ERR_PTR(-ENOMEM);
330
334
331
335
gck = kzalloc(sizeof(*gck), GFP_KERNEL);
332
336
if (!gck)
···
338
334
339
335
init.name = name;
340
336
init.ops = &generated_ops;
341
-
init.parent_names = parent_names;
337
+
if (parent_hws)
338
+
init.parent_hws = (const struct clk_hw **)parent_hws;
339
+
else
340
+
init.parent_names = parent_names;
342
341
init.num_parents = num_parents;
343
342
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
344
343
if (chg_pid >= 0)
+22
-10
drivers/clk/at91/clk-main.c
+22
-10
drivers/clk/at91/clk-main.c
···
152
152
at91_clk_register_main_osc(struct regmap *regmap,
153
153
const char *name,
154
154
const char *parent_name,
155
+
struct clk_parent_data *parent_data,
155
156
bool bypass)
156
157
{
157
158
struct clk_main_osc *osc;
158
-
struct clk_init_data init;
159
+
struct clk_init_data init = {};
159
160
struct clk_hw *hw;
160
161
int ret;
161
162
162
-
if (!name || !parent_name)
163
+
if (!name || !(parent_name || parent_data))
163
164
return ERR_PTR(-EINVAL);
164
165
165
166
osc = kzalloc(sizeof(*osc), GFP_KERNEL);
···
169
168
170
169
init.name = name;
171
170
init.ops = &main_osc_ops;
172
-
init.parent_names = &parent_name;
171
+
if (parent_data)
172
+
init.parent_data = (const struct clk_parent_data *)parent_data;
173
+
else
174
+
init.parent_names = &parent_name;
173
175
init.num_parents = 1;
174
176
init.flags = CLK_IGNORE_UNUSED;
175
177
···
401
397
struct clk_hw * __init
402
398
at91_clk_register_rm9200_main(struct regmap *regmap,
403
399
const char *name,
404
-
const char *parent_name)
400
+
const char *parent_name,
401
+
struct clk_hw *parent_hw)
405
402
{
406
403
struct clk_rm9200_main *clkmain;
407
-
struct clk_init_data init;
404
+
struct clk_init_data init = {};
408
405
struct clk_hw *hw;
409
406
int ret;
410
407
411
408
if (!name)
412
409
return ERR_PTR(-EINVAL);
413
410
414
-
if (!parent_name)
411
+
if (!(parent_name || parent_hw))
415
412
return ERR_PTR(-EINVAL);
416
413
417
414
clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
···
421
416
422
417
init.name = name;
423
418
init.ops = &rm9200_main_ops;
424
-
init.parent_names = &parent_name;
419
+
if (parent_hw)
420
+
init.parent_hws = (const struct clk_hw **)&parent_hw;
421
+
else
422
+
init.parent_names = &parent_name;
425
423
init.num_parents = 1;
426
424
init.flags = 0;
427
425
···
552
544
at91_clk_register_sam9x5_main(struct regmap *regmap,
553
545
const char *name,
554
546
const char **parent_names,
547
+
struct clk_hw **parent_hws,
555
548
int num_parents)
556
549
{
557
550
struct clk_sam9x5_main *clkmain;
558
-
struct clk_init_data init;
551
+
struct clk_init_data init = {};
559
552
unsigned int status;
560
553
struct clk_hw *hw;
561
554
int ret;
···
564
555
if (!name)
565
556
return ERR_PTR(-EINVAL);
566
557
567
-
if (!parent_names || !num_parents)
558
+
if (!(parent_hws || parent_names) || !num_parents)
568
559
return ERR_PTR(-EINVAL);
569
560
570
561
clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
···
573
564
574
565
init.name = name;
575
566
init.ops = &sam9x5_main_ops;
576
-
init.parent_names = parent_names;
567
+
if (parent_hws)
568
+
init.parent_hws = (const struct clk_hw **)parent_hws;
569
+
else
570
+
init.parent_names = parent_names;
577
571
init.num_parents = num_parents;
578
572
init.flags = CLK_SET_PARENT_GATE;
579
573
+19
-9
drivers/clk/at91/clk-master.c
+19
-9
drivers/clk/at91/clk-master.c
···
473
473
at91_clk_register_master_internal(struct regmap *regmap,
474
474
const char *name, int num_parents,
475
475
const char **parent_names,
476
+
struct clk_hw **parent_hws,
476
477
const struct clk_master_layout *layout,
477
478
const struct clk_master_characteristics *characteristics,
478
479
const struct clk_ops *ops, spinlock_t *lock, u32 flags)
479
480
{
480
481
struct clk_master *master;
481
-
struct clk_init_data init;
482
+
struct clk_init_data init = {};
482
483
struct clk_hw *hw;
483
484
unsigned int mckr;
484
485
unsigned long irqflags;
485
486
int ret;
486
487
487
-
if (!name || !num_parents || !parent_names || !lock)
488
+
if (!name || !num_parents || !(parent_names || parent_hws) || !lock)
488
489
return ERR_PTR(-EINVAL);
489
490
490
491
master = kzalloc(sizeof(*master), GFP_KERNEL);
···
494
493
495
494
init.name = name;
496
495
init.ops = ops;
497
-
init.parent_names = parent_names;
496
+
if (parent_hws)
497
+
init.parent_hws = (const struct clk_hw **)parent_hws;
498
+
else
499
+
init.parent_names = parent_names;
498
500
init.num_parents = num_parents;
499
501
init.flags = flags;
500
502
···
531
527
at91_clk_register_master_pres(struct regmap *regmap,
532
528
const char *name, int num_parents,
533
529
const char **parent_names,
530
+
struct clk_hw **parent_hws,
534
531
const struct clk_master_layout *layout,
535
532
const struct clk_master_characteristics *characteristics,
536
533
spinlock_t *lock)
537
534
{
538
535
return at91_clk_register_master_internal(regmap, name, num_parents,
539
-
parent_names, layout,
536
+
parent_names, parent_hws, layout,
540
537
characteristics,
541
538
&master_pres_ops,
542
539
lock, CLK_SET_RATE_GATE);
···
546
541
struct clk_hw * __init
547
542
at91_clk_register_master_div(struct regmap *regmap,
548
543
const char *name, const char *parent_name,
549
-
const struct clk_master_layout *layout,
544
+
struct clk_hw *parent_hw, const struct clk_master_layout *layout,
550
545
const struct clk_master_characteristics *characteristics,
551
546
spinlock_t *lock, u32 flags, u32 safe_div)
552
547
{
···
559
554
ops = &master_div_ops_chg;
560
555
561
556
hw = at91_clk_register_master_internal(regmap, name, 1,
562
-
&parent_name, layout,
557
+
parent_name ? &parent_name : NULL,
558
+
parent_hw ? &parent_hw : NULL, layout,
563
559
characteristics, ops,
564
560
lock, flags);
565
561
···
812
806
at91_clk_sama7g5_register_master(struct regmap *regmap,
813
807
const char *name, int num_parents,
814
808
const char **parent_names,
809
+
struct clk_hw **parent_hws,
815
810
u32 *mux_table,
816
811
spinlock_t *lock, u8 id,
817
812
bool critical, int chg_pid)
818
813
{
819
814
struct clk_master *master;
820
815
struct clk_hw *hw;
821
-
struct clk_init_data init;
816
+
struct clk_init_data init = {};
822
817
unsigned long flags;
823
818
unsigned int val;
824
819
int ret;
825
820
826
-
if (!name || !num_parents || !parent_names || !mux_table ||
821
+
if (!name || !num_parents || !(parent_names || parent_hws) || !mux_table ||
827
822
!lock || id > MASTER_MAX_ID)
828
823
return ERR_PTR(-EINVAL);
829
824
···
834
827
835
828
init.name = name;
836
829
init.ops = &sama7g5_master_ops;
837
-
init.parent_names = parent_names;
830
+
if (parent_hws)
831
+
init.parent_hws = (const struct clk_hw **)parent_hws;
832
+
else
833
+
init.parent_names = parent_names;
838
834
init.num_parents = num_parents;
839
835
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
840
836
if (chg_pid >= 0)
+15
-7
drivers/clk/at91/clk-peripheral.c
+15
-7
drivers/clk/at91/clk-peripheral.c
···
97
97
98
98
struct clk_hw * __init
99
99
at91_clk_register_peripheral(struct regmap *regmap, const char *name,
100
-
const char *parent_name, u32 id)
100
+
const char *parent_name, struct clk_hw *parent_hw,
101
+
u32 id)
101
102
{
102
103
struct clk_peripheral *periph;
103
-
struct clk_init_data init;
104
+
struct clk_init_data init = {};
104
105
struct clk_hw *hw;
105
106
int ret;
106
107
107
-
if (!name || !parent_name || id > PERIPHERAL_ID_MAX)
108
+
if (!name || !(parent_name || parent_hw) || id > PERIPHERAL_ID_MAX)
108
109
return ERR_PTR(-EINVAL);
109
110
110
111
periph = kzalloc(sizeof(*periph), GFP_KERNEL);
···
114
113
115
114
init.name = name;
116
115
init.ops = &peripheral_ops;
117
-
init.parent_names = &parent_name;
116
+
if (parent_hw)
117
+
init.parent_hws = (const struct clk_hw **)&parent_hw;
118
+
else
119
+
init.parent_names = &parent_name;
118
120
init.num_parents = 1;
119
121
init.flags = 0;
120
122
···
448
444
at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
449
445
const struct clk_pcr_layout *layout,
450
446
const char *name, const char *parent_name,
447
+
struct clk_hw *parent_hw,
451
448
u32 id, const struct clk_range *range,
452
449
int chg_pid, unsigned long flags)
453
450
{
454
451
struct clk_sam9x5_peripheral *periph;
455
-
struct clk_init_data init;
452
+
struct clk_init_data init = {};
456
453
struct clk_hw *hw;
457
454
int ret;
458
455
459
-
if (!name || !parent_name)
456
+
if (!name || !(parent_name || parent_hw))
460
457
return ERR_PTR(-EINVAL);
461
458
462
459
periph = kzalloc(sizeof(*periph), GFP_KERNEL);
···
465
460
return ERR_PTR(-ENOMEM);
466
461
467
462
init.name = name;
468
-
init.parent_names = &parent_name;
463
+
if (parent_hw)
464
+
init.parent_hws = (const struct clk_hw **)&parent_hw;
465
+
else
466
+
init.parent_names = &parent_name;
469
467
init.num_parents = 1;
470
468
init.flags = flags;
471
469
if (chg_pid < 0) {
+7
-4
drivers/clk/at91/clk-programmable.c
+7
-4
drivers/clk/at91/clk-programmable.c
···
215
215
struct clk_hw * __init
216
216
at91_clk_register_programmable(struct regmap *regmap,
217
217
const char *name, const char **parent_names,
218
-
u8 num_parents, u8 id,
218
+
struct clk_hw **parent_hws, u8 num_parents, u8 id,
219
219
const struct clk_programmable_layout *layout,
220
220
u32 *mux_table)
221
221
{
222
222
struct clk_programmable *prog;
223
223
struct clk_hw *hw;
224
-
struct clk_init_data init;
224
+
struct clk_init_data init = {};
225
225
int ret;
226
226
227
-
if (id > PROG_ID_MAX)
227
+
if (id > PROG_ID_MAX || !(parent_names || parent_hws))
228
228
return ERR_PTR(-EINVAL);
229
229
230
230
prog = kzalloc(sizeof(*prog), GFP_KERNEL);
···
233
233
234
234
init.name = name;
235
235
init.ops = &programmable_ops;
236
-
init.parent_names = parent_names;
236
+
if (parent_hws)
237
+
init.parent_hws = (const struct clk_hw **)parent_hws;
238
+
else
239
+
init.parent_names = parent_names;
237
240
init.num_parents = num_parents;
238
241
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
239
242
+12
-5
drivers/clk/at91/clk-sam9x60-pll.c
+12
-5
drivers/clk/at91/clk-sam9x60-pll.c
···
616
616
{
617
617
struct sam9x60_frac *frac;
618
618
struct clk_hw *hw;
619
-
struct clk_init_data init;
619
+
struct clk_init_data init = {};
620
620
unsigned long parent_rate, irqflags;
621
621
unsigned int val;
622
622
int ret;
···
629
629
return ERR_PTR(-ENOMEM);
630
630
631
631
init.name = name;
632
-
init.parent_names = &parent_name;
632
+
if (parent_name)
633
+
init.parent_names = &parent_name;
634
+
else
635
+
init.parent_hws = (const struct clk_hw **)&parent_hw;
633
636
init.num_parents = 1;
634
637
if (flags & CLK_SET_RATE_GATE)
635
638
init.ops = &sam9x60_frac_pll_ops;
···
695
692
696
693
struct clk_hw * __init
697
694
sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
698
-
const char *name, const char *parent_name, u8 id,
695
+
const char *name, const char *parent_name,
696
+
struct clk_hw *parent_hw, u8 id,
699
697
const struct clk_pll_characteristics *characteristics,
700
698
const struct clk_pll_layout *layout, u32 flags,
701
699
u32 safe_div)
702
700
{
703
701
struct sam9x60_div *div;
704
702
struct clk_hw *hw;
705
-
struct clk_init_data init;
703
+
struct clk_init_data init = {};
706
704
unsigned long irqflags;
707
705
unsigned int val;
708
706
int ret;
···
720
716
return ERR_PTR(-ENOMEM);
721
717
722
718
init.name = name;
723
-
init.parent_names = &parent_name;
719
+
if (parent_hw)
720
+
init.parent_hws = (const struct clk_hw **)&parent_hw;
721
+
else
722
+
init.parent_names = &parent_name;
724
723
init.num_parents = 1;
725
724
if (flags & CLK_SET_RATE_GATE)
726
725
init.ops = &sam9x60_div_pll_ops;
+8
-4
drivers/clk/at91/clk-system.c
+8
-4
drivers/clk/at91/clk-system.c
···
105
105
106
106
struct clk_hw * __init
107
107
at91_clk_register_system(struct regmap *regmap, const char *name,
108
-
const char *parent_name, u8 id, unsigned long flags)
108
+
const char *parent_name, struct clk_hw *parent_hw, u8 id,
109
+
unsigned long flags)
109
110
{
110
111
struct clk_system *sys;
111
112
struct clk_hw *hw;
112
-
struct clk_init_data init;
113
+
struct clk_init_data init = {};
113
114
int ret;
114
115
115
-
if (!parent_name || id > SYSTEM_MAX_ID)
116
+
if (!(parent_name || parent_hw) || id > SYSTEM_MAX_ID)
116
117
return ERR_PTR(-EINVAL);
117
118
118
119
sys = kzalloc(sizeof(*sys), GFP_KERNEL);
···
122
121
123
122
init.name = name;
124
123
init.ops = &system_ops;
125
-
init.parent_names = &parent_name;
124
+
if (parent_hw)
125
+
init.parent_hws = (const struct clk_hw **)&parent_hw;
126
+
else
127
+
init.parent_names = &parent_name;
126
128
init.num_parents = 1;
127
129
init.flags = CLK_SET_RATE_PARENT | flags;
128
130
+17
-7
drivers/clk/at91/clk-utmi.c
+17
-7
drivers/clk/at91/clk-utmi.c
···
144
144
at91_clk_register_utmi_internal(struct regmap *regmap_pmc,
145
145
struct regmap *regmap_sfr,
146
146
const char *name, const char *parent_name,
147
+
struct clk_hw *parent_hw,
147
148
const struct clk_ops *ops, unsigned long flags)
148
149
{
149
150
struct clk_utmi *utmi;
150
151
struct clk_hw *hw;
151
-
struct clk_init_data init;
152
+
struct clk_init_data init = {};
152
153
int ret;
154
+
155
+
if (!(parent_name || parent_hw))
156
+
return ERR_PTR(-EINVAL);
153
157
154
158
utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
155
159
if (!utmi)
···
161
157
162
158
init.name = name;
163
159
init.ops = ops;
164
-
init.parent_names = parent_name ? &parent_name : NULL;
165
-
init.num_parents = parent_name ? 1 : 0;
160
+
if (parent_hw) {
161
+
init.parent_hws = parent_hw ? (const struct clk_hw **)&parent_hw : NULL;
162
+
init.num_parents = parent_hw ? 1 : 0;
163
+
} else {
164
+
init.parent_names = parent_name ? &parent_name : NULL;
165
+
init.num_parents = parent_name ? 1 : 0;
166
+
}
166
167
init.flags = flags;
167
168
168
169
utmi->hw.init = &init;
···
186
177
187
178
struct clk_hw * __init
188
179
at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
189
-
const char *name, const char *parent_name)
180
+
const char *name, const char *parent_name,
181
+
struct clk_hw *parent_hw)
190
182
{
191
183
return at91_clk_register_utmi_internal(regmap_pmc, regmap_sfr, name,
192
-
parent_name, &utmi_ops, CLK_SET_RATE_GATE);
184
+
parent_name, parent_hw, &utmi_ops, CLK_SET_RATE_GATE);
193
185
}
194
186
195
187
static int clk_utmi_sama7g5_prepare(struct clk_hw *hw)
···
289
279
290
280
struct clk_hw * __init
291
281
at91_clk_sama7g5_register_utmi(struct regmap *regmap_pmc, const char *name,
292
-
const char *parent_name)
282
+
const char *parent_name, struct clk_hw *parent_hw)
293
283
{
294
284
return at91_clk_register_utmi_internal(regmap_pmc, NULL, name,
295
-
parent_name, &sama7g5_utmi_ops, 0);
285
+
parent_name, parent_hw, &sama7g5_utmi_ops, 0);
296
286
}
+12
-11
drivers/clk/at91/dt-compat.c
+12
-11
drivers/clk/at91/dt-compat.c
···
171
171
172
172
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
173
173
&dt_pcr_layout, name,
174
-
parent_names, NULL,
174
+
parent_names, NULL, NULL,
175
175
num_parents, id, &range,
176
176
chg_pid);
177
177
if (IS_ERR(hw))
···
269
269
if (IS_ERR(regmap))
270
270
return;
271
271
272
-
hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
272
+
hw = at91_clk_register_main_osc(regmap, name, parent_name, NULL, bypass);
273
273
if (IS_ERR(hw))
274
274
return;
275
275
···
323
323
if (IS_ERR(regmap))
324
324
return;
325
325
326
-
hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
326
+
hw = at91_clk_register_rm9200_main(regmap, name, parent_name, NULL);
327
327
if (IS_ERR(hw))
328
328
return;
329
329
···
354
354
355
355
of_property_read_string(np, "clock-output-names", &name);
356
356
357
-
hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
357
+
hw = at91_clk_register_sam9x5_main(regmap, name, parent_names, NULL,
358
358
num_parents);
359
359
if (IS_ERR(hw))
360
360
return;
···
420
420
return;
421
421
422
422
hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents,
423
-
parent_names, layout,
423
+
parent_names, NULL, layout,
424
424
characteristics, &mck_lock);
425
425
if (IS_ERR(hw))
426
426
goto out_free_characteristics;
427
427
428
-
hw = at91_clk_register_master_div(regmap, name, "masterck_pres",
428
+
hw = at91_clk_register_master_div(regmap, name, "masterck_pres", NULL,
429
429
layout, characteristics,
430
430
&mck_lock, CLK_SET_RATE_GATE, 0);
431
431
if (IS_ERR(hw))
···
490
490
491
491
if (type == PERIPHERAL_AT91RM9200) {
492
492
hw = at91_clk_register_peripheral(regmap, name,
493
-
parent_name, id);
493
+
parent_name, NULL, id);
494
494
} else {
495
495
struct clk_range range = CLK_RANGE(0, 0);
496
496
unsigned long flags = 0;
···
512
512
&dt_pcr_layout,
513
513
name,
514
514
parent_name,
515
+
NULL,
515
516
id, &range,
516
517
INT_MIN,
517
518
flags);
···
770
769
name = progclknp->name;
771
770
772
771
hw = at91_clk_register_programmable(regmap, name,
773
-
parent_names, num_parents,
772
+
parent_names, NULL, num_parents,
774
773
id, layout, mux_table);
775
774
if (IS_ERR(hw))
776
775
continue;
···
908
907
if (!strcmp(sysclknp->name, "ddrck"))
909
908
flags = CLK_IS_CRITICAL;
910
909
911
-
hw = at91_clk_register_system(regmap, name, parent_name, id,
912
-
flags);
910
+
hw = at91_clk_register_system(regmap, name, parent_name, NULL,
911
+
id, flags);
913
912
if (IS_ERR(hw))
914
913
continue;
915
914
···
1055
1054
regmap_sfr = NULL;
1056
1055
}
1057
1056
1058
-
hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
1057
+
hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name, NULL);
1059
1058
if (IS_ERR(hw))
1060
1059
return;
1061
1060
+24
-12
drivers/clk/at91/pmc.h
+24
-12
drivers/clk/at91/pmc.h
···
144
144
at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
145
145
const struct clk_pcr_layout *layout,
146
146
const char *name, const char **parent_names,
147
-
u32 *mux_table, u8 num_parents, u8 id,
147
+
struct clk_hw **parent_hws, u32 *mux_table,
148
+
u8 num_parents, u8 id,
148
149
const struct clk_range *range, int chg_pid);
149
150
150
151
struct clk_hw * __init
···
162
161
u32 frequency, u32 accuracy);
163
162
struct clk_hw * __init
164
163
at91_clk_register_main_osc(struct regmap *regmap, const char *name,
165
-
const char *parent_name, bool bypass);
164
+
const char *parent_name,
165
+
struct clk_parent_data *parent_data, bool bypass);
166
166
struct clk_hw * __init
167
167
at91_clk_register_rm9200_main(struct regmap *regmap,
168
168
const char *name,
169
-
const char *parent_name);
169
+
const char *parent_name,
170
+
struct clk_hw *parent_hw);
170
171
struct clk_hw * __init
171
172
at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name,
172
-
const char **parent_names, int num_parents);
173
+
const char **parent_names,
174
+
struct clk_hw **parent_hws, int num_parents);
173
175
174
176
struct clk_hw * __init
175
177
at91_clk_register_master_pres(struct regmap *regmap, const char *name,
176
178
int num_parents, const char **parent_names,
179
+
struct clk_hw **parent_hws,
177
180
const struct clk_master_layout *layout,
178
181
const struct clk_master_characteristics *characteristics,
179
182
spinlock_t *lock);
180
183
181
184
struct clk_hw * __init
182
185
at91_clk_register_master_div(struct regmap *regmap, const char *name,
183
-
const char *parent_names,
186
+
const char *parent_names, struct clk_hw *parent_hw,
184
187
const struct clk_master_layout *layout,
185
188
const struct clk_master_characteristics *characteristics,
186
189
spinlock_t *lock, u32 flags, u32 safe_div);
···
192
187
struct clk_hw * __init
193
188
at91_clk_sama7g5_register_master(struct regmap *regmap,
194
189
const char *name, int num_parents,
195
-
const char **parent_names, u32 *mux_table,
190
+
const char **parent_names,
191
+
struct clk_hw **parent_hws, u32 *mux_table,
196
192
spinlock_t *lock, u8 id, bool critical,
197
193
int chg_pid);
198
194
199
195
struct clk_hw * __init
200
196
at91_clk_register_peripheral(struct regmap *regmap, const char *name,
201
-
const char *parent_name, u32 id);
197
+
const char *parent_name, struct clk_hw *parent_hw,
198
+
u32 id);
202
199
struct clk_hw * __init
203
200
at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
204
201
const struct clk_pcr_layout *layout,
205
202
const char *name, const char *parent_name,
203
+
struct clk_hw *parent_hw,
206
204
u32 id, const struct clk_range *range,
207
205
int chg_pid, unsigned long flags);
208
206
···
220
212
221
213
struct clk_hw * __init
222
214
sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
223
-
const char *name, const char *parent_name, u8 id,
215
+
const char *name, const char *parent_name,
216
+
struct clk_hw *parent_hw, u8 id,
224
217
const struct clk_pll_characteristics *characteristics,
225
218
const struct clk_pll_layout *layout, u32 flags,
226
219
u32 safe_div);
···
235
226
236
227
struct clk_hw * __init
237
228
at91_clk_register_programmable(struct regmap *regmap, const char *name,
238
-
const char **parent_names, u8 num_parents, u8 id,
229
+
const char **parent_names, struct clk_hw **parent_hws,
230
+
u8 num_parents, u8 id,
239
231
const struct clk_programmable_layout *layout,
240
232
u32 *mux_table);
241
233
···
252
242
253
243
struct clk_hw * __init
254
244
at91_clk_register_system(struct regmap *regmap, const char *name,
255
-
const char *parent_name, u8 id, unsigned long flags);
245
+
const char *parent_name, struct clk_hw *parent_hw,
246
+
u8 id, unsigned long flags);
256
247
257
248
struct clk_hw * __init
258
249
at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
···
270
259
271
260
struct clk_hw * __init
272
261
at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
273
-
const char *name, const char *parent_name);
262
+
const char *name, const char *parent_name,
263
+
struct clk_hw *parent_hw);
274
264
275
265
struct clk_hw * __init
276
266
at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name,
277
-
const char *parent_name);
267
+
const char *parent_name, struct clk_hw *parent_hw);
278
268
279
269
#endif /* __PMC_H_ */
+10
-10
drivers/clk/at91/sam9x60.c
+10
-10
drivers/clk/at91/sam9x60.c
···
219
219
if (IS_ERR(hw))
220
220
goto err_free;
221
221
222
-
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 0);
222
+
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0);
223
223
if (IS_ERR(hw))
224
224
goto err_free;
225
225
main_osc_hw = hw;
226
226
227
227
parent_names[0] = "main_rc_osc";
228
228
parent_names[1] = "main_osc";
229
-
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
229
+
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
230
230
if (IS_ERR(hw))
231
231
goto err_free;
232
232
···
246
246
goto err_free;
247
247
248
248
hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck",
249
-
"pllack_fracck", 0, &plla_characteristics,
249
+
"pllack_fracck", NULL, 0, &plla_characteristics,
250
250
&pll_div_layout,
251
251
/*
252
252
* This feeds CPU. It should not
···
266
266
goto err_free;
267
267
268
268
hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck",
269
-
"upllck_fracck", 1, &upll_characteristics,
269
+
"upllck_fracck", NULL, 1, &upll_characteristics,
270
270
&pll_div_layout,
271
271
CLK_SET_RATE_GATE |
272
272
CLK_SET_PARENT_GATE |
···
280
280
parent_names[1] = "mainck";
281
281
parent_names[2] = "pllack_divck";
282
282
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3,
283
-
parent_names, &sam9x60_master_layout,
283
+
parent_names, NULL, &sam9x60_master_layout,
284
284
&mck_characteristics, &mck_lock);
285
285
if (IS_ERR(hw))
286
286
goto err_free;
287
287
288
288
hw = at91_clk_register_master_div(regmap, "masterck_div",
289
-
"masterck_pres", &sam9x60_master_layout,
289
+
"masterck_pres", NULL, &sam9x60_master_layout,
290
290
&mck_characteristics, &mck_lock,
291
291
CLK_SET_RATE_GATE, 0);
292
292
if (IS_ERR(hw))
···
313
313
snprintf(name, sizeof(name), "prog%d", i);
314
314
315
315
hw = at91_clk_register_programmable(regmap, name,
316
-
parent_names, 6, i,
316
+
parent_names, NULL, 6, i,
317
317
&sam9x60_programmable_layout,
318
318
NULL);
319
319
if (IS_ERR(hw))
···
324
324
325
325
for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) {
326
326
hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n,
327
-
sam9x60_systemck[i].p,
327
+
sam9x60_systemck[i].p, NULL,
328
328
sam9x60_systemck[i].id,
329
329
sam9x60_systemck[i].flags);
330
330
if (IS_ERR(hw))
···
337
337
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
338
338
&sam9x60_pcr_layout,
339
339
sam9x60_periphck[i].n,
340
-
"masterck_div",
340
+
"masterck_div", NULL,
341
341
sam9x60_periphck[i].id,
342
342
&range, INT_MIN,
343
343
sam9x60_periphck[i].flags);
···
351
351
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
352
352
&sam9x60_pcr_layout,
353
353
sam9x60_gck[i].n,
354
-
parent_names, NULL, 6,
354
+
parent_names, NULL, NULL, 6,
355
355
sam9x60_gck[i].id,
356
356
&sam9x60_gck[i].r, INT_MIN);
357
357
if (IS_ERR(hw))
+10
-10
drivers/clk/at91/sama5d2.c
+10
-10
drivers/clk/at91/sama5d2.c
···
202
202
203
203
bypass = of_property_read_bool(np, "atmel,osc-bypass");
204
204
205
-
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
205
+
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
206
206
bypass);
207
207
if (IS_ERR(hw))
208
208
goto err_free;
209
209
210
210
parent_names[0] = "main_rc_osc";
211
211
parent_names[1] = "main_osc";
212
-
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
212
+
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
213
213
if (IS_ERR(hw))
214
214
goto err_free;
215
215
···
249
249
if (IS_ERR(regmap_sfr))
250
250
regmap_sfr = NULL;
251
251
252
-
hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck");
252
+
hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck", NULL);
253
253
if (IS_ERR(hw))
254
254
goto err_free;
255
255
···
260
260
parent_names[2] = "plladivck";
261
261
parent_names[3] = "utmick";
262
262
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
263
-
parent_names,
263
+
parent_names, NULL,
264
264
&at91sam9x5_master_layout,
265
265
&mck_characteristics, &mck_lock);
266
266
if (IS_ERR(hw))
267
267
goto err_free;
268
268
269
269
hw = at91_clk_register_master_div(regmap, "masterck_div",
270
-
"masterck_pres",
270
+
"masterck_pres", NULL,
271
271
&at91sam9x5_master_layout,
272
272
&mck_characteristics, &mck_lock,
273
273
CLK_SET_RATE_GATE, 0);
···
300
300
snprintf(name, sizeof(name), "prog%d", i);
301
301
302
302
hw = at91_clk_register_programmable(regmap, name,
303
-
parent_names, 6, i,
303
+
parent_names, NULL, 6, i,
304
304
&sama5d2_programmable_layout,
305
305
NULL);
306
306
if (IS_ERR(hw))
···
311
311
312
312
for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) {
313
313
hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n,
314
-
sama5d2_systemck[i].p,
314
+
sama5d2_systemck[i].p, NULL,
315
315
sama5d2_systemck[i].id,
316
316
sama5d2_systemck[i].flags);
317
317
if (IS_ERR(hw))
···
324
324
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
325
325
&sama5d2_pcr_layout,
326
326
sama5d2_periphck[i].n,
327
-
"masterck_div",
327
+
"masterck_div", NULL,
328
328
sama5d2_periphck[i].id,
329
329
&range, INT_MIN,
330
330
sama5d2_periphck[i].flags);
···
338
338
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
339
339
&sama5d2_pcr_layout,
340
340
sama5d2_periph32ck[i].n,
341
-
"h32mxck",
341
+
"h32mxck", NULL,
342
342
sama5d2_periph32ck[i].id,
343
343
&sama5d2_periph32ck[i].r,
344
344
INT_MIN, 0);
···
358
358
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
359
359
&sama5d2_pcr_layout,
360
360
sama5d2_gck[i].n,
361
-
parent_names, NULL, 6,
361
+
parent_names, NULL, NULL, 6,
362
362
sama5d2_gck[i].id,
363
363
&sama5d2_gck[i].r,
364
364
sama5d2_gck[i].chg_pid);
+8
-8
drivers/clk/at91/sama5d3.c
+8
-8
drivers/clk/at91/sama5d3.c
···
150
150
151
151
bypass = of_property_read_bool(np, "atmel,osc-bypass");
152
152
153
-
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
153
+
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
154
154
bypass);
155
155
if (IS_ERR(hw))
156
156
goto err_free;
157
157
158
158
parent_names[0] = "main_rc_osc";
159
159
parent_names[1] = "main_osc";
160
-
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
160
+
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
161
161
if (IS_ERR(hw))
162
162
goto err_free;
163
163
···
172
172
173
173
sama5d3_pmc->chws[PMC_PLLACK] = hw;
174
174
175
-
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
175
+
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
176
176
if (IS_ERR(hw))
177
177
goto err_free;
178
178
···
183
183
parent_names[2] = "plladivck";
184
184
parent_names[3] = "utmick";
185
185
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
186
-
parent_names,
186
+
parent_names, NULL,
187
187
&at91sam9x5_master_layout,
188
188
&mck_characteristics, &mck_lock);
189
189
if (IS_ERR(hw))
190
190
goto err_free;
191
191
192
192
hw = at91_clk_register_master_div(regmap, "masterck_div",
193
-
"masterck_pres",
193
+
"masterck_pres", NULL,
194
194
&at91sam9x5_master_layout,
195
195
&mck_characteristics, &mck_lock,
196
196
CLK_SET_RATE_GATE, 0);
···
220
220
snprintf(name, sizeof(name), "prog%d", i);
221
221
222
222
hw = at91_clk_register_programmable(regmap, name,
223
-
parent_names, 5, i,
223
+
parent_names, NULL, 5, i,
224
224
&at91sam9x5_programmable_layout,
225
225
NULL);
226
226
if (IS_ERR(hw))
···
231
231
232
232
for (i = 0; i < ARRAY_SIZE(sama5d3_systemck); i++) {
233
233
hw = at91_clk_register_system(regmap, sama5d3_systemck[i].n,
234
-
sama5d3_systemck[i].p,
234
+
sama5d3_systemck[i].p, NULL,
235
235
sama5d3_systemck[i].id,
236
236
sama5d3_systemck[i].flags);
237
237
if (IS_ERR(hw))
···
244
244
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
245
245
&sama5d3_pcr_layout,
246
246
sama5d3_periphck[i].n,
247
-
"masterck_div",
247
+
"masterck_div", NULL,
248
248
sama5d3_periphck[i].id,
249
249
&sama5d3_periphck[i].r,
250
250
INT_MIN,
+9
-9
drivers/clk/at91/sama5d4.c
+9
-9
drivers/clk/at91/sama5d4.c
···
165
165
166
166
bypass = of_property_read_bool(np, "atmel,osc-bypass");
167
167
168
-
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
168
+
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
169
169
bypass);
170
170
if (IS_ERR(hw))
171
171
goto err_free;
172
172
173
173
parent_names[0] = "main_rc_osc";
174
174
parent_names[1] = "main_osc";
175
-
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
175
+
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
176
176
if (IS_ERR(hw))
177
177
goto err_free;
178
178
···
187
187
188
188
sama5d4_pmc->chws[PMC_PLLACK] = hw;
189
189
190
-
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
190
+
hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
191
191
if (IS_ERR(hw))
192
192
goto err_free;
193
193
···
198
198
parent_names[2] = "plladivck";
199
199
parent_names[3] = "utmick";
200
200
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
201
-
parent_names,
201
+
parent_names, NULL,
202
202
&at91sam9x5_master_layout,
203
203
&mck_characteristics, &mck_lock);
204
204
if (IS_ERR(hw))
205
205
goto err_free;
206
206
207
207
hw = at91_clk_register_master_div(regmap, "masterck_div",
208
-
"masterck_pres",
208
+
"masterck_pres", NULL,
209
209
&at91sam9x5_master_layout,
210
210
&mck_characteristics, &mck_lock,
211
211
CLK_SET_RATE_GATE, 0);
···
243
243
snprintf(name, sizeof(name), "prog%d", i);
244
244
245
245
hw = at91_clk_register_programmable(regmap, name,
246
-
parent_names, 5, i,
246
+
parent_names, NULL, 5, i,
247
247
&at91sam9x5_programmable_layout,
248
248
NULL);
249
249
if (IS_ERR(hw))
···
254
254
255
255
for (i = 0; i < ARRAY_SIZE(sama5d4_systemck); i++) {
256
256
hw = at91_clk_register_system(regmap, sama5d4_systemck[i].n,
257
-
sama5d4_systemck[i].p,
257
+
sama5d4_systemck[i].p, NULL,
258
258
sama5d4_systemck[i].id,
259
259
sama5d4_systemck[i].flags);
260
260
if (IS_ERR(hw))
···
267
267
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
268
268
&sama5d4_pcr_layout,
269
269
sama5d4_periphck[i].n,
270
-
"masterck_div",
270
+
"masterck_div", NULL,
271
271
sama5d4_periphck[i].id,
272
272
&range, INT_MIN,
273
273
sama5d4_periphck[i].flags);
···
281
281
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
282
282
&sama5d4_pcr_layout,
283
283
sama5d4_periph32ck[i].n,
284
-
"h32mxck",
284
+
"h32mxck", NULL,
285
285
sama5d4_periph32ck[i].id,
286
286
&range, INT_MIN, 0);
287
287
if (IS_ERR(hw))
+447
-335
drivers/clk/at91/sama7g5.c
+447
-335
drivers/clk/at91/sama7g5.c
···
57
57
};
58
58
59
59
/*
60
+
* PLL component identifier
61
+
* @PLL_COMPID_FRAC: Fractional PLL component identifier
62
+
* @PLL_COMPID_DIV0: 1st PLL divider component identifier
63
+
* @PLL_COMPID_DIV1: 2nd PLL divider component identifier
64
+
*/
65
+
enum pll_component_id {
66
+
PLL_COMPID_FRAC,
67
+
PLL_COMPID_DIV0,
68
+
PLL_COMPID_DIV1,
69
+
};
70
+
71
+
/*
60
72
* PLL type identifiers
61
73
* @PLL_TYPE_FRAC: fractional PLL identifier
62
74
* @PLL_TYPE_DIV: divider PLL identifier
···
131
119
};
132
120
133
121
/*
122
+
* SAMA7G5 PLL possible parents
123
+
* @SAMA7G5_PLL_PARENT_MAINCK: MAINCK is PLL a parent
124
+
* @SAMA7G5_PLL_PARENT_MAIN_XTAL: MAIN XTAL is a PLL parent
125
+
* @SAMA7G5_PLL_PARENT_FRACCK: Frac PLL is a PLL parent (for PLL dividers)
126
+
*/
127
+
enum sama7g5_pll_parent {
128
+
SAMA7G5_PLL_PARENT_MAINCK,
129
+
SAMA7G5_PLL_PARENT_MAIN_XTAL,
130
+
SAMA7G5_PLL_PARENT_FRACCK,
131
+
};
132
+
133
+
/*
134
134
* PLL clocks description
135
135
* @n: clock name
136
-
* @p: clock parent
137
136
* @l: clock layout
138
137
* @c: clock characteristics
138
+
* @hw: pointer to clk_hw
139
139
* @t: clock type
140
140
* @f: clock flags
141
+
* @p: clock parent
141
142
* @eid: export index in sama7g5->chws[] array
142
143
* @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE
143
144
* notification
144
145
*/
145
-
static const struct {
146
+
static struct sama7g5_pll {
146
147
const char *n;
147
-
const char *p;
148
148
const struct clk_pll_layout *l;
149
149
const struct clk_pll_characteristics *c;
150
+
struct clk_hw *hw;
150
151
unsigned long f;
152
+
enum sama7g5_pll_parent p;
151
153
u8 t;
152
154
u8 eid;
153
155
u8 safe_div;
154
156
} sama7g5_plls[][PLL_ID_MAX] = {
155
157
[PLL_ID_CPU] = {
156
-
{ .n = "cpupll_fracck",
157
-
.p = "mainck",
158
-
.l = &pll_layout_frac,
159
-
.c = &cpu_pll_characteristics,
160
-
.t = PLL_TYPE_FRAC,
161
-
/*
162
-
* This feeds cpupll_divpmcck which feeds CPU. It should
163
-
* not be disabled.
164
-
*/
165
-
.f = CLK_IS_CRITICAL, },
158
+
[PLL_COMPID_FRAC] = {
159
+
.n = "cpupll_fracck",
160
+
.p = SAMA7G5_PLL_PARENT_MAINCK,
161
+
.l = &pll_layout_frac,
162
+
.c = &cpu_pll_characteristics,
163
+
.t = PLL_TYPE_FRAC,
164
+
/*
165
+
* This feeds cpupll_divpmcck which feeds CPU. It should
166
+
* not be disabled.
167
+
*/
168
+
.f = CLK_IS_CRITICAL,
169
+
},
166
170
167
-
{ .n = "cpupll_divpmcck",
168
-
.p = "cpupll_fracck",
169
-
.l = &pll_layout_divpmc,
170
-
.c = &cpu_pll_characteristics,
171
-
.t = PLL_TYPE_DIV,
172
-
/* This feeds CPU. It should not be disabled. */
173
-
.f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
174
-
.eid = PMC_CPUPLL,
175
-
/*
176
-
* Safe div=15 should be safe even for switching b/w 1GHz and
177
-
* 90MHz (frac pll might go up to 1.2GHz).
178
-
*/
179
-
.safe_div = 15, },
171
+
[PLL_COMPID_DIV0] = {
172
+
.n = "cpupll_divpmcck",
173
+
.p = SAMA7G5_PLL_PARENT_FRACCK,
174
+
.l = &pll_layout_divpmc,
175
+
.c = &cpu_pll_characteristics,
176
+
.t = PLL_TYPE_DIV,
177
+
/* This feeds CPU. It should not be disabled. */
178
+
.f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
179
+
.eid = PMC_CPUPLL,
180
+
/*
181
+
* Safe div=15 should be safe even for switching b/w 1GHz and
182
+
* 90MHz (frac pll might go up to 1.2GHz).
183
+
*/
184
+
.safe_div = 15,
185
+
},
180
186
},
181
187
182
188
[PLL_ID_SYS] = {
183
-
{ .n = "syspll_fracck",
184
-
.p = "mainck",
185
-
.l = &pll_layout_frac,
186
-
.c = &pll_characteristics,
187
-
.t = PLL_TYPE_FRAC,
188
-
/*
189
-
* This feeds syspll_divpmcck which may feed critical parts
190
-
* of the systems like timers. Therefore it should not be
191
-
* disabled.
192
-
*/
193
-
.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
189
+
[PLL_COMPID_FRAC] = {
190
+
.n = "syspll_fracck",
191
+
.p = SAMA7G5_PLL_PARENT_MAINCK,
192
+
.l = &pll_layout_frac,
193
+
.c = &pll_characteristics,
194
+
.t = PLL_TYPE_FRAC,
195
+
/*
196
+
* This feeds syspll_divpmcck which may feed critical parts
197
+
* of the systems like timers. Therefore it should not be
198
+
* disabled.
199
+
*/
200
+
.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
201
+
},
194
202
195
-
{ .n = "syspll_divpmcck",
196
-
.p = "syspll_fracck",
197
-
.l = &pll_layout_divpmc,
198
-
.c = &pll_characteristics,
199
-
.t = PLL_TYPE_DIV,
200
-
/*
201
-
* This may feed critical parts of the systems like timers.
202
-
* Therefore it should not be disabled.
203
-
*/
204
-
.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
205
-
.eid = PMC_SYSPLL, },
203
+
[PLL_COMPID_DIV0] = {
204
+
.n = "syspll_divpmcck",
205
+
.p = SAMA7G5_PLL_PARENT_FRACCK,
206
+
.l = &pll_layout_divpmc,
207
+
.c = &pll_characteristics,
208
+
.t = PLL_TYPE_DIV,
209
+
/*
210
+
* This may feed critical parts of the systems like timers.
211
+
* Therefore it should not be disabled.
212
+
*/
213
+
.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
214
+
.eid = PMC_SYSPLL,
215
+
},
206
216
},
207
217
208
218
[PLL_ID_DDR] = {
209
-
{ .n = "ddrpll_fracck",
210
-
.p = "mainck",
211
-
.l = &pll_layout_frac,
212
-
.c = &pll_characteristics,
213
-
.t = PLL_TYPE_FRAC,
214
-
/*
215
-
* This feeds ddrpll_divpmcck which feeds DDR. It should not
216
-
* be disabled.
217
-
*/
218
-
.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
219
+
[PLL_COMPID_FRAC] = {
220
+
.n = "ddrpll_fracck",
221
+
.p = SAMA7G5_PLL_PARENT_MAINCK,
222
+
.l = &pll_layout_frac,
223
+
.c = &pll_characteristics,
224
+
.t = PLL_TYPE_FRAC,
225
+
/*
226
+
* This feeds ddrpll_divpmcck which feeds DDR. It should not
227
+
* be disabled.
228
+
*/
229
+
.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
230
+
},
219
231
220
-
{ .n = "ddrpll_divpmcck",
221
-
.p = "ddrpll_fracck",
222
-
.l = &pll_layout_divpmc,
223
-
.c = &pll_characteristics,
224
-
.t = PLL_TYPE_DIV,
225
-
/* This feeds DDR. It should not be disabled. */
226
-
.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
232
+
[PLL_COMPID_DIV0] = {
233
+
.n = "ddrpll_divpmcck",
234
+
.p = SAMA7G5_PLL_PARENT_FRACCK,
235
+
.l = &pll_layout_divpmc,
236
+
.c = &pll_characteristics,
237
+
.t = PLL_TYPE_DIV,
238
+
/* This feeds DDR. It should not be disabled. */
239
+
.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
240
+
},
227
241
},
228
242
229
243
[PLL_ID_IMG] = {
230
-
{ .n = "imgpll_fracck",
231
-
.p = "mainck",
232
-
.l = &pll_layout_frac,
233
-
.c = &pll_characteristics,
234
-
.t = PLL_TYPE_FRAC,
235
-
.f = CLK_SET_RATE_GATE, },
244
+
[PLL_COMPID_FRAC] = {
245
+
.n = "imgpll_fracck",
246
+
.p = SAMA7G5_PLL_PARENT_MAINCK,
247
+
.l = &pll_layout_frac,
248
+
.c = &pll_characteristics,
249
+
.t = PLL_TYPE_FRAC,
250
+
.f = CLK_SET_RATE_GATE,
251
+
},
236
252
237
-
{ .n = "imgpll_divpmcck",
238
-
.p = "imgpll_fracck",
239
-
.l = &pll_layout_divpmc,
240
-
.c = &pll_characteristics,
241
-
.t = PLL_TYPE_DIV,
242
-
.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
243
-
CLK_SET_RATE_PARENT, },
253
+
[PLL_COMPID_DIV0] = {
254
+
.n = "imgpll_divpmcck",
255
+
.p = SAMA7G5_PLL_PARENT_FRACCK,
256
+
.l = &pll_layout_divpmc,
257
+
.c = &pll_characteristics,
258
+
.t = PLL_TYPE_DIV,
259
+
.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
260
+
CLK_SET_RATE_PARENT,
261
+
},
244
262
},
245
263
246
264
[PLL_ID_BAUD] = {
247
-
{ .n = "baudpll_fracck",
248
-
.p = "mainck",
249
-
.l = &pll_layout_frac,
250
-
.c = &pll_characteristics,
251
-
.t = PLL_TYPE_FRAC,
252
-
.f = CLK_SET_RATE_GATE, },
265
+
[PLL_COMPID_FRAC] = {
266
+
.n = "baudpll_fracck",
267
+
.p = SAMA7G5_PLL_PARENT_MAINCK,
268
+
.l = &pll_layout_frac,
269
+
.c = &pll_characteristics,
270
+
.t = PLL_TYPE_FRAC,
271
+
.f = CLK_SET_RATE_GATE, },
253
272
254
-
{ .n = "baudpll_divpmcck",
255
-
.p = "baudpll_fracck",
256
-
.l = &pll_layout_divpmc,
257
-
.c = &pll_characteristics,
258
-
.t = PLL_TYPE_DIV,
259
-
.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
260
-
CLK_SET_RATE_PARENT, },
273
+
[PLL_COMPID_DIV0] = {
274
+
.n = "baudpll_divpmcck",
275
+
.p = SAMA7G5_PLL_PARENT_FRACCK,
276
+
.l = &pll_layout_divpmc,
277
+
.c = &pll_characteristics,
278
+
.t = PLL_TYPE_DIV,
279
+
.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
280
+
CLK_SET_RATE_PARENT,
281
+
},
261
282
},
262
283
263
284
[PLL_ID_AUDIO] = {
264
-
{ .n = "audiopll_fracck",
265
-
.p = "main_xtal",
266
-
.l = &pll_layout_frac,
267
-
.c = &pll_characteristics,
268
-
.t = PLL_TYPE_FRAC,
269
-
.f = CLK_SET_RATE_GATE, },
285
+
[PLL_COMPID_FRAC] = {
286
+
.n = "audiopll_fracck",
287
+
.p = SAMA7G5_PLL_PARENT_MAIN_XTAL,
288
+
.l = &pll_layout_frac,
289
+
.c = &pll_characteristics,
290
+
.t = PLL_TYPE_FRAC,
291
+
.f = CLK_SET_RATE_GATE,
292
+
},
270
293
271
-
{ .n = "audiopll_divpmcck",
272
-
.p = "audiopll_fracck",
273
-
.l = &pll_layout_divpmc,
274
-
.c = &pll_characteristics,
275
-
.t = PLL_TYPE_DIV,
276
-
.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
277
-
CLK_SET_RATE_PARENT,
278
-
.eid = PMC_AUDIOPMCPLL, },
294
+
[PLL_COMPID_DIV0] = {
295
+
.n = "audiopll_divpmcck",
296
+
.p = SAMA7G5_PLL_PARENT_FRACCK,
297
+
.l = &pll_layout_divpmc,
298
+
.c = &pll_characteristics,
299
+
.t = PLL_TYPE_DIV,
300
+
.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
301
+
CLK_SET_RATE_PARENT,
302
+
.eid = PMC_AUDIOPMCPLL,
303
+
},
279
304
280
-
{ .n = "audiopll_diviock",
281
-
.p = "audiopll_fracck",
282
-
.l = &pll_layout_divio,
283
-
.c = &pll_characteristics,
284
-
.t = PLL_TYPE_DIV,
285
-
.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
286
-
CLK_SET_RATE_PARENT,
287
-
.eid = PMC_AUDIOIOPLL, },
305
+
[PLL_COMPID_DIV1] = {
306
+
.n = "audiopll_diviock",
307
+
.p = SAMA7G5_PLL_PARENT_FRACCK,
308
+
.l = &pll_layout_divio,
309
+
.c = &pll_characteristics,
310
+
.t = PLL_TYPE_DIV,
311
+
.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
312
+
CLK_SET_RATE_PARENT,
313
+
.eid = PMC_AUDIOIOPLL,
314
+
},
288
315
},
289
316
290
317
[PLL_ID_ETH] = {
291
-
{ .n = "ethpll_fracck",
292
-
.p = "main_xtal",
293
-
.l = &pll_layout_frac,
294
-
.c = &pll_characteristics,
295
-
.t = PLL_TYPE_FRAC,
296
-
.f = CLK_SET_RATE_GATE, },
318
+
[PLL_COMPID_FRAC] = {
319
+
.n = "ethpll_fracck",
320
+
.p = SAMA7G5_PLL_PARENT_MAIN_XTAL,
321
+
.l = &pll_layout_frac,
322
+
.c = &pll_characteristics,
323
+
.t = PLL_TYPE_FRAC,
324
+
.f = CLK_SET_RATE_GATE,
325
+
},
297
326
298
-
{ .n = "ethpll_divpmcck",
299
-
.p = "ethpll_fracck",
300
-
.l = &pll_layout_divpmc,
301
-
.c = &pll_characteristics,
302
-
.t = PLL_TYPE_DIV,
303
-
.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
304
-
CLK_SET_RATE_PARENT, },
327
+
[PLL_COMPID_DIV0] = {
328
+
.n = "ethpll_divpmcck",
329
+
.p = SAMA7G5_PLL_PARENT_FRACCK,
330
+
.l = &pll_layout_divpmc,
331
+
.c = &pll_characteristics,
332
+
.t = PLL_TYPE_DIV,
333
+
.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
334
+
CLK_SET_RATE_PARENT,
335
+
},
305
336
},
306
337
};
338
+
339
+
/* Used to create an array entry identifying a PLL by its components. */
340
+
#define PLL_IDS_TO_ARR_ENTRY(_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_comp}
307
341
308
342
/*
309
343
* Master clock (MCK[1..4]) description
310
344
* @n: clock name
311
-
* @ep: extra parents names array
312
-
* @ep_chg_chg_id: index in parents array that specifies the changeable
345
+
* @ep: extra parents names array (entry formed by PLL components
346
+
* identifiers (see enum pll_component_id))
347
+
* @hw: pointer to clk_hw
348
+
* @ep_chg_id: index in parents array that specifies the changeable
313
349
* parent
314
350
* @ep_count: extra parents count
315
351
* @ep_mux_table: mux table for extra parents
···
365
305
* @eid: export index in sama7g5->chws[] array
366
306
* @c: true if clock is critical and cannot be disabled
367
307
*/
368
-
static const struct {
308
+
static struct {
369
309
const char *n;
370
-
const char *ep[4];
310
+
struct {
311
+
int pll_id;
312
+
int pll_compid;
313
+
} ep[4];
314
+
struct clk_hw *hw;
371
315
int ep_chg_id;
372
316
u8 ep_count;
373
317
u8 ep_mux_table[4];
···
379
315
u8 eid;
380
316
u8 c;
381
317
} sama7g5_mckx[] = {
318
+
{ .n = "mck0", }, /* Dummy entry for MCK0 to store hw in probe. */
382
319
{ .n = "mck1",
383
320
.id = 1,
384
-
.ep = { "syspll_divpmcck", },
321
+
.ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), },
385
322
.ep_mux_table = { 5, },
386
323
.ep_count = 1,
387
324
.ep_chg_id = INT_MIN,
···
391
326
392
327
{ .n = "mck2",
393
328
.id = 2,
394
-
.ep = { "ddrpll_divpmcck", },
329
+
.ep = { PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), },
395
330
.ep_mux_table = { 6, },
396
331
.ep_count = 1,
397
332
.ep_chg_id = INT_MIN,
···
399
334
400
335
{ .n = "mck3",
401
336
.id = 3,
402
-
.ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", },
337
+
.ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(DDR, DIV0),
338
+
PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), },
403
339
.ep_mux_table = { 5, 6, 7, },
404
340
.ep_count = 3,
405
341
.ep_chg_id = 5, },
406
342
407
343
{ .n = "mck4",
408
344
.id = 4,
409
-
.ep = { "syspll_divpmcck", },
345
+
.ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), },
410
346
.ep_mux_table = { 5, },
411
347
.ep_count = 1,
412
348
.ep_chg_id = INT_MIN,
···
417
351
/*
418
352
* System clock description
419
353
* @n: clock name
420
-
* @p: clock parent name
421
354
* @id: clock id
422
355
*/
423
356
static const struct {
424
357
const char *n;
425
-
const char *p;
426
358
u8 id;
427
359
} sama7g5_systemck[] = {
428
-
{ .n = "pck0", .p = "prog0", .id = 8, },
429
-
{ .n = "pck1", .p = "prog1", .id = 9, },
430
-
{ .n = "pck2", .p = "prog2", .id = 10, },
431
-
{ .n = "pck3", .p = "prog3", .id = 11, },
432
-
{ .n = "pck4", .p = "prog4", .id = 12, },
433
-
{ .n = "pck5", .p = "prog5", .id = 13, },
434
-
{ .n = "pck6", .p = "prog6", .id = 14, },
435
-
{ .n = "pck7", .p = "prog7", .id = 15, },
360
+
{ .n = "pck0", .id = 8, },
361
+
{ .n = "pck1", .id = 9, },
362
+
{ .n = "pck2", .id = 10, },
363
+
{ .n = "pck3", .id = 11, },
364
+
{ .n = "pck4", .id = 12, },
365
+
{ .n = "pck5", .id = 13, },
366
+
{ .n = "pck6", .id = 14, },
367
+
{ .n = "pck7", .id = 15, },
436
368
};
437
369
438
370
/* Mux table for programmable clocks. */
439
371
static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, };
440
372
441
373
/*
374
+
* Peripheral clock parent hw identifier (used to index in sama7g5_mckx[])
375
+
* @PCK_PARENT_HW_MCK0: pck parent hw identifier is MCK0
376
+
* @PCK_PARENT_HW_MCK1: pck parent hw identifier is MCK1
377
+
* @PCK_PARENT_HW_MCK2: pck parent hw identifier is MCK2
378
+
* @PCK_PARENT_HW_MCK3: pck parent hw identifier is MCK3
379
+
* @PCK_PARENT_HW_MCK4: pck parent hw identifier is MCK4
380
+
* @PCK_PARENT_HW_MAX: max identifier
381
+
*/
382
+
enum sama7g5_pck_parent_hw_id {
383
+
PCK_PARENT_HW_MCK0,
384
+
PCK_PARENT_HW_MCK1,
385
+
PCK_PARENT_HW_MCK2,
386
+
PCK_PARENT_HW_MCK3,
387
+
PCK_PARENT_HW_MCK4,
388
+
PCK_PARENT_HW_MAX,
389
+
};
390
+
391
+
/*
442
392
* Peripheral clock description
443
393
* @n: clock name
444
-
* @p: clock parent name
394
+
* @p: clock parent hw id
445
395
* @r: clock range values
446
396
* @id: clock id
447
397
* @chgp: index in parent array of the changeable parent
448
398
*/
449
-
static const struct {
399
+
static struct {
450
400
const char *n;
451
-
const char *p;
401
+
enum sama7g5_pck_parent_hw_id p;
452
402
struct clk_range r;
453
403
u8 chgp;
454
404
u8 id;
455
405
} sama7g5_periphck[] = {
456
-
{ .n = "pioA_clk", .p = "mck0", .id = 11, },
457
-
{ .n = "securam_clk", .p = "mck0", .id = 18, },
458
-
{ .n = "sfr_clk", .p = "mck1", .id = 19, },
459
-
{ .n = "hsmc_clk", .p = "mck1", .id = 21, },
460
-
{ .n = "xdmac0_clk", .p = "mck1", .id = 22, },
461
-
{ .n = "xdmac1_clk", .p = "mck1", .id = 23, },
462
-
{ .n = "xdmac2_clk", .p = "mck1", .id = 24, },
463
-
{ .n = "acc_clk", .p = "mck1", .id = 25, },
464
-
{ .n = "aes_clk", .p = "mck1", .id = 27, },
465
-
{ .n = "tzaesbasc_clk", .p = "mck1", .id = 28, },
466
-
{ .n = "asrc_clk", .p = "mck1", .id = 30, .r = { .max = 200000000, }, },
467
-
{ .n = "cpkcc_clk", .p = "mck0", .id = 32, },
468
-
{ .n = "csi_clk", .p = "mck3", .id = 33, .r = { .max = 266000000, }, .chgp = 1, },
469
-
{ .n = "csi2dc_clk", .p = "mck3", .id = 34, .r = { .max = 266000000, }, .chgp = 1, },
470
-
{ .n = "eic_clk", .p = "mck1", .id = 37, },
471
-
{ .n = "flex0_clk", .p = "mck1", .id = 38, },
472
-
{ .n = "flex1_clk", .p = "mck1", .id = 39, },
473
-
{ .n = "flex2_clk", .p = "mck1", .id = 40, },
474
-
{ .n = "flex3_clk", .p = "mck1", .id = 41, },
475
-
{ .n = "flex4_clk", .p = "mck1", .id = 42, },
476
-
{ .n = "flex5_clk", .p = "mck1", .id = 43, },
477
-
{ .n = "flex6_clk", .p = "mck1", .id = 44, },
478
-
{ .n = "flex7_clk", .p = "mck1", .id = 45, },
479
-
{ .n = "flex8_clk", .p = "mck1", .id = 46, },
480
-
{ .n = "flex9_clk", .p = "mck1", .id = 47, },
481
-
{ .n = "flex10_clk", .p = "mck1", .id = 48, },
482
-
{ .n = "flex11_clk", .p = "mck1", .id = 49, },
483
-
{ .n = "gmac0_clk", .p = "mck1", .id = 51, },
484
-
{ .n = "gmac1_clk", .p = "mck1", .id = 52, },
485
-
{ .n = "icm_clk", .p = "mck1", .id = 55, },
486
-
{ .n = "isc_clk", .p = "mck3", .id = 56, .r = { .max = 266000000, }, .chgp = 1, },
487
-
{ .n = "i2smcc0_clk", .p = "mck1", .id = 57, .r = { .max = 200000000, }, },
488
-
{ .n = "i2smcc1_clk", .p = "mck1", .id = 58, .r = { .max = 200000000, }, },
489
-
{ .n = "matrix_clk", .p = "mck1", .id = 60, },
490
-
{ .n = "mcan0_clk", .p = "mck1", .id = 61, .r = { .max = 200000000, }, },
491
-
{ .n = "mcan1_clk", .p = "mck1", .id = 62, .r = { .max = 200000000, }, },
492
-
{ .n = "mcan2_clk", .p = "mck1", .id = 63, .r = { .max = 200000000, }, },
493
-
{ .n = "mcan3_clk", .p = "mck1", .id = 64, .r = { .max = 200000000, }, },
494
-
{ .n = "mcan4_clk", .p = "mck1", .id = 65, .r = { .max = 200000000, }, },
495
-
{ .n = "mcan5_clk", .p = "mck1", .id = 66, .r = { .max = 200000000, }, },
496
-
{ .n = "pdmc0_clk", .p = "mck1", .id = 68, .r = { .max = 200000000, }, },
497
-
{ .n = "pdmc1_clk", .p = "mck1", .id = 69, .r = { .max = 200000000, }, },
498
-
{ .n = "pit64b0_clk", .p = "mck1", .id = 70, },
499
-
{ .n = "pit64b1_clk", .p = "mck1", .id = 71, },
500
-
{ .n = "pit64b2_clk", .p = "mck1", .id = 72, },
501
-
{ .n = "pit64b3_clk", .p = "mck1", .id = 73, },
502
-
{ .n = "pit64b4_clk", .p = "mck1", .id = 74, },
503
-
{ .n = "pit64b5_clk", .p = "mck1", .id = 75, },
504
-
{ .n = "pwm_clk", .p = "mck1", .id = 77, },
505
-
{ .n = "qspi0_clk", .p = "mck1", .id = 78, },
506
-
{ .n = "qspi1_clk", .p = "mck1", .id = 79, },
507
-
{ .n = "sdmmc0_clk", .p = "mck1", .id = 80, },
508
-
{ .n = "sdmmc1_clk", .p = "mck1", .id = 81, },
509
-
{ .n = "sdmmc2_clk", .p = "mck1", .id = 82, },
510
-
{ .n = "sha_clk", .p = "mck1", .id = 83, },
511
-
{ .n = "spdifrx_clk", .p = "mck1", .id = 84, .r = { .max = 200000000, }, },
512
-
{ .n = "spdiftx_clk", .p = "mck1", .id = 85, .r = { .max = 200000000, }, },
513
-
{ .n = "ssc0_clk", .p = "mck1", .id = 86, .r = { .max = 200000000, }, },
514
-
{ .n = "ssc1_clk", .p = "mck1", .id = 87, .r = { .max = 200000000, }, },
515
-
{ .n = "tcb0_ch0_clk", .p = "mck1", .id = 88, .r = { .max = 200000000, }, },
516
-
{ .n = "tcb0_ch1_clk", .p = "mck1", .id = 89, .r = { .max = 200000000, }, },
517
-
{ .n = "tcb0_ch2_clk", .p = "mck1", .id = 90, .r = { .max = 200000000, }, },
518
-
{ .n = "tcb1_ch0_clk", .p = "mck1", .id = 91, .r = { .max = 200000000, }, },
519
-
{ .n = "tcb1_ch1_clk", .p = "mck1", .id = 92, .r = { .max = 200000000, }, },
520
-
{ .n = "tcb1_ch2_clk", .p = "mck1", .id = 93, .r = { .max = 200000000, }, },
521
-
{ .n = "tcpca_clk", .p = "mck1", .id = 94, },
522
-
{ .n = "tcpcb_clk", .p = "mck1", .id = 95, },
523
-
{ .n = "tdes_clk", .p = "mck1", .id = 96, },
524
-
{ .n = "trng_clk", .p = "mck1", .id = 97, },
525
-
{ .n = "udphsa_clk", .p = "mck1", .id = 104, },
526
-
{ .n = "udphsb_clk", .p = "mck1", .id = 105, },
527
-
{ .n = "uhphs_clk", .p = "mck1", .id = 106, },
406
+
{ .n = "pioA_clk", .p = PCK_PARENT_HW_MCK0, .id = 11, },
407
+
{ .n = "securam_clk", .p = PCK_PARENT_HW_MCK0, .id = 18, },
408
+
{ .n = "sfr_clk", .p = PCK_PARENT_HW_MCK1, .id = 19, },
409
+
{ .n = "hsmc_clk", .p = PCK_PARENT_HW_MCK1, .id = 21, },
410
+
{ .n = "xdmac0_clk", .p = PCK_PARENT_HW_MCK1, .id = 22, },
411
+
{ .n = "xdmac1_clk", .p = PCK_PARENT_HW_MCK1, .id = 23, },
412
+
{ .n = "xdmac2_clk", .p = PCK_PARENT_HW_MCK1, .id = 24, },
413
+
{ .n = "acc_clk", .p = PCK_PARENT_HW_MCK1, .id = 25, },
414
+
{ .n = "aes_clk", .p = PCK_PARENT_HW_MCK1, .id = 27, },
415
+
{ .n = "tzaesbasc_clk", .p = PCK_PARENT_HW_MCK1, .id = 28, },
416
+
{ .n = "asrc_clk", .p = PCK_PARENT_HW_MCK1, .id = 30, .r = { .max = 200000000, }, },
417
+
{ .n = "cpkcc_clk", .p = PCK_PARENT_HW_MCK0, .id = 32, },
418
+
{ .n = "csi_clk", .p = PCK_PARENT_HW_MCK3, .id = 33, .r = { .max = 266000000, }, .chgp = 1, },
419
+
{ .n = "csi2dc_clk", .p = PCK_PARENT_HW_MCK3, .id = 34, .r = { .max = 266000000, }, .chgp = 1, },
420
+
{ .n = "eic_clk", .p = PCK_PARENT_HW_MCK1, .id = 37, },
421
+
{ .n = "flex0_clk", .p = PCK_PARENT_HW_MCK1, .id = 38, },
422
+
{ .n = "flex1_clk", .p = PCK_PARENT_HW_MCK1, .id = 39, },
423
+
{ .n = "flex2_clk", .p = PCK_PARENT_HW_MCK1, .id = 40, },
424
+
{ .n = "flex3_clk", .p = PCK_PARENT_HW_MCK1, .id = 41, },
425
+
{ .n = "flex4_clk", .p = PCK_PARENT_HW_MCK1, .id = 42, },
426
+
{ .n = "flex5_clk", .p = PCK_PARENT_HW_MCK1, .id = 43, },
427
+
{ .n = "flex6_clk", .p = PCK_PARENT_HW_MCK1, .id = 44, },
428
+
{ .n = "flex7_clk", .p = PCK_PARENT_HW_MCK1, .id = 45, },
429
+
{ .n = "flex8_clk", .p = PCK_PARENT_HW_MCK1, .id = 46, },
430
+
{ .n = "flex9_clk", .p = PCK_PARENT_HW_MCK1, .id = 47, },
431
+
{ .n = "flex10_clk", .p = PCK_PARENT_HW_MCK1, .id = 48, },
432
+
{ .n = "flex11_clk", .p = PCK_PARENT_HW_MCK1, .id = 49, },
433
+
{ .n = "gmac0_clk", .p = PCK_PARENT_HW_MCK1, .id = 51, },
434
+
{ .n = "gmac1_clk", .p = PCK_PARENT_HW_MCK1, .id = 52, },
435
+
{ .n = "icm_clk", .p = PCK_PARENT_HW_MCK1, .id = 55, },
436
+
{ .n = "isc_clk", .p = PCK_PARENT_HW_MCK3, .id = 56, .r = { .max = 266000000, }, .chgp = 1, },
437
+
{ .n = "i2smcc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 57, .r = { .max = 200000000, }, },
438
+
{ .n = "i2smcc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 58, .r = { .max = 200000000, }, },
439
+
{ .n = "matrix_clk", .p = PCK_PARENT_HW_MCK1, .id = 60, },
440
+
{ .n = "mcan0_clk", .p = PCK_PARENT_HW_MCK1, .id = 61, .r = { .max = 200000000, }, },
441
+
{ .n = "mcan1_clk", .p = PCK_PARENT_HW_MCK1, .id = 62, .r = { .max = 200000000, }, },
442
+
{ .n = "mcan2_clk", .p = PCK_PARENT_HW_MCK1, .id = 63, .r = { .max = 200000000, }, },
443
+
{ .n = "mcan3_clk", .p = PCK_PARENT_HW_MCK1, .id = 64, .r = { .max = 200000000, }, },
444
+
{ .n = "mcan4_clk", .p = PCK_PARENT_HW_MCK1, .id = 65, .r = { .max = 200000000, }, },
445
+
{ .n = "mcan5_clk", .p = PCK_PARENT_HW_MCK1, .id = 66, .r = { .max = 200000000, }, },
446
+
{ .n = "pdmc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 68, .r = { .max = 200000000, }, },
447
+
{ .n = "pdmc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 69, .r = { .max = 200000000, }, },
448
+
{ .n = "pit64b0_clk", .p = PCK_PARENT_HW_MCK1, .id = 70, },
449
+
{ .n = "pit64b1_clk", .p = PCK_PARENT_HW_MCK1, .id = 71, },
450
+
{ .n = "pit64b2_clk", .p = PCK_PARENT_HW_MCK1, .id = 72, },
451
+
{ .n = "pit64b3_clk", .p = PCK_PARENT_HW_MCK1, .id = 73, },
452
+
{ .n = "pit64b4_clk", .p = PCK_PARENT_HW_MCK1, .id = 74, },
453
+
{ .n = "pit64b5_clk", .p = PCK_PARENT_HW_MCK1, .id = 75, },
454
+
{ .n = "pwm_clk", .p = PCK_PARENT_HW_MCK1, .id = 77, },
455
+
{ .n = "qspi0_clk", .p = PCK_PARENT_HW_MCK1, .id = 78, },
456
+
{ .n = "qspi1_clk", .p = PCK_PARENT_HW_MCK1, .id = 79, },
457
+
{ .n = "sdmmc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 80, },
458
+
{ .n = "sdmmc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 81, },
459
+
{ .n = "sdmmc2_clk", .p = PCK_PARENT_HW_MCK1, .id = 82, },
460
+
{ .n = "sha_clk", .p = PCK_PARENT_HW_MCK1, .id = 83, },
461
+
{ .n = "spdifrx_clk", .p = PCK_PARENT_HW_MCK1, .id = 84, .r = { .max = 200000000, }, },
462
+
{ .n = "spdiftx_clk", .p = PCK_PARENT_HW_MCK1, .id = 85, .r = { .max = 200000000, }, },
463
+
{ .n = "ssc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 86, .r = { .max = 200000000, }, },
464
+
{ .n = "ssc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 87, .r = { .max = 200000000, }, },
465
+
{ .n = "tcb0_ch0_clk", .p = PCK_PARENT_HW_MCK1, .id = 88, .r = { .max = 200000000, }, },
466
+
{ .n = "tcb0_ch1_clk", .p = PCK_PARENT_HW_MCK1, .id = 89, .r = { .max = 200000000, }, },
467
+
{ .n = "tcb0_ch2_clk", .p = PCK_PARENT_HW_MCK1, .id = 90, .r = { .max = 200000000, }, },
468
+
{ .n = "tcb1_ch0_clk", .p = PCK_PARENT_HW_MCK1, .id = 91, .r = { .max = 200000000, }, },
469
+
{ .n = "tcb1_ch1_clk", .p = PCK_PARENT_HW_MCK1, .id = 92, .r = { .max = 200000000, }, },
470
+
{ .n = "tcb1_ch2_clk", .p = PCK_PARENT_HW_MCK1, .id = 93, .r = { .max = 200000000, }, },
471
+
{ .n = "tcpca_clk", .p = PCK_PARENT_HW_MCK1, .id = 94, },
472
+
{ .n = "tcpcb_clk", .p = PCK_PARENT_HW_MCK1, .id = 95, },
473
+
{ .n = "tdes_clk", .p = PCK_PARENT_HW_MCK1, .id = 96, },
474
+
{ .n = "trng_clk", .p = PCK_PARENT_HW_MCK1, .id = 97, },
475
+
{ .n = "udphsa_clk", .p = PCK_PARENT_HW_MCK1, .id = 104, },
476
+
{ .n = "udphsb_clk", .p = PCK_PARENT_HW_MCK1, .id = 105, },
477
+
{ .n = "uhphs_clk", .p = PCK_PARENT_HW_MCK1, .id = 106, },
528
478
};
529
479
530
480
/*
531
481
* Generic clock description
532
482
* @n: clock name
533
-
* @pp: PLL parents
483
+
* @pp: PLL parents (entry formed by PLL components identifiers
484
+
* (see enum pll_component_id))
534
485
* @pp_mux_table: PLL parents mux table
535
486
* @r: clock output range
536
487
* @pp_chg_id: id in parent array of changeable PLL parent
···
556
473
*/
557
474
static const struct {
558
475
const char *n;
559
-
const char *pp[8];
476
+
struct {
477
+
int pll_id;
478
+
int pll_compid;
479
+
} pp[8];
560
480
const char pp_mux_table[8];
561
481
struct clk_range r;
562
482
int pp_chg_id;
···
569
483
{ .n = "adc_gclk",
570
484
.id = 26,
571
485
.r = { .max = 100000000, },
572
-
.pp = { "syspll_divpmcck", "imgpll_divpmcck", "audiopll_divpmcck", },
486
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
487
+
PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
573
488
.pp_mux_table = { 5, 7, 9, },
574
489
.pp_count = 3,
575
490
.pp_chg_id = INT_MIN, },
···
578
491
{ .n = "asrc_gclk",
579
492
.id = 30,
580
493
.r = { .max = 200000000 },
581
-
.pp = { "audiopll_divpmcck", },
494
+
.pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
582
495
.pp_mux_table = { 9, },
583
496
.pp_count = 1,
584
497
.pp_chg_id = 3, },
···
586
499
{ .n = "csi_gclk",
587
500
.id = 33,
588
501
.r = { .max = 27000000 },
589
-
.pp = { "ddrpll_divpmcck", "imgpll_divpmcck", },
502
+
.pp = { PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), },
590
503
.pp_mux_table = { 6, 7, },
591
504
.pp_count = 2,
592
505
.pp_chg_id = INT_MIN, },
···
594
507
{ .n = "flex0_gclk",
595
508
.id = 38,
596
509
.r = { .max = 200000000 },
597
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
510
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
598
511
.pp_mux_table = { 5, 8, },
599
512
.pp_count = 2,
600
513
.pp_chg_id = INT_MIN, },
···
602
515
{ .n = "flex1_gclk",
603
516
.id = 39,
604
517
.r = { .max = 200000000 },
605
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
518
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
606
519
.pp_mux_table = { 5, 8, },
607
520
.pp_count = 2,
608
521
.pp_chg_id = INT_MIN, },
···
610
523
{ .n = "flex2_gclk",
611
524
.id = 40,
612
525
.r = { .max = 200000000 },
613
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
526
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
614
527
.pp_mux_table = { 5, 8, },
615
528
.pp_count = 2,
616
529
.pp_chg_id = INT_MIN, },
···
618
531
{ .n = "flex3_gclk",
619
532
.id = 41,
620
533
.r = { .max = 200000000 },
621
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
534
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
622
535
.pp_mux_table = { 5, 8, },
623
536
.pp_count = 2,
624
537
.pp_chg_id = INT_MIN, },
···
626
539
{ .n = "flex4_gclk",
627
540
.id = 42,
628
541
.r = { .max = 200000000 },
629
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
542
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
630
543
.pp_mux_table = { 5, 8, },
631
544
.pp_count = 2,
632
545
.pp_chg_id = INT_MIN, },
···
634
547
{ .n = "flex5_gclk",
635
548
.id = 43,
636
549
.r = { .max = 200000000 },
637
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
550
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
638
551
.pp_mux_table = { 5, 8, },
639
552
.pp_count = 2,
640
553
.pp_chg_id = INT_MIN, },
···
642
555
{ .n = "flex6_gclk",
643
556
.id = 44,
644
557
.r = { .max = 200000000 },
645
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
558
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
646
559
.pp_mux_table = { 5, 8, },
647
560
.pp_count = 2,
648
561
.pp_chg_id = INT_MIN, },
···
650
563
{ .n = "flex7_gclk",
651
564
.id = 45,
652
565
.r = { .max = 200000000 },
653
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
566
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
654
567
.pp_mux_table = { 5, 8, },
655
568
.pp_count = 2,
656
569
.pp_chg_id = INT_MIN, },
···
658
571
{ .n = "flex8_gclk",
659
572
.id = 46,
660
573
.r = { .max = 200000000 },
661
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
574
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
662
575
.pp_mux_table = { 5, 8, },
663
576
.pp_count = 2,
664
577
.pp_chg_id = INT_MIN, },
···
666
579
{ .n = "flex9_gclk",
667
580
.id = 47,
668
581
.r = { .max = 200000000 },
669
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
582
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
670
583
.pp_mux_table = { 5, 8, },
671
584
.pp_count = 2,
672
585
.pp_chg_id = INT_MIN, },
···
674
587
{ .n = "flex10_gclk",
675
588
.id = 48,
676
589
.r = { .max = 200000000 },
677
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
590
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
678
591
.pp_mux_table = { 5, 8, },
679
592
.pp_count = 2,
680
593
.pp_chg_id = INT_MIN, },
···
682
595
{ .n = "flex11_gclk",
683
596
.id = 49,
684
597
.r = { .max = 200000000 },
685
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
598
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
686
599
.pp_mux_table = { 5, 8, },
687
600
.pp_count = 2,
688
601
.pp_chg_id = INT_MIN, },
···
690
603
{ .n = "gmac0_gclk",
691
604
.id = 51,
692
605
.r = { .max = 125000000 },
693
-
.pp = { "ethpll_divpmcck", },
606
+
.pp = { PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
694
607
.pp_mux_table = { 10, },
695
608
.pp_count = 1,
696
609
.pp_chg_id = 3, },
···
698
611
{ .n = "gmac1_gclk",
699
612
.id = 52,
700
613
.r = { .max = 50000000 },
701
-
.pp = { "ethpll_divpmcck", },
614
+
.pp = { PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
702
615
.pp_mux_table = { 10, },
703
616
.pp_count = 1,
704
617
.pp_chg_id = INT_MIN, },
···
706
619
{ .n = "gmac0_tsu_gclk",
707
620
.id = 53,
708
621
.r = { .max = 300000000 },
709
-
.pp = { "audiopll_divpmcck", "ethpll_divpmcck", },
622
+
.pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
710
623
.pp_mux_table = { 9, 10, },
711
624
.pp_count = 2,
712
625
.pp_chg_id = INT_MIN, },
···
714
627
{ .n = "gmac1_tsu_gclk",
715
628
.id = 54,
716
629
.r = { .max = 300000000 },
717
-
.pp = { "audiopll_divpmcck", "ethpll_divpmcck", },
630
+
.pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
718
631
.pp_mux_table = { 9, 10, },
719
632
.pp_count = 2,
720
633
.pp_chg_id = INT_MIN, },
···
722
635
{ .n = "i2smcc0_gclk",
723
636
.id = 57,
724
637
.r = { .max = 100000000 },
725
-
.pp = { "syspll_divpmcck", "audiopll_divpmcck", },
638
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
726
639
.pp_mux_table = { 5, 9, },
727
640
.pp_count = 2,
728
641
.pp_chg_id = 4, },
···
730
643
{ .n = "i2smcc1_gclk",
731
644
.id = 58,
732
645
.r = { .max = 100000000 },
733
-
.pp = { "syspll_divpmcck", "audiopll_divpmcck", },
646
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
734
647
.pp_mux_table = { 5, 9, },
735
648
.pp_count = 2,
736
649
.pp_chg_id = 4, },
···
738
651
{ .n = "mcan0_gclk",
739
652
.id = 61,
740
653
.r = { .max = 200000000 },
741
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
654
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
742
655
.pp_mux_table = { 5, 8, },
743
656
.pp_count = 2,
744
657
.pp_chg_id = INT_MIN, },
···
746
659
{ .n = "mcan1_gclk",
747
660
.id = 62,
748
661
.r = { .max = 200000000 },
749
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
662
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
750
663
.pp_mux_table = { 5, 8, },
751
664
.pp_count = 2,
752
665
.pp_chg_id = INT_MIN, },
···
754
667
{ .n = "mcan2_gclk",
755
668
.id = 63,
756
669
.r = { .max = 200000000 },
757
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
670
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
758
671
.pp_mux_table = { 5, 8, },
759
672
.pp_count = 2,
760
673
.pp_chg_id = INT_MIN, },
···
762
675
{ .n = "mcan3_gclk",
763
676
.id = 64,
764
677
.r = { .max = 200000000 },
765
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
678
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
766
679
.pp_mux_table = { 5, 8, },
767
680
.pp_count = 2,
768
681
.pp_chg_id = INT_MIN, },
···
770
683
{ .n = "mcan4_gclk",
771
684
.id = 65,
772
685
.r = { .max = 200000000 },
773
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
686
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
774
687
.pp_mux_table = { 5, 8, },
775
688
.pp_count = 2,
776
689
.pp_chg_id = INT_MIN, },
···
778
691
{ .n = "mcan5_gclk",
779
692
.id = 66,
780
693
.r = { .max = 200000000 },
781
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
694
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
782
695
.pp_mux_table = { 5, 8, },
783
696
.pp_count = 2,
784
697
.pp_chg_id = INT_MIN, },
···
786
699
{ .n = "pdmc0_gclk",
787
700
.id = 68,
788
701
.r = { .max = 50000000 },
789
-
.pp = { "syspll_divpmcck", "audiopll_divpmcck", },
702
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
790
703
.pp_mux_table = { 5, 9, },
791
704
.pp_count = 2,
792
705
.pp_chg_id = INT_MIN, },
···
794
707
{ .n = "pdmc1_gclk",
795
708
.id = 69,
796
709
.r = { .max = 50000000, },
797
-
.pp = { "syspll_divpmcck", "audiopll_divpmcck", },
710
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
798
711
.pp_mux_table = { 5, 9, },
799
712
.pp_count = 2,
800
713
.pp_chg_id = INT_MIN, },
···
802
715
{ .n = "pit64b0_gclk",
803
716
.id = 70,
804
717
.r = { .max = 200000000 },
805
-
.pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
806
-
"audiopll_divpmcck", "ethpll_divpmcck", },
718
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
719
+
PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
720
+
PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
807
721
.pp_mux_table = { 5, 7, 8, 9, 10, },
808
722
.pp_count = 5,
809
723
.pp_chg_id = INT_MIN, },
···
812
724
{ .n = "pit64b1_gclk",
813
725
.id = 71,
814
726
.r = { .max = 200000000 },
815
-
.pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
816
-
"audiopll_divpmcck", "ethpll_divpmcck", },
727
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
728
+
PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
729
+
PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
817
730
.pp_mux_table = { 5, 7, 8, 9, 10, },
818
731
.pp_count = 5,
819
732
.pp_chg_id = INT_MIN, },
···
822
733
{ .n = "pit64b2_gclk",
823
734
.id = 72,
824
735
.r = { .max = 200000000 },
825
-
.pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
826
-
"audiopll_divpmcck", "ethpll_divpmcck", },
736
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
737
+
PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
738
+
PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
827
739
.pp_mux_table = { 5, 7, 8, 9, 10, },
828
740
.pp_count = 5,
829
741
.pp_chg_id = INT_MIN, },
···
832
742
{ .n = "pit64b3_gclk",
833
743
.id = 73,
834
744
.r = { .max = 200000000 },
835
-
.pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
836
-
"audiopll_divpmcck", "ethpll_divpmcck", },
745
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
746
+
PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
747
+
PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
837
748
.pp_mux_table = { 5, 7, 8, 9, 10, },
838
749
.pp_count = 5,
839
750
.pp_chg_id = INT_MIN, },
···
842
751
{ .n = "pit64b4_gclk",
843
752
.id = 74,
844
753
.r = { .max = 200000000 },
845
-
.pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
846
-
"audiopll_divpmcck", "ethpll_divpmcck", },
754
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
755
+
PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
756
+
PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
847
757
.pp_mux_table = { 5, 7, 8, 9, 10, },
848
758
.pp_count = 5,
849
759
.pp_chg_id = INT_MIN, },
···
852
760
{ .n = "pit64b5_gclk",
853
761
.id = 75,
854
762
.r = { .max = 200000000 },
855
-
.pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
856
-
"audiopll_divpmcck", "ethpll_divpmcck", },
763
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
764
+
PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
765
+
PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
857
766
.pp_mux_table = { 5, 7, 8, 9, 10, },
858
767
.pp_count = 5,
859
768
.pp_chg_id = INT_MIN, },
···
862
769
{ .n = "qspi0_gclk",
863
770
.id = 78,
864
771
.r = { .max = 200000000 },
865
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
772
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
866
773
.pp_mux_table = { 5, 8, },
867
774
.pp_count = 2,
868
775
.pp_chg_id = INT_MIN, },
···
870
777
{ .n = "qspi1_gclk",
871
778
.id = 79,
872
779
.r = { .max = 200000000 },
873
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
780
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
874
781
.pp_mux_table = { 5, 8, },
875
782
.pp_count = 2,
876
783
.pp_chg_id = INT_MIN, },
···
878
785
{ .n = "sdmmc0_gclk",
879
786
.id = 80,
880
787
.r = { .max = 208000000 },
881
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
788
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
882
789
.pp_mux_table = { 5, 8, },
883
790
.pp_count = 2,
884
791
.pp_chg_id = 4, },
···
886
793
{ .n = "sdmmc1_gclk",
887
794
.id = 81,
888
795
.r = { .max = 208000000 },
889
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
796
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
890
797
.pp_mux_table = { 5, 8, },
891
798
.pp_count = 2,
892
799
.pp_chg_id = 4, },
···
894
801
{ .n = "sdmmc2_gclk",
895
802
.id = 82,
896
803
.r = { .max = 208000000 },
897
-
.pp = { "syspll_divpmcck", "baudpll_divpmcck", },
804
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), },
898
805
.pp_mux_table = { 5, 8, },
899
806
.pp_count = 2,
900
807
.pp_chg_id = 4, },
···
902
809
{ .n = "spdifrx_gclk",
903
810
.id = 84,
904
811
.r = { .max = 150000000 },
905
-
.pp = { "syspll_divpmcck", "audiopll_divpmcck", },
812
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
906
813
.pp_mux_table = { 5, 9, },
907
814
.pp_count = 2,
908
815
.pp_chg_id = 4, },
···
910
817
{ .n = "spdiftx_gclk",
911
818
.id = 85,
912
819
.r = { .max = 25000000 },
913
-
.pp = { "syspll_divpmcck", "audiopll_divpmcck", },
820
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), },
914
821
.pp_mux_table = { 5, 9, },
915
822
.pp_count = 2,
916
823
.pp_chg_id = 4, },
···
918
825
{ .n = "tcb0_ch0_gclk",
919
826
.id = 88,
920
827
.r = { .max = 200000000 },
921
-
.pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
922
-
"audiopll_divpmcck", "ethpll_divpmcck", },
828
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
829
+
PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
830
+
PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
923
831
.pp_mux_table = { 5, 7, 8, 9, 10, },
924
832
.pp_count = 5,
925
833
.pp_chg_id = INT_MIN, },
···
928
834
{ .n = "tcb1_ch0_gclk",
929
835
.id = 91,
930
836
.r = { .max = 200000000 },
931
-
.pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
932
-
"audiopll_divpmcck", "ethpll_divpmcck", },
837
+
.pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0),
838
+
PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0),
839
+
PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), },
933
840
.pp_mux_table = { 5, 7, 8, 9, 10, },
934
841
.pp_count = 5,
935
842
.pp_chg_id = INT_MIN, },
···
979
884
980
885
static void __init sama7g5_pmc_setup(struct device_node *np)
981
886
{
982
-
const char *td_slck_name, *md_slck_name, *mainxtal_name;
887
+
const char *main_xtal_name = "main_xtal";
983
888
struct pmc_data *sama7g5_pmc;
984
-
const char *parent_names[10];
985
889
void **alloc_mem = NULL;
986
890
int alloc_mem_size = 0;
987
891
struct regmap *regmap;
988
-
struct clk_hw *hw;
892
+
struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw;
893
+
struct clk_hw *td_slck_hw, *md_slck_hw;
894
+
static struct clk_parent_data parent_data;
895
+
struct clk_hw *parent_hws[10];
989
896
bool bypass;
990
897
int i, j;
991
898
992
-
i = of_property_match_string(np, "clock-names", "td_slck");
993
-
if (i < 0)
899
+
td_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "td_slck"));
900
+
md_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "md_slck"));
901
+
main_xtal_hw = __clk_get_hw(of_clk_get_by_name(np, main_xtal_name));
902
+
903
+
if (!td_slck_hw || !md_slck_hw || !main_xtal_hw)
994
904
return;
995
-
996
-
td_slck_name = of_clk_get_parent_name(np, i);
997
-
998
-
i = of_property_match_string(np, "clock-names", "md_slck");
999
-
if (i < 0)
1000
-
return;
1001
-
1002
-
md_slck_name = of_clk_get_parent_name(np, i);
1003
-
1004
-
i = of_property_match_string(np, "clock-names", "main_xtal");
1005
-
if (i < 0)
1006
-
return;
1007
-
1008
-
mainxtal_name = of_clk_get_parent_name(np, i);
1009
905
1010
906
regmap = device_node_to_regmap(np);
1011
907
if (IS_ERR(regmap))
···
1015
929
if (!alloc_mem)
1016
930
goto err_free;
1017
931
1018
-
hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
1019
-
50000000);
1020
-
if (IS_ERR(hw))
932
+
main_rc_hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
933
+
50000000);
934
+
if (IS_ERR(main_rc_hw))
1021
935
goto err_free;
1022
936
1023
937
bypass = of_property_read_bool(np, "atmel,osc-bypass");
1024
938
1025
-
hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
1026
-
bypass);
1027
-
if (IS_ERR(hw))
939
+
parent_data.name = main_xtal_name;
940
+
parent_data.fw_name = main_xtal_name;
941
+
main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL,
942
+
&parent_data, bypass);
943
+
if (IS_ERR(main_osc_hw))
1028
944
goto err_free;
1029
945
1030
-
parent_names[0] = "main_rc_osc";
1031
-
parent_names[1] = "main_osc";
1032
-
hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
946
+
parent_hws[0] = main_rc_hw;
947
+
parent_hws[1] = main_osc_hw;
948
+
hw = at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, 2);
1033
949
if (IS_ERR(hw))
1034
950
goto err_free;
1035
951
···
1046
958
1047
959
switch (sama7g5_plls[i][j].t) {
1048
960
case PLL_TYPE_FRAC:
1049
-
if (!strcmp(sama7g5_plls[i][j].p, "mainck"))
961
+
switch (sama7g5_plls[i][j].p) {
962
+
case SAMA7G5_PLL_PARENT_MAINCK:
1050
963
parent_hw = sama7g5_pmc->chws[PMC_MAIN];
1051
-
else
1052
-
parent_hw = __clk_get_hw(of_clk_get_by_name(np,
1053
-
sama7g5_plls[i][j].p));
964
+
break;
965
+
case SAMA7G5_PLL_PARENT_MAIN_XTAL:
966
+
parent_hw = main_xtal_hw;
967
+
break;
968
+
default:
969
+
/* Should not happen. */
970
+
parent_hw = NULL;
971
+
break;
972
+
}
1054
973
1055
974
hw = sam9x60_clk_register_frac_pll(regmap,
1056
975
&pmc_pll_lock, sama7g5_plls[i][j].n,
1057
-
sama7g5_plls[i][j].p, parent_hw, i,
976
+
NULL, parent_hw, i,
1058
977
sama7g5_plls[i][j].c,
1059
978
sama7g5_plls[i][j].l,
1060
979
sama7g5_plls[i][j].f);
···
1070
975
case PLL_TYPE_DIV:
1071
976
hw = sam9x60_clk_register_div_pll(regmap,
1072
977
&pmc_pll_lock, sama7g5_plls[i][j].n,
1073
-
sama7g5_plls[i][j].p, i,
978
+
NULL, sama7g5_plls[i][0].hw, i,
1074
979
sama7g5_plls[i][j].c,
1075
980
sama7g5_plls[i][j].l,
1076
981
sama7g5_plls[i][j].f,
···
1084
989
if (IS_ERR(hw))
1085
990
goto err_free;
1086
991
992
+
sama7g5_plls[i][j].hw = hw;
1087
993
if (sama7g5_plls[i][j].eid)
1088
994
sama7g5_pmc->chws[sama7g5_plls[i][j].eid] = hw;
1089
995
}
1090
996
}
1091
997
1092
-
parent_names[0] = "cpupll_divpmcck";
1093
-
hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck",
998
+
hw = at91_clk_register_master_div(regmap, "mck0", NULL,
999
+
sama7g5_plls[PLL_ID_CPU][1].hw,
1094
1000
&mck0_layout, &mck0_characteristics,
1095
1001
&pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);
1096
1002
if (IS_ERR(hw))
1097
1003
goto err_free;
1098
1004
1099
-
sama7g5_pmc->chws[PMC_MCK] = hw;
1005
+
sama7g5_mckx[PCK_PARENT_HW_MCK0].hw = sama7g5_pmc->chws[PMC_MCK] = hw;
1100
1006
1101
-
parent_names[0] = md_slck_name;
1102
-
parent_names[1] = td_slck_name;
1103
-
parent_names[2] = "mainck";
1104
-
for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) {
1007
+
parent_hws[0] = md_slck_hw;
1008
+
parent_hws[1] = td_slck_hw;
1009
+
parent_hws[2] = sama7g5_pmc->chws[PMC_MAIN];
1010
+
for (i = PCK_PARENT_HW_MCK1; i < ARRAY_SIZE(sama7g5_mckx); i++) {
1105
1011
u8 num_parents = 3 + sama7g5_mckx[i].ep_count;
1012
+
struct clk_hw *tmp_parent_hws[8];
1106
1013
u32 *mux_table;
1107
1014
1108
1015
mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
···
1115
1018
SAMA7G5_INIT_TABLE(mux_table, 3);
1116
1019
SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,
1117
1020
sama7g5_mckx[i].ep_count);
1118
-
SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep,
1021
+
for (j = 0; j < sama7g5_mckx[i].ep_count; j++) {
1022
+
u8 pll_id = sama7g5_mckx[i].ep[j].pll_id;
1023
+
u8 pll_compid = sama7g5_mckx[i].ep[j].pll_compid;
1024
+
1025
+
tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw;
1026
+
}
1027
+
SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
1119
1028
sama7g5_mckx[i].ep_count);
1120
1029
1121
1030
hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n,
1122
-
num_parents, parent_names, mux_table,
1031
+
num_parents, NULL, parent_hws, mux_table,
1123
1032
&pmc_mckX_lock, sama7g5_mckx[i].id,
1124
1033
sama7g5_mckx[i].c,
1125
1034
sama7g5_mckx[i].ep_chg_id);
···
1134
1031
1135
1032
alloc_mem[alloc_mem_size++] = mux_table;
1136
1033
1034
+
sama7g5_mckx[i].hw = hw;
1137
1035
if (sama7g5_mckx[i].eid)
1138
1036
sama7g5_pmc->chws[sama7g5_mckx[i].eid] = hw;
1139
1037
}
1140
1038
1141
-
hw = at91_clk_sama7g5_register_utmi(regmap, "utmick", "main_xtal");
1039
+
hw = at91_clk_sama7g5_register_utmi(regmap, "utmick", NULL, main_xtal_hw);
1142
1040
if (IS_ERR(hw))
1143
1041
goto err_free;
1144
1042
1145
1043
sama7g5_pmc->chws[PMC_UTMI] = hw;
1146
1044
1147
-
parent_names[0] = md_slck_name;
1148
-
parent_names[1] = td_slck_name;
1149
-
parent_names[2] = "mainck";
1150
-
parent_names[3] = "syspll_divpmcck";
1151
-
parent_names[4] = "ddrpll_divpmcck";
1152
-
parent_names[5] = "imgpll_divpmcck";
1153
-
parent_names[6] = "baudpll_divpmcck";
1154
-
parent_names[7] = "audiopll_divpmcck";
1155
-
parent_names[8] = "ethpll_divpmcck";
1045
+
parent_hws[0] = md_slck_hw;
1046
+
parent_hws[1] = td_slck_hw;
1047
+
parent_hws[2] = sama7g5_pmc->chws[PMC_MAIN];
1048
+
parent_hws[3] = sama7g5_plls[PLL_ID_SYS][PLL_COMPID_DIV0].hw;
1049
+
parent_hws[4] = sama7g5_plls[PLL_ID_DDR][PLL_COMPID_DIV0].hw;
1050
+
parent_hws[5] = sama7g5_plls[PLL_ID_IMG][PLL_COMPID_DIV0].hw;
1051
+
parent_hws[6] = sama7g5_plls[PLL_ID_BAUD][PLL_COMPID_DIV0].hw;
1052
+
parent_hws[7] = sama7g5_plls[PLL_ID_AUDIO][PLL_COMPID_DIV0].hw;
1053
+
parent_hws[8] = sama7g5_plls[PLL_ID_ETH][PLL_COMPID_DIV0].hw;
1156
1054
for (i = 0; i < 8; i++) {
1157
1055
char name[6];
1158
1056
1159
1057
snprintf(name, sizeof(name), "prog%d", i);
1160
1058
1161
-
hw = at91_clk_register_programmable(regmap, name, parent_names,
1059
+
hw = at91_clk_register_programmable(regmap, name, NULL, parent_hws,
1162
1060
9, i,
1163
1061
&programmable_layout,
1164
1062
sama7g5_prog_mux_table);
···
1171
1067
1172
1068
for (i = 0; i < ARRAY_SIZE(sama7g5_systemck); i++) {
1173
1069
hw = at91_clk_register_system(regmap, sama7g5_systemck[i].n,
1174
-
sama7g5_systemck[i].p,
1070
+
NULL, sama7g5_pmc->pchws[i],
1175
1071
sama7g5_systemck[i].id, 0);
1176
1072
if (IS_ERR(hw))
1177
1073
goto err_free;
···
1183
1079
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
1184
1080
&sama7g5_pcr_layout,
1185
1081
sama7g5_periphck[i].n,
1186
-
sama7g5_periphck[i].p,
1082
+
NULL,
1083
+
sama7g5_mckx[sama7g5_periphck[i].p].hw,
1187
1084
sama7g5_periphck[i].id,
1188
1085
&sama7g5_periphck[i].r,
1189
1086
sama7g5_periphck[i].chgp ? 0 :
···
1195
1090
sama7g5_pmc->phws[sama7g5_periphck[i].id] = hw;
1196
1091
}
1197
1092
1198
-
parent_names[0] = md_slck_name;
1199
-
parent_names[1] = td_slck_name;
1200
-
parent_names[2] = "mainck";
1093
+
parent_hws[0] = md_slck_hw;
1094
+
parent_hws[1] = td_slck_hw;
1095
+
parent_hws[2] = sama7g5_pmc->chws[PMC_MAIN];
1201
1096
for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) {
1202
1097
u8 num_parents = 3 + sama7g5_gck[i].pp_count;
1098
+
struct clk_hw *tmp_parent_hws[8];
1203
1099
u32 *mux_table;
1204
1100
1205
1101
mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
···
1211
1105
SAMA7G5_INIT_TABLE(mux_table, 3);
1212
1106
SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,
1213
1107
sama7g5_gck[i].pp_count);
1214
-
SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp,
1108
+
for (j = 0; j < sama7g5_gck[i].pp_count; j++) {
1109
+
u8 pll_id = sama7g5_gck[i].pp[j].pll_id;
1110
+
u8 pll_compid = sama7g5_gck[i].pp[j].pll_compid;
1111
+
1112
+
tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw;
1113
+
}
1114
+
SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
1215
1115
sama7g5_gck[i].pp_count);
1216
1116
1217
1117
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
1218
1118
&sama7g5_pcr_layout,
1219
-
sama7g5_gck[i].n,
1220
-
parent_names, mux_table,
1119
+
sama7g5_gck[i].n, NULL,
1120
+
parent_hws, mux_table,
1221
1121
num_parents,
1222
1122
sama7g5_gck[i].id,
1223
1123
&sama7g5_gck[i].r,
+48
-27
drivers/clk/at91/sckc.c
+48
-27
drivers/clk/at91/sckc.c
···
117
117
static struct clk_hw * __init
118
118
at91_clk_register_slow_osc(void __iomem *sckcr,
119
119
const char *name,
120
-
const char *parent_name,
120
+
const struct clk_parent_data *parent_data,
121
121
unsigned long startup,
122
122
bool bypass,
123
123
const struct clk_slow_bits *bits)
124
124
{
125
125
struct clk_slow_osc *osc;
126
126
struct clk_hw *hw;
127
-
struct clk_init_data init;
127
+
struct clk_init_data init = {};
128
128
int ret;
129
129
130
-
if (!sckcr || !name || !parent_name)
130
+
if (!sckcr || !name || !parent_data)
131
131
return ERR_PTR(-EINVAL);
132
132
133
133
osc = kzalloc(sizeof(*osc), GFP_KERNEL);
···
136
136
137
137
init.name = name;
138
138
init.ops = &slow_osc_ops;
139
-
init.parent_names = &parent_name;
139
+
init.parent_data = parent_data;
140
140
init.num_parents = 1;
141
141
init.flags = CLK_IGNORE_UNUSED;
142
142
···
318
318
static struct clk_hw * __init
319
319
at91_clk_register_sam9x5_slow(void __iomem *sckcr,
320
320
const char *name,
321
-
const char **parent_names,
321
+
const struct clk_hw **parent_hws,
322
322
int num_parents,
323
323
const struct clk_slow_bits *bits)
324
324
{
325
325
struct clk_sam9x5_slow *slowck;
326
326
struct clk_hw *hw;
327
-
struct clk_init_data init;
327
+
struct clk_init_data init = {};
328
328
int ret;
329
329
330
-
if (!sckcr || !name || !parent_names || !num_parents)
330
+
if (!sckcr || !name || !parent_hws || !num_parents)
331
331
return ERR_PTR(-EINVAL);
332
332
333
333
slowck = kzalloc(sizeof(*slowck), GFP_KERNEL);
···
336
336
337
337
init.name = name;
338
338
init.ops = &sam9x5_slow_ops;
339
-
init.parent_names = parent_names;
339
+
init.parent_hws = parent_hws;
340
340
init.num_parents = num_parents;
341
341
init.flags = 0;
342
342
···
367
367
unsigned int rc_osc_startup_us,
368
368
const struct clk_slow_bits *bits)
369
369
{
370
-
const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
371
370
void __iomem *regbase = of_iomap(np, 0);
372
371
struct device_node *child = NULL;
373
372
const char *xtal_name;
374
373
struct clk_hw *slow_rc, *slow_osc, *slowck;
374
+
static struct clk_parent_data parent_data = {
375
+
.name = "slow_xtal",
376
+
};
377
+
const struct clk_hw *parent_hws[2];
375
378
bool bypass;
376
379
int ret;
377
380
378
381
if (!regbase)
379
382
return;
380
383
381
-
slow_rc = at91_clk_register_slow_rc_osc(regbase, parent_names[0],
384
+
slow_rc = at91_clk_register_slow_rc_osc(regbase, "slow_rc_osc",
382
385
32768, 50000000,
383
386
rc_osc_startup_us, bits);
384
387
if (IS_ERR(slow_rc))
···
405
402
if (!xtal_name)
406
403
goto unregister_slow_rc;
407
404
408
-
slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
409
-
xtal_name, 1200000, bypass, bits);
405
+
parent_data.fw_name = xtal_name;
406
+
407
+
slow_osc = at91_clk_register_slow_osc(regbase, "slow_osc",
408
+
&parent_data, 1200000, bypass, bits);
410
409
if (IS_ERR(slow_osc))
411
410
goto unregister_slow_rc;
412
411
413
-
slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names,
412
+
parent_hws[0] = slow_rc;
413
+
parent_hws[1] = slow_osc;
414
+
slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_hws,
414
415
2, bits);
415
416
if (IS_ERR(slowck))
416
417
goto unregister_slow_osc;
···
472
465
struct clk_hw_onecell_data *clk_data;
473
466
struct clk_hw *slow_rc, *slow_osc;
474
467
const char *xtal_name;
475
-
const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
468
+
const struct clk_hw *parent_hws[2];
469
+
static struct clk_parent_data parent_data = {
470
+
.name = "slow_xtal",
471
+
};
476
472
bool bypass;
477
473
int ret;
478
474
479
475
if (!regbase)
480
476
return;
481
477
482
-
slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL, parent_names[0],
478
+
slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL, "slow_rc_osc",
483
479
NULL, 0, 32768,
484
480
93750000);
485
481
if (IS_ERR(slow_rc))
···
492
482
if (!xtal_name)
493
483
goto unregister_slow_rc;
494
484
485
+
parent_data.fw_name = xtal_name;
495
486
bypass = of_property_read_bool(np, "atmel,osc-bypass");
496
-
slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
497
-
xtal_name, 5000000, bypass,
487
+
slow_osc = at91_clk_register_slow_osc(regbase, "slow_osc",
488
+
&parent_data, 5000000, bypass,
498
489
&at91sam9x60_bits);
499
490
if (IS_ERR(slow_osc))
500
491
goto unregister_slow_rc;
···
506
495
507
496
/* MD_SLCK and TD_SLCK. */
508
497
clk_data->num = 2;
509
-
clk_data->hws[0] = clk_hw_register_fixed_rate(NULL, "md_slck",
510
-
parent_names[0],
511
-
0, 32768);
498
+
clk_data->hws[0] = clk_hw_register_fixed_rate_parent_hw(NULL, "md_slck",
499
+
slow_rc,
500
+
0, 32768);
512
501
if (IS_ERR(clk_data->hws[0]))
513
502
goto clk_data_free;
514
503
504
+
parent_hws[0] = slow_rc;
505
+
parent_hws[1] = slow_osc;
515
506
clk_data->hws[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck",
516
-
parent_names, 2,
507
+
parent_hws, 2,
517
508
&at91sam9x60_bits);
518
509
if (IS_ERR(clk_data->hws[1]))
519
510
goto unregister_md_slck;
···
586
573
void __iomem *regbase = of_iomap(np, 0);
587
574
struct clk_hw *slow_rc, *slowck;
588
575
struct clk_sama5d4_slow_osc *osc;
589
-
struct clk_init_data init;
576
+
struct clk_init_data init = {};
590
577
const char *xtal_name;
591
-
const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
578
+
const struct clk_hw *parent_hws[2];
579
+
static struct clk_parent_data parent_data = {
580
+
.name = "slow_xtal",
581
+
};
592
582
int ret;
593
583
594
584
if (!regbase)
595
585
return;
596
586
597
587
slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL,
598
-
parent_names[0],
588
+
"slow_rc_osc",
599
589
NULL, 0, 32768,
600
590
250000000);
601
591
if (IS_ERR(slow_rc))
602
592
return;
603
593
604
594
xtal_name = of_clk_get_parent_name(np, 0);
595
+
if (!xtal_name)
596
+
goto unregister_slow_rc;
597
+
parent_data.fw_name = xtal_name;
605
598
606
599
osc = kzalloc(sizeof(*osc), GFP_KERNEL);
607
600
if (!osc)
608
601
goto unregister_slow_rc;
609
602
610
-
init.name = parent_names[1];
603
+
init.name = "slow_osc";
611
604
init.ops = &sama5d4_slow_osc_ops;
612
-
init.parent_names = &xtal_name;
605
+
init.parent_data = &parent_data;
613
606
init.num_parents = 1;
614
607
init.flags = CLK_IGNORE_UNUSED;
615
608
···
628
609
if (ret)
629
610
goto free_slow_osc_data;
630
611
612
+
parent_hws[0] = slow_rc;
613
+
parent_hws[1] = &osc->hw;
631
614
slowck = at91_clk_register_sam9x5_slow(regbase, "slowck",
632
-
parent_names, 2,
615
+
parent_hws, 2,
633
616
&at91sama5d4_bits);
634
617
if (IS_ERR(slowck))
635
618
goto unregister_slow_osc;
+132
drivers/clk/qcom/Kconfig
+132
drivers/clk/qcom/Kconfig
···
57
57
config QCOM_CLK_APCS_SDX55
58
58
tristate "SDX55 and SDX65 APCS Clock Controller"
59
59
depends on QCOM_APCS_IPC || COMPILE_TEST
60
+
depends on ARM || COMPILE_TEST
60
61
help
61
62
Support for the APCS Clock Controller on SDX55, SDX65 platforms. The
62
63
APCS is managing the mux and divider which feeds the CPUs.
···
101
100
102
101
config APQ_GCC_8084
103
102
tristate "APQ8084 Global Clock Controller"
103
+
depends on ARM || COMPILE_TEST
104
104
select QCOM_GDSC
105
105
help
106
106
Support for the global clock controller on apq8084 devices.
···
110
108
111
109
config APQ_MMCC_8084
112
110
tristate "APQ8084 Multimedia Clock Controller"
111
+
depends on ARM || COMPILE_TEST
113
112
select APQ_GCC_8084
114
113
select QCOM_GDSC
115
114
help
···
162
159
163
160
config IPQ_GCC_806X
164
161
tristate "IPQ806x Global Clock Controller"
162
+
depends on ARM || COMPILE_TEST
165
163
help
166
164
Support for the global clock controller on ipq806x devices.
167
165
Say Y if you want to use peripheral devices such as UART, SPI,
···
170
166
171
167
config IPQ_LCC_806X
172
168
tristate "IPQ806x LPASS Clock Controller"
169
+
depends on ARM || COMPILE_TEST
173
170
select IPQ_GCC_806X
174
171
help
175
172
Support for the LPASS clock controller on ipq806x devices.
···
196
191
197
192
config MSM_GCC_8660
198
193
tristate "MSM8660 Global Clock Controller"
194
+
depends on ARM || COMPILE_TEST
199
195
help
200
196
Support for the global clock controller on msm8660 devices.
201
197
Say Y if you want to use peripheral devices such as UART, SPI,
···
204
198
205
199
config MSM_GCC_8909
206
200
tristate "MSM8909 Global Clock Controller"
201
+
depends on ARM || COMPILE_TEST
207
202
select QCOM_GDSC
208
203
help
209
204
Support for the global clock controller on msm8909 devices.
···
239
232
240
233
config MSM_GCC_8960
241
234
tristate "APQ8064/MSM8960 Global Clock Controller"
235
+
depends on ARM || COMPILE_TEST
242
236
help
243
237
Support for the global clock controller on apq8064/msm8960 devices.
244
238
Say Y if you want to use peripheral devices such as UART, SPI,
···
247
239
248
240
config MSM_LCC_8960
249
241
tristate "APQ8064/MSM8960 LPASS Clock Controller"
242
+
depends on ARM || COMPILE_TEST
250
243
select MSM_GCC_8960
251
244
help
252
245
Support for the LPASS clock controller on apq8064/msm8960 devices.
···
256
247
257
248
config MDM_GCC_9607
258
249
tristate "MDM9607 Global Clock Controller"
250
+
depends on ARM || COMPILE_TEST
259
251
help
260
252
Support for the global clock controller on mdm9607 devices.
261
253
Say Y if you want to use peripheral devices such as UART, SPI,
···
264
254
265
255
config MDM_GCC_9615
266
256
tristate "MDM9615 Global Clock Controller"
257
+
depends on ARM || COMPILE_TEST
267
258
help
268
259
Support for the global clock controller on mdm9615 devices.
269
260
Say Y if you want to use peripheral devices such as UART, SPI,
···
272
261
273
262
config MDM_LCC_9615
274
263
tristate "MDM9615 LPASS Clock Controller"
264
+
depends on ARM || COMPILE_TEST
275
265
select MDM_GCC_9615
276
266
help
277
267
Support for the LPASS clock controller on mdm9615 devices.
···
281
269
282
270
config MSM_MMCC_8960
283
271
tristate "MSM8960 Multimedia Clock Controller"
272
+
depends on ARM || COMPILE_TEST
284
273
select MSM_GCC_8960
285
274
help
286
275
Support for the multimedia clock controller on msm8960 devices.
···
298
285
299
286
config MSM_GCC_8974
300
287
tristate "MSM8974 Global Clock Controller"
288
+
depends on ARM || COMPILE_TEST
301
289
select QCOM_GDSC
302
290
help
303
291
Support for the global clock controller on msm8974 devices.
···
307
293
308
294
config MSM_MMCC_8974
309
295
tristate "MSM8974 Multimedia Clock Controller"
296
+
depends on ARM || COMPILE_TEST
310
297
select MSM_GCC_8974
311
298
select QCOM_GDSC
312
299
help
···
408
393
409
394
config SC_CAMCC_7180
410
395
tristate "SC7180 Camera Clock Controller"
396
+
depends on ARM64 || COMPILE_TEST
411
397
select SC_GCC_7180
412
398
help
413
399
Support for the camera clock controller on Qualcomm Technologies, Inc
···
418
402
419
403
config SC_CAMCC_7280
420
404
tristate "SC7280 Camera Clock Controller"
405
+
depends on ARM64 || COMPILE_TEST
421
406
select SC_GCC_7280
422
407
help
423
408
Support for the camera clock controller on Qualcomm Technologies, Inc
···
428
411
429
412
config SC_DISPCC_7180
430
413
tristate "SC7180 Display Clock Controller"
414
+
depends on ARM64 || COMPILE_TEST
431
415
select SC_GCC_7180
432
416
help
433
417
Support for the display clock controller on Qualcomm Technologies, Inc
···
438
420
439
421
config SC_DISPCC_7280
440
422
tristate "SC7280 Display Clock Controller"
423
+
depends on ARM64 || COMPILE_TEST
441
424
select SC_GCC_7280
442
425
help
443
426
Support for the display clock controller on Qualcomm Technologies, Inc.
···
448
429
449
430
config SC_DISPCC_8280XP
450
431
tristate "SC8280XP Display Clock Controller"
432
+
depends on ARM64 || COMPILE_TEST
451
433
select SC_GCC_8280XP
452
434
help
453
435
Support for the two display clock controllers on Qualcomm
···
478
458
tristate "SC7180 Global Clock Controller"
479
459
select QCOM_GDSC
480
460
depends on COMMON_CLK_QCOM
461
+
depends on ARM64 || COMPILE_TEST
481
462
help
482
463
Support for the global clock controller on SC7180 devices.
483
464
Say Y if you want to use peripheral devices such as UART, SPI,
···
488
467
tristate "SC7280 Global Clock Controller"
489
468
select QCOM_GDSC
490
469
depends on COMMON_CLK_QCOM
470
+
depends on ARM64 || COMPILE_TEST
491
471
help
492
472
Support for the global clock controller on SC7280 devices.
493
473
Say Y if you want to use peripheral devices such as UART, SPI,
···
498
476
tristate "SC8180X Global Clock Controller"
499
477
select QCOM_GDSC
500
478
depends on COMMON_CLK_QCOM
479
+
depends on ARM64 || COMPILE_TEST
501
480
help
502
481
Support for the global clock controller on SC8180X devices.
503
482
Say Y if you want to use peripheral devices such as UART, SPI,
···
508
485
tristate "SC8280XP Global Clock Controller"
509
486
select QCOM_GDSC
510
487
depends on COMMON_CLK_QCOM
488
+
depends on ARM64 || COMPILE_TEST
511
489
help
512
490
Support for the global clock controller on SC8280XP devices.
513
491
Say Y if you want to use peripheral devices such as UART, SPI,
···
516
492
517
493
config SC_GPUCC_7180
518
494
tristate "SC7180 Graphics Clock Controller"
495
+
depends on ARM64 || COMPILE_TEST
519
496
select SC_GCC_7180
520
497
help
521
498
Support for the graphics clock controller on SC7180 devices.
···
525
500
526
501
config SC_GPUCC_7280
527
502
tristate "SC7280 Graphics Clock Controller"
503
+
depends on ARM64 || COMPILE_TEST
528
504
select SC_GCC_7280
529
505
help
530
506
Support for the graphics clock controller on SC7280 devices.
···
534
508
535
509
config SC_GPUCC_8280XP
536
510
tristate "SC8280XP Graphics Clock Controller"
511
+
depends on ARM64 || COMPILE_TEST
537
512
select SC_GCC_8280XP
538
513
help
539
514
Support for the graphics clock controller on SC8280XP devices.
···
543
516
544
517
config SC_LPASSCC_7280
545
518
tristate "SC7280 Low Power Audio Subsystem (LPASS) Clock Controller"
519
+
depends on ARM64 || COMPILE_TEST
546
520
select SC_GCC_7280
547
521
help
548
522
Support for the LPASS clock controller on SC7280 devices.
549
523
Say Y if you want to use the LPASS branch clocks of the LPASS clock
550
524
controller to reset the LPASS subsystem.
551
525
526
+
config SC_LPASSCC_8280XP
527
+
tristate "SC8280 Low Power Audio Subsystem (LPASS) Clock Controller"
528
+
depends on ARM64 || COMPILE_TEST
529
+
select SC_GCC_8280XP
530
+
help
531
+
Support for the LPASS clock controller on SC8280XP devices.
532
+
Say Y if you want to use the LPASS branch clocks of the LPASS clock
533
+
controller to reset the LPASS subsystem.
534
+
552
535
config SC_LPASS_CORECC_7180
553
536
tristate "SC7180 LPASS Core Clock Controller"
537
+
depends on ARM64 || COMPILE_TEST
554
538
select SC_GCC_7180
555
539
help
556
540
Support for the LPASS(Low Power Audio Subsystem) core clock controller
···
571
533
572
534
config SC_LPASS_CORECC_7280
573
535
tristate "SC7280 LPASS Core & Audio Clock Controller"
536
+
depends on ARM64 || COMPILE_TEST
574
537
select SC_GCC_7280
575
538
select QCOM_GDSC
576
539
help
···
582
543
583
544
config SC_MSS_7180
584
545
tristate "SC7180 Modem Clock Controller"
546
+
depends on ARM64 || COMPILE_TEST
585
547
select SC_GCC_7180
586
548
help
587
549
Support for the Modem Subsystem clock controller on Qualcomm
···
592
552
593
553
config SC_VIDEOCC_7180
594
554
tristate "SC7180 Video Clock Controller"
555
+
depends on ARM64 || COMPILE_TEST
595
556
select SC_GCC_7180
596
557
help
597
558
Support for the video clock controller on SC7180 devices.
···
601
560
602
561
config SC_VIDEOCC_7280
603
562
tristate "SC7280 Video Clock Controller"
563
+
depends on ARM64 || COMPILE_TEST
604
564
select SC_GCC_7280
605
565
help
606
566
Support for the video clock controller on SC7280 devices.
···
610
568
611
569
config SDM_CAMCC_845
612
570
tristate "SDM845 Camera Clock Controller"
571
+
depends on ARM64 || COMPILE_TEST
613
572
select SDM_GCC_845
614
573
help
615
574
Support for the camera clock controller on SDM845 devices.
···
618
575
619
576
config SDM_GCC_660
620
577
tristate "SDM660 Global Clock Controller"
578
+
depends on ARM64 || COMPILE_TEST
621
579
select QCOM_GDSC
622
580
help
623
581
Support for the global clock controller on SDM660 devices.
···
627
583
628
584
config SDM_MMCC_660
629
585
tristate "SDM660 Multimedia Clock Controller"
586
+
depends on ARM64 || COMPILE_TEST
630
587
select SDM_GCC_660
631
588
select QCOM_GDSC
632
589
help
···
637
592
638
593
config SDM_GPUCC_660
639
594
tristate "SDM660 Graphics Clock Controller"
595
+
depends on ARM64 || COMPILE_TEST
640
596
select SDM_GCC_660
641
597
select QCOM_GDSC
642
598
help
···
669
623
670
624
config SDM_GCC_845
671
625
tristate "SDM845/SDM670 Global Clock Controller"
626
+
depends on ARM64 || COMPILE_TEST
672
627
select QCOM_GDSC
673
628
help
674
629
Support for the global clock controller on SDM845 and SDM670 devices.
···
678
631
679
632
config SDM_GPUCC_845
680
633
tristate "SDM845 Graphics Clock Controller"
634
+
depends on ARM64 || COMPILE_TEST
681
635
select SDM_GCC_845
682
636
help
683
637
Support for the graphics clock controller on SDM845 devices.
···
687
639
688
640
config SDM_VIDEOCC_845
689
641
tristate "SDM845 Video Clock Controller"
642
+
depends on ARM64 || COMPILE_TEST
690
643
select SDM_GCC_845
691
644
select QCOM_GDSC
692
645
help
···
697
648
698
649
config SDM_DISPCC_845
699
650
tristate "SDM845 Display Clock Controller"
651
+
depends on ARM64 || COMPILE_TEST
700
652
select SDM_GCC_845
701
653
help
702
654
Support for the display clock controller on Qualcomm Technologies, Inc
···
707
657
708
658
config SDM_LPASSCC_845
709
659
tristate "SDM845 Low Power Audio Subsystem (LPAAS) Clock Controller"
660
+
depends on ARM64 || COMPILE_TEST
710
661
select SDM_GCC_845
711
662
help
712
663
Support for the LPASS clock controller on SDM845 devices.
···
716
665
717
666
config SDX_GCC_55
718
667
tristate "SDX55 Global Clock Controller"
668
+
depends on ARM || COMPILE_TEST
719
669
select QCOM_GDSC
720
670
help
721
671
Support for the global clock controller on SDX55 devices.
···
725
673
726
674
config SDX_GCC_65
727
675
tristate "SDX65 Global Clock Controller"
676
+
depends on ARM || COMPILE_TEST
728
677
select QCOM_GDSC
729
678
help
730
679
Support for the global clock controller on SDX65 devices.
731
680
Say Y if you want to use peripheral devices such as UART,
732
681
SPI, I2C, USB, SD/UFS, PCIe etc.
733
682
683
+
config SDX_GCC_75
684
+
tristate "SDX75 Global Clock Controller"
685
+
select QCOM_GDSC
686
+
help
687
+
Support for the global clock controller on SDX75 devices.
688
+
Say Y if you want to use peripheral devices such as UART,
689
+
SPI, I2C, USB, SD/eMMC, PCIe etc.
690
+
734
691
config SM_CAMCC_6350
735
692
tristate "SM6350 Camera Clock Controller"
693
+
depends on ARM64 || COMPILE_TEST
736
694
select SM_GCC_6350
737
695
help
738
696
Support for the camera clock controller on SM6350 devices.
···
750
688
751
689
config SM_CAMCC_8250
752
690
tristate "SM8250 Camera Clock Controller"
691
+
depends on ARM64 || COMPILE_TEST
753
692
select SM_GCC_8250
754
693
help
755
694
Support for the camera clock controller on SM8250 devices.
···
758
695
759
696
config SM_CAMCC_8450
760
697
tristate "SM8450 Camera Clock Controller"
698
+
depends on ARM64 || COMPILE_TEST
761
699
select SM_GCC_8450
762
700
help
763
701
Support for the camera clock controller on SM8450 devices.
···
766
702
767
703
config SM_DISPCC_6115
768
704
tristate "SM6115 Display Clock Controller"
705
+
depends on ARM64 || COMPILE_TEST
769
706
depends on SM_GCC_6115
770
707
help
771
708
Support for the display clock controller on Qualcomm Technologies, Inc
···
776
711
777
712
config SM_DISPCC_6125
778
713
tristate "SM6125 Display Clock Controller"
714
+
depends on ARM64 || COMPILE_TEST
779
715
depends on SM_GCC_6125
780
716
help
781
717
Support for the display clock controller on Qualcomm Technologies, Inc
···
786
720
787
721
config SM_DISPCC_8250
788
722
tristate "SM8150/SM8250/SM8350 Display Clock Controller"
723
+
depends on ARM64 || COMPILE_TEST
789
724
depends on SM_GCC_8150 || SM_GCC_8250 || SM_GCC_8350
790
725
help
791
726
Support for the display clock controller on Qualcomm Technologies, Inc
···
796
729
797
730
config SM_DISPCC_6350
798
731
tristate "SM6350 Display Clock Controller"
732
+
depends on ARM64 || COMPILE_TEST
799
733
depends on SM_GCC_6350
800
734
help
801
735
Support for the display clock controller on Qualcomm Technologies, Inc
···
806
738
807
739
config SM_DISPCC_6375
808
740
tristate "SM6375 Display Clock Controller"
741
+
depends on ARM64 || COMPILE_TEST
809
742
depends on SM_GCC_6375
810
743
help
811
744
Support for the display clock controller on Qualcomm Technologies, Inc
···
816
747
817
748
config SM_DISPCC_8450
818
749
tristate "SM8450 Display Clock Controller"
750
+
depends on ARM64 || COMPILE_TEST
819
751
depends on SM_GCC_8450
820
752
help
821
753
Support for the display clock controller on Qualcomm Technologies, Inc
···
826
756
827
757
config SM_DISPCC_8550
828
758
tristate "SM8550 Display Clock Controller"
759
+
depends on ARM64 || COMPILE_TEST
829
760
depends on SM_GCC_8550
830
761
help
831
762
Support for the display clock controller on Qualcomm Technologies, Inc
···
836
765
837
766
config SM_GCC_6115
838
767
tristate "SM6115 and SM4250 Global Clock Controller"
768
+
depends on ARM64 || COMPILE_TEST
839
769
select QCOM_GDSC
840
770
help
841
771
Support for the global clock controller on SM6115 and SM4250 devices.
···
845
773
846
774
config SM_GCC_6125
847
775
tristate "SM6125 Global Clock Controller"
776
+
depends on ARM64 || COMPILE_TEST
848
777
help
849
778
Support for the global clock controller on SM6125 devices.
850
779
Say Y if you want to use peripheral devices such as UART,
···
853
780
854
781
config SM_GCC_6350
855
782
tristate "SM6350 Global Clock Controller"
783
+
depends on ARM64 || COMPILE_TEST
856
784
select QCOM_GDSC
857
785
help
858
786
Support for the global clock controller on SM6350 devices.
···
862
788
863
789
config SM_GCC_6375
864
790
tristate "SM6375 Global Clock Controller"
791
+
depends on ARM64 || COMPILE_TEST
865
792
select QCOM_GDSC
866
793
help
867
794
Support for the global clock controller on SM6375 devices.
···
879
804
880
805
config SM_GCC_8150
881
806
tristate "SM8150 Global Clock Controller"
807
+
depends on ARM64 || COMPILE_TEST
882
808
help
883
809
Support for the global clock controller on SM8150 devices.
884
810
Say Y if you want to use peripheral devices such as UART,
···
887
811
888
812
config SM_GCC_8250
889
813
tristate "SM8250 Global Clock Controller"
814
+
depends on ARM64 || COMPILE_TEST
890
815
select QCOM_GDSC
891
816
help
892
817
Support for the global clock controller on SM8250 devices.
···
896
819
897
820
config SM_GCC_8350
898
821
tristate "SM8350 Global Clock Controller"
822
+
depends on ARM64 || COMPILE_TEST
899
823
select QCOM_GDSC
900
824
help
901
825
Support for the global clock controller on SM8350 devices.
···
905
827
906
828
config SM_GCC_8450
907
829
tristate "SM8450 Global Clock Controller"
830
+
depends on ARM64 || COMPILE_TEST
908
831
select QCOM_GDSC
909
832
help
910
833
Support for the global clock controller on SM8450 devices.
···
914
835
915
836
config SM_GCC_8550
916
837
tristate "SM8550 Global Clock Controller"
838
+
depends on ARM64 || COMPILE_TEST
917
839
select QCOM_GDSC
918
840
help
919
841
Support for the global clock controller on SM8550 devices.
···
950
870
951
871
config SM_GPUCC_6350
952
872
tristate "SM6350 Graphics Clock Controller"
873
+
depends on ARM64 || COMPILE_TEST
953
874
select SM_GCC_6350
954
875
help
955
876
Support for the graphics clock controller on SM6350 devices.
···
959
878
960
879
config SM_GPUCC_8150
961
880
tristate "SM8150 Graphics Clock Controller"
881
+
depends on ARM64 || COMPILE_TEST
962
882
select SM_GCC_8150
963
883
help
964
884
Support for the graphics clock controller on SM8150 devices.
···
968
886
969
887
config SM_GPUCC_8250
970
888
tristate "SM8250 Graphics Clock Controller"
889
+
depends on ARM64 || COMPILE_TEST
971
890
select SM_GCC_8250
972
891
help
973
892
Support for the graphics clock controller on SM8250 devices.
···
977
894
978
895
config SM_GPUCC_8350
979
896
tristate "SM8350 Graphics Clock Controller"
897
+
depends on ARM64 || COMPILE_TEST
980
898
select SM_GCC_8350
981
899
help
982
900
Support for the graphics clock controller on SM8350 devices.
983
901
Say Y if you want to support graphics controller devices and
984
902
functionality such as 3D graphics.
985
903
904
+
config SM_GPUCC_8450
905
+
tristate "SM8450 Graphics Clock Controller"
906
+
select SM_GCC_8450
907
+
help
908
+
Support for the graphics clock controller on SM8450 devices.
909
+
Say Y if you want to support graphics controller devices and
910
+
functionality such as 3D graphics.
911
+
912
+
config SM_GPUCC_8550
913
+
tristate "SM8550 Graphics Clock Controller"
914
+
select SM_GCC_8550
915
+
help
916
+
Support for the graphics clock controller on SM8550 devices.
917
+
Say Y if you want to support graphics controller devices and
918
+
functionality such as 3D graphics.
919
+
986
920
config SM_TCSRCC_8550
987
921
tristate "SM8550 TCSR Clock Controller"
922
+
depends on ARM64 || COMPILE_TEST
988
923
select QCOM_GDSC
989
924
help
990
925
Support for the TCSR clock controller on SM8550 devices.
···
1010
909
1011
910
config SM_VIDEOCC_8150
1012
911
tristate "SM8150 Video Clock Controller"
912
+
depends on ARM64 || COMPILE_TEST
1013
913
select SM_GCC_8150
1014
914
select QCOM_GDSC
1015
915
help
···
1020
918
1021
919
config SM_VIDEOCC_8250
1022
920
tristate "SM8250 Video Clock Controller"
921
+
depends on ARM64 || COMPILE_TEST
1023
922
select SM_GCC_8250
1024
923
select QCOM_GDSC
1025
924
help
1026
925
Support for the video clock controller on SM8250 devices.
1027
926
Say Y if you want to support video devices and functionality such as
1028
927
video encode and decode.
928
+
929
+
config SM_VIDEOCC_8350
930
+
tristate "SM8350 Video Clock Controller"
931
+
select SM_GCC_8350
932
+
select QCOM_GDSC
933
+
help
934
+
Support for the video clock controller on SM8350 devices.
935
+
Say Y if you want to support video devices and functionality such as
936
+
video encode and decode.
937
+
938
+
config SM_VIDEOCC_8550
939
+
tristate "SM8550 Video Clock Controller"
940
+
select SM_GCC_8550
941
+
select QCOM_GDSC
942
+
help
943
+
Support for the video clock controller on Qualcomm Technologies, Inc.
944
+
SM8550 devices.
945
+
Say Y if you want to support video devices and functionality such as
946
+
video encode/decode.
1029
947
1030
948
config SPMI_PMIC_CLKDIV
1031
949
tristate "SPMI PMIC clkdiv Support"
···
1080
958
1081
959
config CLK_GFM_LPASS_SM8250
1082
960
tristate "SM8250 GFM LPASS Clocks"
961
+
depends on ARM64 || COMPILE_TEST
1083
962
help
1084
963
Support for the Glitch Free Mux (GFM) Low power audio
1085
964
subsystem (LPASS) clocks found on SM8250 SoCs.
1086
965
966
+
config SM_VIDEOCC_8450
967
+
tristate "SM8450 Video Clock Controller"
968
+
select SM_GCC_8450
969
+
select QCOM_GDSC
970
+
help
971
+
Support for the video clock controller on Qualcomm Technologies, Inc.
972
+
SM8450 devices.
973
+
Say Y if you want to support video devices and functionality such as
974
+
video encode/decode.
1087
975
endif
+7
drivers/clk/qcom/Makefile
+7
drivers/clk/qcom/Makefile
···
81
81
obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o
82
82
obj-$(CONFIG_SC_GPUCC_8280XP) += gpucc-sc8280xp.o
83
83
obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o
84
+
obj-$(CONFIG_SC_LPASSCC_8280XP) += lpasscc-sc8280xp.o
84
85
obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o
85
86
obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o
86
87
obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o
···
98
97
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
99
98
obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
100
99
obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
100
+
obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
101
101
obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
102
102
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
103
103
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
···
126
124
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
127
125
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
128
126
obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
127
+
obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
128
+
obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
129
129
obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
130
130
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
131
131
obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
132
+
obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o
133
+
obj-$(CONFIG_SM_VIDEOCC_8450) += videocc-sm8450.o
134
+
obj-$(CONFIG_SM_VIDEOCC_8550) += videocc-sm8550.o
132
135
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
133
136
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
134
137
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
+19
drivers/clk/qcom/apss-ipq-pll.c
+19
drivers/clk/qcom/apss-ipq-pll.c
···
111
111
.test_ctl_hi_val = 0x4000,
112
112
};
113
113
114
+
static const struct alpha_pll_config ipq9574_pll_config = {
115
+
.l = 0x3b,
116
+
.config_ctl_val = 0x200d4828,
117
+
.config_ctl_hi_val = 0x6,
118
+
.early_output_mask = BIT(3),
119
+
.aux2_output_mask = BIT(2),
120
+
.aux_output_mask = BIT(1),
121
+
.main_output_mask = BIT(0),
122
+
.test_ctl_val = 0x0,
123
+
.test_ctl_hi_val = 0x4000,
124
+
};
125
+
114
126
struct apss_pll_data {
115
127
int pll_type;
116
128
struct clk_alpha_pll *pll;
···
145
133
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
146
134
.pll = &ipq_pll_huayra,
147
135
.pll_config = &ipq6018_pll_config,
136
+
};
137
+
138
+
static struct apss_pll_data ipq9574_pll_data = {
139
+
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
140
+
.pll = &ipq_pll_huayra,
141
+
.pll_config = &ipq9574_pll_config,
148
142
};
149
143
150
144
static const struct regmap_config ipq_pll_regmap_config = {
···
198
180
{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
199
181
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
200
182
{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
183
+
{ .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
201
184
{ }
202
185
};
203
186
MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
+12
-7
drivers/clk/qcom/camcc-sc7180.c
+12
-7
drivers/clk/qcom/camcc-sc7180.c
···
1480
1480
},
1481
1481
};
1482
1482
1483
+
static struct gdsc titan_top_gdsc = {
1484
+
.gdscr = 0xb134,
1485
+
.pd = {
1486
+
.name = "titan_top_gdsc",
1487
+
},
1488
+
.pwrsts = PWRSTS_OFF_ON,
1489
+
};
1490
+
1483
1491
static struct gdsc bps_gdsc = {
1484
1492
.gdscr = 0x6004,
1485
1493
.pd = {
1486
1494
.name = "bps_gdsc",
1487
1495
},
1488
1496
.pwrsts = PWRSTS_OFF_ON,
1497
+
.parent = &titan_top_gdsc.pd,
1489
1498
.flags = HW_CTRL,
1490
1499
};
1491
1500
···
1504
1495
.name = "ife_0_gdsc",
1505
1496
},
1506
1497
.pwrsts = PWRSTS_OFF_ON,
1498
+
.parent = &titan_top_gdsc.pd,
1507
1499
};
1508
1500
1509
1501
static struct gdsc ife_1_gdsc = {
···
1513
1503
.name = "ife_1_gdsc",
1514
1504
},
1515
1505
.pwrsts = PWRSTS_OFF_ON,
1506
+
.parent = &titan_top_gdsc.pd,
1516
1507
};
1517
1508
1518
1509
static struct gdsc ipe_0_gdsc = {
···
1523
1512
},
1524
1513
.pwrsts = PWRSTS_OFF_ON,
1525
1514
.flags = HW_CTRL,
1515
+
.parent = &titan_top_gdsc.pd,
1526
1516
};
1527
1517
1528
-
static struct gdsc titan_top_gdsc = {
1529
-
.gdscr = 0xb134,
1530
-
.pd = {
1531
-
.name = "titan_top_gdsc",
1532
-
},
1533
-
.pwrsts = PWRSTS_OFF_ON,
1534
-
};
1535
1518
1536
1519
static struct clk_hw *cam_cc_sc7180_hws[] = {
1537
1520
[CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw,
+17
-4
drivers/clk/qcom/clk-alpha-pll.c
+17
-4
drivers/clk/qcom/clk-alpha-pll.c
···
55
55
#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
56
56
#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
57
57
#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
58
+
#define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
58
59
#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
59
60
#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
60
61
#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
···
384
383
385
384
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
386
385
387
-
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
388
-
config->test_ctl_val);
389
-
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
390
-
config->test_ctl_hi_val);
386
+
if (config->test_ctl_mask)
387
+
regmap_update_bits(regmap, PLL_TEST_CTL(pll),
388
+
config->test_ctl_mask,
389
+
config->test_ctl_val);
390
+
else
391
+
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
392
+
config->test_ctl_val);
393
+
394
+
if (config->test_ctl_hi_mask)
395
+
regmap_update_bits(regmap, PLL_TEST_CTL_U(pll),
396
+
config->test_ctl_hi_mask,
397
+
config->test_ctl_hi_val);
398
+
else
399
+
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
400
+
config->test_ctl_hi_val);
391
401
392
402
if (pll->flags & SUPPORTS_FSM_MODE)
393
403
qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
···
2108
2096
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2109
2097
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2110
2098
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2099
+
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2111
2100
2112
2101
/* Disable PLL output */
2113
2102
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
+3
drivers/clk/qcom/clk-alpha-pll.h
+3
drivers/clk/qcom/clk-alpha-pll.h
···
123
123
u32 user_ctl_hi_val;
124
124
u32 user_ctl_hi1_val;
125
125
u32 test_ctl_val;
126
+
u32 test_ctl_mask;
126
127
u32 test_ctl_hi_val;
128
+
u32 test_ctl_hi_mask;
127
129
u32 test_ctl_hi1_val;
130
+
u32 test_ctl_hi2_val;
128
131
u32 main_output_mask;
129
132
u32 aux_output_mask;
130
133
u32 aux2_output_mask;
+3
-3
drivers/clk/qcom/clk-branch.c
+3
-3
drivers/clk/qcom/clk-branch.c
···
43
43
{
44
44
u32 val;
45
45
u32 mask;
46
+
bool invert = (br->halt_check == BRANCH_HALT_ENABLE);
46
47
47
48
mask = CBCR_NOC_FSM_STATUS;
48
49
mask |= CBCR_CLK_OFF;
···
52
51
53
52
if (enabling) {
54
53
val &= mask;
55
-
return (val & CBCR_CLK_OFF) == 0 ||
54
+
return (val & CBCR_CLK_OFF) == (invert ? CBCR_CLK_OFF : 0) ||
56
55
FIELD_GET(CBCR_NOC_FSM_STATUS, val) == FSM_STATUS_ON;
57
-
} else {
58
-
return val & CBCR_CLK_OFF;
59
56
}
57
+
return (val & CBCR_CLK_OFF) == (invert ? 0 : CBCR_CLK_OFF);
60
58
}
61
59
62
60
static int clk_branch_wait(const struct clk_branch *br, bool enabling,
+2
drivers/clk/qcom/clk-rcg.h
+2
drivers/clk/qcom/clk-rcg.h
···
141
141
* @clkr: regmap clock handle
142
142
* @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
143
143
* @parked_cfg: cached value of the CFG register for parked RCGs
144
+
* @hw_clk_ctrl: whether to enable hardware clock control
144
145
*/
145
146
struct clk_rcg2 {
146
147
u32 cmd_rcgr;
···
153
152
struct clk_regmap clkr;
154
153
u8 cfg_off;
155
154
u32 parked_cfg;
155
+
bool hw_clk_ctrl;
156
156
};
157
157
158
158
#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
+2
drivers/clk/qcom/clk-rcg2.c
+2
drivers/clk/qcom/clk-rcg2.c
+19
drivers/clk/qcom/clk-rpmh.c
+19
drivers/clk/qcom/clk-rpmh.c
···
700
700
.num_clks = ARRAY_SIZE(qdu1000_rpmh_clocks),
701
701
};
702
702
703
+
static struct clk_hw *sdx75_rpmh_clocks[] = {
704
+
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
705
+
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
706
+
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
707
+
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
708
+
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
709
+
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
710
+
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
711
+
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
712
+
[RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
713
+
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
714
+
};
715
+
716
+
static const struct clk_rpmh_desc clk_rpmh_sdx75 = {
717
+
.clks = sdx75_rpmh_clocks,
718
+
.num_clks = ARRAY_SIZE(sdx75_rpmh_clocks),
719
+
};
720
+
703
721
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
704
722
void *data)
705
723
{
···
810
792
{ .compatible = "qcom,sdm670-rpmh-clk", .data = &clk_rpmh_sdm670},
811
793
{ .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
812
794
{ .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65},
795
+
{ .compatible = "qcom,sdx75-rpmh-clk", .data = &clk_rpmh_sdx75},
813
796
{ .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
814
797
{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
815
798
{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
+34
-24
drivers/clk/qcom/clk-smd-rpm.c
+34
-24
drivers/clk/qcom/clk-smd-rpm.c
···
67
67
type, r_id, key)
68
68
69
69
#define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\
70
-
type, r_id, r, key) \
70
+
type, r_id, r, key, ao_flags) \
71
71
static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \
72
72
static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \
73
73
.rpm_res_type = (type), \
···
102
102
.name = "xo_board", \
103
103
}, \
104
104
.num_parents = 1, \
105
+
.flags = (ao_flags), \
105
106
}, \
106
107
}
107
108
108
109
#define __DEFINE_CLK_SMD_RPM_BRANCH(_name, _active, type, r_id, r, key) \
109
110
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(/* empty */, \
110
-
_name, _active, type, r_id, r, key)
111
+
_name, _active, type, r_id, r, key, 0)
111
112
112
113
#define DEFINE_CLK_SMD_RPM(_name, type, r_id) \
113
114
__DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
···
127
126
#define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \
128
127
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \
129
128
_name##_clk, _name##_a_clk, \
130
-
type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE)
129
+
type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE, 0)
131
130
132
-
#define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r) \
131
+
#define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r, ao_flags) \
133
132
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \
134
133
_name, _name##_a, type, \
135
-
r_id, r, QCOM_RPM_SMD_KEY_ENABLE)
134
+
r_id, r, QCOM_RPM_SMD_KEY_ENABLE, ao_flags)
136
135
137
136
#define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \
138
137
__DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
···
147
146
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, \
148
147
_name, _name##_a, \
149
148
QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \
150
-
QCOM_RPM_KEY_SOFTWARE_ENABLE)
149
+
QCOM_RPM_KEY_SOFTWARE_ENABLE, 0)
151
150
152
151
#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, r_id, r) \
153
152
DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r); \
···
156
155
QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
157
156
158
157
#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
158
+
159
+
static struct qcom_smd_rpm *rpmcc_smd_rpm;
159
160
160
161
struct clk_smd_rpm {
161
162
const int rpm_res_type;
···
169
166
struct clk_smd_rpm *peer;
170
167
struct clk_hw hw;
171
168
unsigned long rate;
172
-
struct qcom_smd_rpm *rpm;
173
169
};
174
170
175
171
struct clk_smd_rpm_req {
···
180
178
struct rpm_smd_clk_desc {
181
179
struct clk_smd_rpm **clks;
182
180
size_t num_clks;
181
+
bool scaling_before_handover;
183
182
};
184
183
185
184
static DEFINE_MUTEX(rpm_smd_clk_lock);
···
194
191
.value = cpu_to_le32(r->branch ? 1 : INT_MAX),
195
192
};
196
193
197
-
ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
194
+
ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
198
195
r->rpm_res_type, r->rpm_clk_id, &req,
199
196
sizeof(req));
200
197
if (ret)
201
198
return ret;
202
-
ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
199
+
ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,
203
200
r->rpm_res_type, r->rpm_clk_id, &req,
204
201
sizeof(req));
205
202
if (ret)
···
217
214
.value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
218
215
};
219
216
220
-
return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
217
+
return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
221
218
r->rpm_res_type, r->rpm_clk_id, &req,
222
219
sizeof(req));
223
220
}
···
231
228
.value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
232
229
};
233
230
234
-
return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
231
+
return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,
235
232
r->rpm_res_type, r->rpm_clk_id, &req,
236
233
sizeof(req));
237
234
}
···
398
395
return r->rate;
399
396
}
400
397
401
-
static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
398
+
static int clk_smd_rpm_enable_scaling(void)
402
399
{
403
400
int ret;
404
401
struct clk_smd_rpm_req req = {
···
407
404
.value = cpu_to_le32(1),
408
405
};
409
406
410
-
ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
407
+
ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,
411
408
QCOM_SMD_RPM_MISC_CLK,
412
409
QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
413
410
if (ret) {
···
415
412
return ret;
416
413
}
417
414
418
-
ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
415
+
ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
419
416
QCOM_SMD_RPM_MISC_CLK,
420
417
QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
421
418
if (ret) {
···
441
438
.recalc_rate = clk_smd_rpm_recalc_rate,
442
439
};
443
440
444
-
DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
441
+
/* Disabling BI_TCXO_AO could gate the root clock source of the entire system. */
442
+
DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000, CLK_IS_CRITICAL);
445
443
DEFINE_CLK_SMD_RPM_BRANCH(qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000);
446
444
DEFINE_CLK_SMD_RPM_QDSS(qdss, QCOM_SMD_RPM_MISC_CLK, 1);
447
-
DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1);
445
+
DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1, 0);
448
446
449
447
DEFINE_CLK_SMD_RPM_BRANCH(mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000);
450
448
···
697
693
static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
698
694
.clks = msm8974_clks,
699
695
.num_clks = ARRAY_SIZE(msm8974_clks),
696
+
.scaling_before_handover = true,
700
697
};
701
698
702
699
static struct clk_smd_rpm *msm8976_clks[] = {
···
1306
1301
{
1307
1302
int ret;
1308
1303
size_t num_clks, i;
1309
-
struct qcom_smd_rpm *rpm;
1310
1304
struct clk_smd_rpm **rpm_smd_clks;
1311
1305
const struct rpm_smd_clk_desc *desc;
1312
1306
1313
-
rpm = dev_get_drvdata(pdev->dev.parent);
1314
-
if (!rpm) {
1307
+
rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent);
1308
+
if (!rpmcc_smd_rpm) {
1315
1309
dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
1316
1310
return -ENODEV;
1317
1311
}
···
1322
1318
rpm_smd_clks = desc->clks;
1323
1319
num_clks = desc->num_clks;
1324
1320
1321
+
if (desc->scaling_before_handover) {
1322
+
ret = clk_smd_rpm_enable_scaling();
1323
+
if (ret)
1324
+
goto err;
1325
+
}
1326
+
1325
1327
for (i = 0; i < num_clks; i++) {
1326
1328
if (!rpm_smd_clks[i])
1327
1329
continue;
1328
-
1329
-
rpm_smd_clks[i]->rpm = rpm;
1330
1330
1331
1331
ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
1332
1332
if (ret)
1333
1333
goto err;
1334
1334
}
1335
1335
1336
-
ret = clk_smd_rpm_enable_scaling(rpm);
1337
-
if (ret)
1338
-
goto err;
1336
+
if (!desc->scaling_before_handover) {
1337
+
ret = clk_smd_rpm_enable_scaling();
1338
+
if (ret)
1339
+
goto err;
1340
+
}
1339
1341
1340
1342
for (i = 0; i < num_clks; i++) {
1341
1343
if (!rpm_smd_clks[i])
+7
-5
drivers/clk/qcom/dispcc-qcm2290.c
+7
-5
drivers/clk/qcom/dispcc-qcm2290.c
···
24
24
25
25
enum {
26
26
P_BI_TCXO,
27
+
P_BI_TCXO_AO,
27
28
P_DISP_CC_PLL0_OUT_MAIN,
28
29
P_DSI0_PHY_PLL_OUT_BYTECLK,
29
30
P_DSI0_PHY_PLL_OUT_DSICLK,
31
+
P_GPLL0_OUT_DIV,
30
32
P_GPLL0_OUT_MAIN,
31
33
P_SLEEP_CLK,
32
34
};
···
84
82
};
85
83
86
84
static const struct parent_map disp_cc_parent_map_2[] = {
87
-
{ P_BI_TCXO, 0 },
88
-
{ P_GPLL0_OUT_MAIN, 4 },
85
+
{ P_BI_TCXO_AO, 0 },
86
+
{ P_GPLL0_OUT_DIV, 4 },
89
87
};
90
88
91
89
static const struct clk_parent_data disp_cc_parent_data_2[] = {
···
153
151
};
154
152
155
153
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
156
-
F(19200000, P_BI_TCXO, 1, 0, 0),
157
-
F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
158
-
F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
154
+
F(19200000, P_BI_TCXO_AO, 1, 0, 0),
155
+
F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0),
156
+
F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0),
159
157
{ }
160
158
};
161
159
+3
-3
drivers/clk/qcom/gcc-ipq5332.c
+3
-3
drivers/clk/qcom/gcc-ipq5332.c
···
20
20
#include "reset.h"
21
21
22
22
enum {
23
-
DT_SLEEP_CLK,
24
23
DT_XO,
24
+
DT_SLEEP_CLK,
25
25
DT_PCIE_2LANE_PHY_PIPE_CLK,
26
26
DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
27
27
DT_USB_PCIE_WRAPPER_PIPE_CLK,
···
366
366
};
367
367
368
368
static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = {
369
-
F(480000000, P_GPLL4_OUT_MAIN, 2.5, 0, 0),
369
+
F(480000000, P_GPLL4_OUT_AUX, 2.5, 0, 0),
370
370
F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
371
371
{ }
372
372
};
···
963
963
.name = "gcc_sdcc1_apps_clk_src",
964
964
.parent_data = gcc_parent_data_9,
965
965
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
966
-
.ops = &clk_rcg2_ops,
966
+
.ops = &clk_rcg2_floor_ops,
967
967
},
968
968
};
969
969
+23
-22
drivers/clk/qcom/gcc-ipq6018.c
+23
-22
drivers/clk/qcom/gcc-ipq6018.c
···
26
26
#include "clk-regmap-mux.h"
27
27
#include "reset.h"
28
28
29
-
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
30
-
31
29
enum {
32
30
P_XO,
33
31
P_BIAS_PLL,
···
1652
1654
.name = "sdcc1_apps_clk_src",
1653
1655
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1654
1656
.num_parents = 4,
1655
-
.ops = &clk_rcg2_ops,
1657
+
.ops = &clk_rcg2_floor_ops,
1656
1658
},
1657
1659
};
1658
1660
···
4149
4151
4150
4152
static const struct alpha_pll_config ubi32_pll_config = {
4151
4153
.l = 0x3e,
4152
-
.alpha = 0x57,
4153
-
.config_ctl_val = 0x240d6aa8,
4154
-
.config_ctl_hi_val = 0x3c2,
4154
+
.alpha = 0x6667,
4155
+
.config_ctl_val = 0x240d4828,
4156
+
.config_ctl_hi_val = 0x6,
4155
4157
.main_output_mask = BIT(0),
4156
4158
.aux_output_mask = BIT(1),
4157
4159
.pre_div_val = 0x0,
4158
4160
.pre_div_mask = BIT(12),
4159
4161
.post_div_val = 0x0,
4160
4162
.post_div_mask = GENMASK(9, 8),
4163
+
.alpha_en_mask = BIT(24),
4164
+
.test_ctl_val = 0x1C0000C0,
4165
+
.test_ctl_hi_val = 0x4000,
4161
4166
};
4162
4167
4163
4168
static const struct alpha_pll_config nss_crypto_pll_config = {
···
4518
4517
[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4519
4518
[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4520
4519
[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4521
-
[GCC_PPE_FULL_RESET] = { 0x68014, 0 },
4522
-
[GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 },
4520
+
[GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
4521
+
[GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
4523
4522
[GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4524
-
[GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 },
4523
+
[GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
4525
4524
[GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4526
-
[GCC_EDMA_HW_RESET] = { 0x68014, 0 },
4527
-
[GCC_NSSPORT1_RESET] = { 0x68014, 0 },
4528
-
[GCC_NSSPORT2_RESET] = { 0x68014, 0 },
4529
-
[GCC_NSSPORT3_RESET] = { 0x68014, 0 },
4530
-
[GCC_NSSPORT4_RESET] = { 0x68014, 0 },
4531
-
[GCC_NSSPORT5_RESET] = { 0x68014, 0 },
4532
-
[GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 },
4533
-
[GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 },
4534
-
[GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 },
4535
-
[GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 },
4536
-
[GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 },
4537
-
[GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 },
4538
-
[GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 },
4525
+
[GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
4526
+
[GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
4527
+
[GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
4528
+
[GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
4529
+
[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
4530
+
[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
4531
+
[GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
4532
+
[GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
4533
+
[GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
4534
+
[GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
4535
+
[GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
4536
+
[GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
4537
+
[GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
4539
4538
[GCC_LPASS_BCR] = {0x1F000, 0},
4540
4539
[GCC_UBI32_TBU_BCR] = {0x65000, 0},
4541
4540
[GCC_LPASS_TBU_BCR] = {0x6C000, 0},
+289
-217
drivers/clk/qcom/gcc-ipq9574.c
+289
-217
drivers/clk/qcom/gcc-ipq9574.c
···
3
3
* Copyright (c) 2023 The Linux Foundation. All rights reserved.
4
4
*/
5
5
6
+
#include <linux/clk-provider.h>
6
7
#include <linux/kernel.h>
7
-
#include <linux/err.h>
8
-
#include <linux/platform_device.h>
9
8
#include <linux/module.h>
10
9
#include <linux/of.h>
11
-
#include <linux/of_device.h>
10
+
#include <linux/platform_device.h>
12
11
#include <linux/regmap.h>
13
12
14
-
#include <linux/reset-controller.h>
15
13
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
16
14
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
17
15
18
-
#include "clk-rcg.h"
19
-
#include "clk-branch.h"
20
16
#include "clk-alpha-pll.h"
17
+
#include "clk-branch.h"
18
+
#include "clk-rcg.h"
19
+
#include "clk-regmap.h"
21
20
#include "clk-regmap-divider.h"
22
21
#include "clk-regmap-mux.h"
23
22
#include "clk-regmap-phy-mux.h"
23
+
#include "common.h"
24
24
#include "reset.h"
25
25
26
26
/* Need to match the order of clocks in DT binding */
···
69
69
.clkr = {
70
70
.enable_reg = 0x0b000,
71
71
.enable_mask = BIT(0),
72
-
.hw.init = &(struct clk_init_data) {
72
+
.hw.init = &(const struct clk_init_data) {
73
73
.name = "gpll0_main",
74
74
.parent_data = gcc_xo_data,
75
75
.num_parents = ARRAY_SIZE(gcc_xo_data),
···
81
81
static struct clk_fixed_factor gpll0_out_main_div2 = {
82
82
.mult = 1,
83
83
.div = 2,
84
-
.hw.init = &(struct clk_init_data) {
84
+
.hw.init = &(const struct clk_init_data) {
85
85
.name = "gpll0_out_main_div2",
86
86
.parent_hws = (const struct clk_hw *[]) {
87
87
&gpll0_main.clkr.hw
···
96
96
.offset = 0x20000,
97
97
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
98
98
.width = 4,
99
-
.clkr.hw.init = &(struct clk_init_data) {
99
+
.clkr.hw.init = &(const struct clk_init_data) {
100
100
.name = "gpll0",
101
101
.parent_hws = (const struct clk_hw *[]) {
102
102
&gpll0_main.clkr.hw
···
113
113
.clkr = {
114
114
.enable_reg = 0x0b000,
115
115
.enable_mask = BIT(2),
116
-
.hw.init = &(struct clk_init_data) {
116
+
.hw.init = &(const struct clk_init_data) {
117
117
.name = "gpll4_main",
118
118
.parent_data = gcc_xo_data,
119
119
.num_parents = ARRAY_SIZE(gcc_xo_data),
···
126
126
.offset = 0x22000,
127
127
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
128
128
.width = 4,
129
-
.clkr.hw.init = &(struct clk_init_data) {
129
+
.clkr.hw.init = &(const struct clk_init_data) {
130
130
.name = "gpll4",
131
131
.parent_hws = (const struct clk_hw *[]) {
132
132
&gpll4_main.clkr.hw
···
143
143
.clkr = {
144
144
.enable_reg = 0x0b000,
145
145
.enable_mask = BIT(1),
146
-
.hw.init = &(struct clk_init_data) {
146
+
.hw.init = &(const struct clk_init_data) {
147
147
.name = "gpll2_main",
148
148
.parent_data = gcc_xo_data,
149
149
.num_parents = ARRAY_SIZE(gcc_xo_data),
···
156
156
.offset = 0x21000,
157
157
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
158
158
.width = 4,
159
-
.clkr.hw.init = &(struct clk_init_data) {
159
+
.clkr.hw.init = &(const struct clk_init_data) {
160
160
.name = "gpll2",
161
161
.parent_hws = (const struct clk_hw *[]) {
162
162
&gpll2_main.clkr.hw
···
172
172
.clkr = {
173
173
.enable_reg = 0x3400c,
174
174
.enable_mask = BIT(1),
175
-
.hw.init = &(struct clk_init_data) {
175
+
.hw.init = &(const struct clk_init_data) {
176
176
.name = "gcc_sleep_clk_src",
177
177
.parent_data = gcc_sleep_clk_data,
178
178
.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
···
420
420
.freq_tbl = ftbl_apss_ahb_clk_src,
421
421
.hid_width = 5,
422
422
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
423
-
.clkr.hw.init = &(struct clk_init_data) {
423
+
.clkr.hw.init = &(const struct clk_init_data) {
424
424
.name = "apss_ahb_clk_src",
425
425
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
426
426
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
438
438
.freq_tbl = ftbl_apss_axi_clk_src,
439
439
.hid_width = 5,
440
440
.parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map,
441
-
.clkr.hw.init = &(struct clk_init_data) {
441
+
.clkr.hw.init = &(const struct clk_init_data) {
442
442
.name = "apss_axi_clk_src",
443
443
.parent_data = gcc_xo_gpll0_gpll0_div2_gpll0,
444
444
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0),
···
458
458
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
459
459
.hid_width = 5,
460
460
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
461
-
.clkr.hw.init = &(struct clk_init_data) {
461
+
.clkr.hw.init = &(const struct clk_init_data) {
462
462
.name = "blsp1_qup1_i2c_apps_clk_src",
463
463
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
464
464
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
483
483
.mnd_width = 8,
484
484
.hid_width = 5,
485
485
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
486
-
.clkr.hw.init = &(struct clk_init_data) {
486
+
.clkr.hw.init = &(const struct clk_init_data) {
487
487
.name = "blsp1_qup1_spi_apps_clk_src",
488
488
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
489
489
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
496
496
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
497
497
.hid_width = 5,
498
498
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
499
-
.clkr.hw.init = &(struct clk_init_data) {
499
+
.clkr.hw.init = &(const struct clk_init_data) {
500
500
.name = "blsp1_qup2_i2c_apps_clk_src",
501
501
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
502
502
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
510
510
.mnd_width = 8,
511
511
.hid_width = 5,
512
512
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
513
-
.clkr.hw.init = &(struct clk_init_data) {
513
+
.clkr.hw.init = &(const struct clk_init_data) {
514
514
.name = "blsp1_qup2_spi_apps_clk_src",
515
515
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
516
516
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
523
523
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
524
524
.hid_width = 5,
525
525
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
526
-
.clkr.hw.init = &(struct clk_init_data) {
526
+
.clkr.hw.init = &(const struct clk_init_data) {
527
527
.name = "blsp1_qup3_i2c_apps_clk_src",
528
528
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
529
529
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
537
537
.mnd_width = 8,
538
538
.hid_width = 5,
539
539
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
540
-
.clkr.hw.init = &(struct clk_init_data) {
540
+
.clkr.hw.init = &(const struct clk_init_data) {
541
541
.name = "blsp1_qup3_spi_apps_clk_src",
542
542
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
543
543
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
550
550
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
551
551
.hid_width = 5,
552
552
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
553
-
.clkr.hw.init = &(struct clk_init_data) {
553
+
.clkr.hw.init = &(const struct clk_init_data) {
554
554
.name = "blsp1_qup4_i2c_apps_clk_src",
555
555
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
556
556
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
564
564
.mnd_width = 8,
565
565
.hid_width = 5,
566
566
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
567
-
.clkr.hw.init = &(struct clk_init_data) {
567
+
.clkr.hw.init = &(const struct clk_init_data) {
568
568
.name = "blsp1_qup4_spi_apps_clk_src",
569
569
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
570
570
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
577
577
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
578
578
.hid_width = 5,
579
579
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
580
-
.clkr.hw.init = &(struct clk_init_data) {
580
+
.clkr.hw.init = &(const struct clk_init_data) {
581
581
.name = "blsp1_qup5_i2c_apps_clk_src",
582
582
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
583
583
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
591
591
.mnd_width = 8,
592
592
.hid_width = 5,
593
593
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
594
-
.clkr.hw.init = &(struct clk_init_data) {
594
+
.clkr.hw.init = &(const struct clk_init_data) {
595
595
.name = "blsp1_qup5_spi_apps_clk_src",
596
596
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
597
597
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
604
604
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
605
605
.hid_width = 5,
606
606
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
607
-
.clkr.hw.init = &(struct clk_init_data) {
607
+
.clkr.hw.init = &(const struct clk_init_data) {
608
608
.name = "blsp1_qup6_i2c_apps_clk_src",
609
609
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
610
610
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
618
618
.mnd_width = 8,
619
619
.hid_width = 5,
620
620
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
621
-
.clkr.hw.init = &(struct clk_init_data) {
621
+
.clkr.hw.init = &(const struct clk_init_data) {
622
622
.name = "blsp1_qup6_spi_apps_clk_src",
623
623
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
624
624
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
650
650
.mnd_width = 16,
651
651
.hid_width = 5,
652
652
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
653
-
.clkr.hw.init = &(struct clk_init_data) {
653
+
.clkr.hw.init = &(const struct clk_init_data) {
654
654
.name = "blsp1_uart1_apps_clk_src",
655
655
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
656
656
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
664
664
.mnd_width = 16,
665
665
.hid_width = 5,
666
666
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
667
-
.clkr.hw.init = &(struct clk_init_data) {
667
+
.clkr.hw.init = &(const struct clk_init_data) {
668
668
.name = "blsp1_uart2_apps_clk_src",
669
669
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
670
670
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
678
678
.mnd_width = 16,
679
679
.hid_width = 5,
680
680
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
681
-
.clkr.hw.init = &(struct clk_init_data) {
681
+
.clkr.hw.init = &(const struct clk_init_data) {
682
682
.name = "blsp1_uart3_apps_clk_src",
683
683
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
684
684
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
692
692
.mnd_width = 16,
693
693
.hid_width = 5,
694
694
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
695
-
.clkr.hw.init = &(struct clk_init_data) {
695
+
.clkr.hw.init = &(const struct clk_init_data) {
696
696
.name = "blsp1_uart4_apps_clk_src",
697
697
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
698
698
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
706
706
.mnd_width = 16,
707
707
.hid_width = 5,
708
708
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
709
-
.clkr.hw.init = &(struct clk_init_data) {
709
+
.clkr.hw.init = &(const struct clk_init_data) {
710
710
.name = "blsp1_uart5_apps_clk_src",
711
711
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
712
712
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
720
720
.mnd_width = 16,
721
721
.hid_width = 5,
722
722
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
723
-
.clkr.hw.init = &(struct clk_init_data) {
723
+
.clkr.hw.init = &(const struct clk_init_data) {
724
724
.name = "blsp1_uart6_apps_clk_src",
725
725
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
726
726
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
727
727
.ops = &clk_rcg2_ops,
728
+
},
729
+
};
730
+
731
+
static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = {
732
+
F(160000000, P_GPLL0, 5, 0, 0),
733
+
{ }
734
+
};
735
+
736
+
static struct clk_rcg2 gcc_crypto_clk_src = {
737
+
.cmd_rcgr = 0x16004,
738
+
.freq_tbl = ftbl_gcc_crypto_clk_src,
739
+
.hid_width = 5,
740
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
741
+
.clkr.hw.init = &(const struct clk_init_data) {
742
+
.name = "gcc_crypto_clk_src",
743
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
744
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
745
+
.ops = &clk_rcg2_ops,
746
+
},
747
+
};
748
+
749
+
static struct clk_branch gcc_crypto_clk = {
750
+
.halt_reg = 0x1600c,
751
+
.halt_check = BRANCH_HALT_VOTED,
752
+
.clkr = {
753
+
.enable_reg = 0x0b004,
754
+
.enable_mask = BIT(14),
755
+
.hw.init = &(const struct clk_init_data) {
756
+
.name = "gcc_crypto_clk",
757
+
.parent_hws = (const struct clk_hw *[]) {
758
+
&gcc_crypto_clk_src.clkr.hw },
759
+
.num_parents = 1,
760
+
.flags = CLK_SET_RATE_PARENT,
761
+
.ops = &clk_branch2_ops,
762
+
},
728
763
},
729
764
};
730
765
···
769
734
.clkr = {
770
735
.enable_reg = 0x0b004,
771
736
.enable_mask = BIT(0),
772
-
.hw.init = &(struct clk_init_data) {
737
+
.hw.init = &(const struct clk_init_data) {
773
738
.name = "gcc_apss_ahb_clk",
774
739
.parent_hws = (const struct clk_hw *[]) {
775
740
&apss_ahb_clk_src.clkr.hw
···
787
752
.clkr = {
788
753
.enable_reg = 0x0b004,
789
754
.enable_mask = BIT(1),
790
-
.hw.init = &(struct clk_init_data) {
755
+
.hw.init = &(const struct clk_init_data) {
791
756
.name = "gcc_apss_axi_clk",
792
757
.parent_hws = (const struct clk_hw *[]) {
793
758
&apss_axi_clk_src.clkr.hw
···
804
769
.clkr = {
805
770
.enable_reg = 0x2024,
806
771
.enable_mask = BIT(0),
807
-
.hw.init = &(struct clk_init_data) {
772
+
.hw.init = &(const struct clk_init_data) {
808
773
.name = "gcc_blsp1_qup1_i2c_apps_clk",
809
774
.parent_hws = (const struct clk_hw *[]) {
810
775
&blsp1_qup1_i2c_apps_clk_src.clkr.hw
···
821
786
.clkr = {
822
787
.enable_reg = 0x02020,
823
788
.enable_mask = BIT(0),
824
-
.hw.init = &(struct clk_init_data) {
789
+
.hw.init = &(const struct clk_init_data) {
825
790
.name = "gcc_blsp1_qup1_spi_apps_clk",
826
791
.parent_hws = (const struct clk_hw *[]) {
827
792
&blsp1_qup1_spi_apps_clk_src.clkr.hw
···
838
803
.clkr = {
839
804
.enable_reg = 0x03024,
840
805
.enable_mask = BIT(0),
841
-
.hw.init = &(struct clk_init_data) {
806
+
.hw.init = &(const struct clk_init_data) {
842
807
.name = "gcc_blsp1_qup2_i2c_apps_clk",
843
808
.parent_hws = (const struct clk_hw *[]) {
844
809
&blsp1_qup2_i2c_apps_clk_src.clkr.hw
···
855
820
.clkr = {
856
821
.enable_reg = 0x03020,
857
822
.enable_mask = BIT(0),
858
-
.hw.init = &(struct clk_init_data) {
823
+
.hw.init = &(const struct clk_init_data) {
859
824
.name = "gcc_blsp1_qup2_spi_apps_clk",
860
825
.parent_hws = (const struct clk_hw *[]) {
861
826
&blsp1_qup2_spi_apps_clk_src.clkr.hw
···
872
837
.clkr = {
873
838
.enable_reg = 0x04024,
874
839
.enable_mask = BIT(0),
875
-
.hw.init = &(struct clk_init_data) {
840
+
.hw.init = &(const struct clk_init_data) {
876
841
.name = "gcc_blsp1_qup3_i2c_apps_clk",
877
842
.parent_hws = (const struct clk_hw *[]) {
878
843
&blsp1_qup3_i2c_apps_clk_src.clkr.hw
···
889
854
.clkr = {
890
855
.enable_reg = 0x04020,
891
856
.enable_mask = BIT(0),
892
-
.hw.init = &(struct clk_init_data) {
857
+
.hw.init = &(const struct clk_init_data) {
893
858
.name = "gcc_blsp1_qup3_spi_apps_clk",
894
859
.parent_hws = (const struct clk_hw *[]) {
895
860
&blsp1_qup3_spi_apps_clk_src.clkr.hw
···
906
871
.clkr = {
907
872
.enable_reg = 0x05024,
908
873
.enable_mask = BIT(0),
909
-
.hw.init = &(struct clk_init_data) {
874
+
.hw.init = &(const struct clk_init_data) {
910
875
.name = "gcc_blsp1_qup4_i2c_apps_clk",
911
876
.parent_hws = (const struct clk_hw *[]) {
912
877
&blsp1_qup4_i2c_apps_clk_src.clkr.hw
···
923
888
.clkr = {
924
889
.enable_reg = 0x05020,
925
890
.enable_mask = BIT(0),
926
-
.hw.init = &(struct clk_init_data) {
891
+
.hw.init = &(const struct clk_init_data) {
927
892
.name = "gcc_blsp1_qup4_spi_apps_clk",
928
893
.parent_hws = (const struct clk_hw *[]) {
929
894
&blsp1_qup4_spi_apps_clk_src.clkr.hw
···
940
905
.clkr = {
941
906
.enable_reg = 0x06024,
942
907
.enable_mask = BIT(0),
943
-
.hw.init = &(struct clk_init_data) {
908
+
.hw.init = &(const struct clk_init_data) {
944
909
.name = "gcc_blsp1_qup5_i2c_apps_clk",
945
910
.parent_hws = (const struct clk_hw *[]) {
946
911
&blsp1_qup5_i2c_apps_clk_src.clkr.hw
···
957
922
.clkr = {
958
923
.enable_reg = 0x06020,
959
924
.enable_mask = BIT(0),
960
-
.hw.init = &(struct clk_init_data) {
925
+
.hw.init = &(const struct clk_init_data) {
961
926
.name = "gcc_blsp1_qup5_spi_apps_clk",
962
927
.parent_hws = (const struct clk_hw *[]) {
963
928
&blsp1_qup5_spi_apps_clk_src.clkr.hw
···
974
939
.clkr = {
975
940
.enable_reg = 0x07024,
976
941
.enable_mask = BIT(0),
977
-
.hw.init = &(struct clk_init_data) {
942
+
.hw.init = &(const struct clk_init_data) {
978
943
.name = "gcc_blsp1_qup6_i2c_apps_clk",
979
944
.parent_hws = (const struct clk_hw *[]) {
980
945
&blsp1_qup6_i2c_apps_clk_src.clkr.hw
···
991
956
.clkr = {
992
957
.enable_reg = 0x07020,
993
958
.enable_mask = BIT(0),
994
-
.hw.init = &(struct clk_init_data) {
959
+
.hw.init = &(const struct clk_init_data) {
995
960
.name = "gcc_blsp1_qup6_spi_apps_clk",
996
961
.parent_hws = (const struct clk_hw *[]) {
997
962
&blsp1_qup6_spi_apps_clk_src.clkr.hw
···
1008
973
.clkr = {
1009
974
.enable_reg = 0x02040,
1010
975
.enable_mask = BIT(0),
1011
-
.hw.init = &(struct clk_init_data) {
976
+
.hw.init = &(const struct clk_init_data) {
1012
977
.name = "gcc_blsp1_uart1_apps_clk",
1013
978
.parent_hws = (const struct clk_hw *[]) {
1014
979
&blsp1_uart1_apps_clk_src.clkr.hw
···
1025
990
.clkr = {
1026
991
.enable_reg = 0x03040,
1027
992
.enable_mask = BIT(0),
1028
-
.hw.init = &(struct clk_init_data) {
993
+
.hw.init = &(const struct clk_init_data) {
1029
994
.name = "gcc_blsp1_uart2_apps_clk",
1030
995
.parent_hws = (const struct clk_hw *[]) {
1031
996
&blsp1_uart2_apps_clk_src.clkr.hw
···
1042
1007
.clkr = {
1043
1008
.enable_reg = 0x04054,
1044
1009
.enable_mask = BIT(0),
1045
-
.hw.init = &(struct clk_init_data) {
1010
+
.hw.init = &(const struct clk_init_data) {
1046
1011
.name = "gcc_blsp1_uart3_apps_clk",
1047
1012
.parent_hws = (const struct clk_hw *[]) {
1048
1013
&blsp1_uart3_apps_clk_src.clkr.hw
···
1059
1024
.clkr = {
1060
1025
.enable_reg = 0x05040,
1061
1026
.enable_mask = BIT(0),
1062
-
.hw.init = &(struct clk_init_data) {
1027
+
.hw.init = &(const struct clk_init_data) {
1063
1028
.name = "gcc_blsp1_uart4_apps_clk",
1064
1029
.parent_hws = (const struct clk_hw *[]) {
1065
1030
&blsp1_uart4_apps_clk_src.clkr.hw
···
1076
1041
.clkr = {
1077
1042
.enable_reg = 0x06040,
1078
1043
.enable_mask = BIT(0),
1079
-
.hw.init = &(struct clk_init_data) {
1044
+
.hw.init = &(const struct clk_init_data) {
1080
1045
.name = "gcc_blsp1_uart5_apps_clk",
1081
1046
.parent_hws = (const struct clk_hw *[]) {
1082
1047
&blsp1_uart5_apps_clk_src.clkr.hw
···
1093
1058
.clkr = {
1094
1059
.enable_reg = 0x07040,
1095
1060
.enable_mask = BIT(0),
1096
-
.hw.init = &(struct clk_init_data) {
1061
+
.hw.init = &(const struct clk_init_data) {
1097
1062
.name = "gcc_blsp1_uart6_apps_clk",
1098
1063
.parent_hws = (const struct clk_hw *[]) {
1099
1064
&blsp1_uart6_apps_clk_src.clkr.hw
···
1115
1080
.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1116
1081
.hid_width = 5,
1117
1082
.parent_map = gcc_xo_gpll0_gpll4_map,
1118
-
.clkr.hw.init = &(struct clk_init_data) {
1083
+
.clkr.hw.init = &(const struct clk_init_data) {
1119
1084
.name = "pcie0_axi_m_clk_src",
1120
1085
.parent_data = gcc_xo_gpll0_gpll4,
1121
1086
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
···
1128
1093
.clkr = {
1129
1094
.enable_reg = 0x28038,
1130
1095
.enable_mask = BIT(0),
1131
-
.hw.init = &(struct clk_init_data) {
1096
+
.hw.init = &(const struct clk_init_data) {
1132
1097
.name = "gcc_pcie0_axi_m_clk",
1133
1098
.parent_hws = (const struct clk_hw *[]) {
1134
1099
&pcie0_axi_m_clk_src.clkr.hw
···
1145
1110
.clkr = {
1146
1111
.enable_reg = 0x2e07c,
1147
1112
.enable_mask = BIT(0),
1148
-
.hw.init = &(struct clk_init_data) {
1113
+
.hw.init = &(const struct clk_init_data) {
1149
1114
.name = "gcc_anoc_pcie0_1lane_m_clk",
1150
1115
.parent_hws = (const struct clk_hw *[]) {
1151
1116
&pcie0_axi_m_clk_src.clkr.hw
···
1162
1127
.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1163
1128
.hid_width = 5,
1164
1129
.parent_map = gcc_xo_gpll0_gpll4_map,
1165
-
.clkr.hw.init = &(struct clk_init_data) {
1130
+
.clkr.hw.init = &(const struct clk_init_data) {
1166
1131
.name = "pcie1_axi_m_clk_src",
1167
1132
.parent_data = gcc_xo_gpll0_gpll4,
1168
1133
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
···
1175
1140
.clkr = {
1176
1141
.enable_reg = 0x29038,
1177
1142
.enable_mask = BIT(0),
1178
-
.hw.init = &(struct clk_init_data) {
1143
+
.hw.init = &(const struct clk_init_data) {
1179
1144
.name = "gcc_pcie1_axi_m_clk",
1180
1145
.parent_hws = (const struct clk_hw *[]) {
1181
1146
&pcie1_axi_m_clk_src.clkr.hw
···
1192
1157
.clkr = {
1193
1158
.enable_reg = 0x2e08c,
1194
1159
.enable_mask = BIT(0),
1195
-
.hw.init = &(struct clk_init_data) {
1160
+
.hw.init = &(const struct clk_init_data) {
1196
1161
.name = "gcc_anoc_pcie1_1lane_m_clk",
1197
1162
.parent_hws = (const struct clk_hw *[]) {
1198
1163
&pcie1_axi_m_clk_src.clkr.hw
···
1214
1179
.freq_tbl = ftbl_pcie2_axi_m_clk_src,
1215
1180
.hid_width = 5,
1216
1181
.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
1217
-
.clkr.hw.init = &(struct clk_init_data) {
1182
+
.clkr.hw.init = &(const struct clk_init_data) {
1218
1183
.name = "pcie2_axi_m_clk_src",
1219
1184
.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
1220
1185
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
···
1227
1192
.clkr = {
1228
1193
.enable_reg = 0x2a038,
1229
1194
.enable_mask = BIT(0),
1230
-
.hw.init = &(struct clk_init_data) {
1195
+
.hw.init = &(const struct clk_init_data) {
1231
1196
.name = "gcc_pcie2_axi_m_clk",
1232
1197
.parent_hws = (const struct clk_hw *[]) {
1233
1198
&pcie2_axi_m_clk_src.clkr.hw
···
1244
1209
.clkr = {
1245
1210
.enable_reg = 0x2e080,
1246
1211
.enable_mask = BIT(0),
1247
-
.hw.init = &(struct clk_init_data) {
1212
+
.hw.init = &(const struct clk_init_data) {
1248
1213
.name = "gcc_anoc_pcie2_2lane_m_clk",
1249
1214
.parent_hws = (const struct clk_hw *[]) {
1250
1215
&pcie2_axi_m_clk_src.clkr.hw
···
1261
1226
.freq_tbl = ftbl_pcie2_axi_m_clk_src,
1262
1227
.hid_width = 5,
1263
1228
.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
1264
-
.clkr.hw.init = &(struct clk_init_data) {
1229
+
.clkr.hw.init = &(const struct clk_init_data) {
1265
1230
.name = "pcie3_axi_m_clk_src",
1266
1231
.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
1267
1232
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
···
1274
1239
.clkr = {
1275
1240
.enable_reg = 0x2b038,
1276
1241
.enable_mask = BIT(0),
1277
-
.hw.init = &(struct clk_init_data) {
1242
+
.hw.init = &(const struct clk_init_data) {
1278
1243
.name = "gcc_pcie3_axi_m_clk",
1279
1244
.parent_hws = (const struct clk_hw *[]) {
1280
1245
&pcie3_axi_m_clk_src.clkr.hw
···
1291
1256
.clkr = {
1292
1257
.enable_reg = 0x2e090,
1293
1258
.enable_mask = BIT(0),
1294
-
.hw.init = &(struct clk_init_data) {
1259
+
.hw.init = &(const struct clk_init_data) {
1295
1260
.name = "gcc_anoc_pcie3_2lane_m_clk",
1296
1261
.parent_hws = (const struct clk_hw *[]) {
1297
1262
&pcie3_axi_m_clk_src.clkr.hw
···
1308
1273
.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1309
1274
.hid_width = 5,
1310
1275
.parent_map = gcc_xo_gpll0_gpll4_map,
1311
-
.clkr.hw.init = &(struct clk_init_data) {
1276
+
.clkr.hw.init = &(const struct clk_init_data) {
1312
1277
.name = "pcie0_axi_s_clk_src",
1313
1278
.parent_data = gcc_xo_gpll0_gpll4,
1314
1279
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
···
1321
1286
.clkr = {
1322
1287
.enable_reg = 0x2803c,
1323
1288
.enable_mask = BIT(0),
1324
-
.hw.init = &(struct clk_init_data) {
1289
+
.hw.init = &(const struct clk_init_data) {
1325
1290
.name = "gcc_pcie0_axi_s_clk",
1326
1291
.parent_hws = (const struct clk_hw *[]) {
1327
1292
&pcie0_axi_s_clk_src.clkr.hw
···
1338
1303
.clkr = {
1339
1304
.enable_reg = 0x28040,
1340
1305
.enable_mask = BIT(0),
1341
-
.hw.init = &(struct clk_init_data) {
1306
+
.hw.init = &(const struct clk_init_data) {
1342
1307
.name = "gcc_pcie0_axi_s_bridge_clk",
1343
1308
.parent_hws = (const struct clk_hw *[]) {
1344
1309
&pcie0_axi_s_clk_src.clkr.hw
···
1355
1320
.clkr = {
1356
1321
.enable_reg = 0x2e048,
1357
1322
.enable_mask = BIT(0),
1358
-
.hw.init = &(struct clk_init_data) {
1323
+
.hw.init = &(const struct clk_init_data) {
1359
1324
.name = "gcc_snoc_pcie0_1lane_s_clk",
1360
1325
.parent_hws = (const struct clk_hw *[]) {
1361
1326
&pcie0_axi_s_clk_src.clkr.hw
···
1372
1337
.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1373
1338
.hid_width = 5,
1374
1339
.parent_map = gcc_xo_gpll0_gpll4_map,
1375
-
.clkr.hw.init = &(struct clk_init_data) {
1340
+
.clkr.hw.init = &(const struct clk_init_data) {
1376
1341
.name = "pcie1_axi_s_clk_src",
1377
1342
.parent_data = gcc_xo_gpll0_gpll4,
1378
1343
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
···
1385
1350
.clkr = {
1386
1351
.enable_reg = 0x2903c,
1387
1352
.enable_mask = BIT(0),
1388
-
.hw.init = &(struct clk_init_data) {
1353
+
.hw.init = &(const struct clk_init_data) {
1389
1354
.name = "gcc_pcie1_axi_s_clk",
1390
1355
.parent_hws = (const struct clk_hw *[]) {
1391
1356
&pcie1_axi_s_clk_src.clkr.hw
···
1402
1367
.clkr = {
1403
1368
.enable_reg = 0x29040,
1404
1369
.enable_mask = BIT(0),
1405
-
.hw.init = &(struct clk_init_data) {
1370
+
.hw.init = &(const struct clk_init_data) {
1406
1371
.name = "gcc_pcie1_axi_s_bridge_clk",
1407
1372
.parent_hws = (const struct clk_hw *[]) {
1408
1373
&pcie1_axi_s_clk_src.clkr.hw
···
1419
1384
.clkr = {
1420
1385
.enable_reg = 0x2e04c,
1421
1386
.enable_mask = BIT(0),
1422
-
.hw.init = &(struct clk_init_data) {
1387
+
.hw.init = &(const struct clk_init_data) {
1423
1388
.name = "gcc_snoc_pcie1_1lane_s_clk",
1424
1389
.parent_hws = (const struct clk_hw *[]) {
1425
1390
&pcie1_axi_s_clk_src.clkr.hw
···
1436
1401
.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1437
1402
.hid_width = 5,
1438
1403
.parent_map = gcc_xo_gpll0_gpll4_map,
1439
-
.clkr.hw.init = &(struct clk_init_data) {
1404
+
.clkr.hw.init = &(const struct clk_init_data) {
1440
1405
.name = "pcie2_axi_s_clk_src",
1441
1406
.parent_data = gcc_xo_gpll0_gpll4,
1442
1407
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
···
1449
1414
.clkr = {
1450
1415
.enable_reg = 0x2a03c,
1451
1416
.enable_mask = BIT(0),
1452
-
.hw.init = &(struct clk_init_data) {
1417
+
.hw.init = &(const struct clk_init_data) {
1453
1418
.name = "gcc_pcie2_axi_s_clk",
1454
1419
.parent_hws = (const struct clk_hw *[]) {
1455
1420
&pcie2_axi_s_clk_src.clkr.hw
···
1466
1431
.clkr = {
1467
1432
.enable_reg = 0x2a040,
1468
1433
.enable_mask = BIT(0),
1469
-
.hw.init = &(struct clk_init_data) {
1434
+
.hw.init = &(const struct clk_init_data) {
1470
1435
.name = "gcc_pcie2_axi_s_bridge_clk",
1471
1436
.parent_hws = (const struct clk_hw *[]) {
1472
1437
&pcie2_axi_s_clk_src.clkr.hw
···
1483
1448
.clkr = {
1484
1449
.enable_reg = 0x2e050,
1485
1450
.enable_mask = BIT(0),
1486
-
.hw.init = &(struct clk_init_data) {
1451
+
.hw.init = &(const struct clk_init_data) {
1487
1452
.name = "gcc_snoc_pcie2_2lane_s_clk",
1488
1453
.parent_hws = (const struct clk_hw *[]) {
1489
1454
&pcie2_axi_s_clk_src.clkr.hw
···
1500
1465
.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1501
1466
.hid_width = 5,
1502
1467
.parent_map = gcc_xo_gpll0_gpll4_map,
1503
-
.clkr.hw.init = &(struct clk_init_data) {
1468
+
.clkr.hw.init = &(const struct clk_init_data) {
1504
1469
.name = "pcie3_axi_s_clk_src",
1505
1470
.parent_data = gcc_xo_gpll0_gpll4,
1506
1471
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
···
1513
1478
.clkr = {
1514
1479
.enable_reg = 0x2b03c,
1515
1480
.enable_mask = BIT(0),
1516
-
.hw.init = &(struct clk_init_data) {
1481
+
.hw.init = &(const struct clk_init_data) {
1517
1482
.name = "gcc_pcie3_axi_s_clk",
1518
1483
.parent_hws = (const struct clk_hw *[]) {
1519
1484
&pcie3_axi_s_clk_src.clkr.hw
···
1530
1495
.clkr = {
1531
1496
.enable_reg = 0x2b040,
1532
1497
.enable_mask = BIT(0),
1533
-
.hw.init = &(struct clk_init_data) {
1498
+
.hw.init = &(const struct clk_init_data) {
1534
1499
.name = "gcc_pcie3_axi_s_bridge_clk",
1535
1500
.parent_hws = (const struct clk_hw *[]) {
1536
1501
&pcie3_axi_s_clk_src.clkr.hw
···
1547
1512
.clkr = {
1548
1513
.enable_reg = 0x2e054,
1549
1514
.enable_mask = BIT(0),
1550
-
.hw.init = &(struct clk_init_data) {
1515
+
.hw.init = &(const struct clk_init_data) {
1551
1516
.name = "gcc_snoc_pcie3_2lane_s_clk",
1552
1517
.parent_hws = (const struct clk_hw *[]) {
1553
1518
&pcie3_axi_s_clk_src.clkr.hw
···
1562
1527
static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
1563
1528
.reg = 0x28064,
1564
1529
.clkr = {
1565
-
.hw.init = &(struct clk_init_data) {
1530
+
.hw.init = &(const struct clk_init_data) {
1566
1531
.name = "pcie0_pipe_clk_src",
1567
1532
.parent_data = &(const struct clk_parent_data) {
1568
1533
.index = DT_PCIE30_PHY0_PIPE_CLK,
···
1576
1541
static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
1577
1542
.reg = 0x29064,
1578
1543
.clkr = {
1579
-
.hw.init = &(struct clk_init_data) {
1544
+
.hw.init = &(const struct clk_init_data) {
1580
1545
.name = "pcie1_pipe_clk_src",
1581
1546
.parent_data = &(const struct clk_parent_data) {
1582
1547
.index = DT_PCIE30_PHY1_PIPE_CLK,
···
1590
1555
static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
1591
1556
.reg = 0x2a064,
1592
1557
.clkr = {
1593
-
.hw.init = &(struct clk_init_data) {
1558
+
.hw.init = &(const struct clk_init_data) {
1594
1559
.name = "pcie2_pipe_clk_src",
1595
1560
.parent_data = &(const struct clk_parent_data) {
1596
1561
.index = DT_PCIE30_PHY2_PIPE_CLK,
···
1604
1569
static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
1605
1570
.reg = 0x2b064,
1606
1571
.clkr = {
1607
-
.hw.init = &(struct clk_init_data) {
1572
+
.hw.init = &(const struct clk_init_data) {
1608
1573
.name = "pcie3_pipe_clk_src",
1609
1574
.parent_data = &(const struct clk_parent_data) {
1610
1575
.index = DT_PCIE30_PHY3_PIPE_CLK,
···
1626
1591
.freq_tbl = ftbl_pcie_rchng_clk_src,
1627
1592
.hid_width = 5,
1628
1593
.parent_map = gcc_xo_gpll0_map,
1629
-
.clkr.hw.init = &(struct clk_init_data) {
1594
+
.clkr.hw.init = &(const struct clk_init_data) {
1630
1595
.name = "pcie0_rchng_clk_src",
1631
1596
.parent_data = gcc_xo_gpll0,
1632
1597
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
···
1639
1604
.clkr = {
1640
1605
.enable_reg = 0x28028,
1641
1606
.enable_mask = BIT(1),
1642
-
.hw.init = &(struct clk_init_data) {
1607
+
.hw.init = &(const struct clk_init_data) {
1643
1608
.name = "gcc_pcie0_rchng_clk",
1644
1609
.parent_hws = (const struct clk_hw *[]) {
1645
1610
&pcie0_rchng_clk_src.clkr.hw
···
1657
1622
.freq_tbl = ftbl_pcie_rchng_clk_src,
1658
1623
.hid_width = 5,
1659
1624
.parent_map = gcc_xo_gpll0_map,
1660
-
.clkr.hw.init = &(struct clk_init_data) {
1625
+
.clkr.hw.init = &(const struct clk_init_data) {
1661
1626
.name = "pcie1_rchng_clk_src",
1662
1627
.parent_data = gcc_xo_gpll0,
1663
1628
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
···
1670
1635
.clkr = {
1671
1636
.enable_reg = 0x29028,
1672
1637
.enable_mask = BIT(1),
1673
-
.hw.init = &(struct clk_init_data) {
1638
+
.hw.init = &(const struct clk_init_data) {
1674
1639
.name = "gcc_pcie1_rchng_clk",
1675
1640
.parent_hws = (const struct clk_hw *[]) {
1676
1641
&pcie1_rchng_clk_src.clkr.hw
···
1687
1652
.freq_tbl = ftbl_pcie_rchng_clk_src,
1688
1653
.hid_width = 5,
1689
1654
.parent_map = gcc_xo_gpll0_map,
1690
-
.clkr.hw.init = &(struct clk_init_data) {
1655
+
.clkr.hw.init = &(const struct clk_init_data) {
1691
1656
.name = "pcie2_rchng_clk_src",
1692
1657
.parent_data = gcc_xo_gpll0,
1693
1658
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
···
1700
1665
.clkr = {
1701
1666
.enable_reg = 0x2a028,
1702
1667
.enable_mask = BIT(1),
1703
-
.hw.init = &(struct clk_init_data) {
1668
+
.hw.init = &(const struct clk_init_data) {
1704
1669
.name = "gcc_pcie2_rchng_clk",
1705
1670
.parent_hws = (const struct clk_hw *[]) {
1706
1671
&pcie2_rchng_clk_src.clkr.hw
···
1717
1682
.freq_tbl = ftbl_pcie_rchng_clk_src,
1718
1683
.hid_width = 5,
1719
1684
.parent_map = gcc_xo_gpll0_map,
1720
-
.clkr.hw.init = &(struct clk_init_data) {
1685
+
.clkr.hw.init = &(const struct clk_init_data) {
1721
1686
.name = "pcie3_rchng_clk_src",
1722
1687
.parent_data = gcc_xo_gpll0,
1723
1688
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
···
1730
1695
.clkr = {
1731
1696
.enable_reg = 0x2b028,
1732
1697
.enable_mask = BIT(1),
1733
-
.hw.init = &(struct clk_init_data) {
1698
+
.hw.init = &(const struct clk_init_data) {
1734
1699
.name = "gcc_pcie3_rchng_clk",
1735
1700
.parent_hws = (const struct clk_hw *[]) {
1736
1701
&pcie3_rchng_clk_src.clkr.hw
···
1753
1718
.mnd_width = 16,
1754
1719
.hid_width = 5,
1755
1720
.parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map,
1756
-
.clkr.hw.init = &(struct clk_init_data) {
1721
+
.clkr.hw.init = &(const struct clk_init_data) {
1757
1722
.name = "pcie_aux_clk_src",
1758
1723
.parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk,
1759
1724
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk),
···
1766
1731
.clkr = {
1767
1732
.enable_reg = 0x28034,
1768
1733
.enable_mask = BIT(0),
1769
-
.hw.init = &(struct clk_init_data) {
1734
+
.hw.init = &(const struct clk_init_data) {
1770
1735
.name = "gcc_pcie0_aux_clk",
1771
1736
.parent_hws = (const struct clk_hw *[]) {
1772
1737
&pcie_aux_clk_src.clkr.hw
···
1783
1748
.clkr = {
1784
1749
.enable_reg = 0x29034,
1785
1750
.enable_mask = BIT(0),
1786
-
.hw.init = &(struct clk_init_data) {
1751
+
.hw.init = &(const struct clk_init_data) {
1787
1752
.name = "gcc_pcie1_aux_clk",
1788
1753
.parent_hws = (const struct clk_hw *[]) {
1789
1754
&pcie_aux_clk_src.clkr.hw
···
1800
1765
.clkr = {
1801
1766
.enable_reg = 0x2a034,
1802
1767
.enable_mask = BIT(0),
1803
-
.hw.init = &(struct clk_init_data) {
1768
+
.hw.init = &(const struct clk_init_data) {
1804
1769
.name = "gcc_pcie2_aux_clk",
1805
1770
.parent_hws = (const struct clk_hw *[]) {
1806
1771
&pcie_aux_clk_src.clkr.hw
···
1817
1782
.clkr = {
1818
1783
.enable_reg = 0x2b034,
1819
1784
.enable_mask = BIT(0),
1820
-
.hw.init = &(struct clk_init_data) {
1785
+
.hw.init = &(const struct clk_init_data) {
1821
1786
.name = "gcc_pcie3_aux_clk",
1822
1787
.parent_hws = (const struct clk_hw *[]) {
1823
1788
&pcie_aux_clk_src.clkr.hw
···
1840
1805
.mnd_width = 16,
1841
1806
.hid_width = 5,
1842
1807
.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1843
-
.clkr.hw.init = &(struct clk_init_data) {
1808
+
.clkr.hw.init = &(const struct clk_init_data) {
1844
1809
.name = "usb0_aux_clk_src",
1845
1810
.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1846
1811
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
···
1853
1818
.clkr = {
1854
1819
.enable_reg = 0x2c048,
1855
1820
.enable_mask = BIT(0),
1856
-
.hw.init = &(struct clk_init_data) {
1821
+
.hw.init = &(const struct clk_init_data) {
1857
1822
.name = "gcc_usb0_aux_clk",
1858
1823
.parent_hws = (const struct clk_hw *[]) {
1859
1824
&usb0_aux_clk_src.clkr.hw
···
1877
1842
.mnd_width = 8,
1878
1843
.hid_width = 5,
1879
1844
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1880
-
.clkr.hw.init = &(struct clk_init_data) {
1845
+
.clkr.hw.init = &(const struct clk_init_data) {
1881
1846
.name = "usb0_master_clk_src",
1882
1847
.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1883
1848
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
···
1890
1855
.clkr = {
1891
1856
.enable_reg = 0x2c044,
1892
1857
.enable_mask = BIT(0),
1893
-
.hw.init = &(struct clk_init_data) {
1858
+
.hw.init = &(const struct clk_init_data) {
1894
1859
.name = "gcc_usb0_master_clk",
1895
1860
.parent_hws = (const struct clk_hw *[]) {
1896
1861
&usb0_master_clk_src.clkr.hw
···
1907
1872
.clkr = {
1908
1873
.enable_reg = 0x2e058,
1909
1874
.enable_mask = BIT(0),
1910
-
.hw.init = &(struct clk_init_data) {
1875
+
.hw.init = &(const struct clk_init_data) {
1911
1876
.name = "gcc_snoc_usb_clk",
1912
1877
.parent_hws = (const struct clk_hw *[]) {
1913
1878
&usb0_master_clk_src.clkr.hw
···
1924
1889
.clkr = {
1925
1890
.enable_reg = 0x2e084,
1926
1891
.enable_mask = BIT(0),
1927
-
.hw.init = &(struct clk_init_data) {
1892
+
.hw.init = &(const struct clk_init_data) {
1928
1893
.name = "gcc_anoc_usb_axi_clk",
1929
1894
.parent_hws = (const struct clk_hw *[]) {
1930
1895
&usb0_master_clk_src.clkr.hw
···
1948
1913
.mnd_width = 8,
1949
1914
.hid_width = 5,
1950
1915
.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map,
1951
-
.clkr.hw.init = &(struct clk_init_data) {
1916
+
.clkr.hw.init = &(const struct clk_init_data) {
1952
1917
.name = "usb0_mock_utmi_clk_src",
1953
1918
.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1954
1919
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
···
1960
1925
.reg = 0x2c040,
1961
1926
.shift = 0,
1962
1927
.width = 2,
1963
-
.clkr.hw.init = &(struct clk_init_data) {
1928
+
.clkr.hw.init = &(const struct clk_init_data) {
1964
1929
.name = "usb0_mock_utmi_div_clk_src",
1965
1930
.parent_data = &(const struct clk_parent_data) {
1966
1931
.hw = &usb0_mock_utmi_clk_src.clkr.hw,
···
1976
1941
.clkr = {
1977
1942
.enable_reg = 0x2c04c,
1978
1943
.enable_mask = BIT(0),
1979
-
.hw.init = &(struct clk_init_data) {
1944
+
.hw.init = &(const struct clk_init_data) {
1980
1945
.name = "gcc_usb0_mock_utmi_clk",
1981
1946
.parent_hws = (const struct clk_hw *[]) {
1982
1947
&usb0_mock_utmi_div_clk_src.clkr.hw
···
1994
1959
.width = 2,
1995
1960
.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1996
1961
.clkr = {
1997
-
.hw.init = &(struct clk_init_data) {
1962
+
.hw.init = &(const struct clk_init_data) {
1998
1963
.name = "usb0_pipe_clk_src",
1999
1964
.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
2000
1965
.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
···
2023
1988
.mnd_width = 8,
2024
1989
.hid_width = 5,
2025
1990
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
2026
-
.clkr.hw.init = &(struct clk_init_data) {
1991
+
.clkr.hw.init = &(const struct clk_init_data) {
2027
1992
.name = "sdcc1_apps_clk_src",
2028
1993
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
2029
1994
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
···
2036
2001
.clkr = {
2037
2002
.enable_reg = 0x3302c,
2038
2003
.enable_mask = BIT(0),
2039
-
.hw.init = &(struct clk_init_data) {
2004
+
.hw.init = &(const struct clk_init_data) {
2040
2005
.name = "gcc_sdcc1_apps_clk",
2041
2006
.parent_hws = (const struct clk_hw *[]) {
2042
2007
&sdcc1_apps_clk_src.clkr.hw
···
2059
2024
.mnd_width = 8,
2060
2025
.hid_width = 5,
2061
2026
.parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map,
2062
-
.clkr.hw.init = &(struct clk_init_data) {
2027
+
.clkr.hw.init = &(const struct clk_init_data) {
2063
2028
.name = "sdcc1_ice_core_clk_src",
2064
2029
.parent_data = gcc_xo_gpll0_gpll4_gpll0_div2,
2065
2030
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2),
···
2072
2037
.clkr = {
2073
2038
.enable_reg = 0x33030,
2074
2039
.enable_mask = BIT(0),
2075
-
.hw.init = &(struct clk_init_data) {
2040
+
.hw.init = &(const struct clk_init_data) {
2076
2041
.name = "gcc_sdcc1_ice_core_clk",
2077
2042
.parent_hws = (const struct clk_hw *[]) {
2078
2043
&sdcc1_ice_core_clk_src.clkr.hw
···
2097
2062
.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
2098
2063
.hid_width = 5,
2099
2064
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
2100
-
.clkr.hw.init = &(struct clk_init_data) {
2065
+
.clkr.hw.init = &(const struct clk_init_data) {
2101
2066
.name = "pcnoc_bfdcd_clk_src",
2102
2067
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
2103
2068
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
2106
2071
},
2107
2072
};
2108
2073
2074
+
static struct clk_branch gcc_crypto_axi_clk = {
2075
+
.halt_reg = 0x16010,
2076
+
.clkr = {
2077
+
.enable_reg = 0x16010,
2078
+
.enable_mask = BIT(0),
2079
+
.hw.init = &(const struct clk_init_data) {
2080
+
.name = "gcc_crypto_axi_clk",
2081
+
.parent_hws = (const struct clk_hw *[]) {
2082
+
&pcnoc_bfdcd_clk_src.clkr.hw },
2083
+
.num_parents = 1,
2084
+
.flags = CLK_SET_RATE_PARENT,
2085
+
.ops = &clk_branch2_ops,
2086
+
},
2087
+
},
2088
+
};
2089
+
2090
+
static struct clk_branch gcc_crypto_ahb_clk = {
2091
+
.halt_reg = 0x16014,
2092
+
.clkr = {
2093
+
.enable_reg = 0x16014,
2094
+
.enable_mask = BIT(0),
2095
+
.hw.init = &(const struct clk_init_data) {
2096
+
.name = "gcc_crypto_ahb_clk",
2097
+
.parent_hws = (const struct clk_hw *[]) {
2098
+
&pcnoc_bfdcd_clk_src.clkr.hw },
2099
+
.num_parents = 1,
2100
+
.flags = CLK_SET_RATE_PARENT,
2101
+
.ops = &clk_branch2_ops,
2102
+
},
2103
+
},
2104
+
};
2105
+
2109
2106
static struct clk_branch gcc_nsscfg_clk = {
2110
2107
.halt_reg = 0x1702c,
2111
2108
.clkr = {
2112
2109
.enable_reg = 0x1702c,
2113
2110
.enable_mask = BIT(0),
2114
-
.hw.init = &(struct clk_init_data) {
2111
+
.hw.init = &(const struct clk_init_data) {
2115
2112
.name = "gcc_nsscfg_clk",
2116
2113
.parent_hws = (const struct clk_hw *[]) {
2117
2114
&pcnoc_bfdcd_clk_src.clkr.hw
···
2160
2093
.clkr = {
2161
2094
.enable_reg = 0x17030,
2162
2095
.enable_mask = BIT(0),
2163
-
.hw.init = &(struct clk_init_data) {
2096
+
.hw.init = &(const struct clk_init_data) {
2164
2097
.name = "gcc_nssnoc_nsscc_clk",
2165
2098
.parent_hws = (const struct clk_hw *[]) {
2166
2099
&pcnoc_bfdcd_clk_src.clkr.hw
···
2177
2110
.clkr = {
2178
2111
.enable_reg = 0x17034,
2179
2112
.enable_mask = BIT(0),
2180
-
.hw.init = &(struct clk_init_data) {
2113
+
.hw.init = &(const struct clk_init_data) {
2181
2114
.name = "gcc_nsscc_clk",
2182
2115
.parent_hws = (const struct clk_hw *[]) {
2183
2116
&pcnoc_bfdcd_clk_src.clkr.hw
···
2194
2127
.clkr = {
2195
2128
.enable_reg = 0x17080,
2196
2129
.enable_mask = BIT(0),
2197
-
.hw.init = &(struct clk_init_data) {
2130
+
.hw.init = &(const struct clk_init_data) {
2198
2131
.name = "gcc_nssnoc_pcnoc_1_clk",
2199
2132
.parent_hws = (const struct clk_hw *[]) {
2200
2133
&pcnoc_bfdcd_clk_src.clkr.hw
···
2211
2144
.clkr = {
2212
2145
.enable_reg = 0x2d064,
2213
2146
.enable_mask = BIT(0),
2214
-
.hw.init = &(struct clk_init_data) {
2147
+
.hw.init = &(const struct clk_init_data) {
2215
2148
.name = "gcc_qdss_dap_ahb_clk",
2216
2149
.parent_hws = (const struct clk_hw *[]) {
2217
2150
&pcnoc_bfdcd_clk_src.clkr.hw
···
2228
2161
.clkr = {
2229
2162
.enable_reg = 0x2d068,
2230
2163
.enable_mask = BIT(0),
2231
-
.hw.init = &(struct clk_init_data) {
2164
+
.hw.init = &(const struct clk_init_data) {
2232
2165
.name = "gcc_qdss_cfg_ahb_clk",
2233
2166
.parent_hws = (const struct clk_hw *[]) {
2234
2167
&pcnoc_bfdcd_clk_src.clkr.hw
···
2245
2178
.clkr = {
2246
2179
.enable_reg = 0x32010,
2247
2180
.enable_mask = BIT(0),
2248
-
.hw.init = &(struct clk_init_data) {
2181
+
.hw.init = &(const struct clk_init_data) {
2249
2182
.name = "gcc_qpic_ahb_clk",
2250
2183
.parent_hws = (const struct clk_hw *[]) {
2251
2184
&pcnoc_bfdcd_clk_src.clkr.hw
···
2262
2195
.clkr = {
2263
2196
.enable_reg = 0x32014,
2264
2197
.enable_mask = BIT(0),
2265
-
.hw.init = &(struct clk_init_data) {
2198
+
.hw.init = &(const struct clk_init_data) {
2266
2199
.name = "gcc_qpic_clk",
2267
2200
.parent_hws = (const struct clk_hw *[]) {
2268
2201
&pcnoc_bfdcd_clk_src.clkr.hw
···
2280
2213
.clkr = {
2281
2214
.enable_reg = 0x0b004,
2282
2215
.enable_mask = BIT(4),
2283
-
.hw.init = &(struct clk_init_data) {
2216
+
.hw.init = &(const struct clk_init_data) {
2284
2217
.name = "gcc_blsp1_ahb_clk",
2285
2218
.parent_hws = (const struct clk_hw *[]) {
2286
2219
&pcnoc_bfdcd_clk_src.clkr.hw
···
2297
2230
.clkr = {
2298
2231
.enable_reg = 0x17040,
2299
2232
.enable_mask = BIT(0),
2300
-
.hw.init = &(struct clk_init_data) {
2233
+
.hw.init = &(const struct clk_init_data) {
2301
2234
.name = "gcc_mdio_ahb_clk",
2302
2235
.parent_hws = (const struct clk_hw *[]) {
2303
2236
&pcnoc_bfdcd_clk_src.clkr.hw
···
2315
2248
.clkr = {
2316
2249
.enable_reg = 0x0b004,
2317
2250
.enable_mask = BIT(10),
2318
-
.hw.init = &(struct clk_init_data) {
2251
+
.hw.init = &(const struct clk_init_data) {
2319
2252
.name = "gcc_prng_ahb_clk",
2320
2253
.parent_hws = (const struct clk_hw *[]) {
2321
2254
&pcnoc_bfdcd_clk_src.clkr.hw
···
2332
2265
.clkr = {
2333
2266
.enable_reg = 0x1704c,
2334
2267
.enable_mask = BIT(0),
2335
-
.hw.init = &(struct clk_init_data) {
2268
+
.hw.init = &(const struct clk_init_data) {
2336
2269
.name = "gcc_uniphy0_ahb_clk",
2337
2270
.parent_hws = (const struct clk_hw *[]) {
2338
2271
&pcnoc_bfdcd_clk_src.clkr.hw
···
2349
2282
.clkr = {
2350
2283
.enable_reg = 0x1705c,
2351
2284
.enable_mask = BIT(0),
2352
-
.hw.init = &(struct clk_init_data) {
2285
+
.hw.init = &(const struct clk_init_data) {
2353
2286
.name = "gcc_uniphy1_ahb_clk",
2354
2287
.parent_hws = (const struct clk_hw *[]) {
2355
2288
&pcnoc_bfdcd_clk_src.clkr.hw
···
2366
2299
.clkr = {
2367
2300
.enable_reg = 0x1706c,
2368
2301
.enable_mask = BIT(0),
2369
-
.hw.init = &(struct clk_init_data) {
2302
+
.hw.init = &(const struct clk_init_data) {
2370
2303
.name = "gcc_uniphy2_ahb_clk",
2371
2304
.parent_hws = (const struct clk_hw *[]) {
2372
2305
&pcnoc_bfdcd_clk_src.clkr.hw
···
2383
2316
.clkr = {
2384
2317
.enable_reg = 0x3a004,
2385
2318
.enable_mask = BIT(0),
2386
-
.hw.init = &(struct clk_init_data) {
2319
+
.hw.init = &(const struct clk_init_data) {
2387
2320
.name = "gcc_cmn_12gpll_ahb_clk",
2388
2321
.parent_hws = (const struct clk_hw *[]) {
2389
2322
&pcnoc_bfdcd_clk_src.clkr.hw
···
2400
2333
.clkr = {
2401
2334
.enable_reg = 0x3a00c,
2402
2335
.enable_mask = BIT(0),
2403
-
.hw.init = &(struct clk_init_data) {
2336
+
.hw.init = &(const struct clk_init_data) {
2404
2337
.name = "gcc_cmn_12gpll_apu_clk",
2405
2338
.parent_hws = (const struct clk_hw *[]) {
2406
2339
&pcnoc_bfdcd_clk_src.clkr.hw
···
2417
2350
.clkr = {
2418
2351
.enable_reg = 0x28030,
2419
2352
.enable_mask = BIT(0),
2420
-
.hw.init = &(struct clk_init_data) {
2353
+
.hw.init = &(const struct clk_init_data) {
2421
2354
.name = "gcc_pcie0_ahb_clk",
2422
2355
.parent_hws = (const struct clk_hw *[]) {
2423
2356
&pcnoc_bfdcd_clk_src.clkr.hw
···
2434
2367
.clkr = {
2435
2368
.enable_reg = 0x29030,
2436
2369
.enable_mask = BIT(0),
2437
-
.hw.init = &(struct clk_init_data) {
2370
+
.hw.init = &(const struct clk_init_data) {
2438
2371
.name = "gcc_pcie1_ahb_clk",
2439
2372
.parent_hws = (const struct clk_hw *[]) {
2440
2373
&pcnoc_bfdcd_clk_src.clkr.hw
···
2451
2384
.clkr = {
2452
2385
.enable_reg = 0x2a030,
2453
2386
.enable_mask = BIT(0),
2454
-
.hw.init = &(struct clk_init_data) {
2387
+
.hw.init = &(const struct clk_init_data) {
2455
2388
.name = "gcc_pcie2_ahb_clk",
2456
2389
.parent_hws = (const struct clk_hw *[]) {
2457
2390
&pcnoc_bfdcd_clk_src.clkr.hw
···
2468
2401
.clkr = {
2469
2402
.enable_reg = 0x2b030,
2470
2403
.enable_mask = BIT(0),
2471
-
.hw.init = &(struct clk_init_data) {
2404
+
.hw.init = &(const struct clk_init_data) {
2472
2405
.name = "gcc_pcie3_ahb_clk",
2473
2406
.parent_hws = (const struct clk_hw *[]) {
2474
2407
&pcnoc_bfdcd_clk_src.clkr.hw
···
2485
2418
.clkr = {
2486
2419
.enable_reg = 0x2c05c,
2487
2420
.enable_mask = BIT(0),
2488
-
.hw.init = &(struct clk_init_data) {
2421
+
.hw.init = &(const struct clk_init_data) {
2489
2422
.name = "gcc_usb0_phy_cfg_ahb_clk",
2490
2423
.parent_hws = (const struct clk_hw *[]) {
2491
2424
&pcnoc_bfdcd_clk_src.clkr.hw
···
2502
2435
.clkr = {
2503
2436
.enable_reg = 0x33034,
2504
2437
.enable_mask = BIT(0),
2505
-
.hw.init = &(struct clk_init_data) {
2438
+
.hw.init = &(const struct clk_init_data) {
2506
2439
.name = "gcc_sdcc1_ahb_clk",
2507
2440
.parent_hws = (const struct clk_hw *[]) {
2508
2441
&pcnoc_bfdcd_clk_src.clkr.hw
···
2527
2460
.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
2528
2461
.hid_width = 5,
2529
2462
.parent_map = gcc_xo_gpll0_gpll4_map,
2530
-
.clkr.hw.init = &(struct clk_init_data) {
2463
+
.clkr.hw.init = &(const struct clk_init_data) {
2531
2464
.name = "system_noc_bfdcd_clk_src",
2532
2465
.parent_data = gcc_xo_gpll0_gpll4,
2533
2466
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
···
2542
2475
.clkr = {
2543
2476
.enable_reg = 0x25080,
2544
2477
.enable_mask = BIT(0),
2545
-
.hw.init = &(struct clk_init_data) {
2478
+
.hw.init = &(const struct clk_init_data) {
2546
2479
.name = "gcc_q6ss_boot_clk",
2547
2480
.parent_hws = (const struct clk_hw *[]) {
2548
2481
&system_noc_bfdcd_clk_src.clkr.hw
···
2559
2492
.clkr = {
2560
2493
.enable_reg = 0x17028,
2561
2494
.enable_mask = BIT(0),
2562
-
.hw.init = &(struct clk_init_data) {
2495
+
.hw.init = &(const struct clk_init_data) {
2563
2496
.name = "gcc_nssnoc_snoc_clk",
2564
2497
.parent_hws = (const struct clk_hw *[]) {
2565
2498
&system_noc_bfdcd_clk_src.clkr.hw
···
2576
2509
.clkr = {
2577
2510
.enable_reg = 0x1707c,
2578
2511
.enable_mask = BIT(0),
2579
-
.hw.init = &(struct clk_init_data) {
2512
+
.hw.init = &(const struct clk_init_data) {
2580
2513
.name = "gcc_nssnoc_snoc_1_clk",
2581
2514
.parent_hws = (const struct clk_hw *[]) {
2582
2515
&system_noc_bfdcd_clk_src.clkr.hw
···
2593
2526
.clkr = {
2594
2527
.enable_reg = 0x2d060,
2595
2528
.enable_mask = BIT(0),
2596
-
.hw.init = &(struct clk_init_data) {
2529
+
.hw.init = &(const struct clk_init_data) {
2597
2530
.name = "gcc_qdss_etr_usb_clk",
2598
2531
.parent_hws = (const struct clk_hw *[]) {
2599
2532
&system_noc_bfdcd_clk_src.clkr.hw
···
2616
2549
.freq_tbl = ftbl_wcss_ahb_clk_src,
2617
2550
.hid_width = 5,
2618
2551
.parent_map = gcc_xo_gpll0_map,
2619
-
.clkr.hw.init = &(struct clk_init_data) {
2552
+
.clkr.hw.init = &(const struct clk_init_data) {
2620
2553
.name = "wcss_ahb_clk_src",
2621
2554
.parent_data = gcc_xo_gpll0,
2622
2555
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
···
2629
2562
.clkr = {
2630
2563
.enable_reg = 0x25014,
2631
2564
.enable_mask = BIT(0),
2632
-
.hw.init = &(struct clk_init_data) {
2565
+
.hw.init = &(const struct clk_init_data) {
2633
2566
.name = "gcc_q6_ahb_clk",
2634
2567
.parent_hws = (const struct clk_hw *[]) {
2635
2568
&wcss_ahb_clk_src.clkr.hw
···
2646
2579
.clkr = {
2647
2580
.enable_reg = 0x25018,
2648
2581
.enable_mask = BIT(0),
2649
-
.hw.init = &(struct clk_init_data) {
2582
+
.hw.init = &(const struct clk_init_data) {
2650
2583
.name = "gcc_q6_ahb_s_clk",
2651
2584
.parent_hws = (const struct clk_hw *[]) {
2652
2585
&wcss_ahb_clk_src.clkr.hw
···
2663
2596
.clkr = {
2664
2597
.enable_reg = 0x25058,
2665
2598
.enable_mask = BIT(0),
2666
-
.hw.init = &(struct clk_init_data) {
2599
+
.hw.init = &(const struct clk_init_data) {
2667
2600
.name = "gcc_wcss_ecahb_clk",
2668
2601
.parent_hws = (const struct clk_hw *[]) {
2669
2602
&wcss_ahb_clk_src.clkr.hw
···
2680
2613
.clkr = {
2681
2614
.enable_reg = 0x2505c,
2682
2615
.enable_mask = BIT(0),
2683
-
.hw.init = &(struct clk_init_data) {
2616
+
.hw.init = &(const struct clk_init_data) {
2684
2617
.name = "gcc_wcss_acmt_clk",
2685
2618
.parent_hws = (const struct clk_hw *[]) {
2686
2619
&wcss_ahb_clk_src.clkr.hw
···
2697
2630
.clkr = {
2698
2631
.enable_reg = 0x2e030,
2699
2632
.enable_mask = BIT(0),
2700
-
.hw.init = &(struct clk_init_data) {
2633
+
.hw.init = &(const struct clk_init_data) {
2701
2634
.name = "gcc_sys_noc_wcss_ahb_clk",
2702
2635
.parent_hws = (const struct clk_hw *[]) {
2703
2636
&wcss_ahb_clk_src.clkr.hw
···
2721
2654
.freq_tbl = ftbl_wcss_axi_m_clk_src,
2722
2655
.hid_width = 5,
2723
2656
.parent_map = gcc_xo_gpll0_map,
2724
-
.clkr.hw.init = &(struct clk_init_data) {
2657
+
.clkr.hw.init = &(const struct clk_init_data) {
2725
2658
.name = "wcss_axi_m_clk_src",
2726
2659
.parent_data = gcc_xo_gpll0,
2727
2660
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
···
2734
2667
.clkr = {
2735
2668
.enable_reg = 0x2e0a8,
2736
2669
.enable_mask = BIT(0),
2737
-
.hw.init = &(struct clk_init_data) {
2670
+
.hw.init = &(const struct clk_init_data) {
2738
2671
.name = "gcc_anoc_wcss_axi_m_clk",
2739
2672
.parent_hws = (const struct clk_hw *[]) {
2740
2673
&wcss_axi_m_clk_src.clkr.hw
···
2756
2689
.freq_tbl = ftbl_qdss_at_clk_src,
2757
2690
.hid_width = 5,
2758
2691
.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
2759
-
.clkr.hw.init = &(struct clk_init_data) {
2692
+
.clkr.hw.init = &(const struct clk_init_data) {
2760
2693
.name = "qdss_at_clk_src",
2761
2694
.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
2762
2695
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
···
2769
2702
.clkr = {
2770
2703
.enable_reg = 0x2501c,
2771
2704
.enable_mask = BIT(0),
2772
-
.hw.init = &(struct clk_init_data) {
2705
+
.hw.init = &(const struct clk_init_data) {
2773
2706
.name = "gcc_q6ss_atbm_clk",
2774
2707
.parent_hws = (const struct clk_hw *[]) {
2775
2708
&qdss_at_clk_src.clkr.hw
···
2786
2719
.clkr = {
2787
2720
.enable_reg = 0x2503c,
2788
2721
.enable_mask = BIT(0),
2789
-
.hw.init = &(struct clk_init_data) {
2722
+
.hw.init = &(const struct clk_init_data) {
2790
2723
.name = "gcc_wcss_dbg_ifc_atb_clk",
2791
2724
.parent_hws = (const struct clk_hw *[]) {
2792
2725
&qdss_at_clk_src.clkr.hw
···
2803
2736
.clkr = {
2804
2737
.enable_reg = 0x17014,
2805
2738
.enable_mask = BIT(0),
2806
-
.hw.init = &(struct clk_init_data) {
2739
+
.hw.init = &(const struct clk_init_data) {
2807
2740
.name = "gcc_nssnoc_atb_clk",
2808
2741
.parent_hws = (const struct clk_hw *[]) {
2809
2742
&qdss_at_clk_src.clkr.hw
···
2820
2753
.clkr = {
2821
2754
.enable_reg = 0x2d038,
2822
2755
.enable_mask = BIT(0),
2823
-
.hw.init = &(struct clk_init_data) {
2756
+
.hw.init = &(const struct clk_init_data) {
2824
2757
.name = "gcc_qdss_at_clk",
2825
2758
.parent_hws = (const struct clk_hw *[]) {
2826
2759
&qdss_at_clk_src.clkr.hw
···
2837
2770
.clkr = {
2838
2771
.enable_reg = 0x2e038,
2839
2772
.enable_mask = BIT(0),
2840
-
.hw.init = &(struct clk_init_data) {
2773
+
.hw.init = &(const struct clk_init_data) {
2841
2774
.name = "gcc_sys_noc_at_clk",
2842
2775
.parent_hws = (const struct clk_hw *[]) {
2843
2776
&qdss_at_clk_src.clkr.hw
···
2854
2787
.clkr = {
2855
2788
.enable_reg = 0x31024,
2856
2789
.enable_mask = BIT(0),
2857
-
.hw.init = &(struct clk_init_data) {
2790
+
.hw.init = &(const struct clk_init_data) {
2858
2791
.name = "gcc_pcnoc_at_clk",
2859
2792
.parent_hws = (const struct clk_hw *[]) {
2860
2793
&qdss_at_clk_src.clkr.hw
···
2869
2802
static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
2870
2803
.mult = 1,
2871
2804
.div = 6,
2872
-
.hw.init = &(struct clk_init_data) {
2805
+
.hw.init = &(const struct clk_init_data) {
2873
2806
.name = "gcc_eud_at_div_clk_src",
2874
2807
.parent_hws = (const struct clk_hw *[]) {
2875
2808
&qdss_at_clk_src.clkr.hw
···
2885
2818
.clkr = {
2886
2819
.enable_reg = 0x30004,
2887
2820
.enable_mask = BIT(0),
2888
-
.hw.init = &(struct clk_init_data) {
2821
+
.hw.init = &(const struct clk_init_data) {
2889
2822
.name = "gcc_usb0_eud_at_clk",
2890
2823
.parent_hws = (const struct clk_hw *[]) {
2891
2824
&gcc_eud_at_div_clk_src.hw
···
2902
2835
.clkr = {
2903
2836
.enable_reg = 0x2d06c,
2904
2837
.enable_mask = BIT(0),
2905
-
.hw.init = &(struct clk_init_data) {
2838
+
.hw.init = &(const struct clk_init_data) {
2906
2839
.name = "gcc_qdss_eud_at_clk",
2907
2840
.parent_hws = (const struct clk_hw *[]) {
2908
2841
&gcc_eud_at_div_clk_src.hw
···
2925
2858
.freq_tbl = ftbl_qdss_stm_clk_src,
2926
2859
.hid_width = 5,
2927
2860
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
2928
-
.clkr.hw.init = &(struct clk_init_data) {
2861
+
.clkr.hw.init = &(const struct clk_init_data) {
2929
2862
.name = "qdss_stm_clk_src",
2930
2863
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
2931
2864
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
···
2938
2871
.clkr = {
2939
2872
.enable_reg = 0x2d03c,
2940
2873
.enable_mask = BIT(0),
2941
-
.hw.init = &(struct clk_init_data) {
2874
+
.hw.init = &(const struct clk_init_data) {
2942
2875
.name = "gcc_qdss_stm_clk",
2943
2876
.parent_hws = (const struct clk_hw *[]) {
2944
2877
&qdss_stm_clk_src.clkr.hw
···
2955
2888
.clkr = {
2956
2889
.enable_reg = 0x2e034,
2957
2890
.enable_mask = BIT(0),
2958
-
.hw.init = &(struct clk_init_data) {
2891
+
.hw.init = &(const struct clk_init_data) {
2959
2892
.name = "gcc_sys_noc_qdss_stm_axi_clk",
2960
2893
.parent_hws = (const struct clk_hw *[]) {
2961
2894
&qdss_stm_clk_src.clkr.hw
···
2977
2910
.freq_tbl = ftbl_qdss_traceclkin_clk_src,
2978
2911
.hid_width = 5,
2979
2912
.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
2980
-
.clkr.hw.init = &(struct clk_init_data) {
2913
+
.clkr.hw.init = &(const struct clk_init_data) {
2981
2914
.name = "qdss_traceclkin_clk_src",
2982
2915
.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
2983
2916
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
···
2990
2923
.clkr = {
2991
2924
.enable_reg = 0x2d040,
2992
2925
.enable_mask = BIT(0),
2993
-
.hw.init = &(struct clk_init_data) {
2926
+
.hw.init = &(const struct clk_init_data) {
2994
2927
.name = "gcc_qdss_traceclkin_clk",
2995
2928
.parent_hws = (const struct clk_hw *[]) {
2996
2929
&qdss_traceclkin_clk_src.clkr.hw
···
3012
2945
.freq_tbl = ftbl_qdss_tsctr_clk_src,
3013
2946
.hid_width = 5,
3014
2947
.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
3015
-
.clkr.hw.init = &(struct clk_init_data) {
2948
+
.clkr.hw.init = &(const struct clk_init_data) {
3016
2949
.name = "qdss_tsctr_clk_src",
3017
2950
.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
3018
2951
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
···
3023
2956
static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
3024
2957
.mult = 1,
3025
2958
.div = 2,
3026
-
.hw.init = &(struct clk_init_data) {
2959
+
.hw.init = &(const struct clk_init_data) {
3027
2960
.name = "qdss_tsctr_div2_clk_src",
3028
2961
.parent_hws = (const struct clk_hw *[]) {
3029
2962
&qdss_tsctr_clk_src.clkr.hw
···
3039
2972
.clkr = {
3040
2973
.enable_reg = 0x25020,
3041
2974
.enable_mask = BIT(0),
3042
-
.hw.init = &(struct clk_init_data) {
2975
+
.hw.init = &(const struct clk_init_data) {
3043
2976
.name = "gcc_q6_tsctr_1to2_clk",
3044
2977
.parent_hws = (const struct clk_hw *[]) {
3045
2978
&qdss_tsctr_div2_clk_src.hw
···
3056
2989
.clkr = {
3057
2990
.enable_reg = 0x25040,
3058
2991
.enable_mask = BIT(0),
3059
-
.hw.init = &(struct clk_init_data) {
2992
+
.hw.init = &(const struct clk_init_data) {
3060
2993
.name = "gcc_wcss_dbg_ifc_nts_clk",
3061
2994
.parent_hws = (const struct clk_hw *[]) {
3062
2995
&qdss_tsctr_div2_clk_src.hw
···
3073
3006
.clkr = {
3074
3007
.enable_reg = 0x2d044,
3075
3008
.enable_mask = BIT(0),
3076
-
.hw.init = &(struct clk_init_data) {
3009
+
.hw.init = &(const struct clk_init_data) {
3077
3010
.name = "gcc_qdss_tsctr_div2_clk",
3078
3011
.parent_hws = (const struct clk_hw *[]) {
3079
3012
&qdss_tsctr_div2_clk_src.hw
···
3096
3029
.mnd_width = 8,
3097
3030
.hid_width = 5,
3098
3031
.parent_map = gcc_xo_map,
3099
-
.clkr.hw.init = &(struct clk_init_data) {
3032
+
.clkr.hw.init = &(const struct clk_init_data) {
3100
3033
.name = "uniphy_sys_clk_src",
3101
3034
.parent_data = gcc_xo_data,
3102
3035
.num_parents = ARRAY_SIZE(gcc_xo_data),
···
3110
3043
.mnd_width = 8,
3111
3044
.hid_width = 5,
3112
3045
.parent_map = gcc_xo_map,
3113
-
.clkr.hw.init = &(struct clk_init_data) {
3046
+
.clkr.hw.init = &(const struct clk_init_data) {
3114
3047
.name = "nss_ts_clk_src",
3115
3048
.parent_data = gcc_xo_data,
3116
3049
.num_parents = ARRAY_SIZE(gcc_xo_data),
···
3123
3056
.clkr = {
3124
3057
.enable_reg = 0x2d078,
3125
3058
.enable_mask = BIT(0),
3126
-
.hw.init = &(struct clk_init_data) {
3059
+
.hw.init = &(const struct clk_init_data) {
3127
3060
.name = "gcc_qdss_ts_clk",
3128
3061
.parent_hws = (const struct clk_hw *[]) {
3129
3062
&nss_ts_clk_src.clkr.hw
···
3138
3071
static struct clk_fixed_factor qdss_dap_sync_clk_src = {
3139
3072
.mult = 1,
3140
3073
.div = 4,
3141
-
.hw.init = &(struct clk_init_data) {
3074
+
.hw.init = &(const struct clk_init_data) {
3142
3075
.name = "qdss_dap_sync_clk_src",
3143
3076
.parent_hws = (const struct clk_hw *[]) {
3144
3077
&qdss_tsctr_clk_src.clkr.hw
···
3153
3086
.clkr = {
3154
3087
.enable_reg = 0x2d04c,
3155
3088
.enable_mask = BIT(0),
3156
-
.hw.init = &(struct clk_init_data) {
3089
+
.hw.init = &(const struct clk_init_data) {
3157
3090
.name = "gcc_qdss_tsctr_div4_clk",
3158
3091
.parent_hws = (const struct clk_hw *[]) {
3159
3092
&qdss_dap_sync_clk_src.hw
···
3168
3101
static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {
3169
3102
.mult = 1,
3170
3103
.div = 8,
3171
-
.hw.init = &(struct clk_init_data) {
3104
+
.hw.init = &(const struct clk_init_data) {
3172
3105
.name = "qdss_tsctr_div8_clk_src",
3173
3106
.parent_hws = (const struct clk_hw *[]) {
3174
3107
&qdss_tsctr_clk_src.clkr.hw
···
3183
3116
.clkr = {
3184
3117
.enable_reg = 0x17018,
3185
3118
.enable_mask = BIT(0),
3186
-
.hw.init = &(struct clk_init_data) {
3119
+
.hw.init = &(const struct clk_init_data) {
3187
3120
.name = "gcc_nss_ts_clk",
3188
3121
.parent_hws = (const struct clk_hw *[]) {
3189
3122
&nss_ts_clk_src.clkr.hw
···
3200
3133
.clkr = {
3201
3134
.enable_reg = 0x2d050,
3202
3135
.enable_mask = BIT(0),
3203
-
.hw.init = &(struct clk_init_data) {
3136
+
.hw.init = &(const struct clk_init_data) {
3204
3137
.name = "gcc_qdss_tsctr_div8_clk",
3205
3138
.parent_hws = (const struct clk_hw *[]) {
3206
3139
&qdss_tsctr_div8_clk_src.hw
···
3215
3148
static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {
3216
3149
.mult = 1,
3217
3150
.div = 16,
3218
-
.hw.init = &(struct clk_init_data) {
3151
+
.hw.init = &(const struct clk_init_data) {
3219
3152
.name = "qdss_tsctr_div16_clk_src",
3220
3153
.parent_hws = (const struct clk_hw *[]) {
3221
3154
&qdss_tsctr_clk_src.clkr.hw
···
3230
3163
.clkr = {
3231
3164
.enable_reg = 0x2d054,
3232
3165
.enable_mask = BIT(0),
3233
-
.hw.init = &(struct clk_init_data) {
3166
+
.hw.init = &(const struct clk_init_data) {
3234
3167
.name = "gcc_qdss_tsctr_div16_clk",
3235
3168
.parent_hws = (const struct clk_hw *[]) {
3236
3169
&qdss_tsctr_div16_clk_src.hw
···
3247
3180
.clkr = {
3248
3181
.enable_reg = 0x25024,
3249
3182
.enable_mask = BIT(0),
3250
-
.hw.init = &(struct clk_init_data) {
3183
+
.hw.init = &(const struct clk_init_data) {
3251
3184
.name = "gcc_q6ss_pclkdbg_clk",
3252
3185
.parent_hws = (const struct clk_hw *[]) {
3253
3186
&qdss_dap_sync_clk_src.hw
···
3264
3197
.clkr = {
3265
3198
.enable_reg = 0x25068,
3266
3199
.enable_mask = BIT(0),
3267
-
.hw.init = &(struct clk_init_data) {
3200
+
.hw.init = &(const struct clk_init_data) {
3268
3201
.name = "gcc_q6ss_trig_clk",
3269
3202
.parent_hws = (const struct clk_hw *[]) {
3270
3203
&qdss_dap_sync_clk_src.hw
···
3281
3214
.clkr = {
3282
3215
.enable_reg = 0x25038,
3283
3216
.enable_mask = BIT(0),
3284
-
.hw.init = &(struct clk_init_data) {
3217
+
.hw.init = &(const struct clk_init_data) {
3285
3218
.name = "gcc_wcss_dbg_ifc_apb_clk",
3286
3219
.parent_hws = (const struct clk_hw *[]) {
3287
3220
&qdss_dap_sync_clk_src.hw
···
3298
3231
.clkr = {
3299
3232
.enable_reg = 0x25044,
3300
3233
.enable_mask = BIT(0),
3301
-
.hw.init = &(struct clk_init_data) {
3234
+
.hw.init = &(const struct clk_init_data) {
3302
3235
.name = "gcc_wcss_dbg_ifc_dapbus_clk",
3303
3236
.parent_hws = (const struct clk_hw *[]) {
3304
3237
&qdss_dap_sync_clk_src.hw
···
3315
3248
.clkr = {
3316
3249
.enable_reg = 0x2d058,
3317
3250
.enable_mask = BIT(0),
3318
-
.hw.init = &(struct clk_init_data) {
3251
+
.hw.init = &(const struct clk_init_data) {
3319
3252
.name = "gcc_qdss_dap_clk",
3320
3253
.parent_hws = (const struct clk_hw *[]) {
3321
3254
&qdss_dap_sync_clk_src.hw
···
3332
3265
.clkr = {
3333
3266
.enable_reg = 0x2d05c,
3334
3267
.enable_mask = BIT(0),
3335
-
.hw.init = &(struct clk_init_data) {
3268
+
.hw.init = &(const struct clk_init_data) {
3336
3269
.name = "gcc_qdss_apb2jtag_clk",
3337
3270
.parent_hws = (const struct clk_hw *[]) {
3338
3271
&qdss_dap_sync_clk_src.hw
···
3347
3280
static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {
3348
3281
.mult = 1,
3349
3282
.div = 3,
3350
-
.hw.init = &(struct clk_init_data) {
3283
+
.hw.init = &(const struct clk_init_data) {
3351
3284
.name = "qdss_tsctr_div3_clk_src",
3352
3285
.parent_hws = (const struct clk_hw *[]) {
3353
3286
&qdss_tsctr_clk_src.clkr.hw
···
3362
3295
.clkr = {
3363
3296
.enable_reg = 0x2d048,
3364
3297
.enable_mask = BIT(0),
3365
-
.hw.init = &(struct clk_init_data) {
3298
+
.hw.init = &(const struct clk_init_data) {
3366
3299
.name = "gcc_qdss_tsctr_div3_clk",
3367
3300
.parent_hws = (const struct clk_hw *[]) {
3368
3301
&qdss_tsctr_div3_clk_src.hw
···
3388
3321
.freq_tbl = ftbl_qpic_io_macro_clk_src,
3389
3322
.hid_width = 5,
3390
3323
.parent_map = gcc_xo_gpll0_gpll2_map,
3391
-
.clkr.hw.init = &(struct clk_init_data) {
3324
+
.clkr.hw.init = &(const struct clk_init_data) {
3392
3325
.name = "qpic_io_macro_clk_src",
3393
3326
.parent_data = gcc_xo_gpll0_gpll2,
3394
3327
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
···
3401
3334
.clkr = {
3402
3335
.enable_reg = 0x3200c,
3403
3336
.enable_mask = BIT(0),
3404
-
.hw.init = &(struct clk_init_data){
3337
+
.hw.init = &(const struct clk_init_data){
3405
3338
.name = "gcc_qpic_io_macro_clk",
3406
3339
.parent_hws = (const struct clk_hw *[]){
3407
3340
&qpic_io_macro_clk_src.clkr.hw
···
3423
3356
.freq_tbl = ftbl_q6_axi_clk_src,
3424
3357
.hid_width = 5,
3425
3358
.parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,
3426
-
.clkr.hw.init = &(struct clk_init_data) {
3359
+
.clkr.hw.init = &(const struct clk_init_data) {
3427
3360
.name = "q6_axi_clk_src",
3428
3361
.parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,
3429
3362
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),
···
3436
3369
.clkr = {
3437
3370
.enable_reg = 0x2500c,
3438
3371
.enable_mask = BIT(0),
3439
-
.hw.init = &(struct clk_init_data) {
3372
+
.hw.init = &(const struct clk_init_data) {
3440
3373
.name = "gcc_q6_axim_clk",
3441
3374
.parent_hws = (const struct clk_hw *[]) {
3442
3375
&q6_axi_clk_src.clkr.hw
···
3454
3387
.clkr = {
3455
3388
.enable_reg = 0xb00c,
3456
3389
.enable_mask = BIT(6),
3457
-
.hw.init = &(struct clk_init_data) {
3390
+
.hw.init = &(const struct clk_init_data) {
3458
3391
.name = "gcc_wcss_q6_tbu_clk",
3459
3392
.parent_hws = (const struct clk_hw *[]) {
3460
3393
&q6_axi_clk_src.clkr.hw
···
3471
3404
.clkr = {
3472
3405
.enable_reg = 0x19010,
3473
3406
.enable_mask = BIT(0),
3474
-
.hw.init = &(struct clk_init_data) {
3407
+
.hw.init = &(const struct clk_init_data) {
3475
3408
.name = "gcc_mem_noc_q6_axi_clk",
3476
3409
.parent_hws = (const struct clk_hw *[]) {
3477
3410
&q6_axi_clk_src.clkr.hw
···
3500
3433
.freq_tbl = ftbl_q6_axim2_clk_src,
3501
3434
.hid_width = 5,
3502
3435
.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,
3503
-
.clkr.hw.init = &(struct clk_init_data) {
3436
+
.clkr.hw.init = &(const struct clk_init_data) {
3504
3437
.name = "q6_axim2_clk_src",
3505
3438
.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
3506
3439
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
···
3518
3451
.freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,
3519
3452
.hid_width = 5,
3520
3453
.parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,
3521
-
.clkr.hw.init = &(struct clk_init_data) {
3454
+
.clkr.hw.init = &(const struct clk_init_data) {
3522
3455
.name = "nssnoc_memnoc_bfdcd_clk_src",
3523
3456
.parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,
3524
3457
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),
···
3531
3464
.clkr = {
3532
3465
.enable_reg = 0x17024,
3533
3466
.enable_mask = BIT(0),
3534
-
.hw.init = &(struct clk_init_data) {
3467
+
.hw.init = &(const struct clk_init_data) {
3535
3468
.name = "gcc_nssnoc_memnoc_clk",
3536
3469
.parent_hws = (const struct clk_hw *[]) {
3537
3470
&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
···
3548
3481
.clkr = {
3549
3482
.enable_reg = 0x17084,
3550
3483
.enable_mask = BIT(0),
3551
-
.hw.init = &(struct clk_init_data) {
3484
+
.hw.init = &(const struct clk_init_data) {
3552
3485
.name = "gcc_nssnoc_mem_noc_1_clk",
3553
3486
.parent_hws = (const struct clk_hw *[]) {
3554
3487
&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
···
3565
3498
.clkr = {
3566
3499
.enable_reg = 0xb00c,
3567
3500
.enable_mask = BIT(4),
3568
-
.hw.init = &(struct clk_init_data) {
3501
+
.hw.init = &(const struct clk_init_data) {
3569
3502
.name = "gcc_nss_tbu_clk",
3570
3503
.parent_hws = (const struct clk_hw *[]) {
3571
3504
&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
···
3582
3515
.clkr = {
3583
3516
.enable_reg = 0x19014,
3584
3517
.enable_mask = BIT(0),
3585
-
.hw.init = &(struct clk_init_data) {
3518
+
.hw.init = &(const struct clk_init_data) {
3586
3519
.name = "gcc_mem_noc_nssnoc_clk",
3587
3520
.parent_hws = (const struct clk_hw *[]) {
3588
3521
&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
···
3604
3537
.freq_tbl = ftbl_lpass_axim_clk_src,
3605
3538
.hid_width = 5,
3606
3539
.parent_map = gcc_xo_gpll0_map,
3607
-
.clkr.hw.init = &(struct clk_init_data) {
3540
+
.clkr.hw.init = &(const struct clk_init_data) {
3608
3541
.name = "lpass_axim_clk_src",
3609
3542
.parent_data = gcc_xo_gpll0,
3610
3543
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
···
3617
3550
.freq_tbl = ftbl_lpass_axim_clk_src,
3618
3551
.hid_width = 5,
3619
3552
.parent_map = gcc_xo_gpll0_map,
3620
-
.clkr.hw.init = &(struct clk_init_data) {
3553
+
.clkr.hw.init = &(const struct clk_init_data) {
3621
3554
.name = "lpass_sway_clk_src",
3622
3555
.parent_data = gcc_xo_gpll0,
3623
3556
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
···
3636
3569
.freq_tbl = ftbl_adss_pwm_clk_src,
3637
3570
.hid_width = 5,
3638
3571
.parent_map = gcc_xo_gpll0_map,
3639
-
.clkr.hw.init = &(struct clk_init_data) {
3572
+
.clkr.hw.init = &(const struct clk_init_data) {
3640
3573
.name = "adss_pwm_clk_src",
3641
3574
.parent_data = gcc_xo_gpll0,
3642
3575
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
···
3649
3582
.clkr = {
3650
3583
.enable_reg = 0x1c00c,
3651
3584
.enable_mask = BIT(0),
3652
-
.hw.init = &(struct clk_init_data) {
3585
+
.hw.init = &(const struct clk_init_data) {
3653
3586
.name = "gcc_adss_pwm_clk",
3654
3587
.parent_hws = (const struct clk_hw *[]) {
3655
3588
&adss_pwm_clk_src.clkr.hw
···
3672
3605
.freq_tbl = ftbl_gp1_clk_src,
3673
3606
.hid_width = 5,
3674
3607
.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3675
-
.clkr.hw.init = &(struct clk_init_data) {
3608
+
.clkr.hw.init = &(const struct clk_init_data) {
3676
3609
.name = "gp1_clk_src",
3677
3610
.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3678
3611
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
···
3685
3618
.freq_tbl = ftbl_gp1_clk_src,
3686
3619
.hid_width = 5,
3687
3620
.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3688
-
.clkr.hw.init = &(struct clk_init_data) {
3621
+
.clkr.hw.init = &(const struct clk_init_data) {
3689
3622
.name = "gp2_clk_src",
3690
3623
.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3691
3624
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
···
3698
3631
.freq_tbl = ftbl_gp1_clk_src,
3699
3632
.hid_width = 5,
3700
3633
.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3701
-
.clkr.hw.init = &(struct clk_init_data) {
3634
+
.clkr.hw.init = &(const struct clk_init_data) {
3702
3635
.name = "gp3_clk_src",
3703
3636
.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3704
3637
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
···
3711
3644
.clkr = {
3712
3645
.enable_reg = 0x34004,
3713
3646
.enable_mask = BIT(1),
3714
-
.hw.init = &(struct clk_init_data) {
3647
+
.hw.init = &(const struct clk_init_data) {
3715
3648
.name = "gcc_xo_clk_src",
3716
3649
.parent_data = gcc_xo_data,
3717
3650
.num_parents = ARRAY_SIZE(gcc_xo_data),
···
3726
3659
.clkr = {
3727
3660
.enable_reg = 0x17074,
3728
3661
.enable_mask = BIT(0),
3729
-
.hw.init = &(struct clk_init_data) {
3662
+
.hw.init = &(const struct clk_init_data) {
3730
3663
.name = "gcc_nssnoc_xo_dcd_clk",
3731
3664
.parent_hws = (const struct clk_hw *[]) {
3732
3665
&gcc_xo_clk_src.clkr.hw
···
3743
3676
.clkr = {
3744
3677
.enable_reg = 0x34018,
3745
3678
.enable_mask = BIT(0),
3746
-
.hw.init = &(struct clk_init_data) {
3679
+
.hw.init = &(const struct clk_init_data) {
3747
3680
.name = "gcc_xo_clk",
3748
3681
.parent_hws = (const struct clk_hw *[]) {
3749
3682
&gcc_xo_clk_src.clkr.hw
···
3760
3693
.clkr = {
3761
3694
.enable_reg = 0x17048,
3762
3695
.enable_mask = BIT(0),
3763
-
.hw.init = &(struct clk_init_data) {
3696
+
.hw.init = &(const struct clk_init_data) {
3764
3697
.name = "gcc_uniphy0_sys_clk",
3765
3698
.parent_hws = (const struct clk_hw *[]) {
3766
3699
&uniphy_sys_clk_src.clkr.hw
···
3777
3710
.clkr = {
3778
3711
.enable_reg = 0x17058,
3779
3712
.enable_mask = BIT(0),
3780
-
.hw.init = &(struct clk_init_data) {
3713
+
.hw.init = &(const struct clk_init_data) {
3781
3714
.name = "gcc_uniphy1_sys_clk",
3782
3715
.parent_hws = (const struct clk_hw *[]) {
3783
3716
&uniphy_sys_clk_src.clkr.hw
···
3794
3727
.clkr = {
3795
3728
.enable_reg = 0x17068,
3796
3729
.enable_mask = BIT(0),
3797
-
.hw.init = &(struct clk_init_data) {
3730
+
.hw.init = &(const struct clk_init_data) {
3798
3731
.name = "gcc_uniphy2_sys_clk",
3799
3732
.parent_hws = (const struct clk_hw *[]) {
3800
3733
&uniphy_sys_clk_src.clkr.hw
···
3811
3744
.clkr = {
3812
3745
.enable_reg = 0x3a008,
3813
3746
.enable_mask = BIT(0),
3814
-
.hw.init = &(struct clk_init_data) {
3747
+
.hw.init = &(const struct clk_init_data) {
3815
3748
.name = "gcc_cmn_12gpll_sys_clk",
3816
3749
.parent_hws = (const struct clk_hw *[]) {
3817
3750
&uniphy_sys_clk_src.clkr.hw
···
3826
3759
static struct clk_fixed_factor gcc_xo_div4_clk_src = {
3827
3760
.mult = 1,
3828
3761
.div = 4,
3829
-
.hw.init = &(struct clk_init_data) {
3762
+
.hw.init = &(const struct clk_init_data) {
3830
3763
.name = "gcc_xo_div4_clk_src",
3831
3764
.parent_hws = (const struct clk_hw *[]) {
3832
3765
&gcc_xo_clk_src.clkr.hw
···
3842
3775
.clkr = {
3843
3776
.enable_reg = 0x1701c,
3844
3777
.enable_mask = BIT(0),
3845
-
.hw.init = &(struct clk_init_data) {
3778
+
.hw.init = &(const struct clk_init_data) {
3846
3779
.name = "gcc_nssnoc_qosgen_ref_clk",
3847
3780
.parent_hws = (const struct clk_hw *[]) {
3848
3781
&gcc_xo_div4_clk_src.hw
···
3859
3792
.clkr = {
3860
3793
.enable_reg = 0x17020,
3861
3794
.enable_mask = BIT(0),
3862
-
.hw.init = &(struct clk_init_data) {
3795
+
.hw.init = &(const struct clk_init_data) {
3863
3796
.name = "gcc_nssnoc_timeout_ref_clk",
3864
3797
.parent_hws = (const struct clk_hw *[]) {
3865
3798
&gcc_xo_div4_clk_src.hw
···
3876
3809
.clkr = {
3877
3810
.enable_reg = 0x3401c,
3878
3811
.enable_mask = BIT(0),
3879
-
.hw.init = &(struct clk_init_data) {
3812
+
.hw.init = &(const struct clk_init_data) {
3880
3813
.name = "gcc_xo_div4_clk",
3881
3814
.parent_hws = (const struct clk_hw *[]) {
3882
3815
&gcc_xo_div4_clk_src.hw
···
3947
3880
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3948
3881
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3949
3882
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3883
+
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3884
+
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3885
+
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3886
+
[GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr,
3950
3887
[PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
3951
3888
[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
3952
3889
[PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
···
4134
4063
[GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 },
4135
4064
[GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 },
4136
4065
[GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },
4066
+
[GCC_CRYPTO_BCR] = { 0x16000, 0 },
4137
4067
[GCC_DCC_BCR] = { 0x35000, 0 },
4138
4068
[GCC_DDRSS_BCR] = { 0x11000, 0 },
4139
4069
[GCC_IMEM_BCR] = { 0x0e000, 0 },
+31
-31
drivers/clk/qcom/gcc-qcm2290.c
+31
-31
drivers/clk/qcom/gcc-qcm2290.c
···
650
650
.name = "gcc_usb30_prim_mock_utmi_clk_src",
651
651
.parent_data = gcc_parents_0,
652
652
.num_parents = ARRAY_SIZE(gcc_parents_0),
653
-
.ops = &clk_rcg2_ops,
653
+
.ops = &clk_rcg2_shared_ops,
654
654
},
655
655
};
656
656
···
686
686
.name = "gcc_camss_axi_clk_src",
687
687
.parent_data = gcc_parents_4,
688
688
.num_parents = ARRAY_SIZE(gcc_parents_4),
689
-
.ops = &clk_rcg2_ops,
689
+
.ops = &clk_rcg2_shared_ops,
690
690
},
691
691
};
692
692
···
706
706
.name = "gcc_camss_cci_clk_src",
707
707
.parent_data = gcc_parents_9,
708
708
.num_parents = ARRAY_SIZE(gcc_parents_9),
709
-
.ops = &clk_rcg2_ops,
709
+
.ops = &clk_rcg2_shared_ops,
710
710
},
711
711
};
712
712
···
728
728
.name = "gcc_camss_csi0phytimer_clk_src",
729
729
.parent_data = gcc_parents_5,
730
730
.num_parents = ARRAY_SIZE(gcc_parents_5),
731
-
.ops = &clk_rcg2_ops,
731
+
.ops = &clk_rcg2_shared_ops,
732
732
},
733
733
};
734
734
···
742
742
.name = "gcc_camss_csi1phytimer_clk_src",
743
743
.parent_data = gcc_parents_5,
744
744
.num_parents = ARRAY_SIZE(gcc_parents_5),
745
-
.ops = &clk_rcg2_ops,
745
+
.ops = &clk_rcg2_shared_ops,
746
746
},
747
747
};
748
748
···
764
764
.parent_data = gcc_parents_3,
765
765
.num_parents = ARRAY_SIZE(gcc_parents_3),
766
766
.flags = CLK_OPS_PARENT_ENABLE,
767
-
.ops = &clk_rcg2_ops,
767
+
.ops = &clk_rcg2_shared_ops,
768
768
},
769
769
};
770
770
···
779
779
.parent_data = gcc_parents_3,
780
780
.num_parents = ARRAY_SIZE(gcc_parents_3),
781
781
.flags = CLK_OPS_PARENT_ENABLE,
782
-
.ops = &clk_rcg2_ops,
782
+
.ops = &clk_rcg2_shared_ops,
783
783
},
784
784
};
785
785
···
794
794
.parent_data = gcc_parents_3,
795
795
.num_parents = ARRAY_SIZE(gcc_parents_3),
796
796
.flags = CLK_OPS_PARENT_ENABLE,
797
-
.ops = &clk_rcg2_ops,
797
+
.ops = &clk_rcg2_shared_ops,
798
798
},
799
799
};
800
800
···
809
809
.parent_data = gcc_parents_3,
810
810
.num_parents = ARRAY_SIZE(gcc_parents_3),
811
811
.flags = CLK_OPS_PARENT_ENABLE,
812
-
.ops = &clk_rcg2_ops,
812
+
.ops = &clk_rcg2_shared_ops,
813
813
},
814
814
};
815
815
···
830
830
.name = "gcc_camss_ope_ahb_clk_src",
831
831
.parent_data = gcc_parents_6,
832
832
.num_parents = ARRAY_SIZE(gcc_parents_6),
833
-
.ops = &clk_rcg2_ops,
833
+
.ops = &clk_rcg2_shared_ops,
834
834
},
835
835
};
836
836
···
854
854
.parent_data = gcc_parents_6,
855
855
.num_parents = ARRAY_SIZE(gcc_parents_6),
856
856
.flags = CLK_SET_RATE_PARENT,
857
-
.ops = &clk_rcg2_ops,
857
+
.ops = &clk_rcg2_shared_ops,
858
858
},
859
859
};
860
860
···
888
888
.name = "gcc_camss_tfe_0_clk_src",
889
889
.parent_data = gcc_parents_7,
890
890
.num_parents = ARRAY_SIZE(gcc_parents_7),
891
-
.ops = &clk_rcg2_ops,
891
+
.ops = &clk_rcg2_shared_ops,
892
892
},
893
893
};
894
894
···
912
912
.name = "gcc_camss_tfe_0_csid_clk_src",
913
913
.parent_data = gcc_parents_8,
914
914
.num_parents = ARRAY_SIZE(gcc_parents_8),
915
-
.ops = &clk_rcg2_ops,
915
+
.ops = &clk_rcg2_shared_ops,
916
916
},
917
917
};
918
918
···
926
926
.name = "gcc_camss_tfe_1_clk_src",
927
927
.parent_data = gcc_parents_7,
928
928
.num_parents = ARRAY_SIZE(gcc_parents_7),
929
-
.ops = &clk_rcg2_ops,
929
+
.ops = &clk_rcg2_shared_ops,
930
930
},
931
931
};
932
932
···
940
940
.name = "gcc_camss_tfe_1_csid_clk_src",
941
941
.parent_data = gcc_parents_8,
942
942
.num_parents = ARRAY_SIZE(gcc_parents_8),
943
-
.ops = &clk_rcg2_ops,
943
+
.ops = &clk_rcg2_shared_ops,
944
944
},
945
945
};
946
946
···
963
963
.parent_data = gcc_parents_10,
964
964
.num_parents = ARRAY_SIZE(gcc_parents_10),
965
965
.flags = CLK_OPS_PARENT_ENABLE,
966
-
.ops = &clk_rcg2_ops,
966
+
.ops = &clk_rcg2_shared_ops,
967
967
},
968
968
};
969
969
···
984
984
.name = "gcc_camss_top_ahb_clk_src",
985
985
.parent_data = gcc_parents_4,
986
986
.num_parents = ARRAY_SIZE(gcc_parents_4),
987
-
.ops = &clk_rcg2_ops,
987
+
.ops = &clk_rcg2_shared_ops,
988
988
},
989
989
};
990
990
···
1006
1006
.name = "gcc_gp1_clk_src",
1007
1007
.parent_data = gcc_parents_2,
1008
1008
.num_parents = ARRAY_SIZE(gcc_parents_2),
1009
-
.ops = &clk_rcg2_ops,
1009
+
.ops = &clk_rcg2_shared_ops,
1010
1010
},
1011
1011
};
1012
1012
···
1020
1020
.name = "gcc_gp2_clk_src",
1021
1021
.parent_data = gcc_parents_2,
1022
1022
.num_parents = ARRAY_SIZE(gcc_parents_2),
1023
-
.ops = &clk_rcg2_ops,
1023
+
.ops = &clk_rcg2_shared_ops,
1024
1024
},
1025
1025
};
1026
1026
···
1034
1034
.name = "gcc_gp3_clk_src",
1035
1035
.parent_data = gcc_parents_2,
1036
1036
.num_parents = ARRAY_SIZE(gcc_parents_2),
1037
-
.ops = &clk_rcg2_ops,
1037
+
.ops = &clk_rcg2_shared_ops,
1038
1038
},
1039
1039
};
1040
1040
···
1054
1054
.name = "gcc_pdm2_clk_src",
1055
1055
.parent_data = gcc_parents_0,
1056
1056
.num_parents = ARRAY_SIZE(gcc_parents_0),
1057
-
.ops = &clk_rcg2_ops,
1057
+
.ops = &clk_rcg2_shared_ops,
1058
1058
},
1059
1059
};
1060
1060
···
1082
1082
.name = "gcc_qupv3_wrap0_s0_clk_src",
1083
1083
.parent_data = gcc_parents_1,
1084
1084
.num_parents = ARRAY_SIZE(gcc_parents_1),
1085
-
.ops = &clk_rcg2_ops,
1085
+
.ops = &clk_rcg2_shared_ops,
1086
1086
};
1087
1087
1088
1088
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
···
1098
1098
.name = "gcc_qupv3_wrap0_s1_clk_src",
1099
1099
.parent_data = gcc_parents_1,
1100
1100
.num_parents = ARRAY_SIZE(gcc_parents_1),
1101
-
.ops = &clk_rcg2_ops,
1101
+
.ops = &clk_rcg2_shared_ops,
1102
1102
};
1103
1103
1104
1104
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
···
1114
1114
.name = "gcc_qupv3_wrap0_s2_clk_src",
1115
1115
.parent_data = gcc_parents_1,
1116
1116
.num_parents = ARRAY_SIZE(gcc_parents_1),
1117
-
.ops = &clk_rcg2_ops,
1117
+
.ops = &clk_rcg2_shared_ops,
1118
1118
};
1119
1119
1120
1120
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
···
1130
1130
.name = "gcc_qupv3_wrap0_s3_clk_src",
1131
1131
.parent_data = gcc_parents_1,
1132
1132
.num_parents = ARRAY_SIZE(gcc_parents_1),
1133
-
.ops = &clk_rcg2_ops,
1133
+
.ops = &clk_rcg2_shared_ops,
1134
1134
};
1135
1135
1136
1136
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
···
1146
1146
.name = "gcc_qupv3_wrap0_s4_clk_src",
1147
1147
.parent_data = gcc_parents_1,
1148
1148
.num_parents = ARRAY_SIZE(gcc_parents_1),
1149
-
.ops = &clk_rcg2_ops,
1149
+
.ops = &clk_rcg2_shared_ops,
1150
1150
};
1151
1151
1152
1152
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
···
1162
1162
.name = "gcc_qupv3_wrap0_s5_clk_src",
1163
1163
.parent_data = gcc_parents_1,
1164
1164
.num_parents = ARRAY_SIZE(gcc_parents_1),
1165
-
.ops = &clk_rcg2_ops,
1165
+
.ops = &clk_rcg2_shared_ops,
1166
1166
};
1167
1167
1168
1168
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
···
1219
1219
.name = "gcc_sdcc1_ice_core_clk_src",
1220
1220
.parent_data = gcc_parents_0,
1221
1221
.num_parents = ARRAY_SIZE(gcc_parents_0),
1222
-
.ops = &clk_rcg2_ops,
1222
+
.ops = &clk_rcg2_shared_ops,
1223
1223
},
1224
1224
};
1225
1225
···
1266
1266
.name = "gcc_usb30_prim_master_clk_src",
1267
1267
.parent_data = gcc_parents_0,
1268
1268
.num_parents = ARRAY_SIZE(gcc_parents_0),
1269
-
.ops = &clk_rcg2_ops,
1269
+
.ops = &clk_rcg2_shared_ops,
1270
1270
},
1271
1271
};
1272
1272
···
1280
1280
.name = "gcc_usb3_prim_phy_aux_clk_src",
1281
1281
.parent_data = gcc_parents_13,
1282
1282
.num_parents = ARRAY_SIZE(gcc_parents_13),
1283
-
.ops = &clk_rcg2_ops,
1283
+
.ops = &clk_rcg2_shared_ops,
1284
1284
},
1285
1285
};
1286
1286
···
1303
1303
.parent_data = gcc_parents_14,
1304
1304
.num_parents = ARRAY_SIZE(gcc_parents_14),
1305
1305
.flags = CLK_SET_RATE_PARENT,
1306
-
.ops = &clk_rcg2_ops,
1306
+
.ops = &clk_rcg2_shared_ops,
1307
1307
},
1308
1308
};
1309
1309
+16
-2
drivers/clk/qcom/gcc-sc8280xp.c
+16
-2
drivers/clk/qcom/gcc-sc8280xp.c
···
9
9
#include <linux/kernel.h>
10
10
#include <linux/module.h>
11
11
#include <linux/of_device.h>
12
+
#include <linux/pm_runtime.h>
12
13
#include <linux/of.h>
13
14
#include <linux/regmap.h>
14
15
···
7422
7421
struct regmap *regmap;
7423
7422
int ret;
7424
7423
7424
+
ret = devm_pm_runtime_enable(&pdev->dev);
7425
+
if (ret)
7426
+
return ret;
7427
+
7428
+
ret = pm_runtime_resume_and_get(&pdev->dev);
7429
+
if (ret)
7430
+
return ret;
7431
+
7425
7432
regmap = qcom_cc_map(pdev, &gcc_sc8280xp_desc);
7426
-
if (IS_ERR(regmap))
7433
+
if (IS_ERR(regmap)) {
7434
+
pm_runtime_put(&pdev->dev);
7427
7435
return PTR_ERR(regmap);
7436
+
}
7428
7437
7429
7438
/*
7430
7439
* Keep the clocks always-ON
···
7456
7445
if (ret)
7457
7446
return ret;
7458
7447
7459
-
return qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap);
7448
+
ret = qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap);
7449
+
pm_runtime_put(&pdev->dev);
7450
+
7451
+
return ret;
7460
7452
}
7461
7453
7462
7454
static const struct of_device_id gcc_sc8280xp_match_table[] = {
-2
drivers/clk/qcom/gcc-sdm660.c
-2
drivers/clk/qcom/gcc-sdm660.c
+2970
drivers/clk/qcom/gcc-sdx75.c
+2970
drivers/clk/qcom/gcc-sdx75.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/module.h>
8
+
#include <linux/of_device.h>
9
+
#include <linux/regmap.h>
10
+
11
+
#include <dt-bindings/clock/qcom,sdx75-gcc.h>
12
+
13
+
#include "clk-alpha-pll.h"
14
+
#include "clk-branch.h"
15
+
#include "clk-rcg.h"
16
+
#include "clk-regmap.h"
17
+
#include "clk-regmap-divider.h"
18
+
#include "clk-regmap-mux.h"
19
+
#include "clk-regmap-phy-mux.h"
20
+
#include "gdsc.h"
21
+
#include "reset.h"
22
+
23
+
enum {
24
+
DT_BI_TCXO,
25
+
DT_SLEEP_CLK,
26
+
DT_EMAC0_SGMIIPHY_MAC_RCLK,
27
+
DT_EMAC0_SGMIIPHY_MAC_TCLK,
28
+
DT_EMAC0_SGMIIPHY_RCLK,
29
+
DT_EMAC0_SGMIIPHY_TCLK,
30
+
DT_EMAC1_SGMIIPHY_MAC_RCLK,
31
+
DT_EMAC1_SGMIIPHY_MAC_TCLK,
32
+
DT_EMAC1_SGMIIPHY_RCLK,
33
+
DT_EMAC1_SGMIIPHY_TCLK,
34
+
DT_PCIE20_PHY_AUX_CLK,
35
+
DT_PCIE_1_PIPE_CLK,
36
+
DT_PCIE_2_PIPE_CLK,
37
+
DT_PCIE_PIPE_CLK,
38
+
DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
39
+
};
40
+
41
+
enum {
42
+
P_BI_TCXO,
43
+
P_EMAC0_SGMIIPHY_MAC_RCLK,
44
+
P_EMAC0_SGMIIPHY_MAC_TCLK,
45
+
P_EMAC0_SGMIIPHY_RCLK,
46
+
P_EMAC0_SGMIIPHY_TCLK,
47
+
P_EMAC1_SGMIIPHY_MAC_RCLK,
48
+
P_EMAC1_SGMIIPHY_MAC_TCLK,
49
+
P_EMAC1_SGMIIPHY_RCLK,
50
+
P_EMAC1_SGMIIPHY_TCLK,
51
+
P_GPLL0_OUT_EVEN,
52
+
P_GPLL0_OUT_MAIN,
53
+
P_GPLL4_OUT_MAIN,
54
+
P_GPLL5_OUT_MAIN,
55
+
P_GPLL6_OUT_MAIN,
56
+
P_GPLL8_OUT_MAIN,
57
+
P_PCIE20_PHY_AUX_CLK,
58
+
P_PCIE_1_PIPE_CLK,
59
+
P_PCIE_2_PIPE_CLK,
60
+
P_PCIE_PIPE_CLK,
61
+
P_SLEEP_CLK,
62
+
P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
63
+
};
64
+
65
+
static struct clk_alpha_pll gpll0 = {
66
+
.offset = 0x0,
67
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
68
+
.clkr = {
69
+
.enable_reg = 0x7d000,
70
+
.enable_mask = BIT(0),
71
+
.hw.init = &(const struct clk_init_data) {
72
+
.name = "gpll0",
73
+
.parent_data = &(const struct clk_parent_data) {
74
+
.index = DT_BI_TCXO,
75
+
},
76
+
.num_parents = 1,
77
+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
78
+
},
79
+
},
80
+
};
81
+
82
+
static const struct clk_div_table post_div_table_gpll0_out_even[] = {
83
+
{ 0x1, 2 },
84
+
{ }
85
+
};
86
+
87
+
static struct clk_alpha_pll_postdiv gpll0_out_even = {
88
+
.offset = 0x0,
89
+
.post_div_shift = 10,
90
+
.post_div_table = post_div_table_gpll0_out_even,
91
+
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
92
+
.width = 4,
93
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
94
+
.clkr.hw.init = &(const struct clk_init_data) {
95
+
.name = "gpll0_out_even",
96
+
.parent_hws = (const struct clk_hw*[]) {
97
+
&gpll0.clkr.hw,
98
+
},
99
+
.num_parents = 1,
100
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
101
+
},
102
+
};
103
+
104
+
static struct clk_alpha_pll gpll4 = {
105
+
.offset = 0x4000,
106
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
107
+
.clkr = {
108
+
.enable_reg = 0x7d000,
109
+
.enable_mask = BIT(4),
110
+
.hw.init = &(const struct clk_init_data) {
111
+
.name = "gpll4",
112
+
.parent_data = &(const struct clk_parent_data) {
113
+
.index = DT_BI_TCXO,
114
+
},
115
+
.num_parents = 1,
116
+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
117
+
},
118
+
},
119
+
};
120
+
121
+
static struct clk_alpha_pll gpll5 = {
122
+
.offset = 0x5000,
123
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
124
+
.clkr = {
125
+
.enable_reg = 0x7d000,
126
+
.enable_mask = BIT(5),
127
+
.hw.init = &(const struct clk_init_data) {
128
+
.name = "gpll5",
129
+
.parent_data = &(const struct clk_parent_data) {
130
+
.index = DT_BI_TCXO,
131
+
},
132
+
.num_parents = 1,
133
+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
134
+
},
135
+
},
136
+
};
137
+
138
+
static struct clk_alpha_pll gpll6 = {
139
+
.offset = 0x6000,
140
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
141
+
.clkr = {
142
+
.enable_reg = 0x7d000,
143
+
.enable_mask = BIT(6),
144
+
.hw.init = &(const struct clk_init_data) {
145
+
.name = "gpll6",
146
+
.parent_data = &(const struct clk_parent_data) {
147
+
.index = DT_BI_TCXO,
148
+
},
149
+
.num_parents = 1,
150
+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
151
+
},
152
+
},
153
+
};
154
+
155
+
static struct clk_alpha_pll gpll8 = {
156
+
.offset = 0x8000,
157
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
158
+
.clkr = {
159
+
.enable_reg = 0x7d000,
160
+
.enable_mask = BIT(8),
161
+
.hw.init = &(const struct clk_init_data) {
162
+
.name = "gpll8",
163
+
.parent_data = &(const struct clk_parent_data) {
164
+
.index = DT_BI_TCXO,
165
+
},
166
+
.num_parents = 1,
167
+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
168
+
},
169
+
},
170
+
};
171
+
172
+
static const struct parent_map gcc_parent_map_0[] = {
173
+
{ P_BI_TCXO, 0 },
174
+
{ P_GPLL0_OUT_MAIN, 1 },
175
+
{ P_GPLL0_OUT_EVEN, 6 },
176
+
};
177
+
178
+
static const struct clk_parent_data gcc_parent_data_0[] = {
179
+
{ .index = DT_BI_TCXO },
180
+
{ .hw = &gpll0.clkr.hw },
181
+
{ .hw = &gpll0_out_even.clkr.hw },
182
+
};
183
+
184
+
static const struct parent_map gcc_parent_map_1[] = {
185
+
{ P_BI_TCXO, 0 },
186
+
{ P_GPLL0_OUT_MAIN, 1 },
187
+
{ P_GPLL4_OUT_MAIN, 2 },
188
+
{ P_GPLL5_OUT_MAIN, 5 },
189
+
{ P_GPLL0_OUT_EVEN, 6 },
190
+
};
191
+
192
+
static const struct clk_parent_data gcc_parent_data_1[] = {
193
+
{ .index = DT_BI_TCXO },
194
+
{ .hw = &gpll0.clkr.hw },
195
+
{ .hw = &gpll4.clkr.hw },
196
+
{ .hw = &gpll5.clkr.hw },
197
+
{ .hw = &gpll0_out_even.clkr.hw },
198
+
};
199
+
200
+
static const struct parent_map gcc_parent_map_2[] = {
201
+
{ P_BI_TCXO, 0 },
202
+
{ P_GPLL0_OUT_MAIN, 1 },
203
+
{ P_SLEEP_CLK, 5 },
204
+
{ P_GPLL0_OUT_EVEN, 6 },
205
+
};
206
+
207
+
static const struct clk_parent_data gcc_parent_data_2[] = {
208
+
{ .index = DT_BI_TCXO },
209
+
{ .hw = &gpll0.clkr.hw },
210
+
{ .index = DT_SLEEP_CLK },
211
+
{ .hw = &gpll0_out_even.clkr.hw },
212
+
};
213
+
214
+
static const struct parent_map gcc_parent_map_3[] = {
215
+
{ P_BI_TCXO, 0 },
216
+
{ P_SLEEP_CLK, 5 },
217
+
};
218
+
219
+
static const struct clk_parent_data gcc_parent_data_3[] = {
220
+
{ .index = DT_BI_TCXO },
221
+
{ .index = DT_SLEEP_CLK },
222
+
};
223
+
224
+
static const struct parent_map gcc_parent_map_4[] = {
225
+
{ P_BI_TCXO, 0 },
226
+
{ P_GPLL0_OUT_MAIN, 1 },
227
+
{ P_SLEEP_CLK, 5 },
228
+
};
229
+
230
+
static const struct clk_parent_data gcc_parent_data_4[] = {
231
+
{ .index = DT_BI_TCXO },
232
+
{ .hw = &gpll0.clkr.hw },
233
+
{ .index = DT_SLEEP_CLK },
234
+
};
235
+
236
+
static const struct parent_map gcc_parent_map_5[] = {
237
+
{ P_EMAC0_SGMIIPHY_RCLK, 0 },
238
+
{ P_BI_TCXO, 2 },
239
+
};
240
+
241
+
static const struct clk_parent_data gcc_parent_data_5[] = {
242
+
{ .index = DT_EMAC0_SGMIIPHY_RCLK },
243
+
{ .index = DT_BI_TCXO },
244
+
};
245
+
246
+
static const struct parent_map gcc_parent_map_6[] = {
247
+
{ P_EMAC0_SGMIIPHY_TCLK, 0 },
248
+
{ P_BI_TCXO, 2 },
249
+
};
250
+
251
+
static const struct clk_parent_data gcc_parent_data_6[] = {
252
+
{ .index = DT_EMAC0_SGMIIPHY_TCLK },
253
+
{ .index = DT_BI_TCXO },
254
+
};
255
+
256
+
static const struct parent_map gcc_parent_map_7[] = {
257
+
{ P_EMAC0_SGMIIPHY_MAC_RCLK, 0 },
258
+
{ P_BI_TCXO, 2 },
259
+
};
260
+
261
+
static const struct clk_parent_data gcc_parent_data_7[] = {
262
+
{ .index = DT_EMAC0_SGMIIPHY_MAC_RCLK },
263
+
{ .index = DT_BI_TCXO },
264
+
};
265
+
266
+
static const struct parent_map gcc_parent_map_8[] = {
267
+
{ P_EMAC0_SGMIIPHY_MAC_TCLK, 0 },
268
+
{ P_BI_TCXO, 2 },
269
+
};
270
+
271
+
static const struct clk_parent_data gcc_parent_data_8[] = {
272
+
{ .index = DT_EMAC0_SGMIIPHY_MAC_TCLK },
273
+
{ .index = DT_BI_TCXO },
274
+
};
275
+
276
+
static const struct parent_map gcc_parent_map_9[] = {
277
+
{ P_EMAC1_SGMIIPHY_RCLK, 0 },
278
+
{ P_BI_TCXO, 2 },
279
+
};
280
+
281
+
static const struct clk_parent_data gcc_parent_data_9[] = {
282
+
{ .index = DT_EMAC1_SGMIIPHY_RCLK },
283
+
{ .index = DT_BI_TCXO },
284
+
};
285
+
286
+
static const struct parent_map gcc_parent_map_10[] = {
287
+
{ P_EMAC1_SGMIIPHY_TCLK, 0 },
288
+
{ P_BI_TCXO, 2 },
289
+
};
290
+
291
+
static const struct clk_parent_data gcc_parent_data_10[] = {
292
+
{ .index = DT_EMAC1_SGMIIPHY_TCLK },
293
+
{ .index = DT_BI_TCXO },
294
+
};
295
+
296
+
static const struct parent_map gcc_parent_map_11[] = {
297
+
{ P_EMAC1_SGMIIPHY_MAC_RCLK, 0 },
298
+
{ P_BI_TCXO, 2 },
299
+
};
300
+
301
+
static const struct clk_parent_data gcc_parent_data_11[] = {
302
+
{ .index = DT_EMAC1_SGMIIPHY_MAC_RCLK },
303
+
{ .index = DT_BI_TCXO },
304
+
};
305
+
306
+
static const struct parent_map gcc_parent_map_12[] = {
307
+
{ P_EMAC1_SGMIIPHY_MAC_TCLK, 0 },
308
+
{ P_BI_TCXO, 2 },
309
+
};
310
+
311
+
static const struct clk_parent_data gcc_parent_data_12[] = {
312
+
{ .index = DT_EMAC1_SGMIIPHY_MAC_TCLK },
313
+
{ .index = DT_BI_TCXO },
314
+
};
315
+
316
+
static const struct parent_map gcc_parent_map_15[] = {
317
+
{ P_PCIE20_PHY_AUX_CLK, 0 },
318
+
{ P_BI_TCXO, 2 },
319
+
};
320
+
321
+
static const struct clk_parent_data gcc_parent_data_15[] = {
322
+
{ .index = DT_PCIE20_PHY_AUX_CLK },
323
+
{ .index = DT_BI_TCXO },
324
+
};
325
+
326
+
static const struct parent_map gcc_parent_map_17[] = {
327
+
{ P_BI_TCXO, 0 },
328
+
{ P_GPLL0_OUT_MAIN, 1 },
329
+
{ P_GPLL6_OUT_MAIN, 2 },
330
+
{ P_GPLL0_OUT_EVEN, 6 },
331
+
};
332
+
333
+
static const struct clk_parent_data gcc_parent_data_17[] = {
334
+
{ .index = DT_BI_TCXO },
335
+
{ .hw = &gpll0.clkr.hw },
336
+
{ .hw = &gpll6.clkr.hw },
337
+
{ .hw = &gpll0_out_even.clkr.hw },
338
+
};
339
+
340
+
static const struct parent_map gcc_parent_map_18[] = {
341
+
{ P_BI_TCXO, 0 },
342
+
{ P_GPLL0_OUT_MAIN, 1 },
343
+
{ P_GPLL8_OUT_MAIN, 2 },
344
+
{ P_GPLL0_OUT_EVEN, 6 },
345
+
};
346
+
347
+
static const struct clk_parent_data gcc_parent_data_18[] = {
348
+
{ .index = DT_BI_TCXO },
349
+
{ .hw = &gpll0.clkr.hw },
350
+
{ .hw = &gpll8.clkr.hw },
351
+
{ .hw = &gpll0_out_even.clkr.hw },
352
+
};
353
+
354
+
static const struct parent_map gcc_parent_map_19[] = {
355
+
{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
356
+
{ P_BI_TCXO, 2 },
357
+
};
358
+
359
+
static const struct clk_parent_data gcc_parent_data_19[] = {
360
+
{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK },
361
+
{ .index = DT_BI_TCXO },
362
+
};
363
+
364
+
static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_rx_clk_src = {
365
+
.reg = 0x71060,
366
+
.shift = 0,
367
+
.width = 2,
368
+
.parent_map = gcc_parent_map_5,
369
+
.clkr = {
370
+
.hw.init = &(const struct clk_init_data) {
371
+
.name = "gcc_emac0_cc_sgmiiphy_rx_clk_src",
372
+
.parent_data = gcc_parent_data_5,
373
+
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
374
+
.ops = &clk_regmap_mux_closest_ops,
375
+
},
376
+
},
377
+
};
378
+
379
+
static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_tx_clk_src = {
380
+
.reg = 0x71058,
381
+
.shift = 0,
382
+
.width = 2,
383
+
.parent_map = gcc_parent_map_6,
384
+
.clkr = {
385
+
.hw.init = &(const struct clk_init_data) {
386
+
.name = "gcc_emac0_cc_sgmiiphy_tx_clk_src",
387
+
.parent_data = gcc_parent_data_6,
388
+
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
389
+
.ops = &clk_regmap_mux_closest_ops,
390
+
},
391
+
},
392
+
};
393
+
394
+
static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_rclk_src = {
395
+
.reg = 0x71098,
396
+
.shift = 0,
397
+
.width = 2,
398
+
.parent_map = gcc_parent_map_7,
399
+
.clkr = {
400
+
.hw.init = &(const struct clk_init_data) {
401
+
.name = "gcc_emac0_sgmiiphy_mac_rclk_src",
402
+
.parent_data = gcc_parent_data_7,
403
+
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
404
+
.ops = &clk_regmap_mux_closest_ops,
405
+
},
406
+
},
407
+
};
408
+
409
+
static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_tclk_src = {
410
+
.reg = 0x71094,
411
+
.shift = 0,
412
+
.width = 2,
413
+
.parent_map = gcc_parent_map_8,
414
+
.clkr = {
415
+
.hw.init = &(const struct clk_init_data) {
416
+
.name = "gcc_emac0_sgmiiphy_mac_tclk_src",
417
+
.parent_data = gcc_parent_data_8,
418
+
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
419
+
.ops = &clk_regmap_mux_closest_ops,
420
+
},
421
+
},
422
+
};
423
+
424
+
static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_rx_clk_src = {
425
+
.reg = 0x72060,
426
+
.shift = 0,
427
+
.width = 2,
428
+
.parent_map = gcc_parent_map_9,
429
+
.clkr = {
430
+
.hw.init = &(const struct clk_init_data) {
431
+
.name = "gcc_emac1_cc_sgmiiphy_rx_clk_src",
432
+
.parent_data = gcc_parent_data_9,
433
+
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
434
+
.ops = &clk_regmap_mux_closest_ops,
435
+
},
436
+
},
437
+
};
438
+
439
+
static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_tx_clk_src = {
440
+
.reg = 0x72058,
441
+
.shift = 0,
442
+
.width = 2,
443
+
.parent_map = gcc_parent_map_10,
444
+
.clkr = {
445
+
.hw.init = &(const struct clk_init_data) {
446
+
.name = "gcc_emac1_cc_sgmiiphy_tx_clk_src",
447
+
.parent_data = gcc_parent_data_10,
448
+
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
449
+
.ops = &clk_regmap_mux_closest_ops,
450
+
},
451
+
},
452
+
};
453
+
454
+
static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_rclk_src = {
455
+
.reg = 0x72098,
456
+
.shift = 0,
457
+
.width = 2,
458
+
.parent_map = gcc_parent_map_11,
459
+
.clkr = {
460
+
.hw.init = &(const struct clk_init_data) {
461
+
.name = "gcc_emac1_sgmiiphy_mac_rclk_src",
462
+
.parent_data = gcc_parent_data_11,
463
+
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
464
+
.ops = &clk_regmap_mux_closest_ops,
465
+
},
466
+
},
467
+
};
468
+
469
+
static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_tclk_src = {
470
+
.reg = 0x72094,
471
+
.shift = 0,
472
+
.width = 2,
473
+
.parent_map = gcc_parent_map_12,
474
+
.clkr = {
475
+
.hw.init = &(const struct clk_init_data) {
476
+
.name = "gcc_emac1_sgmiiphy_mac_tclk_src",
477
+
.parent_data = gcc_parent_data_12,
478
+
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
479
+
.ops = &clk_regmap_mux_closest_ops,
480
+
},
481
+
},
482
+
};
483
+
484
+
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
485
+
.reg = 0x67084,
486
+
.clkr = {
487
+
.hw.init = &(const struct clk_init_data) {
488
+
.name = "gcc_pcie_1_pipe_clk_src",
489
+
.parent_data = &(const struct clk_parent_data) {
490
+
.index = DT_PCIE_1_PIPE_CLK,
491
+
},
492
+
.num_parents = 1,
493
+
.ops = &clk_regmap_phy_mux_ops,
494
+
},
495
+
},
496
+
};
497
+
498
+
static struct clk_regmap_phy_mux gcc_pcie_2_pipe_clk_src = {
499
+
.reg = 0x68050,
500
+
.clkr = {
501
+
.hw.init = &(const struct clk_init_data) {
502
+
.name = "gcc_pcie_2_pipe_clk_src",
503
+
.parent_data = &(const struct clk_parent_data) {
504
+
.index = DT_PCIE_2_PIPE_CLK,
505
+
},
506
+
.num_parents = 1,
507
+
.ops = &clk_regmap_phy_mux_ops,
508
+
},
509
+
},
510
+
};
511
+
512
+
static struct clk_regmap_mux gcc_pcie_aux_clk_src = {
513
+
.reg = 0x53074,
514
+
.shift = 0,
515
+
.width = 2,
516
+
.parent_map = gcc_parent_map_15,
517
+
.clkr = {
518
+
.hw.init = &(const struct clk_init_data) {
519
+
.name = "gcc_pcie_aux_clk_src",
520
+
.parent_data = gcc_parent_data_15,
521
+
.num_parents = ARRAY_SIZE(gcc_parent_data_15),
522
+
.ops = &clk_regmap_mux_closest_ops,
523
+
},
524
+
},
525
+
};
526
+
527
+
static struct clk_regmap_phy_mux gcc_pcie_pipe_clk_src = {
528
+
.reg = 0x53058,
529
+
.clkr = {
530
+
.hw.init = &(const struct clk_init_data) {
531
+
.name = "gcc_pcie_pipe_clk_src",
532
+
.parent_data = &(const struct clk_parent_data) {
533
+
.index = DT_PCIE_PIPE_CLK,
534
+
},
535
+
.num_parents = 1,
536
+
.ops = &clk_regmap_phy_mux_ops,
537
+
},
538
+
},
539
+
};
540
+
541
+
static struct clk_regmap_mux gcc_usb3_phy_pipe_clk_src = {
542
+
.reg = 0x27070,
543
+
.shift = 0,
544
+
.width = 2,
545
+
.parent_map = gcc_parent_map_19,
546
+
.clkr = {
547
+
.hw.init = &(const struct clk_init_data) {
548
+
.name = "gcc_usb3_phy_pipe_clk_src",
549
+
.parent_data = gcc_parent_data_19,
550
+
.num_parents = ARRAY_SIZE(gcc_parent_data_19),
551
+
.ops = &clk_regmap_mux_closest_ops,
552
+
},
553
+
},
554
+
};
555
+
556
+
static const struct freq_tbl ftbl_gcc_eee_emac0_clk_src[] = {
557
+
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
558
+
{ }
559
+
};
560
+
561
+
static struct clk_rcg2 gcc_eee_emac0_clk_src = {
562
+
.cmd_rcgr = 0x710b0,
563
+
.mnd_width = 16,
564
+
.hid_width = 5,
565
+
.parent_map = gcc_parent_map_2,
566
+
.freq_tbl = ftbl_gcc_eee_emac0_clk_src,
567
+
.clkr.hw.init = &(const struct clk_init_data) {
568
+
.name = "gcc_eee_emac0_clk_src",
569
+
.parent_data = gcc_parent_data_2,
570
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
571
+
.ops = &clk_rcg2_shared_ops,
572
+
},
573
+
};
574
+
575
+
static struct clk_rcg2 gcc_eee_emac1_clk_src = {
576
+
.cmd_rcgr = 0x720b0,
577
+
.mnd_width = 16,
578
+
.hid_width = 5,
579
+
.parent_map = gcc_parent_map_2,
580
+
.freq_tbl = ftbl_gcc_eee_emac0_clk_src,
581
+
.clkr.hw.init = &(const struct clk_init_data) {
582
+
.name = "gcc_eee_emac1_clk_src",
583
+
.parent_data = gcc_parent_data_2,
584
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
585
+
.ops = &clk_rcg2_shared_ops,
586
+
},
587
+
};
588
+
589
+
static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = {
590
+
F(19200000, P_BI_TCXO, 1, 0, 0),
591
+
{ }
592
+
};
593
+
594
+
static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = {
595
+
.cmd_rcgr = 0x7102c,
596
+
.mnd_width = 0,
597
+
.hid_width = 5,
598
+
.parent_map = gcc_parent_map_4,
599
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
600
+
.clkr.hw.init = &(const struct clk_init_data) {
601
+
.name = "gcc_emac0_phy_aux_clk_src",
602
+
.parent_data = gcc_parent_data_4,
603
+
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
604
+
.ops = &clk_rcg2_shared_ops,
605
+
},
606
+
};
607
+
608
+
static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {
609
+
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
610
+
F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0),
611
+
F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0),
612
+
{ }
613
+
};
614
+
615
+
static struct clk_rcg2 gcc_emac0_ptp_clk_src = {
616
+
.cmd_rcgr = 0x7107c,
617
+
.mnd_width = 16,
618
+
.hid_width = 5,
619
+
.parent_map = gcc_parent_map_1,
620
+
.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
621
+
.clkr.hw.init = &(const struct clk_init_data) {
622
+
.name = "gcc_emac0_ptp_clk_src",
623
+
.parent_data = gcc_parent_data_1,
624
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
625
+
.ops = &clk_rcg2_shared_ops,
626
+
},
627
+
};
628
+
629
+
static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {
630
+
F(5000000, P_GPLL0_OUT_EVEN, 10, 1, 6),
631
+
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
632
+
F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0),
633
+
F(250000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
634
+
{ }
635
+
};
636
+
637
+
static struct clk_rcg2 gcc_emac0_rgmii_clk_src = {
638
+
.cmd_rcgr = 0x71064,
639
+
.mnd_width = 16,
640
+
.hid_width = 5,
641
+
.parent_map = gcc_parent_map_1,
642
+
.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
643
+
.clkr.hw.init = &(const struct clk_init_data) {
644
+
.name = "gcc_emac0_rgmii_clk_src",
645
+
.parent_data = gcc_parent_data_1,
646
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
647
+
.ops = &clk_rcg2_shared_ops,
648
+
},
649
+
};
650
+
651
+
static struct clk_rcg2 gcc_emac1_phy_aux_clk_src = {
652
+
.cmd_rcgr = 0x7202c,
653
+
.mnd_width = 0,
654
+
.hid_width = 5,
655
+
.parent_map = gcc_parent_map_4,
656
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
657
+
.clkr.hw.init = &(const struct clk_init_data) {
658
+
.name = "gcc_emac1_phy_aux_clk_src",
659
+
.parent_data = gcc_parent_data_4,
660
+
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
661
+
.ops = &clk_rcg2_shared_ops,
662
+
},
663
+
};
664
+
665
+
static struct clk_rcg2 gcc_emac1_ptp_clk_src = {
666
+
.cmd_rcgr = 0x7207c,
667
+
.mnd_width = 16,
668
+
.hid_width = 5,
669
+
.parent_map = gcc_parent_map_1,
670
+
.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
671
+
.clkr.hw.init = &(const struct clk_init_data) {
672
+
.name = "gcc_emac1_ptp_clk_src",
673
+
.parent_data = gcc_parent_data_1,
674
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
675
+
.ops = &clk_rcg2_shared_ops,
676
+
},
677
+
};
678
+
679
+
static struct clk_rcg2 gcc_emac1_rgmii_clk_src = {
680
+
.cmd_rcgr = 0x72064,
681
+
.mnd_width = 16,
682
+
.hid_width = 5,
683
+
.parent_map = gcc_parent_map_1,
684
+
.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
685
+
.clkr.hw.init = &(const struct clk_init_data) {
686
+
.name = "gcc_emac1_rgmii_clk_src",
687
+
.parent_data = gcc_parent_data_1,
688
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
689
+
.ops = &clk_rcg2_shared_ops,
690
+
},
691
+
};
692
+
693
+
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
694
+
F(19200000, P_BI_TCXO, 1, 0, 0),
695
+
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
696
+
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
697
+
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
698
+
{ }
699
+
};
700
+
701
+
static struct clk_rcg2 gcc_gp1_clk_src = {
702
+
.cmd_rcgr = 0x47004,
703
+
.mnd_width = 16,
704
+
.hid_width = 5,
705
+
.parent_map = gcc_parent_map_2,
706
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
707
+
.clkr.hw.init = &(const struct clk_init_data) {
708
+
.name = "gcc_gp1_clk_src",
709
+
.parent_data = gcc_parent_data_2,
710
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
711
+
.ops = &clk_rcg2_shared_ops,
712
+
},
713
+
};
714
+
715
+
static struct clk_rcg2 gcc_gp2_clk_src = {
716
+
.cmd_rcgr = 0x48004,
717
+
.mnd_width = 16,
718
+
.hid_width = 5,
719
+
.parent_map = gcc_parent_map_2,
720
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
721
+
.clkr.hw.init = &(const struct clk_init_data) {
722
+
.name = "gcc_gp2_clk_src",
723
+
.parent_data = gcc_parent_data_2,
724
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
725
+
.ops = &clk_rcg2_shared_ops,
726
+
},
727
+
};
728
+
729
+
static struct clk_rcg2 gcc_gp3_clk_src = {
730
+
.cmd_rcgr = 0x49004,
731
+
.mnd_width = 16,
732
+
.hid_width = 5,
733
+
.parent_map = gcc_parent_map_2,
734
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
735
+
.clkr.hw.init = &(const struct clk_init_data) {
736
+
.name = "gcc_gp3_clk_src",
737
+
.parent_data = gcc_parent_data_2,
738
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
739
+
.ops = &clk_rcg2_shared_ops,
740
+
},
741
+
};
742
+
743
+
static struct clk_rcg2 gcc_pcie_1_aux_phy_clk_src = {
744
+
.cmd_rcgr = 0x67044,
745
+
.mnd_width = 16,
746
+
.hid_width = 5,
747
+
.parent_map = gcc_parent_map_3,
748
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
749
+
.clkr.hw.init = &(const struct clk_init_data) {
750
+
.name = "gcc_pcie_1_aux_phy_clk_src",
751
+
.parent_data = gcc_parent_data_3,
752
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
753
+
.ops = &clk_rcg2_shared_ops,
754
+
},
755
+
};
756
+
757
+
static const struct freq_tbl ftbl_gcc_pcie_1_phy_rchng_clk_src[] = {
758
+
F(19200000, P_BI_TCXO, 1, 0, 0),
759
+
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
760
+
{ }
761
+
};
762
+
763
+
static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
764
+
.cmd_rcgr = 0x6706c,
765
+
.mnd_width = 0,
766
+
.hid_width = 5,
767
+
.parent_map = gcc_parent_map_2,
768
+
.freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src,
769
+
.clkr.hw.init = &(const struct clk_init_data) {
770
+
.name = "gcc_pcie_1_phy_rchng_clk_src",
771
+
.parent_data = gcc_parent_data_2,
772
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
773
+
.ops = &clk_rcg2_shared_ops,
774
+
},
775
+
};
776
+
777
+
static struct clk_rcg2 gcc_pcie_2_aux_phy_clk_src = {
778
+
.cmd_rcgr = 0x68064,
779
+
.mnd_width = 16,
780
+
.hid_width = 5,
781
+
.parent_map = gcc_parent_map_3,
782
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
783
+
.clkr.hw.init = &(const struct clk_init_data) {
784
+
.name = "gcc_pcie_2_aux_phy_clk_src",
785
+
.parent_data = gcc_parent_data_3,
786
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
787
+
.ops = &clk_rcg2_shared_ops,
788
+
},
789
+
};
790
+
791
+
static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = {
792
+
.cmd_rcgr = 0x68038,
793
+
.mnd_width = 0,
794
+
.hid_width = 5,
795
+
.parent_map = gcc_parent_map_2,
796
+
.freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src,
797
+
.clkr.hw.init = &(const struct clk_init_data) {
798
+
.name = "gcc_pcie_2_phy_rchng_clk_src",
799
+
.parent_data = gcc_parent_data_2,
800
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
801
+
.ops = &clk_rcg2_shared_ops,
802
+
},
803
+
};
804
+
805
+
static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = {
806
+
.cmd_rcgr = 0x5305c,
807
+
.mnd_width = 16,
808
+
.hid_width = 5,
809
+
.parent_map = gcc_parent_map_3,
810
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
811
+
.clkr.hw.init = &(const struct clk_init_data) {
812
+
.name = "gcc_pcie_aux_phy_clk_src",
813
+
.parent_data = gcc_parent_data_3,
814
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
815
+
.ops = &clk_rcg2_shared_ops,
816
+
},
817
+
};
818
+
819
+
static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = {
820
+
.cmd_rcgr = 0x53078,
821
+
.mnd_width = 0,
822
+
.hid_width = 5,
823
+
.parent_map = gcc_parent_map_2,
824
+
.freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src,
825
+
.clkr.hw.init = &(const struct clk_init_data) {
826
+
.name = "gcc_pcie_rchng_phy_clk_src",
827
+
.parent_data = gcc_parent_data_2,
828
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
829
+
.ops = &clk_rcg2_shared_ops,
830
+
},
831
+
};
832
+
833
+
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
834
+
F(19200000, P_BI_TCXO, 1, 0, 0),
835
+
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
836
+
{ }
837
+
};
838
+
839
+
static struct clk_rcg2 gcc_pdm2_clk_src = {
840
+
.cmd_rcgr = 0x34010,
841
+
.mnd_width = 0,
842
+
.hid_width = 5,
843
+
.parent_map = gcc_parent_map_0,
844
+
.freq_tbl = ftbl_gcc_pdm2_clk_src,
845
+
.clkr.hw.init = &(const struct clk_init_data) {
846
+
.name = "gcc_pdm2_clk_src",
847
+
.parent_data = gcc_parent_data_0,
848
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
849
+
.ops = &clk_rcg2_shared_ops,
850
+
},
851
+
};
852
+
853
+
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
854
+
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
855
+
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
856
+
F(19200000, P_BI_TCXO, 1, 0, 0),
857
+
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
858
+
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
859
+
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
860
+
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
861
+
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
862
+
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
863
+
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
864
+
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
865
+
{ }
866
+
};
867
+
868
+
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
869
+
.name = "gcc_qupv3_wrap0_s0_clk_src",
870
+
.parent_data = gcc_parent_data_0,
871
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
872
+
.ops = &clk_rcg2_shared_ops,
873
+
};
874
+
875
+
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
876
+
.cmd_rcgr = 0x6c010,
877
+
.mnd_width = 16,
878
+
.hid_width = 5,
879
+
.parent_map = gcc_parent_map_0,
880
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
881
+
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
882
+
};
883
+
884
+
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
885
+
.name = "gcc_qupv3_wrap0_s1_clk_src",
886
+
.parent_data = gcc_parent_data_0,
887
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
888
+
.ops = &clk_rcg2_shared_ops,
889
+
};
890
+
891
+
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
892
+
.cmd_rcgr = 0x6c148,
893
+
.mnd_width = 16,
894
+
.hid_width = 5,
895
+
.parent_map = gcc_parent_map_0,
896
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
897
+
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
898
+
};
899
+
900
+
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
901
+
.name = "gcc_qupv3_wrap0_s2_clk_src",
902
+
.parent_data = gcc_parent_data_0,
903
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
904
+
.ops = &clk_rcg2_shared_ops,
905
+
};
906
+
907
+
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
908
+
.cmd_rcgr = 0x6c280,
909
+
.mnd_width = 16,
910
+
.hid_width = 5,
911
+
.parent_map = gcc_parent_map_0,
912
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
913
+
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
914
+
};
915
+
916
+
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
917
+
.name = "gcc_qupv3_wrap0_s3_clk_src",
918
+
.parent_data = gcc_parent_data_0,
919
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
920
+
.ops = &clk_rcg2_shared_ops,
921
+
};
922
+
923
+
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
924
+
.cmd_rcgr = 0x6c3b8,
925
+
.mnd_width = 16,
926
+
.hid_width = 5,
927
+
.parent_map = gcc_parent_map_0,
928
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
929
+
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
930
+
};
931
+
932
+
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
933
+
.name = "gcc_qupv3_wrap0_s4_clk_src",
934
+
.parent_data = gcc_parent_data_0,
935
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
936
+
.ops = &clk_rcg2_shared_ops,
937
+
};
938
+
939
+
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
940
+
.cmd_rcgr = 0x6c4f0,
941
+
.mnd_width = 16,
942
+
.hid_width = 5,
943
+
.parent_map = gcc_parent_map_0,
944
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
945
+
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
946
+
};
947
+
948
+
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
949
+
.name = "gcc_qupv3_wrap0_s5_clk_src",
950
+
.parent_data = gcc_parent_data_0,
951
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
952
+
.ops = &clk_rcg2_shared_ops,
953
+
};
954
+
955
+
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
956
+
.cmd_rcgr = 0x6c628,
957
+
.mnd_width = 16,
958
+
.hid_width = 5,
959
+
.parent_map = gcc_parent_map_0,
960
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
961
+
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
962
+
};
963
+
964
+
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
965
+
.name = "gcc_qupv3_wrap0_s6_clk_src",
966
+
.parent_data = gcc_parent_data_0,
967
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
968
+
.ops = &clk_rcg2_shared_ops,
969
+
};
970
+
971
+
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
972
+
.cmd_rcgr = 0x6c760,
973
+
.mnd_width = 16,
974
+
.hid_width = 5,
975
+
.parent_map = gcc_parent_map_0,
976
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
977
+
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
978
+
};
979
+
980
+
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
981
+
.name = "gcc_qupv3_wrap0_s7_clk_src",
982
+
.parent_data = gcc_parent_data_0,
983
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
984
+
.ops = &clk_rcg2_shared_ops,
985
+
};
986
+
987
+
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
988
+
.cmd_rcgr = 0x6c898,
989
+
.mnd_width = 16,
990
+
.hid_width = 5,
991
+
.parent_map = gcc_parent_map_0,
992
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
993
+
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
994
+
};
995
+
996
+
static struct clk_init_data gcc_qupv3_wrap0_s8_clk_src_init = {
997
+
.name = "gcc_qupv3_wrap0_s8_clk_src",
998
+
.parent_data = gcc_parent_data_0,
999
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1000
+
.ops = &clk_rcg2_shared_ops,
1001
+
};
1002
+
1003
+
static struct clk_rcg2 gcc_qupv3_wrap0_s8_clk_src = {
1004
+
.cmd_rcgr = 0x6c9d0,
1005
+
.mnd_width = 16,
1006
+
.hid_width = 5,
1007
+
.parent_map = gcc_parent_map_0,
1008
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1009
+
.clkr.hw.init = &gcc_qupv3_wrap0_s8_clk_src_init,
1010
+
};
1011
+
1012
+
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
1013
+
F(144000, P_BI_TCXO, 16, 3, 25),
1014
+
F(400000, P_BI_TCXO, 12, 1, 4),
1015
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1016
+
F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
1017
+
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1018
+
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1019
+
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1020
+
F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1021
+
F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1022
+
{ }
1023
+
};
1024
+
1025
+
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
1026
+
.cmd_rcgr = 0x6b014,
1027
+
.mnd_width = 8,
1028
+
.hid_width = 5,
1029
+
.parent_map = gcc_parent_map_17,
1030
+
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
1031
+
.clkr.hw.init = &(const struct clk_init_data) {
1032
+
.name = "gcc_sdcc1_apps_clk_src",
1033
+
.parent_data = gcc_parent_data_17,
1034
+
.num_parents = ARRAY_SIZE(gcc_parent_data_17),
1035
+
.ops = &clk_rcg2_floor_ops,
1036
+
},
1037
+
};
1038
+
1039
+
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1040
+
F(400000, P_BI_TCXO, 12, 1, 4),
1041
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1042
+
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1043
+
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1044
+
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1045
+
F(202000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
1046
+
{ }
1047
+
};
1048
+
1049
+
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1050
+
.cmd_rcgr = 0x6a018,
1051
+
.mnd_width = 8,
1052
+
.hid_width = 5,
1053
+
.parent_map = gcc_parent_map_18,
1054
+
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1055
+
.clkr.hw.init = &(const struct clk_init_data) {
1056
+
.name = "gcc_sdcc2_apps_clk_src",
1057
+
.parent_data = gcc_parent_data_18,
1058
+
.num_parents = ARRAY_SIZE(gcc_parent_data_18),
1059
+
.ops = &clk_rcg2_floor_ops,
1060
+
},
1061
+
};
1062
+
1063
+
static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = {
1064
+
F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
1065
+
{ }
1066
+
};
1067
+
1068
+
static struct clk_rcg2 gcc_usb30_master_clk_src = {
1069
+
.cmd_rcgr = 0x27034,
1070
+
.mnd_width = 8,
1071
+
.hid_width = 5,
1072
+
.parent_map = gcc_parent_map_0,
1073
+
.freq_tbl = ftbl_gcc_usb30_master_clk_src,
1074
+
.clkr.hw.init = &(const struct clk_init_data) {
1075
+
.name = "gcc_usb30_master_clk_src",
1076
+
.parent_data = gcc_parent_data_0,
1077
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1078
+
.ops = &clk_rcg2_shared_ops,
1079
+
},
1080
+
};
1081
+
1082
+
static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = {
1083
+
.cmd_rcgr = 0x2704c,
1084
+
.mnd_width = 0,
1085
+
.hid_width = 5,
1086
+
.parent_map = gcc_parent_map_0,
1087
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1088
+
.clkr.hw.init = &(const struct clk_init_data) {
1089
+
.name = "gcc_usb30_mock_utmi_clk_src",
1090
+
.parent_data = gcc_parent_data_0,
1091
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1092
+
.ops = &clk_rcg2_shared_ops,
1093
+
},
1094
+
};
1095
+
1096
+
static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = {
1097
+
F(1000000, P_BI_TCXO, 1, 5, 96),
1098
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1099
+
{ }
1100
+
};
1101
+
1102
+
static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = {
1103
+
.cmd_rcgr = 0x27074,
1104
+
.mnd_width = 16,
1105
+
.hid_width = 5,
1106
+
.parent_map = gcc_parent_map_3,
1107
+
.freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src,
1108
+
.clkr.hw.init = &(const struct clk_init_data) {
1109
+
.name = "gcc_usb3_phy_aux_clk_src",
1110
+
.parent_data = gcc_parent_data_3,
1111
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1112
+
.ops = &clk_rcg2_shared_ops,
1113
+
},
1114
+
};
1115
+
1116
+
static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src = {
1117
+
.reg = 0x67088,
1118
+
.shift = 0,
1119
+
.width = 4,
1120
+
.clkr.hw.init = &(const struct clk_init_data) {
1121
+
.name = "gcc_pcie_1_pipe_div2_clk_src",
1122
+
.parent_hws = (const struct clk_hw*[]) {
1123
+
&gcc_pcie_1_pipe_clk_src.clkr.hw,
1124
+
},
1125
+
.num_parents = 1,
1126
+
.flags = CLK_SET_RATE_PARENT,
1127
+
.ops = &clk_regmap_div_ro_ops,
1128
+
},
1129
+
};
1130
+
1131
+
static struct clk_regmap_div gcc_pcie_2_pipe_div2_clk_src = {
1132
+
.reg = 0x68088,
1133
+
.shift = 0,
1134
+
.width = 4,
1135
+
.clkr.hw.init = &(const struct clk_init_data) {
1136
+
.name = "gcc_pcie_2_pipe_div2_clk_src",
1137
+
.parent_hws = (const struct clk_hw*[]) {
1138
+
&gcc_pcie_2_pipe_clk_src.clkr.hw,
1139
+
},
1140
+
.num_parents = 1,
1141
+
.flags = CLK_SET_RATE_PARENT,
1142
+
.ops = &clk_regmap_div_ro_ops,
1143
+
},
1144
+
};
1145
+
1146
+
static struct clk_regmap_div gcc_usb30_mock_utmi_postdiv_clk_src = {
1147
+
.reg = 0x27064,
1148
+
.shift = 0,
1149
+
.width = 4,
1150
+
.clkr.hw.init = &(const struct clk_init_data) {
1151
+
.name = "gcc_usb30_mock_utmi_postdiv_clk_src",
1152
+
.parent_hws = (const struct clk_hw*[]) {
1153
+
&gcc_usb30_mock_utmi_clk_src.clkr.hw,
1154
+
},
1155
+
.num_parents = 1,
1156
+
.flags = CLK_SET_RATE_PARENT,
1157
+
.ops = &clk_regmap_div_ro_ops,
1158
+
},
1159
+
};
1160
+
1161
+
static struct clk_branch gcc_boot_rom_ahb_clk = {
1162
+
.halt_reg = 0x37004,
1163
+
.halt_check = BRANCH_HALT_VOTED,
1164
+
.hwcg_reg = 0x37004,
1165
+
.hwcg_bit = 1,
1166
+
.clkr = {
1167
+
.enable_reg = 0x7d008,
1168
+
.enable_mask = BIT(26),
1169
+
.hw.init = &(const struct clk_init_data) {
1170
+
.name = "gcc_boot_rom_ahb_clk",
1171
+
.ops = &clk_branch2_ops,
1172
+
},
1173
+
},
1174
+
};
1175
+
1176
+
static struct clk_branch gcc_eee_emac0_clk = {
1177
+
.halt_reg = 0x710ac,
1178
+
.halt_check = BRANCH_HALT,
1179
+
.clkr = {
1180
+
.enable_reg = 0x710ac,
1181
+
.enable_mask = BIT(0),
1182
+
.hw.init = &(const struct clk_init_data) {
1183
+
.name = "gcc_eee_emac0_clk",
1184
+
.parent_hws = (const struct clk_hw*[]) {
1185
+
&gcc_eee_emac0_clk_src.clkr.hw,
1186
+
},
1187
+
.num_parents = 1,
1188
+
.flags = CLK_SET_RATE_PARENT,
1189
+
.ops = &clk_branch2_ops,
1190
+
},
1191
+
},
1192
+
};
1193
+
1194
+
static struct clk_branch gcc_eee_emac1_clk = {
1195
+
.halt_reg = 0x720ac,
1196
+
.halt_check = BRANCH_HALT,
1197
+
.clkr = {
1198
+
.enable_reg = 0x720ac,
1199
+
.enable_mask = BIT(0),
1200
+
.hw.init = &(const struct clk_init_data) {
1201
+
.name = "gcc_eee_emac1_clk",
1202
+
.parent_hws = (const struct clk_hw*[]) {
1203
+
&gcc_eee_emac1_clk_src.clkr.hw,
1204
+
},
1205
+
.num_parents = 1,
1206
+
.flags = CLK_SET_RATE_PARENT,
1207
+
.ops = &clk_branch2_ops,
1208
+
},
1209
+
},
1210
+
};
1211
+
1212
+
static struct clk_branch gcc_emac0_axi_clk = {
1213
+
.halt_reg = 0x71018,
1214
+
.halt_check = BRANCH_HALT_VOTED,
1215
+
.hwcg_reg = 0x71018,
1216
+
.hwcg_bit = 1,
1217
+
.clkr = {
1218
+
.enable_reg = 0x71018,
1219
+
.enable_mask = BIT(0),
1220
+
.hw.init = &(const struct clk_init_data) {
1221
+
.name = "gcc_emac0_axi_clk",
1222
+
.ops = &clk_branch2_ops,
1223
+
},
1224
+
},
1225
+
};
1226
+
1227
+
static struct clk_branch gcc_emac0_cc_sgmiiphy_rx_clk = {
1228
+
.halt_reg = 0x7105c,
1229
+
.halt_check = BRANCH_HALT_DELAY,
1230
+
.clkr = {
1231
+
.enable_reg = 0x7105c,
1232
+
.enable_mask = BIT(0),
1233
+
.hw.init = &(const struct clk_init_data) {
1234
+
.name = "gcc_emac0_cc_sgmiiphy_rx_clk",
1235
+
.parent_hws = (const struct clk_hw*[]) {
1236
+
&gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr.hw,
1237
+
},
1238
+
.num_parents = 1,
1239
+
.flags = CLK_SET_RATE_PARENT,
1240
+
.ops = &clk_branch2_ops,
1241
+
},
1242
+
},
1243
+
};
1244
+
1245
+
static struct clk_branch gcc_emac0_cc_sgmiiphy_tx_clk = {
1246
+
.halt_reg = 0x71054,
1247
+
.halt_check = BRANCH_HALT_DELAY,
1248
+
.clkr = {
1249
+
.enable_reg = 0x71054,
1250
+
.enable_mask = BIT(0),
1251
+
.hw.init = &(const struct clk_init_data) {
1252
+
.name = "gcc_emac0_cc_sgmiiphy_tx_clk",
1253
+
.parent_hws = (const struct clk_hw*[]) {
1254
+
&gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr.hw,
1255
+
},
1256
+
.num_parents = 1,
1257
+
.flags = CLK_SET_RATE_PARENT,
1258
+
.ops = &clk_branch2_ops,
1259
+
},
1260
+
},
1261
+
};
1262
+
1263
+
static struct clk_branch gcc_emac0_phy_aux_clk = {
1264
+
.halt_reg = 0x71028,
1265
+
.halt_check = BRANCH_HALT,
1266
+
.clkr = {
1267
+
.enable_reg = 0x71028,
1268
+
.enable_mask = BIT(0),
1269
+
.hw.init = &(const struct clk_init_data) {
1270
+
.name = "gcc_emac0_phy_aux_clk",
1271
+
.parent_hws = (const struct clk_hw*[]) {
1272
+
&gcc_emac0_phy_aux_clk_src.clkr.hw,
1273
+
},
1274
+
.num_parents = 1,
1275
+
.flags = CLK_SET_RATE_PARENT,
1276
+
.ops = &clk_branch2_ops,
1277
+
},
1278
+
},
1279
+
};
1280
+
1281
+
static struct clk_branch gcc_emac0_ptp_clk = {
1282
+
.halt_reg = 0x71044,
1283
+
.halt_check = BRANCH_HALT,
1284
+
.clkr = {
1285
+
.enable_reg = 0x71044,
1286
+
.enable_mask = BIT(0),
1287
+
.hw.init = &(const struct clk_init_data) {
1288
+
.name = "gcc_emac0_ptp_clk",
1289
+
.parent_hws = (const struct clk_hw*[]) {
1290
+
&gcc_emac0_ptp_clk_src.clkr.hw,
1291
+
},
1292
+
.num_parents = 1,
1293
+
.flags = CLK_SET_RATE_PARENT,
1294
+
.ops = &clk_branch2_ops,
1295
+
},
1296
+
},
1297
+
};
1298
+
1299
+
static struct clk_branch gcc_emac0_rgmii_clk = {
1300
+
.halt_reg = 0x71050,
1301
+
.halt_check = BRANCH_HALT,
1302
+
.clkr = {
1303
+
.enable_reg = 0x71050,
1304
+
.enable_mask = BIT(0),
1305
+
.hw.init = &(const struct clk_init_data) {
1306
+
.name = "gcc_emac0_rgmii_clk",
1307
+
.parent_hws = (const struct clk_hw*[]) {
1308
+
&gcc_emac0_rgmii_clk_src.clkr.hw,
1309
+
},
1310
+
.num_parents = 1,
1311
+
.flags = CLK_SET_RATE_PARENT,
1312
+
.ops = &clk_branch2_ops,
1313
+
},
1314
+
},
1315
+
};
1316
+
1317
+
static struct clk_branch gcc_emac0_rpcs_rx_clk = {
1318
+
.halt_reg = 0x710a0,
1319
+
.halt_check = BRANCH_HALT_DELAY,
1320
+
.clkr = {
1321
+
.enable_reg = 0x710a0,
1322
+
.enable_mask = BIT(0),
1323
+
.hw.init = &(const struct clk_init_data) {
1324
+
.name = "gcc_emac0_rpcs_rx_clk",
1325
+
.parent_hws = (const struct clk_hw*[]) {
1326
+
&gcc_emac0_sgmiiphy_mac_rclk_src.clkr.hw,
1327
+
},
1328
+
.num_parents = 1,
1329
+
.flags = CLK_SET_RATE_PARENT,
1330
+
.ops = &clk_branch2_ops,
1331
+
},
1332
+
},
1333
+
};
1334
+
1335
+
static struct clk_branch gcc_emac0_rpcs_tx_clk = {
1336
+
.halt_reg = 0x7109c,
1337
+
.halt_check = BRANCH_HALT_DELAY,
1338
+
.clkr = {
1339
+
.enable_reg = 0x7109c,
1340
+
.enable_mask = BIT(0),
1341
+
.hw.init = &(const struct clk_init_data) {
1342
+
.name = "gcc_emac0_rpcs_tx_clk",
1343
+
.parent_hws = (const struct clk_hw*[]) {
1344
+
&gcc_emac0_sgmiiphy_mac_tclk_src.clkr.hw,
1345
+
},
1346
+
.num_parents = 1,
1347
+
.flags = CLK_SET_RATE_PARENT,
1348
+
.ops = &clk_branch2_ops,
1349
+
},
1350
+
},
1351
+
};
1352
+
1353
+
static struct clk_branch gcc_emac0_slv_ahb_clk = {
1354
+
.halt_reg = 0x71024,
1355
+
.halt_check = BRANCH_HALT_VOTED,
1356
+
.hwcg_reg = 0x71024,
1357
+
.hwcg_bit = 1,
1358
+
.clkr = {
1359
+
.enable_reg = 0x71024,
1360
+
.enable_mask = BIT(0),
1361
+
.hw.init = &(const struct clk_init_data) {
1362
+
.name = "gcc_emac0_slv_ahb_clk",
1363
+
.ops = &clk_branch2_ops,
1364
+
},
1365
+
},
1366
+
};
1367
+
1368
+
static struct clk_branch gcc_emac0_xgxs_rx_clk = {
1369
+
.halt_reg = 0x710a8,
1370
+
.halt_check = BRANCH_HALT_DELAY,
1371
+
.clkr = {
1372
+
.enable_reg = 0x710a8,
1373
+
.enable_mask = BIT(0),
1374
+
.hw.init = &(const struct clk_init_data) {
1375
+
.name = "gcc_emac0_xgxs_rx_clk",
1376
+
.parent_hws = (const struct clk_hw*[]) {
1377
+
&gcc_emac0_sgmiiphy_mac_rclk_src.clkr.hw,
1378
+
},
1379
+
.num_parents = 1,
1380
+
.flags = CLK_SET_RATE_PARENT,
1381
+
.ops = &clk_branch2_ops,
1382
+
},
1383
+
},
1384
+
};
1385
+
1386
+
static struct clk_branch gcc_emac0_xgxs_tx_clk = {
1387
+
.halt_reg = 0x710a4,
1388
+
.halt_check = BRANCH_HALT_DELAY,
1389
+
.clkr = {
1390
+
.enable_reg = 0x710a4,
1391
+
.enable_mask = BIT(0),
1392
+
.hw.init = &(const struct clk_init_data) {
1393
+
.name = "gcc_emac0_xgxs_tx_clk",
1394
+
.parent_hws = (const struct clk_hw*[]) {
1395
+
&gcc_emac0_sgmiiphy_mac_tclk_src.clkr.hw,
1396
+
},
1397
+
.num_parents = 1,
1398
+
.flags = CLK_SET_RATE_PARENT,
1399
+
.ops = &clk_branch2_ops,
1400
+
},
1401
+
},
1402
+
};
1403
+
1404
+
static struct clk_branch gcc_emac1_axi_clk = {
1405
+
.halt_reg = 0x72018,
1406
+
.halt_check = BRANCH_HALT_VOTED,
1407
+
.hwcg_reg = 0x72018,
1408
+
.hwcg_bit = 1,
1409
+
.clkr = {
1410
+
.enable_reg = 0x72018,
1411
+
.enable_mask = BIT(0),
1412
+
.hw.init = &(const struct clk_init_data) {
1413
+
.name = "gcc_emac1_axi_clk",
1414
+
.ops = &clk_branch2_ops,
1415
+
},
1416
+
},
1417
+
};
1418
+
1419
+
static struct clk_branch gcc_emac1_cc_sgmiiphy_rx_clk = {
1420
+
.halt_reg = 0x7205c,
1421
+
.halt_check = BRANCH_HALT_DELAY,
1422
+
.clkr = {
1423
+
.enable_reg = 0x7205c,
1424
+
.enable_mask = BIT(0),
1425
+
.hw.init = &(const struct clk_init_data) {
1426
+
.name = "gcc_emac1_cc_sgmiiphy_rx_clk",
1427
+
.parent_hws = (const struct clk_hw*[]) {
1428
+
&gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr.hw,
1429
+
},
1430
+
.num_parents = 1,
1431
+
.flags = CLK_SET_RATE_PARENT,
1432
+
.ops = &clk_branch2_ops,
1433
+
},
1434
+
},
1435
+
};
1436
+
1437
+
static struct clk_branch gcc_emac1_cc_sgmiiphy_tx_clk = {
1438
+
.halt_reg = 0x72054,
1439
+
.halt_check = BRANCH_HALT_DELAY,
1440
+
.clkr = {
1441
+
.enable_reg = 0x72054,
1442
+
.enable_mask = BIT(0),
1443
+
.hw.init = &(const struct clk_init_data) {
1444
+
.name = "gcc_emac1_cc_sgmiiphy_tx_clk",
1445
+
.parent_hws = (const struct clk_hw*[]) {
1446
+
&gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr.hw,
1447
+
},
1448
+
.num_parents = 1,
1449
+
.flags = CLK_SET_RATE_PARENT,
1450
+
.ops = &clk_branch2_ops,
1451
+
},
1452
+
},
1453
+
};
1454
+
1455
+
static struct clk_branch gcc_emac1_phy_aux_clk = {
1456
+
.halt_reg = 0x72028,
1457
+
.halt_check = BRANCH_HALT,
1458
+
.clkr = {
1459
+
.enable_reg = 0x72028,
1460
+
.enable_mask = BIT(0),
1461
+
.hw.init = &(const struct clk_init_data) {
1462
+
.name = "gcc_emac1_phy_aux_clk",
1463
+
.parent_hws = (const struct clk_hw*[]) {
1464
+
&gcc_emac1_phy_aux_clk_src.clkr.hw,
1465
+
},
1466
+
.num_parents = 1,
1467
+
.flags = CLK_SET_RATE_PARENT,
1468
+
.ops = &clk_branch2_ops,
1469
+
},
1470
+
},
1471
+
};
1472
+
1473
+
static struct clk_branch gcc_emac1_ptp_clk = {
1474
+
.halt_reg = 0x72044,
1475
+
.halt_check = BRANCH_HALT,
1476
+
.clkr = {
1477
+
.enable_reg = 0x72044,
1478
+
.enable_mask = BIT(0),
1479
+
.hw.init = &(const struct clk_init_data) {
1480
+
.name = "gcc_emac1_ptp_clk",
1481
+
.parent_hws = (const struct clk_hw*[]) {
1482
+
&gcc_emac1_ptp_clk_src.clkr.hw,
1483
+
},
1484
+
.num_parents = 1,
1485
+
.flags = CLK_SET_RATE_PARENT,
1486
+
.ops = &clk_branch2_ops,
1487
+
},
1488
+
},
1489
+
};
1490
+
1491
+
static struct clk_branch gcc_emac1_rgmii_clk = {
1492
+
.halt_reg = 0x72050,
1493
+
.halt_check = BRANCH_HALT,
1494
+
.clkr = {
1495
+
.enable_reg = 0x72050,
1496
+
.enable_mask = BIT(0),
1497
+
.hw.init = &(const struct clk_init_data) {
1498
+
.name = "gcc_emac1_rgmii_clk",
1499
+
.parent_hws = (const struct clk_hw*[]) {
1500
+
&gcc_emac1_rgmii_clk_src.clkr.hw,
1501
+
},
1502
+
.num_parents = 1,
1503
+
.flags = CLK_SET_RATE_PARENT,
1504
+
.ops = &clk_branch2_ops,
1505
+
},
1506
+
},
1507
+
};
1508
+
1509
+
static struct clk_branch gcc_emac1_rpcs_rx_clk = {
1510
+
.halt_reg = 0x720a0,
1511
+
.halt_check = BRANCH_HALT_DELAY,
1512
+
.clkr = {
1513
+
.enable_reg = 0x720a0,
1514
+
.enable_mask = BIT(0),
1515
+
.hw.init = &(const struct clk_init_data) {
1516
+
.name = "gcc_emac1_rpcs_rx_clk",
1517
+
.parent_hws = (const struct clk_hw*[]) {
1518
+
&gcc_emac1_sgmiiphy_mac_rclk_src.clkr.hw,
1519
+
},
1520
+
.num_parents = 1,
1521
+
.flags = CLK_SET_RATE_PARENT,
1522
+
.ops = &clk_branch2_ops,
1523
+
},
1524
+
},
1525
+
};
1526
+
1527
+
static struct clk_branch gcc_emac1_rpcs_tx_clk = {
1528
+
.halt_reg = 0x7209c,
1529
+
.halt_check = BRANCH_HALT_DELAY,
1530
+
.clkr = {
1531
+
.enable_reg = 0x7209c,
1532
+
.enable_mask = BIT(0),
1533
+
.hw.init = &(const struct clk_init_data) {
1534
+
.name = "gcc_emac1_rpcs_tx_clk",
1535
+
.parent_hws = (const struct clk_hw*[]) {
1536
+
&gcc_emac1_sgmiiphy_mac_tclk_src.clkr.hw,
1537
+
},
1538
+
.num_parents = 1,
1539
+
.flags = CLK_SET_RATE_PARENT,
1540
+
.ops = &clk_branch2_ops,
1541
+
},
1542
+
},
1543
+
};
1544
+
1545
+
static struct clk_branch gcc_emac1_slv_ahb_clk = {
1546
+
.halt_reg = 0x72024,
1547
+
.halt_check = BRANCH_HALT_VOTED,
1548
+
.hwcg_reg = 0x72024,
1549
+
.hwcg_bit = 1,
1550
+
.clkr = {
1551
+
.enable_reg = 0x72024,
1552
+
.enable_mask = BIT(0),
1553
+
.hw.init = &(const struct clk_init_data) {
1554
+
.name = "gcc_emac1_slv_ahb_clk",
1555
+
.ops = &clk_branch2_ops,
1556
+
},
1557
+
},
1558
+
};
1559
+
1560
+
static struct clk_branch gcc_emac1_xgxs_rx_clk = {
1561
+
.halt_reg = 0x720a8,
1562
+
.halt_check = BRANCH_HALT_DELAY,
1563
+
.clkr = {
1564
+
.enable_reg = 0x720a8,
1565
+
.enable_mask = BIT(0),
1566
+
.hw.init = &(const struct clk_init_data) {
1567
+
.name = "gcc_emac1_xgxs_rx_clk",
1568
+
.parent_hws = (const struct clk_hw*[]) {
1569
+
&gcc_emac1_sgmiiphy_mac_rclk_src.clkr.hw,
1570
+
},
1571
+
.num_parents = 1,
1572
+
.flags = CLK_SET_RATE_PARENT,
1573
+
.ops = &clk_branch2_ops,
1574
+
},
1575
+
},
1576
+
};
1577
+
1578
+
static struct clk_branch gcc_emac1_xgxs_tx_clk = {
1579
+
.halt_reg = 0x720a4,
1580
+
.halt_check = BRANCH_HALT_DELAY,
1581
+
.clkr = {
1582
+
.enable_reg = 0x720a4,
1583
+
.enable_mask = BIT(0),
1584
+
.hw.init = &(const struct clk_init_data) {
1585
+
.name = "gcc_emac1_xgxs_tx_clk",
1586
+
.parent_hws = (const struct clk_hw*[]) {
1587
+
&gcc_emac1_sgmiiphy_mac_tclk_src.clkr.hw,
1588
+
},
1589
+
.num_parents = 1,
1590
+
.flags = CLK_SET_RATE_PARENT,
1591
+
.ops = &clk_branch2_ops,
1592
+
},
1593
+
},
1594
+
};
1595
+
1596
+
static struct clk_branch gcc_emac_0_clkref_en = {
1597
+
.halt_reg = 0x98108,
1598
+
.halt_check = BRANCH_HALT_ENABLE,
1599
+
.clkr = {
1600
+
.enable_reg = 0x98108,
1601
+
.enable_mask = BIT(0),
1602
+
.hw.init = &(const struct clk_init_data) {
1603
+
.name = "gcc_emac_0_clkref_en",
1604
+
.ops = &clk_branch2_ops,
1605
+
},
1606
+
},
1607
+
};
1608
+
1609
+
static struct clk_branch gcc_emac_1_clkref_en = {
1610
+
.halt_reg = 0x9810c,
1611
+
.halt_check = BRANCH_HALT_ENABLE,
1612
+
.clkr = {
1613
+
.enable_reg = 0x9810c,
1614
+
.enable_mask = BIT(0),
1615
+
.hw.init = &(const struct clk_init_data) {
1616
+
.name = "gcc_emac_1_clkref_en",
1617
+
.ops = &clk_branch2_ops,
1618
+
},
1619
+
},
1620
+
};
1621
+
1622
+
static struct clk_branch gcc_gp1_clk = {
1623
+
.halt_reg = 0x47000,
1624
+
.halt_check = BRANCH_HALT,
1625
+
.clkr = {
1626
+
.enable_reg = 0x47000,
1627
+
.enable_mask = BIT(0),
1628
+
.hw.init = &(const struct clk_init_data) {
1629
+
.name = "gcc_gp1_clk",
1630
+
.parent_hws = (const struct clk_hw*[]) {
1631
+
&gcc_gp1_clk_src.clkr.hw,
1632
+
},
1633
+
.num_parents = 1,
1634
+
.flags = CLK_SET_RATE_PARENT,
1635
+
.ops = &clk_branch2_ops,
1636
+
},
1637
+
},
1638
+
};
1639
+
1640
+
static struct clk_branch gcc_gp2_clk = {
1641
+
.halt_reg = 0x48000,
1642
+
.halt_check = BRANCH_HALT,
1643
+
.clkr = {
1644
+
.enable_reg = 0x48000,
1645
+
.enable_mask = BIT(0),
1646
+
.hw.init = &(const struct clk_init_data) {
1647
+
.name = "gcc_gp2_clk",
1648
+
.parent_hws = (const struct clk_hw*[]) {
1649
+
&gcc_gp2_clk_src.clkr.hw,
1650
+
},
1651
+
.num_parents = 1,
1652
+
.flags = CLK_SET_RATE_PARENT,
1653
+
.ops = &clk_branch2_ops,
1654
+
},
1655
+
},
1656
+
};
1657
+
1658
+
static struct clk_branch gcc_gp3_clk = {
1659
+
.halt_reg = 0x49000,
1660
+
.halt_check = BRANCH_HALT,
1661
+
.clkr = {
1662
+
.enable_reg = 0x49000,
1663
+
.enable_mask = BIT(0),
1664
+
.hw.init = &(const struct clk_init_data) {
1665
+
.name = "gcc_gp3_clk",
1666
+
.parent_hws = (const struct clk_hw*[]) {
1667
+
&gcc_gp3_clk_src.clkr.hw,
1668
+
},
1669
+
.num_parents = 1,
1670
+
.flags = CLK_SET_RATE_PARENT,
1671
+
.ops = &clk_branch2_ops,
1672
+
},
1673
+
},
1674
+
};
1675
+
1676
+
static struct clk_branch gcc_pcie_0_clkref_en = {
1677
+
.halt_reg = 0x98004,
1678
+
.halt_check = BRANCH_HALT_ENABLE,
1679
+
.clkr = {
1680
+
.enable_reg = 0x98004,
1681
+
.enable_mask = BIT(0),
1682
+
.hw.init = &(const struct clk_init_data) {
1683
+
.name = "gcc_pcie_0_clkref_en",
1684
+
.ops = &clk_branch2_ops,
1685
+
},
1686
+
},
1687
+
};
1688
+
1689
+
static struct clk_branch gcc_pcie_1_aux_clk = {
1690
+
.halt_reg = 0x67038,
1691
+
.halt_check = BRANCH_HALT_DELAY,
1692
+
.clkr = {
1693
+
.enable_reg = 0x7d010,
1694
+
.enable_mask = BIT(22),
1695
+
.hw.init = &(const struct clk_init_data) {
1696
+
.name = "gcc_pcie_1_aux_clk",
1697
+
.parent_hws = (const struct clk_hw*[]) {
1698
+
&gcc_pcie_1_aux_phy_clk_src.clkr.hw,
1699
+
},
1700
+
.num_parents = 1,
1701
+
.flags = CLK_SET_RATE_PARENT,
1702
+
.ops = &clk_branch2_ops,
1703
+
},
1704
+
},
1705
+
};
1706
+
1707
+
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1708
+
.halt_reg = 0x67034,
1709
+
.halt_check = BRANCH_HALT_VOTED,
1710
+
.hwcg_reg = 0x67034,
1711
+
.hwcg_bit = 1,
1712
+
.clkr = {
1713
+
.enable_reg = 0x7d010,
1714
+
.enable_mask = BIT(21),
1715
+
.hw.init = &(const struct clk_init_data) {
1716
+
.name = "gcc_pcie_1_cfg_ahb_clk",
1717
+
.ops = &clk_branch2_ops,
1718
+
},
1719
+
},
1720
+
};
1721
+
1722
+
static struct clk_branch gcc_pcie_1_clkref_en = {
1723
+
.halt_reg = 0x98114,
1724
+
.halt_check = BRANCH_HALT_ENABLE,
1725
+
.clkr = {
1726
+
.enable_reg = 0x98114,
1727
+
.enable_mask = BIT(0),
1728
+
.hw.init = &(const struct clk_init_data) {
1729
+
.name = "gcc_pcie_1_clkref_en",
1730
+
.ops = &clk_branch2_ops,
1731
+
},
1732
+
},
1733
+
};
1734
+
1735
+
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1736
+
.halt_reg = 0x67028,
1737
+
.halt_check = BRANCH_HALT_VOTED,
1738
+
.clkr = {
1739
+
.enable_reg = 0x7d010,
1740
+
.enable_mask = BIT(20),
1741
+
.hw.init = &(const struct clk_init_data) {
1742
+
.name = "gcc_pcie_1_mstr_axi_clk",
1743
+
.ops = &clk_branch2_ops,
1744
+
},
1745
+
},
1746
+
};
1747
+
1748
+
static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
1749
+
.halt_reg = 0x67068,
1750
+
.halt_check = BRANCH_HALT_VOTED,
1751
+
.clkr = {
1752
+
.enable_reg = 0x7d010,
1753
+
.enable_mask = BIT(24),
1754
+
.hw.init = &(const struct clk_init_data) {
1755
+
.name = "gcc_pcie_1_phy_rchng_clk",
1756
+
.parent_hws = (const struct clk_hw*[]) {
1757
+
&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1758
+
},
1759
+
.num_parents = 1,
1760
+
.flags = CLK_SET_RATE_PARENT,
1761
+
.ops = &clk_branch2_ops,
1762
+
},
1763
+
},
1764
+
};
1765
+
1766
+
static struct clk_branch gcc_pcie_1_pipe_clk = {
1767
+
.halt_reg = 0x6705c,
1768
+
.halt_check = BRANCH_HALT_DELAY,
1769
+
.clkr = {
1770
+
.enable_reg = 0x7d010,
1771
+
.enable_mask = BIT(23),
1772
+
.hw.init = &(const struct clk_init_data) {
1773
+
.name = "gcc_pcie_1_pipe_clk",
1774
+
.parent_hws = (const struct clk_hw*[]) {
1775
+
&gcc_pcie_1_pipe_clk_src.clkr.hw,
1776
+
},
1777
+
.num_parents = 1,
1778
+
.flags = CLK_SET_RATE_PARENT,
1779
+
.ops = &clk_branch2_ops,
1780
+
},
1781
+
},
1782
+
};
1783
+
1784
+
static struct clk_branch gcc_pcie_1_pipe_div2_clk = {
1785
+
.halt_reg = 0x6708c,
1786
+
.halt_check = BRANCH_HALT_DELAY,
1787
+
.clkr = {
1788
+
.enable_reg = 0x7d020,
1789
+
.enable_mask = BIT(3),
1790
+
.hw.init = &(const struct clk_init_data) {
1791
+
.name = "gcc_pcie_1_pipe_div2_clk",
1792
+
.parent_hws = (const struct clk_hw*[]) {
1793
+
&gcc_pcie_1_pipe_div2_clk_src.clkr.hw,
1794
+
},
1795
+
.num_parents = 1,
1796
+
.flags = CLK_SET_RATE_PARENT,
1797
+
.ops = &clk_branch2_ops,
1798
+
},
1799
+
},
1800
+
};
1801
+
1802
+
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1803
+
.halt_reg = 0x6701c,
1804
+
.halt_check = BRANCH_HALT_VOTED,
1805
+
.clkr = {
1806
+
.enable_reg = 0x7d010,
1807
+
.enable_mask = BIT(19),
1808
+
.hw.init = &(const struct clk_init_data) {
1809
+
.name = "gcc_pcie_1_slv_axi_clk",
1810
+
.ops = &clk_branch2_ops,
1811
+
},
1812
+
},
1813
+
};
1814
+
1815
+
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1816
+
.halt_reg = 0x67018,
1817
+
.halt_check = BRANCH_HALT_VOTED,
1818
+
.clkr = {
1819
+
.enable_reg = 0x7d010,
1820
+
.enable_mask = BIT(18),
1821
+
.hw.init = &(const struct clk_init_data) {
1822
+
.name = "gcc_pcie_1_slv_q2a_axi_clk",
1823
+
.ops = &clk_branch2_ops,
1824
+
},
1825
+
},
1826
+
};
1827
+
1828
+
static struct clk_branch gcc_pcie_2_aux_clk = {
1829
+
.halt_reg = 0x68058,
1830
+
.halt_check = BRANCH_HALT_DELAY,
1831
+
.clkr = {
1832
+
.enable_reg = 0x7d010,
1833
+
.enable_mask = BIT(29),
1834
+
.hw.init = &(const struct clk_init_data) {
1835
+
.name = "gcc_pcie_2_aux_clk",
1836
+
.parent_hws = (const struct clk_hw*[]) {
1837
+
&gcc_pcie_2_aux_phy_clk_src.clkr.hw,
1838
+
},
1839
+
.num_parents = 1,
1840
+
.flags = CLK_SET_RATE_PARENT,
1841
+
.ops = &clk_branch2_ops,
1842
+
},
1843
+
},
1844
+
};
1845
+
1846
+
static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
1847
+
.halt_reg = 0x68034,
1848
+
.halt_check = BRANCH_HALT_VOTED,
1849
+
.hwcg_reg = 0x68034,
1850
+
.hwcg_bit = 1,
1851
+
.clkr = {
1852
+
.enable_reg = 0x7d010,
1853
+
.enable_mask = BIT(28),
1854
+
.hw.init = &(const struct clk_init_data) {
1855
+
.name = "gcc_pcie_2_cfg_ahb_clk",
1856
+
.ops = &clk_branch2_ops,
1857
+
},
1858
+
},
1859
+
};
1860
+
1861
+
static struct clk_branch gcc_pcie_2_clkref_en = {
1862
+
.halt_reg = 0x98110,
1863
+
.halt_check = BRANCH_HALT_ENABLE,
1864
+
.clkr = {
1865
+
.enable_reg = 0x98110,
1866
+
.enable_mask = BIT(0),
1867
+
.hw.init = &(const struct clk_init_data) {
1868
+
.name = "gcc_pcie_2_clkref_en",
1869
+
.ops = &clk_branch2_ops,
1870
+
},
1871
+
},
1872
+
};
1873
+
1874
+
static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
1875
+
.halt_reg = 0x68028,
1876
+
.halt_check = BRANCH_HALT_VOTED,
1877
+
.clkr = {
1878
+
.enable_reg = 0x7d008,
1879
+
.enable_mask = BIT(8),
1880
+
.hw.init = &(const struct clk_init_data) {
1881
+
.name = "gcc_pcie_2_mstr_axi_clk",
1882
+
.ops = &clk_branch2_ops,
1883
+
},
1884
+
},
1885
+
};
1886
+
1887
+
static struct clk_branch gcc_pcie_2_phy_rchng_clk = {
1888
+
.halt_reg = 0x68098,
1889
+
.halt_check = BRANCH_HALT_VOTED,
1890
+
.clkr = {
1891
+
.enable_reg = 0x7d010,
1892
+
.enable_mask = BIT(31),
1893
+
.hw.init = &(const struct clk_init_data) {
1894
+
.name = "gcc_pcie_2_phy_rchng_clk",
1895
+
.parent_hws = (const struct clk_hw*[]) {
1896
+
&gcc_pcie_2_phy_rchng_clk_src.clkr.hw,
1897
+
},
1898
+
.num_parents = 1,
1899
+
.flags = CLK_SET_RATE_PARENT,
1900
+
.ops = &clk_branch2_ops,
1901
+
},
1902
+
},
1903
+
};
1904
+
1905
+
static struct clk_branch gcc_pcie_2_pipe_clk = {
1906
+
.halt_reg = 0x6807c,
1907
+
.halt_check = BRANCH_HALT_DELAY,
1908
+
.clkr = {
1909
+
.enable_reg = 0x7d010,
1910
+
.enable_mask = BIT(30),
1911
+
.hw.init = &(const struct clk_init_data) {
1912
+
.name = "gcc_pcie_2_pipe_clk",
1913
+
.parent_hws = (const struct clk_hw*[]) {
1914
+
&gcc_pcie_2_pipe_clk_src.clkr.hw,
1915
+
},
1916
+
.num_parents = 1,
1917
+
.flags = CLK_SET_RATE_PARENT,
1918
+
.ops = &clk_branch2_ops,
1919
+
},
1920
+
},
1921
+
};
1922
+
1923
+
static struct clk_branch gcc_pcie_2_pipe_div2_clk = {
1924
+
.halt_reg = 0x6808c,
1925
+
.halt_check = BRANCH_HALT_DELAY,
1926
+
.clkr = {
1927
+
.enable_reg = 0x7d020,
1928
+
.enable_mask = BIT(4),
1929
+
.hw.init = &(const struct clk_init_data) {
1930
+
.name = "gcc_pcie_2_pipe_div2_clk",
1931
+
.parent_hws = (const struct clk_hw*[]) {
1932
+
&gcc_pcie_2_pipe_div2_clk_src.clkr.hw,
1933
+
},
1934
+
.num_parents = 1,
1935
+
.flags = CLK_SET_RATE_PARENT,
1936
+
.ops = &clk_branch2_ops,
1937
+
},
1938
+
},
1939
+
};
1940
+
1941
+
static struct clk_branch gcc_pcie_2_slv_axi_clk = {
1942
+
.halt_reg = 0x6801c,
1943
+
.halt_check = BRANCH_HALT_VOTED,
1944
+
.clkr = {
1945
+
.enable_reg = 0x7d010,
1946
+
.enable_mask = BIT(26),
1947
+
.hw.init = &(const struct clk_init_data) {
1948
+
.name = "gcc_pcie_2_slv_axi_clk",
1949
+
.ops = &clk_branch2_ops,
1950
+
},
1951
+
},
1952
+
};
1953
+
1954
+
static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
1955
+
.halt_reg = 0x68018,
1956
+
.halt_check = BRANCH_HALT_VOTED,
1957
+
.clkr = {
1958
+
.enable_reg = 0x7d010,
1959
+
.enable_mask = BIT(25),
1960
+
.hw.init = &(const struct clk_init_data) {
1961
+
.name = "gcc_pcie_2_slv_q2a_axi_clk",
1962
+
.ops = &clk_branch2_ops,
1963
+
},
1964
+
},
1965
+
};
1966
+
1967
+
static struct clk_branch gcc_pcie_aux_clk = {
1968
+
.halt_reg = 0x5303c,
1969
+
.halt_check = BRANCH_HALT_DELAY,
1970
+
.hwcg_reg = 0x5303c,
1971
+
.hwcg_bit = 1,
1972
+
.clkr = {
1973
+
.enable_reg = 0x7d010,
1974
+
.enable_mask = BIT(15),
1975
+
.hw.init = &(const struct clk_init_data) {
1976
+
.name = "gcc_pcie_aux_clk",
1977
+
.parent_hws = (const struct clk_hw*[]) {
1978
+
&gcc_pcie_aux_clk_src.clkr.hw,
1979
+
},
1980
+
.num_parents = 1,
1981
+
.flags = CLK_SET_RATE_PARENT,
1982
+
.ops = &clk_branch2_ops,
1983
+
},
1984
+
},
1985
+
};
1986
+
1987
+
static struct clk_branch gcc_pcie_cfg_ahb_clk = {
1988
+
.halt_reg = 0x53034,
1989
+
.halt_check = BRANCH_HALT_VOTED,
1990
+
.hwcg_reg = 0x53034,
1991
+
.hwcg_bit = 1,
1992
+
.clkr = {
1993
+
.enable_reg = 0x7d010,
1994
+
.enable_mask = BIT(13),
1995
+
.hw.init = &(const struct clk_init_data) {
1996
+
.name = "gcc_pcie_cfg_ahb_clk",
1997
+
.ops = &clk_branch2_ops,
1998
+
},
1999
+
},
2000
+
};
2001
+
2002
+
static struct clk_branch gcc_pcie_mstr_axi_clk = {
2003
+
.halt_reg = 0x53028,
2004
+
.halt_check = BRANCH_HALT_VOTED,
2005
+
.hwcg_reg = 0x53028,
2006
+
.hwcg_bit = 1,
2007
+
.clkr = {
2008
+
.enable_reg = 0x7d010,
2009
+
.enable_mask = BIT(12),
2010
+
.hw.init = &(const struct clk_init_data) {
2011
+
.name = "gcc_pcie_mstr_axi_clk",
2012
+
.ops = &clk_branch2_ops,
2013
+
},
2014
+
},
2015
+
};
2016
+
2017
+
static struct clk_branch gcc_pcie_pipe_clk = {
2018
+
.halt_reg = 0x5304c,
2019
+
.halt_check = BRANCH_HALT_DELAY,
2020
+
.hwcg_reg = 0x5304c,
2021
+
.hwcg_bit = 1,
2022
+
.clkr = {
2023
+
.enable_reg = 0x7d010,
2024
+
.enable_mask = BIT(17),
2025
+
.hw.init = &(const struct clk_init_data) {
2026
+
.name = "gcc_pcie_pipe_clk",
2027
+
.parent_hws = (const struct clk_hw*[]) {
2028
+
&gcc_pcie_pipe_clk_src.clkr.hw,
2029
+
},
2030
+
.num_parents = 1,
2031
+
.flags = CLK_SET_RATE_PARENT,
2032
+
.ops = &clk_branch2_ops,
2033
+
},
2034
+
},
2035
+
};
2036
+
2037
+
static struct clk_branch gcc_pcie_rchng_phy_clk = {
2038
+
.halt_reg = 0x53038,
2039
+
.halt_check = BRANCH_HALT_VOTED,
2040
+
.hwcg_reg = 0x53038,
2041
+
.hwcg_bit = 1,
2042
+
.clkr = {
2043
+
.enable_reg = 0x7d010,
2044
+
.enable_mask = BIT(14),
2045
+
.hw.init = &(const struct clk_init_data) {
2046
+
.name = "gcc_pcie_rchng_phy_clk",
2047
+
.parent_hws = (const struct clk_hw*[]) {
2048
+
&gcc_pcie_rchng_phy_clk_src.clkr.hw,
2049
+
},
2050
+
.num_parents = 1,
2051
+
.flags = CLK_SET_RATE_PARENT,
2052
+
.ops = &clk_branch2_ops,
2053
+
},
2054
+
},
2055
+
};
2056
+
2057
+
static struct clk_branch gcc_pcie_sleep_clk = {
2058
+
.halt_reg = 0x53048,
2059
+
.halt_check = BRANCH_HALT_VOTED,
2060
+
.hwcg_reg = 0x53048,
2061
+
.hwcg_bit = 1,
2062
+
.clkr = {
2063
+
.enable_reg = 0x7d010,
2064
+
.enable_mask = BIT(16),
2065
+
.hw.init = &(const struct clk_init_data) {
2066
+
.name = "gcc_pcie_sleep_clk",
2067
+
.parent_hws = (const struct clk_hw*[]) {
2068
+
&gcc_pcie_aux_phy_clk_src.clkr.hw,
2069
+
},
2070
+
.num_parents = 1,
2071
+
.flags = CLK_SET_RATE_PARENT,
2072
+
.ops = &clk_branch2_ops,
2073
+
},
2074
+
},
2075
+
};
2076
+
2077
+
static struct clk_branch gcc_pcie_slv_axi_clk = {
2078
+
.halt_reg = 0x5301c,
2079
+
.halt_check = BRANCH_HALT_VOTED,
2080
+
.clkr = {
2081
+
.enable_reg = 0x7d010,
2082
+
.enable_mask = BIT(11),
2083
+
.hw.init = &(const struct clk_init_data) {
2084
+
.name = "gcc_pcie_slv_axi_clk",
2085
+
.ops = &clk_branch2_ops,
2086
+
},
2087
+
},
2088
+
};
2089
+
2090
+
static struct clk_branch gcc_pcie_slv_q2a_axi_clk = {
2091
+
.halt_reg = 0x53018,
2092
+
.halt_check = BRANCH_HALT_VOTED,
2093
+
.hwcg_reg = 0x53018,
2094
+
.hwcg_bit = 1,
2095
+
.clkr = {
2096
+
.enable_reg = 0x7d010,
2097
+
.enable_mask = BIT(10),
2098
+
.hw.init = &(const struct clk_init_data) {
2099
+
.name = "gcc_pcie_slv_q2a_axi_clk",
2100
+
.ops = &clk_branch2_ops,
2101
+
},
2102
+
},
2103
+
};
2104
+
2105
+
static struct clk_branch gcc_pdm2_clk = {
2106
+
.halt_reg = 0x3400c,
2107
+
.halt_check = BRANCH_HALT,
2108
+
.clkr = {
2109
+
.enable_reg = 0x3400c,
2110
+
.enable_mask = BIT(0),
2111
+
.hw.init = &(const struct clk_init_data) {
2112
+
.name = "gcc_pdm2_clk",
2113
+
.parent_hws = (const struct clk_hw*[]) {
2114
+
&gcc_pdm2_clk_src.clkr.hw,
2115
+
},
2116
+
.num_parents = 1,
2117
+
.flags = CLK_SET_RATE_PARENT,
2118
+
.ops = &clk_branch2_ops,
2119
+
},
2120
+
},
2121
+
};
2122
+
2123
+
static struct clk_branch gcc_pdm_ahb_clk = {
2124
+
.halt_reg = 0x34004,
2125
+
.halt_check = BRANCH_HALT,
2126
+
.clkr = {
2127
+
.enable_reg = 0x34004,
2128
+
.enable_mask = BIT(0),
2129
+
.hw.init = &(const struct clk_init_data) {
2130
+
.name = "gcc_pdm_ahb_clk",
2131
+
.ops = &clk_branch2_ops,
2132
+
},
2133
+
},
2134
+
};
2135
+
2136
+
static struct clk_branch gcc_pdm_xo4_clk = {
2137
+
.halt_reg = 0x34008,
2138
+
.halt_check = BRANCH_HALT,
2139
+
.clkr = {
2140
+
.enable_reg = 0x34008,
2141
+
.enable_mask = BIT(0),
2142
+
.hw.init = &(const struct clk_init_data) {
2143
+
.name = "gcc_pdm_xo4_clk",
2144
+
.ops = &clk_branch2_ops,
2145
+
},
2146
+
},
2147
+
};
2148
+
2149
+
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2150
+
.halt_reg = 0x2d018,
2151
+
.halt_check = BRANCH_HALT_VOTED,
2152
+
.clkr = {
2153
+
.enable_reg = 0x7d008,
2154
+
.enable_mask = BIT(15),
2155
+
.hw.init = &(const struct clk_init_data) {
2156
+
.name = "gcc_qupv3_wrap0_core_2x_clk",
2157
+
.ops = &clk_branch2_ops,
2158
+
},
2159
+
},
2160
+
};
2161
+
2162
+
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2163
+
.halt_reg = 0x2d008,
2164
+
.halt_check = BRANCH_HALT_VOTED,
2165
+
.clkr = {
2166
+
.enable_reg = 0x7d008,
2167
+
.enable_mask = BIT(14),
2168
+
.hw.init = &(const struct clk_init_data) {
2169
+
.name = "gcc_qupv3_wrap0_core_clk",
2170
+
.ops = &clk_branch2_ops,
2171
+
},
2172
+
},
2173
+
};
2174
+
2175
+
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2176
+
.halt_reg = 0x6c004,
2177
+
.halt_check = BRANCH_HALT_VOTED,
2178
+
.clkr = {
2179
+
.enable_reg = 0x7d008,
2180
+
.enable_mask = BIT(16),
2181
+
.hw.init = &(const struct clk_init_data) {
2182
+
.name = "gcc_qupv3_wrap0_s0_clk",
2183
+
.parent_hws = (const struct clk_hw*[]) {
2184
+
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2185
+
},
2186
+
.num_parents = 1,
2187
+
.flags = CLK_SET_RATE_PARENT,
2188
+
.ops = &clk_branch2_ops,
2189
+
},
2190
+
},
2191
+
};
2192
+
2193
+
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2194
+
.halt_reg = 0x6c13c,
2195
+
.halt_check = BRANCH_HALT_VOTED,
2196
+
.clkr = {
2197
+
.enable_reg = 0x7d008,
2198
+
.enable_mask = BIT(17),
2199
+
.hw.init = &(const struct clk_init_data) {
2200
+
.name = "gcc_qupv3_wrap0_s1_clk",
2201
+
.parent_hws = (const struct clk_hw*[]) {
2202
+
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2203
+
},
2204
+
.num_parents = 1,
2205
+
.flags = CLK_SET_RATE_PARENT,
2206
+
.ops = &clk_branch2_ops,
2207
+
},
2208
+
},
2209
+
};
2210
+
2211
+
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2212
+
.halt_reg = 0x6c274,
2213
+
.halt_check = BRANCH_HALT_VOTED,
2214
+
.clkr = {
2215
+
.enable_reg = 0x7d008,
2216
+
.enable_mask = BIT(18),
2217
+
.hw.init = &(const struct clk_init_data) {
2218
+
.name = "gcc_qupv3_wrap0_s2_clk",
2219
+
.parent_hws = (const struct clk_hw*[]) {
2220
+
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2221
+
},
2222
+
.num_parents = 1,
2223
+
.flags = CLK_SET_RATE_PARENT,
2224
+
.ops = &clk_branch2_ops,
2225
+
},
2226
+
},
2227
+
};
2228
+
2229
+
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2230
+
.halt_reg = 0x6c3ac,
2231
+
.halt_check = BRANCH_HALT_VOTED,
2232
+
.clkr = {
2233
+
.enable_reg = 0x7d008,
2234
+
.enable_mask = BIT(19),
2235
+
.hw.init = &(const struct clk_init_data) {
2236
+
.name = "gcc_qupv3_wrap0_s3_clk",
2237
+
.parent_hws = (const struct clk_hw*[]) {
2238
+
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2239
+
},
2240
+
.num_parents = 1,
2241
+
.flags = CLK_SET_RATE_PARENT,
2242
+
.ops = &clk_branch2_ops,
2243
+
},
2244
+
},
2245
+
};
2246
+
2247
+
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2248
+
.halt_reg = 0x6c4e4,
2249
+
.halt_check = BRANCH_HALT_VOTED,
2250
+
.clkr = {
2251
+
.enable_reg = 0x7d008,
2252
+
.enable_mask = BIT(20),
2253
+
.hw.init = &(const struct clk_init_data) {
2254
+
.name = "gcc_qupv3_wrap0_s4_clk",
2255
+
.parent_hws = (const struct clk_hw*[]) {
2256
+
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2257
+
},
2258
+
.num_parents = 1,
2259
+
.flags = CLK_SET_RATE_PARENT,
2260
+
.ops = &clk_branch2_ops,
2261
+
},
2262
+
},
2263
+
};
2264
+
2265
+
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2266
+
.halt_reg = 0x6c61c,
2267
+
.halt_check = BRANCH_HALT_VOTED,
2268
+
.clkr = {
2269
+
.enable_reg = 0x7d008,
2270
+
.enable_mask = BIT(21),
2271
+
.hw.init = &(const struct clk_init_data) {
2272
+
.name = "gcc_qupv3_wrap0_s5_clk",
2273
+
.parent_hws = (const struct clk_hw*[]) {
2274
+
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2275
+
},
2276
+
.num_parents = 1,
2277
+
.flags = CLK_SET_RATE_PARENT,
2278
+
.ops = &clk_branch2_ops,
2279
+
},
2280
+
},
2281
+
};
2282
+
2283
+
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2284
+
.halt_reg = 0x6c754,
2285
+
.halt_check = BRANCH_HALT_VOTED,
2286
+
.clkr = {
2287
+
.enable_reg = 0x7d008,
2288
+
.enable_mask = BIT(22),
2289
+
.hw.init = &(const struct clk_init_data) {
2290
+
.name = "gcc_qupv3_wrap0_s6_clk",
2291
+
.parent_hws = (const struct clk_hw*[]) {
2292
+
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2293
+
},
2294
+
.num_parents = 1,
2295
+
.flags = CLK_SET_RATE_PARENT,
2296
+
.ops = &clk_branch2_ops,
2297
+
},
2298
+
},
2299
+
};
2300
+
2301
+
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2302
+
.halt_reg = 0x6c88c,
2303
+
.halt_check = BRANCH_HALT_VOTED,
2304
+
.clkr = {
2305
+
.enable_reg = 0x7d008,
2306
+
.enable_mask = BIT(23),
2307
+
.hw.init = &(const struct clk_init_data) {
2308
+
.name = "gcc_qupv3_wrap0_s7_clk",
2309
+
.parent_hws = (const struct clk_hw*[]) {
2310
+
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2311
+
},
2312
+
.num_parents = 1,
2313
+
.flags = CLK_SET_RATE_PARENT,
2314
+
.ops = &clk_branch2_ops,
2315
+
},
2316
+
},
2317
+
};
2318
+
2319
+
static struct clk_branch gcc_qupv3_wrap0_s8_clk = {
2320
+
.halt_reg = 0x6c9c4,
2321
+
.halt_check = BRANCH_HALT_VOTED,
2322
+
.clkr = {
2323
+
.enable_reg = 0x7d020,
2324
+
.enable_mask = BIT(7),
2325
+
.hw.init = &(const struct clk_init_data) {
2326
+
.name = "gcc_qupv3_wrap0_s8_clk",
2327
+
.parent_hws = (const struct clk_hw*[]) {
2328
+
&gcc_qupv3_wrap0_s8_clk_src.clkr.hw,
2329
+
},
2330
+
.num_parents = 1,
2331
+
.flags = CLK_SET_RATE_PARENT,
2332
+
.ops = &clk_branch2_ops,
2333
+
},
2334
+
},
2335
+
};
2336
+
2337
+
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2338
+
.halt_reg = 0x2d000,
2339
+
.halt_check = BRANCH_HALT_VOTED,
2340
+
.hwcg_reg = 0x2d000,
2341
+
.hwcg_bit = 1,
2342
+
.clkr = {
2343
+
.enable_reg = 0x7d008,
2344
+
.enable_mask = BIT(12),
2345
+
.hw.init = &(const struct clk_init_data) {
2346
+
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2347
+
.ops = &clk_branch2_ops,
2348
+
},
2349
+
},
2350
+
};
2351
+
2352
+
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2353
+
.halt_reg = 0x2d004,
2354
+
.halt_check = BRANCH_HALT_VOTED,
2355
+
.hwcg_reg = 0x2d004,
2356
+
.hwcg_bit = 1,
2357
+
.clkr = {
2358
+
.enable_reg = 0x7d008,
2359
+
.enable_mask = BIT(13),
2360
+
.hw.init = &(const struct clk_init_data) {
2361
+
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2362
+
.ops = &clk_branch2_ops,
2363
+
},
2364
+
},
2365
+
};
2366
+
2367
+
static struct clk_branch gcc_sdcc1_ahb_clk = {
2368
+
.halt_reg = 0x6b004,
2369
+
.halt_check = BRANCH_HALT,
2370
+
.clkr = {
2371
+
.enable_reg = 0x6b004,
2372
+
.enable_mask = BIT(0),
2373
+
.hw.init = &(const struct clk_init_data) {
2374
+
.name = "gcc_sdcc1_ahb_clk",
2375
+
.ops = &clk_branch2_ops,
2376
+
},
2377
+
},
2378
+
};
2379
+
2380
+
static struct clk_branch gcc_sdcc1_apps_clk = {
2381
+
.halt_reg = 0x6b008,
2382
+
.halt_check = BRANCH_HALT,
2383
+
.clkr = {
2384
+
.enable_reg = 0x6b008,
2385
+
.enable_mask = BIT(0),
2386
+
.hw.init = &(const struct clk_init_data) {
2387
+
.name = "gcc_sdcc1_apps_clk",
2388
+
.parent_hws = (const struct clk_hw*[]) {
2389
+
&gcc_sdcc1_apps_clk_src.clkr.hw,
2390
+
},
2391
+
.num_parents = 1,
2392
+
.flags = CLK_SET_RATE_PARENT,
2393
+
.ops = &clk_branch2_ops,
2394
+
},
2395
+
},
2396
+
};
2397
+
2398
+
static struct clk_branch gcc_sdcc2_ahb_clk = {
2399
+
.halt_reg = 0x6a010,
2400
+
.halt_check = BRANCH_HALT,
2401
+
.clkr = {
2402
+
.enable_reg = 0x6a010,
2403
+
.enable_mask = BIT(0),
2404
+
.hw.init = &(const struct clk_init_data) {
2405
+
.name = "gcc_sdcc2_ahb_clk",
2406
+
.ops = &clk_branch2_ops,
2407
+
},
2408
+
},
2409
+
};
2410
+
2411
+
static struct clk_branch gcc_sdcc2_apps_clk = {
2412
+
.halt_reg = 0x6a004,
2413
+
.halt_check = BRANCH_HALT,
2414
+
.clkr = {
2415
+
.enable_reg = 0x6a004,
2416
+
.enable_mask = BIT(0),
2417
+
.hw.init = &(const struct clk_init_data) {
2418
+
.name = "gcc_sdcc2_apps_clk",
2419
+
.parent_hws = (const struct clk_hw*[]) {
2420
+
&gcc_sdcc2_apps_clk_src.clkr.hw,
2421
+
},
2422
+
.num_parents = 1,
2423
+
.flags = CLK_SET_RATE_PARENT,
2424
+
.ops = &clk_branch2_ops,
2425
+
},
2426
+
},
2427
+
};
2428
+
2429
+
static struct clk_branch gcc_usb2_clkref_en = {
2430
+
.halt_reg = 0x98008,
2431
+
.halt_check = BRANCH_HALT_ENABLE,
2432
+
.clkr = {
2433
+
.enable_reg = 0x98008,
2434
+
.enable_mask = BIT(0),
2435
+
.hw.init = &(const struct clk_init_data) {
2436
+
.name = "gcc_usb2_clkref_en",
2437
+
.ops = &clk_branch2_ops,
2438
+
},
2439
+
},
2440
+
};
2441
+
2442
+
static struct clk_branch gcc_usb30_master_clk = {
2443
+
.halt_reg = 0x27018,
2444
+
.halt_check = BRANCH_HALT,
2445
+
.clkr = {
2446
+
.enable_reg = 0x27018,
2447
+
.enable_mask = BIT(0),
2448
+
.hw.init = &(const struct clk_init_data) {
2449
+
.name = "gcc_usb30_master_clk",
2450
+
.parent_hws = (const struct clk_hw*[]) {
2451
+
&gcc_usb30_master_clk_src.clkr.hw,
2452
+
},
2453
+
.num_parents = 1,
2454
+
.flags = CLK_SET_RATE_PARENT,
2455
+
.ops = &clk_branch2_ops,
2456
+
},
2457
+
},
2458
+
};
2459
+
2460
+
static struct clk_branch gcc_usb30_mock_utmi_clk = {
2461
+
.halt_reg = 0x27030,
2462
+
.halt_check = BRANCH_HALT,
2463
+
.clkr = {
2464
+
.enable_reg = 0x27030,
2465
+
.enable_mask = BIT(0),
2466
+
.hw.init = &(const struct clk_init_data) {
2467
+
.name = "gcc_usb30_mock_utmi_clk",
2468
+
.parent_hws = (const struct clk_hw*[]) {
2469
+
&gcc_usb30_mock_utmi_postdiv_clk_src.clkr.hw,
2470
+
},
2471
+
.num_parents = 1,
2472
+
.flags = CLK_SET_RATE_PARENT,
2473
+
.ops = &clk_branch2_ops,
2474
+
},
2475
+
},
2476
+
};
2477
+
2478
+
static struct clk_branch gcc_usb30_mstr_axi_clk = {
2479
+
.halt_reg = 0x27024,
2480
+
.halt_check = BRANCH_HALT,
2481
+
.clkr = {
2482
+
.enable_reg = 0x27024,
2483
+
.enable_mask = BIT(0),
2484
+
.hw.init = &(const struct clk_init_data) {
2485
+
.name = "gcc_usb30_mstr_axi_clk",
2486
+
.ops = &clk_branch2_ops,
2487
+
},
2488
+
},
2489
+
};
2490
+
2491
+
static struct clk_branch gcc_usb30_sleep_clk = {
2492
+
.halt_reg = 0x2702c,
2493
+
.halt_check = BRANCH_HALT,
2494
+
.clkr = {
2495
+
.enable_reg = 0x2702c,
2496
+
.enable_mask = BIT(0),
2497
+
.hw.init = &(const struct clk_init_data) {
2498
+
.name = "gcc_usb30_sleep_clk",
2499
+
.ops = &clk_branch2_ops,
2500
+
},
2501
+
},
2502
+
};
2503
+
2504
+
static struct clk_branch gcc_usb30_slv_ahb_clk = {
2505
+
.halt_reg = 0x27028,
2506
+
.halt_check = BRANCH_HALT,
2507
+
.clkr = {
2508
+
.enable_reg = 0x27028,
2509
+
.enable_mask = BIT(0),
2510
+
.hw.init = &(const struct clk_init_data) {
2511
+
.name = "gcc_usb30_slv_ahb_clk",
2512
+
.ops = &clk_branch2_ops,
2513
+
},
2514
+
},
2515
+
};
2516
+
2517
+
static struct clk_branch gcc_usb3_phy_aux_clk = {
2518
+
.halt_reg = 0x27068,
2519
+
.halt_check = BRANCH_HALT,
2520
+
.clkr = {
2521
+
.enable_reg = 0x27068,
2522
+
.enable_mask = BIT(0),
2523
+
.hw.init = &(const struct clk_init_data) {
2524
+
.name = "gcc_usb3_phy_aux_clk",
2525
+
.parent_hws = (const struct clk_hw*[]) {
2526
+
&gcc_usb3_phy_aux_clk_src.clkr.hw,
2527
+
},
2528
+
.num_parents = 1,
2529
+
.flags = CLK_SET_RATE_PARENT,
2530
+
.ops = &clk_branch2_ops,
2531
+
},
2532
+
},
2533
+
};
2534
+
2535
+
static struct clk_branch gcc_usb3_phy_pipe_clk = {
2536
+
.halt_reg = 0x2706c,
2537
+
.halt_check = BRANCH_HALT_DELAY,
2538
+
.hwcg_reg = 0x2706c,
2539
+
.hwcg_bit = 1,
2540
+
.clkr = {
2541
+
.enable_reg = 0x2706c,
2542
+
.enable_mask = BIT(0),
2543
+
.hw.init = &(const struct clk_init_data) {
2544
+
.name = "gcc_usb3_phy_pipe_clk",
2545
+
.parent_hws = (const struct clk_hw*[]) {
2546
+
&gcc_usb3_phy_pipe_clk_src.clkr.hw,
2547
+
},
2548
+
.num_parents = 1,
2549
+
.flags = CLK_SET_RATE_PARENT,
2550
+
.ops = &clk_branch2_ops,
2551
+
},
2552
+
},
2553
+
};
2554
+
2555
+
static struct clk_branch gcc_usb3_prim_clkref_en = {
2556
+
.halt_reg = 0x98000,
2557
+
.halt_check = BRANCH_HALT_ENABLE,
2558
+
.clkr = {
2559
+
.enable_reg = 0x98000,
2560
+
.enable_mask = BIT(0),
2561
+
.hw.init = &(const struct clk_init_data) {
2562
+
.name = "gcc_usb3_prim_clkref_en",
2563
+
.ops = &clk_branch2_ops,
2564
+
},
2565
+
},
2566
+
};
2567
+
2568
+
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2569
+
.halt_reg = 0x29004,
2570
+
.halt_check = BRANCH_HALT,
2571
+
.hwcg_reg = 0x29004,
2572
+
.hwcg_bit = 1,
2573
+
.clkr = {
2574
+
.enable_reg = 0x29004,
2575
+
.enable_mask = BIT(0),
2576
+
.hw.init = &(const struct clk_init_data) {
2577
+
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
2578
+
.ops = &clk_branch2_aon_ops,
2579
+
},
2580
+
},
2581
+
};
2582
+
2583
+
static struct gdsc gcc_emac0_gdsc = {
2584
+
.gdscr = 0x71004,
2585
+
.en_rest_wait_val = 0x2,
2586
+
.en_few_wait_val = 0x2,
2587
+
.clk_dis_wait_val = 0xf,
2588
+
.pd = {
2589
+
.name = "gcc_emac0_gdsc",
2590
+
},
2591
+
.pwrsts = PWRSTS_OFF_ON,
2592
+
.flags = RETAIN_FF_ENABLE,
2593
+
};
2594
+
2595
+
static struct gdsc gcc_emac1_gdsc = {
2596
+
.gdscr = 0x72004,
2597
+
.en_rest_wait_val = 0x2,
2598
+
.en_few_wait_val = 0x2,
2599
+
.clk_dis_wait_val = 0xf,
2600
+
.pd = {
2601
+
.name = "gcc_emac1_gdsc",
2602
+
},
2603
+
.pwrsts = PWRSTS_OFF_ON,
2604
+
.flags = RETAIN_FF_ENABLE,
2605
+
};
2606
+
2607
+
static struct gdsc gcc_pcie_1_gdsc = {
2608
+
.gdscr = 0x67004,
2609
+
.en_rest_wait_val = 0x2,
2610
+
.en_few_wait_val = 0x2,
2611
+
.clk_dis_wait_val = 0xf,
2612
+
.pd = {
2613
+
.name = "gcc_pcie_1_gdsc",
2614
+
},
2615
+
.pwrsts = PWRSTS_OFF_ON,
2616
+
.flags = RETAIN_FF_ENABLE,
2617
+
};
2618
+
2619
+
static struct gdsc gcc_pcie_1_phy_gdsc = {
2620
+
.gdscr = 0x56004,
2621
+
.en_rest_wait_val = 0x2,
2622
+
.en_few_wait_val = 0x2,
2623
+
.clk_dis_wait_val = 0x2,
2624
+
.pd = {
2625
+
.name = "gcc_pcie_1_phy_gdsc",
2626
+
},
2627
+
.pwrsts = PWRSTS_OFF_ON,
2628
+
.flags = RETAIN_FF_ENABLE,
2629
+
};
2630
+
2631
+
static struct gdsc gcc_pcie_2_gdsc = {
2632
+
.gdscr = 0x68004,
2633
+
.en_rest_wait_val = 0x2,
2634
+
.en_few_wait_val = 0x2,
2635
+
.clk_dis_wait_val = 0xf,
2636
+
.pd = {
2637
+
.name = "gcc_pcie_2_gdsc",
2638
+
},
2639
+
.pwrsts = PWRSTS_OFF_ON,
2640
+
.flags = RETAIN_FF_ENABLE,
2641
+
};
2642
+
2643
+
static struct gdsc gcc_pcie_2_phy_gdsc = {
2644
+
.gdscr = 0x6e004,
2645
+
.en_rest_wait_val = 0x2,
2646
+
.en_few_wait_val = 0x2,
2647
+
.clk_dis_wait_val = 0x2,
2648
+
.pd = {
2649
+
.name = "gcc_pcie_2_phy_gdsc",
2650
+
},
2651
+
.pwrsts = PWRSTS_OFF_ON,
2652
+
.flags = RETAIN_FF_ENABLE,
2653
+
};
2654
+
2655
+
static struct gdsc gcc_pcie_gdsc = {
2656
+
.gdscr = 0x53004,
2657
+
.en_rest_wait_val = 0x2,
2658
+
.en_few_wait_val = 0x2,
2659
+
.clk_dis_wait_val = 0xf,
2660
+
.pd = {
2661
+
.name = "gcc_pcie_gdsc",
2662
+
},
2663
+
.pwrsts = PWRSTS_OFF_ON,
2664
+
.flags = RETAIN_FF_ENABLE,
2665
+
};
2666
+
2667
+
static struct gdsc gcc_pcie_phy_gdsc = {
2668
+
.gdscr = 0x54004,
2669
+
.en_rest_wait_val = 0x2,
2670
+
.en_few_wait_val = 0x2,
2671
+
.clk_dis_wait_val = 0x2,
2672
+
.pd = {
2673
+
.name = "gcc_pcie_phy_gdsc",
2674
+
},
2675
+
.pwrsts = PWRSTS_OFF_ON,
2676
+
.flags = RETAIN_FF_ENABLE,
2677
+
};
2678
+
2679
+
static struct gdsc gcc_usb30_gdsc = {
2680
+
.gdscr = 0x27004,
2681
+
.en_rest_wait_val = 0x2,
2682
+
.en_few_wait_val = 0x2,
2683
+
.clk_dis_wait_val = 0xf,
2684
+
.pd = {
2685
+
.name = "gcc_usb30_gdsc",
2686
+
},
2687
+
.pwrsts = PWRSTS_OFF_ON,
2688
+
.flags = RETAIN_FF_ENABLE,
2689
+
};
2690
+
2691
+
static struct gdsc gcc_usb3_phy_gdsc = {
2692
+
.gdscr = 0x28008,
2693
+
.en_rest_wait_val = 0x2,
2694
+
.en_few_wait_val = 0x2,
2695
+
.clk_dis_wait_val = 0x2,
2696
+
.pd = {
2697
+
.name = "gcc_usb3_phy_gdsc",
2698
+
},
2699
+
.pwrsts = PWRSTS_OFF_ON,
2700
+
.flags = RETAIN_FF_ENABLE,
2701
+
};
2702
+
2703
+
static struct clk_regmap *gcc_sdx75_clocks[] = {
2704
+
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2705
+
[GCC_EEE_EMAC0_CLK] = &gcc_eee_emac0_clk.clkr,
2706
+
[GCC_EEE_EMAC0_CLK_SRC] = &gcc_eee_emac0_clk_src.clkr,
2707
+
[GCC_EEE_EMAC1_CLK] = &gcc_eee_emac1_clk.clkr,
2708
+
[GCC_EEE_EMAC1_CLK_SRC] = &gcc_eee_emac1_clk_src.clkr,
2709
+
[GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr,
2710
+
[GCC_EMAC0_CC_SGMIIPHY_RX_CLK] = &gcc_emac0_cc_sgmiiphy_rx_clk.clkr,
2711
+
[GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC] = &gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr,
2712
+
[GCC_EMAC0_CC_SGMIIPHY_TX_CLK] = &gcc_emac0_cc_sgmiiphy_tx_clk.clkr,
2713
+
[GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC] = &gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr,
2714
+
[GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr,
2715
+
[GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr,
2716
+
[GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr,
2717
+
[GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr,
2718
+
[GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr,
2719
+
[GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr,
2720
+
[GCC_EMAC0_RPCS_RX_CLK] = &gcc_emac0_rpcs_rx_clk.clkr,
2721
+
[GCC_EMAC0_RPCS_TX_CLK] = &gcc_emac0_rpcs_tx_clk.clkr,
2722
+
[GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC] = &gcc_emac0_sgmiiphy_mac_rclk_src.clkr,
2723
+
[GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC] = &gcc_emac0_sgmiiphy_mac_tclk_src.clkr,
2724
+
[GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr,
2725
+
[GCC_EMAC0_XGXS_RX_CLK] = &gcc_emac0_xgxs_rx_clk.clkr,
2726
+
[GCC_EMAC0_XGXS_TX_CLK] = &gcc_emac0_xgxs_tx_clk.clkr,
2727
+
[GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr,
2728
+
[GCC_EMAC1_CC_SGMIIPHY_RX_CLK] = &gcc_emac1_cc_sgmiiphy_rx_clk.clkr,
2729
+
[GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC] = &gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr,
2730
+
[GCC_EMAC1_CC_SGMIIPHY_TX_CLK] = &gcc_emac1_cc_sgmiiphy_tx_clk.clkr,
2731
+
[GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC] = &gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr,
2732
+
[GCC_EMAC1_PHY_AUX_CLK] = &gcc_emac1_phy_aux_clk.clkr,
2733
+
[GCC_EMAC1_PHY_AUX_CLK_SRC] = &gcc_emac1_phy_aux_clk_src.clkr,
2734
+
[GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr,
2735
+
[GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr,
2736
+
[GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr,
2737
+
[GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr,
2738
+
[GCC_EMAC1_RPCS_RX_CLK] = &gcc_emac1_rpcs_rx_clk.clkr,
2739
+
[GCC_EMAC1_RPCS_TX_CLK] = &gcc_emac1_rpcs_tx_clk.clkr,
2740
+
[GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC] = &gcc_emac1_sgmiiphy_mac_rclk_src.clkr,
2741
+
[GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC] = &gcc_emac1_sgmiiphy_mac_tclk_src.clkr,
2742
+
[GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr,
2743
+
[GCC_EMAC1_XGXS_RX_CLK] = &gcc_emac1_xgxs_rx_clk.clkr,
2744
+
[GCC_EMAC1_XGXS_TX_CLK] = &gcc_emac1_xgxs_tx_clk.clkr,
2745
+
[GCC_EMAC_0_CLKREF_EN] = &gcc_emac_0_clkref_en.clkr,
2746
+
[GCC_EMAC_1_CLKREF_EN] = &gcc_emac_1_clkref_en.clkr,
2747
+
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2748
+
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2749
+
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2750
+
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2751
+
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2752
+
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2753
+
[GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
2754
+
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2755
+
[GCC_PCIE_1_AUX_PHY_CLK_SRC] = &gcc_pcie_1_aux_phy_clk_src.clkr,
2756
+
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
2757
+
[GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
2758
+
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
2759
+
[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
2760
+
[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
2761
+
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2762
+
[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
2763
+
[GCC_PCIE_1_PIPE_DIV2_CLK] = &gcc_pcie_1_pipe_div2_clk.clkr,
2764
+
[GCC_PCIE_1_PIPE_DIV2_CLK_SRC] = &gcc_pcie_1_pipe_div2_clk_src.clkr,
2765
+
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
2766
+
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
2767
+
[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
2768
+
[GCC_PCIE_2_AUX_PHY_CLK_SRC] = &gcc_pcie_2_aux_phy_clk_src.clkr,
2769
+
[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
2770
+
[GCC_PCIE_2_CLKREF_EN] = &gcc_pcie_2_clkref_en.clkr,
2771
+
[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
2772
+
[GCC_PCIE_2_PHY_RCHNG_CLK] = &gcc_pcie_2_phy_rchng_clk.clkr,
2773
+
[GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr,
2774
+
[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
2775
+
[GCC_PCIE_2_PIPE_CLK_SRC] = &gcc_pcie_2_pipe_clk_src.clkr,
2776
+
[GCC_PCIE_2_PIPE_DIV2_CLK] = &gcc_pcie_2_pipe_div2_clk.clkr,
2777
+
[GCC_PCIE_2_PIPE_DIV2_CLK_SRC] = &gcc_pcie_2_pipe_div2_clk_src.clkr,
2778
+
[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
2779
+
[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
2780
+
[GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr,
2781
+
[GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
2782
+
[GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr,
2783
+
[GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr,
2784
+
[GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr,
2785
+
[GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr,
2786
+
[GCC_PCIE_PIPE_CLK_SRC] = &gcc_pcie_pipe_clk_src.clkr,
2787
+
[GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr,
2788
+
[GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr,
2789
+
[GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr,
2790
+
[GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr,
2791
+
[GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr,
2792
+
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2793
+
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2794
+
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2795
+
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2796
+
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2797
+
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2798
+
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2799
+
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2800
+
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2801
+
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2802
+
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2803
+
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2804
+
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2805
+
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2806
+
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2807
+
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2808
+
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2809
+
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2810
+
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
2811
+
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
2812
+
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
2813
+
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
2814
+
[GCC_QUPV3_WRAP0_S8_CLK] = &gcc_qupv3_wrap0_s8_clk.clkr,
2815
+
[GCC_QUPV3_WRAP0_S8_CLK_SRC] = &gcc_qupv3_wrap0_s8_clk_src.clkr,
2816
+
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2817
+
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2818
+
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2819
+
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2820
+
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2821
+
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2822
+
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2823
+
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2824
+
[GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr,
2825
+
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2826
+
[GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr,
2827
+
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2828
+
[GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr,
2829
+
[GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mock_utmi_postdiv_clk_src.clkr,
2830
+
[GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr,
2831
+
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2832
+
[GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr,
2833
+
[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2834
+
[GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr,
2835
+
[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2836
+
[GCC_USB3_PHY_PIPE_CLK_SRC] = &gcc_usb3_phy_pipe_clk_src.clkr,
2837
+
[GCC_USB3_PRIM_CLKREF_EN] = &gcc_usb3_prim_clkref_en.clkr,
2838
+
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2839
+
[GPLL0] = &gpll0.clkr,
2840
+
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2841
+
[GPLL4] = &gpll4.clkr,
2842
+
[GPLL5] = &gpll5.clkr,
2843
+
[GPLL6] = &gpll6.clkr,
2844
+
[GPLL8] = &gpll8.clkr,
2845
+
};
2846
+
2847
+
static struct gdsc *gcc_sdx75_gdscs[] = {
2848
+
[GCC_EMAC0_GDSC] = &gcc_emac0_gdsc,
2849
+
[GCC_EMAC1_GDSC] = &gcc_emac1_gdsc,
2850
+
[GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc,
2851
+
[GCC_PCIE_1_PHY_GDSC] = &gcc_pcie_1_phy_gdsc,
2852
+
[GCC_PCIE_2_GDSC] = &gcc_pcie_2_gdsc,
2853
+
[GCC_PCIE_2_PHY_GDSC] = &gcc_pcie_2_phy_gdsc,
2854
+
[GCC_PCIE_GDSC] = &gcc_pcie_gdsc,
2855
+
[GCC_PCIE_PHY_GDSC] = &gcc_pcie_phy_gdsc,
2856
+
[GCC_USB30_GDSC] = &gcc_usb30_gdsc,
2857
+
[GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc,
2858
+
};
2859
+
2860
+
static const struct qcom_reset_map gcc_sdx75_resets[] = {
2861
+
[GCC_EMAC0_BCR] = { 0x71000 },
2862
+
[GCC_EMAC0_RGMII_CLK_ARES] = { 0x71050, 2 },
2863
+
[GCC_EMAC1_BCR] = { 0x72000 },
2864
+
[GCC_EMMC_BCR] = { 0x6b000 },
2865
+
[GCC_PCIE_1_BCR] = { 0x67000 },
2866
+
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e700 },
2867
+
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x56120 },
2868
+
[GCC_PCIE_1_PHY_BCR] = { 0x56000 },
2869
+
[GCC_PCIE_2_BCR] = { 0x68000 },
2870
+
[GCC_PCIE_2_LINK_DOWN_BCR] = { 0x9f700 },
2871
+
[GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x6e130 },
2872
+
[GCC_PCIE_2_PHY_BCR] = { 0x6e000 },
2873
+
[GCC_PCIE_BCR] = { 0x53000 },
2874
+
[GCC_PCIE_LINK_DOWN_BCR] = { 0x87000 },
2875
+
[GCC_PCIE_NOCSR_COM_PHY_BCR] = { 0x88008 },
2876
+
[GCC_PCIE_PHY_BCR] = { 0x54000 },
2877
+
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x88000 },
2878
+
[GCC_PCIE_PHY_COM_BCR] = { 0x88004 },
2879
+
[GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x8800c },
2880
+
[GCC_QUSB2PHY_BCR] = { 0x2a000 },
2881
+
[GCC_TCSR_PCIE_BCR] = { 0x84000 },
2882
+
[GCC_USB30_BCR] = { 0x27000 },
2883
+
[GCC_USB3_PHY_BCR] = { 0x28000 },
2884
+
[GCC_USB3PHY_PHY_BCR] = { 0x28004 },
2885
+
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x29000 },
2886
+
};
2887
+
2888
+
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2889
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2890
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2891
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2892
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2893
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2894
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2895
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
2896
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
2897
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s8_clk_src),
2898
+
};
2899
+
2900
+
static const struct regmap_config gcc_sdx75_regmap_config = {
2901
+
.reg_bits = 32,
2902
+
.reg_stride = 4,
2903
+
.val_bits = 32,
2904
+
.max_register = 0x1f41f0,
2905
+
.fast_io = true,
2906
+
};
2907
+
2908
+
static const struct qcom_cc_desc gcc_sdx75_desc = {
2909
+
.config = &gcc_sdx75_regmap_config,
2910
+
.clks = gcc_sdx75_clocks,
2911
+
.num_clks = ARRAY_SIZE(gcc_sdx75_clocks),
2912
+
.resets = gcc_sdx75_resets,
2913
+
.num_resets = ARRAY_SIZE(gcc_sdx75_resets),
2914
+
.gdscs = gcc_sdx75_gdscs,
2915
+
.num_gdscs = ARRAY_SIZE(gcc_sdx75_gdscs),
2916
+
};
2917
+
2918
+
static const struct of_device_id gcc_sdx75_match_table[] = {
2919
+
{ .compatible = "qcom,sdx75-gcc" },
2920
+
{ }
2921
+
};
2922
+
MODULE_DEVICE_TABLE(of, gcc_sdx75_match_table);
2923
+
2924
+
static int gcc_sdx75_probe(struct platform_device *pdev)
2925
+
{
2926
+
struct regmap *regmap;
2927
+
int ret;
2928
+
2929
+
regmap = qcom_cc_map(pdev, &gcc_sdx75_desc);
2930
+
if (IS_ERR(regmap))
2931
+
return PTR_ERR(regmap);
2932
+
2933
+
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2934
+
ARRAY_SIZE(gcc_dfs_clocks));
2935
+
if (ret)
2936
+
return ret;
2937
+
2938
+
/*
2939
+
* Keep clocks always enabled:
2940
+
* gcc_ahb_pcie_link_clk
2941
+
* gcc_xo_pcie_link_clk
2942
+
*/
2943
+
regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0));
2944
+
regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0));
2945
+
2946
+
return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap);
2947
+
}
2948
+
2949
+
static struct platform_driver gcc_sdx75_driver = {
2950
+
.probe = gcc_sdx75_probe,
2951
+
.driver = {
2952
+
.name = "gcc-sdx75",
2953
+
.of_match_table = gcc_sdx75_match_table,
2954
+
},
2955
+
};
2956
+
2957
+
static int __init gcc_sdx75_init(void)
2958
+
{
2959
+
return platform_driver_register(&gcc_sdx75_driver);
2960
+
}
2961
+
subsys_initcall(gcc_sdx75_init);
2962
+
2963
+
static void __exit gcc_sdx75_exit(void)
2964
+
{
2965
+
platform_driver_unregister(&gcc_sdx75_driver);
2966
+
}
2967
+
module_exit(gcc_sdx75_exit);
2968
+
2969
+
MODULE_DESCRIPTION("QTI GCC SDX75 Driver");
2970
+
MODULE_LICENSE("GPL");
+8
drivers/clk/qcom/gcc-sm6115.c
+8
drivers/clk/qcom/gcc-sm6115.c
···
119
119
.vco_mask = GENMASK(21, 20),
120
120
.main_output_mask = BIT(0),
121
121
.config_ctl_val = 0x4001055b,
122
+
.test_ctl_hi1_val = 0x1,
123
+
.test_ctl_hi_mask = 0x1,
122
124
};
123
125
124
126
static struct clk_alpha_pll gpll10 = {
···
172
170
.vco_val = 0x2 << 20,
173
171
.vco_mask = GENMASK(21, 20),
174
172
.config_ctl_val = 0x4001055b,
173
+
.test_ctl_hi1_val = 0x1,
174
+
.test_ctl_hi_mask = 0x1,
175
175
};
176
176
177
177
static struct clk_alpha_pll gpll11 = {
···
366
362
.post_div_val = 0x1 << 8,
367
363
.post_div_mask = GENMASK(11, 8),
368
364
.config_ctl_val = 0x4001055b,
365
+
.test_ctl_hi1_val = 0x1,
366
+
.test_ctl_hi_mask = 0x1,
369
367
};
370
368
371
369
static struct clk_alpha_pll gpll8 = {
···
419
413
.post_div_mask = GENMASK(9, 8),
420
414
.main_output_mask = BIT(0),
421
415
.config_ctl_val = 0x00004289,
416
+
.test_ctl_mask = GENMASK(31, 0),
417
+
.test_ctl_val = 0x08000000,
422
418
};
423
419
424
420
static struct clk_alpha_pll gpll9 = {
+39
drivers/clk/qcom/gcc-sm8450.c
+39
drivers/clk/qcom/gcc-sm8450.c
···
334
334
.hid_width = 5,
335
335
.parent_map = gcc_parent_map_1,
336
336
.freq_tbl = ftbl_gcc_gp1_clk_src,
337
+
.hw_clk_ctrl = true,
337
338
.clkr.hw.init = &(struct clk_init_data){
338
339
.name = "gcc_gp1_clk_src",
339
340
.parent_data = gcc_parent_data_1,
···
350
349
.hid_width = 5,
351
350
.parent_map = gcc_parent_map_1,
352
351
.freq_tbl = ftbl_gcc_gp1_clk_src,
352
+
.hw_clk_ctrl = true,
353
353
.clkr.hw.init = &(struct clk_init_data){
354
354
.name = "gcc_gp2_clk_src",
355
355
.parent_data = gcc_parent_data_1,
···
366
364
.hid_width = 5,
367
365
.parent_map = gcc_parent_map_1,
368
366
.freq_tbl = ftbl_gcc_gp1_clk_src,
367
+
.hw_clk_ctrl = true,
369
368
.clkr.hw.init = &(struct clk_init_data){
370
369
.name = "gcc_gp3_clk_src",
371
370
.parent_data = gcc_parent_data_1,
···
387
384
.hid_width = 5,
388
385
.parent_map = gcc_parent_map_2,
389
386
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
387
+
.hw_clk_ctrl = true,
390
388
.clkr.hw.init = &(struct clk_init_data){
391
389
.name = "gcc_pcie_0_aux_clk_src",
392
390
.parent_data = gcc_parent_data_2,
···
409
405
.hid_width = 5,
410
406
.parent_map = gcc_parent_map_0,
411
407
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
408
+
.hw_clk_ctrl = true,
412
409
.clkr.hw.init = &(struct clk_init_data){
413
410
.name = "gcc_pcie_0_phy_rchng_clk_src",
414
411
.parent_data = gcc_parent_data_0,
···
425
420
.hid_width = 5,
426
421
.parent_map = gcc_parent_map_2,
427
422
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
423
+
.hw_clk_ctrl = true,
428
424
.clkr.hw.init = &(struct clk_init_data){
429
425
.name = "gcc_pcie_1_aux_clk_src",
430
426
.parent_data = gcc_parent_data_2,
···
441
435
.hid_width = 5,
442
436
.parent_map = gcc_parent_map_0,
443
437
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
438
+
.hw_clk_ctrl = true,
444
439
.clkr.hw.init = &(struct clk_init_data){
445
440
.name = "gcc_pcie_1_phy_rchng_clk_src",
446
441
.parent_data = gcc_parent_data_0,
···
462
455
.hid_width = 5,
463
456
.parent_map = gcc_parent_map_0,
464
457
.freq_tbl = ftbl_gcc_pdm2_clk_src,
458
+
.hw_clk_ctrl = true,
465
459
.clkr.hw.init = &(struct clk_init_data){
466
460
.name = "gcc_pdm2_clk_src",
467
461
.parent_data = gcc_parent_data_0,
···
501
493
.hid_width = 5,
502
494
.parent_map = gcc_parent_map_0,
503
495
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
496
+
.hw_clk_ctrl = true,
504
497
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
505
498
};
506
499
···
519
510
.hid_width = 5,
520
511
.parent_map = gcc_parent_map_0,
521
512
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
513
+
.hw_clk_ctrl = true,
522
514
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
523
515
};
524
516
···
537
527
.hid_width = 5,
538
528
.parent_map = gcc_parent_map_0,
539
529
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
530
+
.hw_clk_ctrl = true,
540
531
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
541
532
};
542
533
···
555
544
.hid_width = 5,
556
545
.parent_map = gcc_parent_map_0,
557
546
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
547
+
.hw_clk_ctrl = true,
558
548
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
559
549
};
560
550
···
573
561
.hid_width = 5,
574
562
.parent_map = gcc_parent_map_0,
575
563
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
564
+
.hw_clk_ctrl = true,
576
565
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
577
566
};
578
567
···
603
590
.hid_width = 5,
604
591
.parent_map = gcc_parent_map_0,
605
592
.freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
593
+
.hw_clk_ctrl = true,
606
594
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
607
595
};
608
596
···
621
607
.hid_width = 5,
622
608
.parent_map = gcc_parent_map_0,
623
609
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
610
+
.hw_clk_ctrl = true,
624
611
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
625
612
};
626
613
···
639
624
.hid_width = 5,
640
625
.parent_map = gcc_parent_map_0,
641
626
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
627
+
.hw_clk_ctrl = true,
642
628
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
643
629
};
644
630
···
676
660
.hid_width = 5,
677
661
.parent_map = gcc_parent_map_0,
678
662
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
663
+
.hw_clk_ctrl = true,
679
664
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
680
665
};
681
666
···
694
677
.hid_width = 5,
695
678
.parent_map = gcc_parent_map_0,
696
679
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
680
+
.hw_clk_ctrl = true,
697
681
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
698
682
};
699
683
···
712
694
.hid_width = 5,
713
695
.parent_map = gcc_parent_map_0,
714
696
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
697
+
.hw_clk_ctrl = true,
715
698
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
716
699
};
717
700
···
730
711
.hid_width = 5,
731
712
.parent_map = gcc_parent_map_0,
732
713
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
714
+
.hw_clk_ctrl = true,
733
715
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
734
716
};
735
717
···
748
728
.hid_width = 5,
749
729
.parent_map = gcc_parent_map_0,
750
730
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
731
+
.hw_clk_ctrl = true,
751
732
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
752
733
};
753
734
···
766
745
.hid_width = 5,
767
746
.parent_map = gcc_parent_map_0,
768
747
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
748
+
.hw_clk_ctrl = true,
769
749
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
770
750
};
771
751
···
784
762
.hid_width = 5,
785
763
.parent_map = gcc_parent_map_0,
786
764
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
765
+
.hw_clk_ctrl = true,
787
766
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
788
767
};
789
768
···
802
779
.hid_width = 5,
803
780
.parent_map = gcc_parent_map_0,
804
781
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
782
+
.hw_clk_ctrl = true,
805
783
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
806
784
};
807
785
···
820
796
.hid_width = 5,
821
797
.parent_map = gcc_parent_map_0,
822
798
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
799
+
.hw_clk_ctrl = true,
823
800
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
824
801
};
825
802
···
838
813
.hid_width = 5,
839
814
.parent_map = gcc_parent_map_0,
840
815
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
816
+
.hw_clk_ctrl = true,
841
817
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
842
818
};
843
819
···
856
830
.hid_width = 5,
857
831
.parent_map = gcc_parent_map_0,
858
832
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
833
+
.hw_clk_ctrl = true,
859
834
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
860
835
};
861
836
···
874
847
.hid_width = 5,
875
848
.parent_map = gcc_parent_map_0,
876
849
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
850
+
.hw_clk_ctrl = true,
877
851
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
878
852
};
879
853
···
892
864
.hid_width = 5,
893
865
.parent_map = gcc_parent_map_0,
894
866
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
867
+
.hw_clk_ctrl = true,
895
868
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
896
869
};
897
870
···
910
881
.hid_width = 5,
911
882
.parent_map = gcc_parent_map_0,
912
883
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
884
+
.hw_clk_ctrl = true,
913
885
.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
914
886
};
915
887
···
929
899
.hid_width = 5,
930
900
.parent_map = gcc_parent_map_7,
931
901
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
902
+
.hw_clk_ctrl = true,
932
903
.clkr.hw.init = &(struct clk_init_data){
933
904
.name = "gcc_sdcc2_apps_clk_src",
934
905
.parent_data = gcc_parent_data_7,
···
952
921
.hid_width = 5,
953
922
.parent_map = gcc_parent_map_0,
954
923
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
924
+
.hw_clk_ctrl = true,
955
925
.clkr.hw.init = &(struct clk_init_data){
956
926
.name = "gcc_sdcc4_apps_clk_src",
957
927
.parent_data = gcc_parent_data_0,
···
976
944
.hid_width = 5,
977
945
.parent_map = gcc_parent_map_0,
978
946
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
947
+
.hw_clk_ctrl = true,
979
948
.clkr.hw.init = &(struct clk_init_data){
980
949
.name = "gcc_ufs_phy_axi_clk_src",
981
950
.parent_data = gcc_parent_data_0,
···
999
966
.hid_width = 5,
1000
967
.parent_map = gcc_parent_map_0,
1001
968
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
969
+
.hw_clk_ctrl = true,
1002
970
.clkr.hw.init = &(struct clk_init_data){
1003
971
.name = "gcc_ufs_phy_ice_core_clk_src",
1004
972
.parent_data = gcc_parent_data_0,
···
1021
987
.hid_width = 5,
1022
988
.parent_map = gcc_parent_map_3,
1023
989
.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
990
+
.hw_clk_ctrl = true,
1024
991
.clkr.hw.init = &(struct clk_init_data){
1025
992
.name = "gcc_ufs_phy_phy_aux_clk_src",
1026
993
.parent_data = gcc_parent_data_3,
···
1037
1002
.hid_width = 5,
1038
1003
.parent_map = gcc_parent_map_0,
1039
1004
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1005
+
.hw_clk_ctrl = true,
1040
1006
.clkr.hw.init = &(struct clk_init_data){
1041
1007
.name = "gcc_ufs_phy_unipro_core_clk_src",
1042
1008
.parent_data = gcc_parent_data_0,
···
1061
1025
.hid_width = 5,
1062
1026
.parent_map = gcc_parent_map_0,
1063
1027
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1028
+
.hw_clk_ctrl = true,
1064
1029
.clkr.hw.init = &(struct clk_init_data){
1065
1030
.name = "gcc_usb30_prim_master_clk_src",
1066
1031
.parent_data = gcc_parent_data_0,
···
1077
1040
.hid_width = 5,
1078
1041
.parent_map = gcc_parent_map_0,
1079
1042
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1043
+
.hw_clk_ctrl = true,
1080
1044
.clkr.hw.init = &(struct clk_init_data){
1081
1045
.name = "gcc_usb30_prim_mock_utmi_clk_src",
1082
1046
.parent_data = gcc_parent_data_0,
···
1093
1055
.hid_width = 5,
1094
1056
.parent_map = gcc_parent_map_2,
1095
1057
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1058
+
.hw_clk_ctrl = true,
1096
1059
.clkr.hw.init = &(struct clk_init_data){
1097
1060
.name = "gcc_usb3_prim_phy_aux_clk_src",
1098
1061
.parent_data = gcc_parent_data_2,
+17
-2
drivers/clk/qcom/gpucc-sc8280xp.c
+17
-2
drivers/clk/qcom/gpucc-sc8280xp.c
···
7
7
#include <linux/kernel.h>
8
8
#include <linux/module.h>
9
9
#include <linux/platform_device.h>
10
+
#include <linux/pm_runtime.h>
10
11
#include <linux/regmap.h>
11
12
12
13
#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
···
425
424
static int gpu_cc_sc8280xp_probe(struct platform_device *pdev)
426
425
{
427
426
struct regmap *regmap;
427
+
int ret;
428
+
429
+
ret = devm_pm_runtime_enable(&pdev->dev);
430
+
if (ret)
431
+
return ret;
432
+
433
+
ret = pm_runtime_resume_and_get(&pdev->dev);
434
+
if (ret)
435
+
return ret;
428
436
429
437
regmap = qcom_cc_map(pdev, &gpu_cc_sc8280xp_desc);
430
-
if (IS_ERR(regmap))
438
+
if (IS_ERR(regmap)) {
439
+
pm_runtime_put(&pdev->dev);
431
440
return PTR_ERR(regmap);
441
+
}
432
442
433
443
clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
434
444
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
···
451
439
regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0));
452
440
regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0));
453
441
454
-
return qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap);
442
+
ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap);
443
+
pm_runtime_put(&pdev->dev);
444
+
445
+
return ret;
455
446
}
456
447
457
448
static const struct of_device_id gpu_cc_sc8280xp_match_table[] = {
+17
-2
drivers/clk/qcom/gpucc-sm6375.c
+17
-2
drivers/clk/qcom/gpucc-sm6375.c
···
7
7
#include <linux/clk-provider.h>
8
8
#include <linux/module.h>
9
9
#include <linux/of_device.h>
10
+
#include <linux/pm_runtime.h>
10
11
#include <linux/regmap.h>
11
12
12
13
#include <dt-bindings/clock/qcom,sm6375-gpucc.h>
···
435
434
static int gpucc_sm6375_probe(struct platform_device *pdev)
436
435
{
437
436
struct regmap *regmap;
437
+
int ret;
438
+
439
+
ret = devm_pm_runtime_enable(&pdev->dev);
440
+
if (ret)
441
+
return ret;
442
+
443
+
ret = pm_runtime_resume_and_get(&pdev->dev);
444
+
if (ret)
445
+
return ret;
438
446
439
447
regmap = qcom_cc_map(pdev, &gpucc_sm6375_desc);
440
-
if (IS_ERR(regmap))
448
+
if (IS_ERR(regmap)) {
449
+
pm_runtime_put(&pdev->dev);
441
450
return PTR_ERR(regmap);
451
+
}
442
452
443
453
clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config);
444
454
clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config);
445
455
446
-
return qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap);
456
+
ret = qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap);
457
+
pm_runtime_put(&pdev->dev);
458
+
459
+
return ret;
447
460
}
448
461
449
462
static struct platform_driver gpucc_sm6375_driver = {
+766
drivers/clk/qcom/gpucc-sm8450.c
+766
drivers/clk/qcom/gpucc-sm8450.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/module.h>
8
+
#include <linux/of_device.h>
9
+
#include <linux/regmap.h>
10
+
11
+
#include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12
+
#include <dt-bindings/reset/qcom,sm8450-gpucc.h>
13
+
14
+
#include "clk-alpha-pll.h"
15
+
#include "clk-branch.h"
16
+
#include "clk-rcg.h"
17
+
#include "clk-regmap.h"
18
+
#include "clk-regmap-divider.h"
19
+
#include "clk-regmap-mux.h"
20
+
#include "clk-regmap-phy-mux.h"
21
+
#include "gdsc.h"
22
+
#include "reset.h"
23
+
24
+
enum {
25
+
DT_BI_TCXO,
26
+
DT_GPLL0_OUT_MAIN,
27
+
DT_GPLL0_OUT_MAIN_DIV,
28
+
};
29
+
30
+
enum {
31
+
P_BI_TCXO,
32
+
P_GPLL0_OUT_MAIN,
33
+
P_GPLL0_OUT_MAIN_DIV,
34
+
P_GPU_CC_PLL0_OUT_MAIN,
35
+
P_GPU_CC_PLL1_OUT_MAIN,
36
+
};
37
+
38
+
static struct pll_vco lucid_evo_vco[] = {
39
+
{ 249600000, 2000000000, 0 },
40
+
};
41
+
42
+
static struct alpha_pll_config gpu_cc_pll0_config = {
43
+
.l = 0x1d,
44
+
.alpha = 0xb000,
45
+
.config_ctl_val = 0x20485699,
46
+
.config_ctl_hi_val = 0x00182261,
47
+
.config_ctl_hi1_val = 0x32aa299c,
48
+
.user_ctl_val = 0x00000000,
49
+
.user_ctl_hi_val = 0x00000805,
50
+
};
51
+
52
+
static struct clk_alpha_pll gpu_cc_pll0 = {
53
+
.offset = 0x0,
54
+
.vco_table = lucid_evo_vco,
55
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
56
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
57
+
.clkr = {
58
+
.hw.init = &(struct clk_init_data){
59
+
.name = "gpu_cc_pll0",
60
+
.parent_data = &(const struct clk_parent_data){
61
+
.index = DT_BI_TCXO,
62
+
},
63
+
.num_parents = 1,
64
+
.ops = &clk_alpha_pll_lucid_evo_ops,
65
+
},
66
+
},
67
+
};
68
+
69
+
static struct alpha_pll_config gpu_cc_pll1_config = {
70
+
.l = 0x34,
71
+
.alpha = 0x1555,
72
+
.config_ctl_val = 0x20485699,
73
+
.config_ctl_hi_val = 0x00182261,
74
+
.config_ctl_hi1_val = 0x32aa299c,
75
+
.user_ctl_val = 0x00000000,
76
+
.user_ctl_hi_val = 0x00000805,
77
+
};
78
+
79
+
static struct clk_alpha_pll gpu_cc_pll1 = {
80
+
.offset = 0x1000,
81
+
.vco_table = lucid_evo_vco,
82
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
83
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
84
+
.clkr = {
85
+
.hw.init = &(struct clk_init_data){
86
+
.name = "gpu_cc_pll1",
87
+
.parent_data = &(const struct clk_parent_data){
88
+
.index = DT_BI_TCXO,
89
+
},
90
+
.num_parents = 1,
91
+
.ops = &clk_alpha_pll_lucid_evo_ops,
92
+
},
93
+
},
94
+
};
95
+
96
+
static const struct parent_map gpu_cc_parent_map_0[] = {
97
+
{ P_BI_TCXO, 0 },
98
+
{ P_GPLL0_OUT_MAIN, 5 },
99
+
{ P_GPLL0_OUT_MAIN_DIV, 6 },
100
+
};
101
+
102
+
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
103
+
{ .index = DT_BI_TCXO },
104
+
{ .index = DT_GPLL0_OUT_MAIN },
105
+
{ .index = DT_GPLL0_OUT_MAIN_DIV },
106
+
};
107
+
108
+
static const struct parent_map gpu_cc_parent_map_1[] = {
109
+
{ P_BI_TCXO, 0 },
110
+
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
111
+
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
112
+
{ P_GPLL0_OUT_MAIN, 5 },
113
+
{ P_GPLL0_OUT_MAIN_DIV, 6 },
114
+
};
115
+
116
+
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
117
+
{ .index = DT_BI_TCXO },
118
+
{ .hw = &gpu_cc_pll0.clkr.hw },
119
+
{ .hw = &gpu_cc_pll1.clkr.hw },
120
+
{ .index = DT_GPLL0_OUT_MAIN },
121
+
{ .index = DT_GPLL0_OUT_MAIN_DIV },
122
+
};
123
+
124
+
static const struct parent_map gpu_cc_parent_map_2[] = {
125
+
{ P_BI_TCXO, 0 },
126
+
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
127
+
{ P_GPLL0_OUT_MAIN, 5 },
128
+
{ P_GPLL0_OUT_MAIN_DIV, 6 },
129
+
};
130
+
131
+
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
132
+
{ .index = DT_BI_TCXO },
133
+
{ .hw = &gpu_cc_pll1.clkr.hw },
134
+
{ .index = DT_GPLL0_OUT_MAIN },
135
+
{ .index = DT_GPLL0_OUT_MAIN_DIV },
136
+
};
137
+
138
+
static const struct parent_map gpu_cc_parent_map_3[] = {
139
+
{ P_BI_TCXO, 0 },
140
+
};
141
+
142
+
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
143
+
{ .index = DT_BI_TCXO },
144
+
};
145
+
146
+
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
147
+
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
148
+
{ }
149
+
};
150
+
151
+
static struct clk_rcg2 gpu_cc_ff_clk_src = {
152
+
.cmd_rcgr = 0x9474,
153
+
.mnd_width = 0,
154
+
.hid_width = 5,
155
+
.parent_map = gpu_cc_parent_map_0,
156
+
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
157
+
.hw_clk_ctrl = true,
158
+
.clkr.hw.init = &(struct clk_init_data){
159
+
.name = "gpu_cc_ff_clk_src",
160
+
.parent_data = gpu_cc_parent_data_0,
161
+
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
162
+
.flags = CLK_SET_RATE_PARENT,
163
+
.ops = &clk_rcg2_shared_ops,
164
+
},
165
+
};
166
+
167
+
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
168
+
F(19200000, P_BI_TCXO, 1, 0, 0),
169
+
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
170
+
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
171
+
{ }
172
+
};
173
+
174
+
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
175
+
.cmd_rcgr = 0x9318,
176
+
.mnd_width = 0,
177
+
.hid_width = 5,
178
+
.parent_map = gpu_cc_parent_map_1,
179
+
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
180
+
.hw_clk_ctrl = true,
181
+
.clkr.hw.init = &(struct clk_init_data){
182
+
.name = "gpu_cc_gmu_clk_src",
183
+
.parent_data = gpu_cc_parent_data_1,
184
+
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
185
+
.flags = CLK_SET_RATE_PARENT,
186
+
.ops = &clk_rcg2_shared_ops,
187
+
},
188
+
};
189
+
190
+
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
191
+
F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
192
+
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
193
+
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
194
+
{ }
195
+
};
196
+
197
+
static struct clk_rcg2 gpu_cc_hub_clk_src = {
198
+
.cmd_rcgr = 0x93ec,
199
+
.mnd_width = 0,
200
+
.hid_width = 5,
201
+
.parent_map = gpu_cc_parent_map_2,
202
+
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
203
+
.hw_clk_ctrl = true,
204
+
.clkr.hw.init = &(struct clk_init_data){
205
+
.name = "gpu_cc_hub_clk_src",
206
+
.parent_data = gpu_cc_parent_data_2,
207
+
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
208
+
.flags = CLK_SET_RATE_PARENT,
209
+
.ops = &clk_rcg2_shared_ops,
210
+
},
211
+
};
212
+
213
+
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
214
+
F(19200000, P_BI_TCXO, 1, 0, 0),
215
+
{ }
216
+
};
217
+
218
+
static struct clk_rcg2 gpu_cc_xo_clk_src = {
219
+
.cmd_rcgr = 0x9010,
220
+
.mnd_width = 0,
221
+
.hid_width = 5,
222
+
.parent_map = gpu_cc_parent_map_3,
223
+
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
224
+
.hw_clk_ctrl = true,
225
+
.clkr.hw.init = &(struct clk_init_data){
226
+
.name = "gpu_cc_xo_clk_src",
227
+
.parent_data = gpu_cc_parent_data_3,
228
+
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
229
+
.flags = CLK_SET_RATE_PARENT,
230
+
.ops = &clk_rcg2_shared_ops,
231
+
},
232
+
};
233
+
234
+
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
235
+
.reg = 0x9054,
236
+
.shift = 0,
237
+
.width = 4,
238
+
.clkr.hw.init = &(struct clk_init_data) {
239
+
.name = "gpu_cc_demet_div_clk_src",
240
+
.parent_hws = (const struct clk_hw*[]){
241
+
&gpu_cc_xo_clk_src.clkr.hw,
242
+
},
243
+
.num_parents = 1,
244
+
.flags = CLK_SET_RATE_PARENT,
245
+
.ops = &clk_regmap_div_ro_ops,
246
+
},
247
+
};
248
+
249
+
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
250
+
.reg = 0x9430,
251
+
.shift = 0,
252
+
.width = 4,
253
+
.clkr.hw.init = &(struct clk_init_data) {
254
+
.name = "gpu_cc_hub_ahb_div_clk_src",
255
+
.parent_hws = (const struct clk_hw*[]){
256
+
&gpu_cc_hub_clk_src.clkr.hw,
257
+
},
258
+
.num_parents = 1,
259
+
.flags = CLK_SET_RATE_PARENT,
260
+
.ops = &clk_regmap_div_ro_ops,
261
+
},
262
+
};
263
+
264
+
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
265
+
.reg = 0x942c,
266
+
.shift = 0,
267
+
.width = 4,
268
+
.clkr.hw.init = &(struct clk_init_data) {
269
+
.name = "gpu_cc_hub_cx_int_div_clk_src",
270
+
.parent_hws = (const struct clk_hw*[]){
271
+
&gpu_cc_hub_clk_src.clkr.hw,
272
+
},
273
+
.num_parents = 1,
274
+
.flags = CLK_SET_RATE_PARENT,
275
+
.ops = &clk_regmap_div_ro_ops,
276
+
},
277
+
};
278
+
279
+
static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
280
+
.reg = 0x9050,
281
+
.shift = 0,
282
+
.width = 4,
283
+
.clkr.hw.init = &(struct clk_init_data) {
284
+
.name = "gpu_cc_xo_div_clk_src",
285
+
.parent_hws = (const struct clk_hw*[]){
286
+
&gpu_cc_xo_clk_src.clkr.hw,
287
+
},
288
+
.num_parents = 1,
289
+
.flags = CLK_SET_RATE_PARENT,
290
+
.ops = &clk_regmap_div_ro_ops,
291
+
},
292
+
};
293
+
294
+
static struct clk_branch gpu_cc_ahb_clk = {
295
+
.halt_reg = 0x911c,
296
+
.halt_check = BRANCH_HALT_DELAY,
297
+
.clkr = {
298
+
.enable_reg = 0x911c,
299
+
.enable_mask = BIT(0),
300
+
.hw.init = &(struct clk_init_data){
301
+
.name = "gpu_cc_ahb_clk",
302
+
.parent_hws = (const struct clk_hw*[]) {
303
+
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
304
+
},
305
+
.num_parents = 1,
306
+
.flags = CLK_SET_RATE_PARENT,
307
+
.ops = &clk_branch2_ops,
308
+
},
309
+
},
310
+
};
311
+
312
+
static struct clk_branch gpu_cc_crc_ahb_clk = {
313
+
.halt_reg = 0x9120,
314
+
.halt_check = BRANCH_HALT_VOTED,
315
+
.clkr = {
316
+
.enable_reg = 0x9120,
317
+
.enable_mask = BIT(0),
318
+
.hw.init = &(struct clk_init_data){
319
+
.name = "gpu_cc_crc_ahb_clk",
320
+
.parent_hws = (const struct clk_hw*[]) {
321
+
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
322
+
},
323
+
.num_parents = 1,
324
+
.flags = CLK_SET_RATE_PARENT,
325
+
.ops = &clk_branch2_ops,
326
+
},
327
+
},
328
+
};
329
+
330
+
static struct clk_branch gpu_cc_cx_apb_clk = {
331
+
.halt_reg = 0x912c,
332
+
.halt_check = BRANCH_HALT_VOTED,
333
+
.clkr = {
334
+
.enable_reg = 0x912c,
335
+
.enable_mask = BIT(0),
336
+
.hw.init = &(struct clk_init_data){
337
+
.name = "gpu_cc_cx_apb_clk",
338
+
.ops = &clk_branch2_ops,
339
+
},
340
+
},
341
+
};
342
+
343
+
static struct clk_branch gpu_cc_cx_ff_clk = {
344
+
.halt_reg = 0x914c,
345
+
.halt_check = BRANCH_HALT,
346
+
.clkr = {
347
+
.enable_reg = 0x914c,
348
+
.enable_mask = BIT(0),
349
+
.hw.init = &(struct clk_init_data){
350
+
.name = "gpu_cc_cx_ff_clk",
351
+
.parent_hws = (const struct clk_hw*[]) {
352
+
&gpu_cc_ff_clk_src.clkr.hw,
353
+
},
354
+
.num_parents = 1,
355
+
.flags = CLK_SET_RATE_PARENT,
356
+
.ops = &clk_branch2_ops,
357
+
},
358
+
},
359
+
};
360
+
361
+
static struct clk_branch gpu_cc_cx_gmu_clk = {
362
+
.halt_reg = 0x913c,
363
+
.halt_check = BRANCH_HALT,
364
+
.clkr = {
365
+
.enable_reg = 0x913c,
366
+
.enable_mask = BIT(0),
367
+
.hw.init = &(struct clk_init_data){
368
+
.name = "gpu_cc_cx_gmu_clk",
369
+
.parent_hws = (const struct clk_hw*[]) {
370
+
&gpu_cc_gmu_clk_src.clkr.hw,
371
+
},
372
+
.num_parents = 1,
373
+
.flags = CLK_SET_RATE_PARENT,
374
+
.ops = &clk_branch2_aon_ops,
375
+
},
376
+
},
377
+
};
378
+
379
+
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
380
+
.halt_reg = 0x9130,
381
+
.halt_check = BRANCH_HALT_VOTED,
382
+
.clkr = {
383
+
.enable_reg = 0x9130,
384
+
.enable_mask = BIT(0),
385
+
.hw.init = &(struct clk_init_data){
386
+
.name = "gpu_cc_cx_snoc_dvm_clk",
387
+
.ops = &clk_branch2_ops,
388
+
},
389
+
},
390
+
};
391
+
392
+
static struct clk_branch gpu_cc_cxo_aon_clk = {
393
+
.halt_reg = 0x9004,
394
+
.halt_check = BRANCH_HALT_VOTED,
395
+
.clkr = {
396
+
.enable_reg = 0x9004,
397
+
.enable_mask = BIT(0),
398
+
.hw.init = &(struct clk_init_data){
399
+
.name = "gpu_cc_cxo_aon_clk",
400
+
.parent_hws = (const struct clk_hw*[]) {
401
+
&gpu_cc_xo_clk_src.clkr.hw,
402
+
},
403
+
.num_parents = 1,
404
+
.flags = CLK_SET_RATE_PARENT,
405
+
.ops = &clk_branch2_ops,
406
+
},
407
+
},
408
+
};
409
+
410
+
static struct clk_branch gpu_cc_cxo_clk = {
411
+
.halt_reg = 0x9144,
412
+
.halt_check = BRANCH_HALT,
413
+
.clkr = {
414
+
.enable_reg = 0x9144,
415
+
.enable_mask = BIT(0),
416
+
.hw.init = &(struct clk_init_data){
417
+
.name = "gpu_cc_cxo_clk",
418
+
.parent_hws = (const struct clk_hw*[]) {
419
+
&gpu_cc_xo_clk_src.clkr.hw,
420
+
},
421
+
.num_parents = 1,
422
+
.flags = CLK_SET_RATE_PARENT,
423
+
.ops = &clk_branch2_ops,
424
+
},
425
+
},
426
+
};
427
+
428
+
static struct clk_branch gpu_cc_demet_clk = {
429
+
.halt_reg = 0x900c,
430
+
.halt_check = BRANCH_HALT,
431
+
.clkr = {
432
+
.enable_reg = 0x900c,
433
+
.enable_mask = BIT(0),
434
+
.hw.init = &(struct clk_init_data){
435
+
.name = "gpu_cc_demet_clk",
436
+
.parent_hws = (const struct clk_hw*[]) {
437
+
&gpu_cc_demet_div_clk_src.clkr.hw,
438
+
},
439
+
.num_parents = 1,
440
+
.flags = CLK_SET_RATE_PARENT,
441
+
.ops = &clk_branch2_aon_ops,
442
+
},
443
+
},
444
+
};
445
+
446
+
static struct clk_branch gpu_cc_freq_measure_clk = {
447
+
.halt_reg = 0x9008,
448
+
.halt_check = BRANCH_HALT,
449
+
.clkr = {
450
+
.enable_reg = 0x9008,
451
+
.enable_mask = BIT(0),
452
+
.hw.init = &(struct clk_init_data){
453
+
.name = "gpu_cc_freq_measure_clk",
454
+
.parent_hws = (const struct clk_hw*[]) {
455
+
&gpu_cc_xo_div_clk_src.clkr.hw,
456
+
},
457
+
.num_parents = 1,
458
+
.flags = CLK_SET_RATE_PARENT,
459
+
.ops = &clk_branch2_ops,
460
+
},
461
+
},
462
+
};
463
+
464
+
static struct clk_branch gpu_cc_gx_ff_clk = {
465
+
.halt_reg = 0x90c0,
466
+
.halt_check = BRANCH_HALT,
467
+
.clkr = {
468
+
.enable_reg = 0x90c0,
469
+
.enable_mask = BIT(0),
470
+
.hw.init = &(struct clk_init_data){
471
+
.name = "gpu_cc_gx_ff_clk",
472
+
.parent_hws = (const struct clk_hw*[]) {
473
+
&gpu_cc_ff_clk_src.clkr.hw,
474
+
},
475
+
.num_parents = 1,
476
+
.flags = CLK_SET_RATE_PARENT,
477
+
.ops = &clk_branch2_ops,
478
+
},
479
+
},
480
+
};
481
+
482
+
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
483
+
.halt_reg = 0x90a8,
484
+
.halt_check = BRANCH_HALT,
485
+
.clkr = {
486
+
.enable_reg = 0x90a8,
487
+
.enable_mask = BIT(0),
488
+
.hw.init = &(struct clk_init_data){
489
+
.name = "gpu_cc_gx_gfx3d_clk",
490
+
.ops = &clk_branch2_ops,
491
+
},
492
+
},
493
+
};
494
+
495
+
static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {
496
+
.halt_reg = 0x90c8,
497
+
.halt_check = BRANCH_HALT,
498
+
.clkr = {
499
+
.enable_reg = 0x90c8,
500
+
.enable_mask = BIT(0),
501
+
.hw.init = &(struct clk_init_data){
502
+
.name = "gpu_cc_gx_gfx3d_rdvm_clk",
503
+
.ops = &clk_branch2_ops,
504
+
},
505
+
},
506
+
};
507
+
508
+
static struct clk_branch gpu_cc_gx_gmu_clk = {
509
+
.halt_reg = 0x90bc,
510
+
.halt_check = BRANCH_HALT,
511
+
.clkr = {
512
+
.enable_reg = 0x90bc,
513
+
.enable_mask = BIT(0),
514
+
.hw.init = &(struct clk_init_data){
515
+
.name = "gpu_cc_gx_gmu_clk",
516
+
.parent_hws = (const struct clk_hw*[]) {
517
+
&gpu_cc_gmu_clk_src.clkr.hw,
518
+
},
519
+
.num_parents = 1,
520
+
.flags = CLK_SET_RATE_PARENT,
521
+
.ops = &clk_branch2_ops,
522
+
},
523
+
},
524
+
};
525
+
526
+
static struct clk_branch gpu_cc_gx_vsense_clk = {
527
+
.halt_reg = 0x90b0,
528
+
.halt_check = BRANCH_HALT_VOTED,
529
+
.clkr = {
530
+
.enable_reg = 0x90b0,
531
+
.enable_mask = BIT(0),
532
+
.hw.init = &(struct clk_init_data){
533
+
.name = "gpu_cc_gx_vsense_clk",
534
+
.ops = &clk_branch2_ops,
535
+
},
536
+
},
537
+
};
538
+
539
+
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
540
+
.halt_reg = 0x7000,
541
+
.halt_check = BRANCH_HALT_VOTED,
542
+
.clkr = {
543
+
.enable_reg = 0x7000,
544
+
.enable_mask = BIT(0),
545
+
.hw.init = &(struct clk_init_data){
546
+
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
547
+
.ops = &clk_branch2_ops,
548
+
},
549
+
},
550
+
};
551
+
552
+
static struct clk_branch gpu_cc_hub_aon_clk = {
553
+
.halt_reg = 0x93e8,
554
+
.halt_check = BRANCH_HALT,
555
+
.clkr = {
556
+
.enable_reg = 0x93e8,
557
+
.enable_mask = BIT(0),
558
+
.hw.init = &(struct clk_init_data){
559
+
.name = "gpu_cc_hub_aon_clk",
560
+
.parent_hws = (const struct clk_hw*[]) {
561
+
&gpu_cc_hub_clk_src.clkr.hw,
562
+
},
563
+
.num_parents = 1,
564
+
.flags = CLK_SET_RATE_PARENT,
565
+
.ops = &clk_branch2_aon_ops,
566
+
},
567
+
},
568
+
};
569
+
570
+
static struct clk_branch gpu_cc_hub_cx_int_clk = {
571
+
.halt_reg = 0x9148,
572
+
.halt_check = BRANCH_HALT,
573
+
.clkr = {
574
+
.enable_reg = 0x9148,
575
+
.enable_mask = BIT(0),
576
+
.hw.init = &(struct clk_init_data){
577
+
.name = "gpu_cc_hub_cx_int_clk",
578
+
.parent_hws = (const struct clk_hw*[]) {
579
+
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
580
+
},
581
+
.num_parents = 1,
582
+
.flags = CLK_SET_RATE_PARENT,
583
+
.ops = &clk_branch2_aon_ops,
584
+
},
585
+
},
586
+
};
587
+
588
+
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
589
+
.halt_reg = 0x9150,
590
+
.halt_check = BRANCH_HALT,
591
+
.clkr = {
592
+
.enable_reg = 0x9150,
593
+
.enable_mask = BIT(0),
594
+
.hw.init = &(struct clk_init_data){
595
+
.name = "gpu_cc_memnoc_gfx_clk",
596
+
.ops = &clk_branch2_ops,
597
+
},
598
+
},
599
+
};
600
+
601
+
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
602
+
.halt_reg = 0x9288,
603
+
.halt_check = BRANCH_HALT,
604
+
.clkr = {
605
+
.enable_reg = 0x9288,
606
+
.enable_mask = BIT(0),
607
+
.hw.init = &(struct clk_init_data){
608
+
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
609
+
.ops = &clk_branch2_ops,
610
+
},
611
+
},
612
+
};
613
+
614
+
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
615
+
.halt_reg = 0x928c,
616
+
.halt_check = BRANCH_HALT,
617
+
.clkr = {
618
+
.enable_reg = 0x928c,
619
+
.enable_mask = BIT(0),
620
+
.hw.init = &(struct clk_init_data){
621
+
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
622
+
.ops = &clk_branch2_ops,
623
+
},
624
+
},
625
+
};
626
+
627
+
static struct clk_branch gpu_cc_sleep_clk = {
628
+
.halt_reg = 0x9134,
629
+
.halt_check = BRANCH_HALT_VOTED,
630
+
.clkr = {
631
+
.enable_reg = 0x9134,
632
+
.enable_mask = BIT(0),
633
+
.hw.init = &(struct clk_init_data){
634
+
.name = "gpu_cc_sleep_clk",
635
+
.ops = &clk_branch2_ops,
636
+
},
637
+
},
638
+
};
639
+
640
+
static struct gdsc gpu_cx_gdsc = {
641
+
.gdscr = 0x9108,
642
+
.gds_hw_ctrl = 0x953c,
643
+
.clk_dis_wait_val = 8,
644
+
.pd = {
645
+
.name = "gpu_cx_gdsc",
646
+
},
647
+
.pwrsts = PWRSTS_OFF_ON,
648
+
.flags = VOTABLE | RETAIN_FF_ENABLE,
649
+
};
650
+
651
+
static struct gdsc gpu_gx_gdsc = {
652
+
.gdscr = 0x905c,
653
+
.clamp_io_ctrl = 0x9504,
654
+
.resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR,
655
+
GPUCC_GPU_CC_ACD_BCR,
656
+
GPUCC_GPU_CC_GX_ACD_IROOT_BCR },
657
+
.reset_count = 3,
658
+
.pd = {
659
+
.name = "gpu_gx_gdsc",
660
+
.power_on = gdsc_gx_do_nothing_enable,
661
+
},
662
+
.pwrsts = PWRSTS_OFF_ON,
663
+
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
664
+
};
665
+
666
+
static struct clk_regmap *gpu_cc_sm8450_clocks[] = {
667
+
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
668
+
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
669
+
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
670
+
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
671
+
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
672
+
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
673
+
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
674
+
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
675
+
[GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
676
+
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
677
+
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
678
+
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
679
+
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
680
+
[GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr,
681
+
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
682
+
[GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr,
683
+
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
684
+
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
685
+
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
686
+
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
687
+
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
688
+
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
689
+
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
690
+
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
691
+
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
692
+
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
693
+
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
694
+
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
695
+
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
696
+
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
697
+
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
698
+
[GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
699
+
};
700
+
701
+
static const struct qcom_reset_map gpu_cc_sm8450_resets[] = {
702
+
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
703
+
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
704
+
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
705
+
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
706
+
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
707
+
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
708
+
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
709
+
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
710
+
[GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c },
711
+
};
712
+
713
+
static struct gdsc *gpu_cc_sm8450_gdscs[] = {
714
+
[GPU_CX_GDSC] = &gpu_cx_gdsc,
715
+
[GPU_GX_GDSC] = &gpu_gx_gdsc,
716
+
};
717
+
718
+
static const struct regmap_config gpu_cc_sm8450_regmap_config = {
719
+
.reg_bits = 32,
720
+
.reg_stride = 4,
721
+
.val_bits = 32,
722
+
.max_register = 0xa000,
723
+
.fast_io = true,
724
+
};
725
+
726
+
static const struct qcom_cc_desc gpu_cc_sm8450_desc = {
727
+
.config = &gpu_cc_sm8450_regmap_config,
728
+
.clks = gpu_cc_sm8450_clocks,
729
+
.num_clks = ARRAY_SIZE(gpu_cc_sm8450_clocks),
730
+
.resets = gpu_cc_sm8450_resets,
731
+
.num_resets = ARRAY_SIZE(gpu_cc_sm8450_resets),
732
+
.gdscs = gpu_cc_sm8450_gdscs,
733
+
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8450_gdscs),
734
+
};
735
+
736
+
static const struct of_device_id gpu_cc_sm8450_match_table[] = {
737
+
{ .compatible = "qcom,sm8450-gpucc" },
738
+
{ }
739
+
};
740
+
MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table);
741
+
742
+
static int gpu_cc_sm8450_probe(struct platform_device *pdev)
743
+
{
744
+
struct regmap *regmap;
745
+
746
+
regmap = qcom_cc_map(pdev, &gpu_cc_sm8450_desc);
747
+
if (IS_ERR(regmap))
748
+
return PTR_ERR(regmap);
749
+
750
+
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
751
+
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
752
+
753
+
return qcom_cc_really_probe(pdev, &gpu_cc_sm8450_desc, regmap);
754
+
}
755
+
756
+
static struct platform_driver gpu_cc_sm8450_driver = {
757
+
.probe = gpu_cc_sm8450_probe,
758
+
.driver = {
759
+
.name = "sm8450-gpucc",
760
+
.of_match_table = gpu_cc_sm8450_match_table,
761
+
},
762
+
};
763
+
module_platform_driver(gpu_cc_sm8450_driver);
764
+
765
+
MODULE_DESCRIPTION("QTI GPU_CC SM8450 Driver");
766
+
MODULE_LICENSE("GPL");
+611
drivers/clk/qcom/gpucc-sm8550.c
+611
drivers/clk/qcom/gpucc-sm8550.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/module.h>
8
+
#include <linux/of_device.h>
9
+
#include <linux/regmap.h>
10
+
11
+
#include <dt-bindings/clock/qcom,sm8550-gpucc.h>
12
+
13
+
#include "clk-alpha-pll.h"
14
+
#include "clk-branch.h"
15
+
#include "clk-rcg.h"
16
+
#include "clk-regmap.h"
17
+
#include "clk-regmap-divider.h"
18
+
#include "common.h"
19
+
#include "gdsc.h"
20
+
#include "reset.h"
21
+
22
+
enum {
23
+
DT_BI_TCXO,
24
+
DT_GPLL0_OUT_MAIN,
25
+
DT_GPLL0_OUT_MAIN_DIV,
26
+
};
27
+
28
+
enum {
29
+
P_BI_TCXO,
30
+
P_GPLL0_OUT_MAIN,
31
+
P_GPLL0_OUT_MAIN_DIV,
32
+
P_GPU_CC_PLL0_OUT_MAIN,
33
+
P_GPU_CC_PLL1_OUT_MAIN,
34
+
};
35
+
36
+
static const struct pll_vco lucid_ole_vco[] = {
37
+
{ 249600000, 2300000000, 0 },
38
+
};
39
+
40
+
static const struct alpha_pll_config gpu_cc_pll0_config = {
41
+
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
42
+
.l = 0x4444000d,
43
+
.alpha = 0x0,
44
+
.config_ctl_val = 0x20485699,
45
+
.config_ctl_hi_val = 0x00182261,
46
+
.config_ctl_hi1_val = 0x82aa299c,
47
+
.test_ctl_val = 0x00000000,
48
+
.test_ctl_hi_val = 0x00000003,
49
+
.test_ctl_hi1_val = 0x00009000,
50
+
.test_ctl_hi2_val = 0x00000034,
51
+
.user_ctl_val = 0x00000000,
52
+
.user_ctl_hi_val = 0x00000005,
53
+
};
54
+
55
+
static struct clk_alpha_pll gpu_cc_pll0 = {
56
+
.offset = 0x0,
57
+
.vco_table = lucid_ole_vco,
58
+
.num_vco = ARRAY_SIZE(lucid_ole_vco),
59
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
60
+
.clkr = {
61
+
.hw.init = &(const struct clk_init_data) {
62
+
.name = "gpu_cc_pll0",
63
+
.parent_data = &(const struct clk_parent_data) {
64
+
.index = DT_BI_TCXO,
65
+
},
66
+
.num_parents = 1,
67
+
.ops = &clk_alpha_pll_lucid_evo_ops,
68
+
},
69
+
},
70
+
};
71
+
72
+
static const struct alpha_pll_config gpu_cc_pll1_config = {
73
+
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
74
+
.l = 0x44440016,
75
+
.alpha = 0xeaaa,
76
+
.config_ctl_val = 0x20485699,
77
+
.config_ctl_hi_val = 0x00182261,
78
+
.config_ctl_hi1_val = 0x82aa299c,
79
+
.test_ctl_val = 0x00000000,
80
+
.test_ctl_hi_val = 0x00000003,
81
+
.test_ctl_hi1_val = 0x00009000,
82
+
.test_ctl_hi2_val = 0x00000034,
83
+
.user_ctl_val = 0x00000000,
84
+
.user_ctl_hi_val = 0x00000005,
85
+
};
86
+
87
+
static struct clk_alpha_pll gpu_cc_pll1 = {
88
+
.offset = 0x1000,
89
+
.vco_table = lucid_ole_vco,
90
+
.num_vco = ARRAY_SIZE(lucid_ole_vco),
91
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
92
+
.clkr = {
93
+
.hw.init = &(const struct clk_init_data) {
94
+
.name = "gpu_cc_pll1",
95
+
.parent_data = &(const struct clk_parent_data) {
96
+
.index = DT_BI_TCXO,
97
+
},
98
+
.num_parents = 1,
99
+
.ops = &clk_alpha_pll_lucid_evo_ops,
100
+
},
101
+
},
102
+
};
103
+
104
+
static const struct parent_map gpu_cc_parent_map_0[] = {
105
+
{ P_BI_TCXO, 0 },
106
+
{ P_GPLL0_OUT_MAIN, 5 },
107
+
{ P_GPLL0_OUT_MAIN_DIV, 6 },
108
+
};
109
+
110
+
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
111
+
{ .index = DT_BI_TCXO },
112
+
{ .index = DT_GPLL0_OUT_MAIN },
113
+
{ .index = DT_GPLL0_OUT_MAIN_DIV },
114
+
};
115
+
116
+
static const struct parent_map gpu_cc_parent_map_1[] = {
117
+
{ P_BI_TCXO, 0 },
118
+
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
119
+
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
120
+
{ P_GPLL0_OUT_MAIN, 5 },
121
+
{ P_GPLL0_OUT_MAIN_DIV, 6 },
122
+
};
123
+
124
+
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
125
+
{ .index = DT_BI_TCXO },
126
+
{ .hw = &gpu_cc_pll0.clkr.hw },
127
+
{ .hw = &gpu_cc_pll1.clkr.hw },
128
+
{ .index = DT_GPLL0_OUT_MAIN },
129
+
{ .index = DT_GPLL0_OUT_MAIN_DIV },
130
+
};
131
+
132
+
static const struct parent_map gpu_cc_parent_map_2[] = {
133
+
{ P_BI_TCXO, 0 },
134
+
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
135
+
{ P_GPLL0_OUT_MAIN, 5 },
136
+
{ P_GPLL0_OUT_MAIN_DIV, 6 },
137
+
};
138
+
139
+
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
140
+
{ .index = DT_BI_TCXO },
141
+
{ .hw = &gpu_cc_pll1.clkr.hw },
142
+
{ .index = DT_GPLL0_OUT_MAIN },
143
+
{ .index = DT_GPLL0_OUT_MAIN_DIV },
144
+
};
145
+
146
+
static const struct parent_map gpu_cc_parent_map_3[] = {
147
+
{ P_BI_TCXO, 0 },
148
+
};
149
+
150
+
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
151
+
{ .index = DT_BI_TCXO },
152
+
};
153
+
154
+
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
155
+
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
156
+
{ }
157
+
};
158
+
159
+
static struct clk_rcg2 gpu_cc_ff_clk_src = {
160
+
.cmd_rcgr = 0x9474,
161
+
.mnd_width = 0,
162
+
.hid_width = 5,
163
+
.parent_map = gpu_cc_parent_map_0,
164
+
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
165
+
.clkr.hw.init = &(const struct clk_init_data) {
166
+
.name = "gpu_cc_ff_clk_src",
167
+
.parent_data = gpu_cc_parent_data_0,
168
+
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
169
+
.flags = CLK_SET_RATE_PARENT,
170
+
.ops = &clk_rcg2_shared_ops,
171
+
},
172
+
};
173
+
174
+
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
175
+
F(19200000, P_BI_TCXO, 1, 0, 0),
176
+
F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
177
+
F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
178
+
{ }
179
+
};
180
+
181
+
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
182
+
.cmd_rcgr = 0x9318,
183
+
.mnd_width = 0,
184
+
.hid_width = 5,
185
+
.parent_map = gpu_cc_parent_map_1,
186
+
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
187
+
.clkr.hw.init = &(const struct clk_init_data) {
188
+
.name = "gpu_cc_gmu_clk_src",
189
+
.parent_data = gpu_cc_parent_data_1,
190
+
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
191
+
.flags = CLK_SET_RATE_PARENT,
192
+
.ops = &clk_rcg2_shared_ops,
193
+
},
194
+
};
195
+
196
+
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
197
+
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
198
+
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
199
+
F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
200
+
{ }
201
+
};
202
+
203
+
static struct clk_rcg2 gpu_cc_hub_clk_src = {
204
+
.cmd_rcgr = 0x93ec,
205
+
.mnd_width = 0,
206
+
.hid_width = 5,
207
+
.parent_map = gpu_cc_parent_map_2,
208
+
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
209
+
.clkr.hw.init = &(const struct clk_init_data) {
210
+
.name = "gpu_cc_hub_clk_src",
211
+
.parent_data = gpu_cc_parent_data_2,
212
+
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
213
+
.flags = CLK_SET_RATE_PARENT,
214
+
.ops = &clk_rcg2_shared_ops,
215
+
},
216
+
};
217
+
218
+
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
219
+
F(19200000, P_BI_TCXO, 1, 0, 0),
220
+
{ }
221
+
};
222
+
223
+
static struct clk_rcg2 gpu_cc_xo_clk_src = {
224
+
.cmd_rcgr = 0x9010,
225
+
.mnd_width = 0,
226
+
.hid_width = 5,
227
+
.parent_map = gpu_cc_parent_map_3,
228
+
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
229
+
.clkr.hw.init = &(const struct clk_init_data) {
230
+
.name = "gpu_cc_xo_clk_src",
231
+
.parent_data = gpu_cc_parent_data_3,
232
+
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
233
+
.flags = CLK_SET_RATE_PARENT,
234
+
.ops = &clk_rcg2_shared_ops,
235
+
},
236
+
};
237
+
238
+
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
239
+
.reg = 0x9054,
240
+
.shift = 0,
241
+
.width = 4,
242
+
.clkr.hw.init = &(const struct clk_init_data) {
243
+
.name = "gpu_cc_demet_div_clk_src",
244
+
.parent_hws = (const struct clk_hw*[]) {
245
+
&gpu_cc_xo_clk_src.clkr.hw,
246
+
},
247
+
.num_parents = 1,
248
+
.flags = CLK_SET_RATE_PARENT,
249
+
.ops = &clk_regmap_div_ro_ops,
250
+
},
251
+
};
252
+
253
+
static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
254
+
.reg = 0x9050,
255
+
.shift = 0,
256
+
.width = 4,
257
+
.clkr.hw.init = &(const struct clk_init_data) {
258
+
.name = "gpu_cc_xo_div_clk_src",
259
+
.parent_hws = (const struct clk_hw*[]) {
260
+
&gpu_cc_xo_clk_src.clkr.hw,
261
+
},
262
+
.num_parents = 1,
263
+
.flags = CLK_SET_RATE_PARENT,
264
+
.ops = &clk_regmap_div_ro_ops,
265
+
},
266
+
};
267
+
268
+
static struct clk_branch gpu_cc_ahb_clk = {
269
+
.halt_reg = 0x911c,
270
+
.halt_check = BRANCH_HALT_DELAY,
271
+
.clkr = {
272
+
.enable_reg = 0x911c,
273
+
.enable_mask = BIT(0),
274
+
.hw.init = &(const struct clk_init_data) {
275
+
.name = "gpu_cc_ahb_clk",
276
+
.parent_hws = (const struct clk_hw*[]) {
277
+
&gpu_cc_hub_clk_src.clkr.hw,
278
+
},
279
+
.num_parents = 1,
280
+
.flags = CLK_SET_RATE_PARENT,
281
+
.ops = &clk_branch2_ops,
282
+
},
283
+
},
284
+
};
285
+
286
+
static struct clk_branch gpu_cc_crc_ahb_clk = {
287
+
.halt_reg = 0x9120,
288
+
.halt_check = BRANCH_HALT_VOTED,
289
+
.clkr = {
290
+
.enable_reg = 0x9120,
291
+
.enable_mask = BIT(0),
292
+
.hw.init = &(const struct clk_init_data) {
293
+
.name = "gpu_cc_crc_ahb_clk",
294
+
.parent_hws = (const struct clk_hw*[]) {
295
+
&gpu_cc_hub_clk_src.clkr.hw,
296
+
},
297
+
.num_parents = 1,
298
+
.flags = CLK_SET_RATE_PARENT,
299
+
.ops = &clk_branch2_ops,
300
+
},
301
+
},
302
+
};
303
+
304
+
static struct clk_branch gpu_cc_cx_ff_clk = {
305
+
.halt_reg = 0x914c,
306
+
.halt_check = BRANCH_HALT,
307
+
.clkr = {
308
+
.enable_reg = 0x914c,
309
+
.enable_mask = BIT(0),
310
+
.hw.init = &(const struct clk_init_data) {
311
+
.name = "gpu_cc_cx_ff_clk",
312
+
.parent_hws = (const struct clk_hw*[]) {
313
+
&gpu_cc_ff_clk_src.clkr.hw,
314
+
},
315
+
.num_parents = 1,
316
+
.flags = CLK_SET_RATE_PARENT,
317
+
.ops = &clk_branch2_ops,
318
+
},
319
+
},
320
+
};
321
+
322
+
static struct clk_branch gpu_cc_cx_gmu_clk = {
323
+
.halt_reg = 0x913c,
324
+
.halt_check = BRANCH_HALT_VOTED,
325
+
.clkr = {
326
+
.enable_reg = 0x913c,
327
+
.enable_mask = BIT(0),
328
+
.hw.init = &(const struct clk_init_data) {
329
+
.name = "gpu_cc_cx_gmu_clk",
330
+
.parent_hws = (const struct clk_hw*[]) {
331
+
&gpu_cc_gmu_clk_src.clkr.hw,
332
+
},
333
+
.num_parents = 1,
334
+
.flags = CLK_SET_RATE_PARENT,
335
+
.ops = &clk_branch2_aon_ops,
336
+
},
337
+
},
338
+
};
339
+
340
+
static struct clk_branch gpu_cc_cxo_clk = {
341
+
.halt_reg = 0x9144,
342
+
.halt_check = BRANCH_HALT,
343
+
.clkr = {
344
+
.enable_reg = 0x9144,
345
+
.enable_mask = BIT(0),
346
+
.hw.init = &(const struct clk_init_data) {
347
+
.name = "gpu_cc_cxo_clk",
348
+
.parent_hws = (const struct clk_hw*[]) {
349
+
&gpu_cc_xo_clk_src.clkr.hw,
350
+
},
351
+
.num_parents = 1,
352
+
.flags = CLK_SET_RATE_PARENT,
353
+
.ops = &clk_branch2_ops,
354
+
},
355
+
},
356
+
};
357
+
358
+
static struct clk_branch gpu_cc_freq_measure_clk = {
359
+
.halt_reg = 0x9008,
360
+
.halt_check = BRANCH_HALT,
361
+
.clkr = {
362
+
.enable_reg = 0x9008,
363
+
.enable_mask = BIT(0),
364
+
.hw.init = &(const struct clk_init_data) {
365
+
.name = "gpu_cc_freq_measure_clk",
366
+
.parent_hws = (const struct clk_hw*[]) {
367
+
&gpu_cc_xo_div_clk_src.clkr.hw,
368
+
},
369
+
.num_parents = 1,
370
+
.flags = CLK_SET_RATE_PARENT,
371
+
.ops = &clk_branch2_ops,
372
+
},
373
+
},
374
+
};
375
+
376
+
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
377
+
.halt_reg = 0x7000,
378
+
.halt_check = BRANCH_HALT_VOTED,
379
+
.clkr = {
380
+
.enable_reg = 0x7000,
381
+
.enable_mask = BIT(0),
382
+
.hw.init = &(const struct clk_init_data) {
383
+
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
384
+
.ops = &clk_branch2_ops,
385
+
},
386
+
},
387
+
};
388
+
389
+
static struct clk_branch gpu_cc_hub_aon_clk = {
390
+
.halt_reg = 0x93e8,
391
+
.halt_check = BRANCH_HALT,
392
+
.clkr = {
393
+
.enable_reg = 0x93e8,
394
+
.enable_mask = BIT(0),
395
+
.hw.init = &(const struct clk_init_data) {
396
+
.name = "gpu_cc_hub_aon_clk",
397
+
.parent_hws = (const struct clk_hw*[]) {
398
+
&gpu_cc_hub_clk_src.clkr.hw,
399
+
},
400
+
.num_parents = 1,
401
+
.flags = CLK_SET_RATE_PARENT,
402
+
.ops = &clk_branch2_aon_ops,
403
+
},
404
+
},
405
+
};
406
+
407
+
static struct clk_branch gpu_cc_hub_cx_int_clk = {
408
+
.halt_reg = 0x9148,
409
+
.halt_check = BRANCH_HALT_VOTED,
410
+
.clkr = {
411
+
.enable_reg = 0x9148,
412
+
.enable_mask = BIT(0),
413
+
.hw.init = &(const struct clk_init_data) {
414
+
.name = "gpu_cc_hub_cx_int_clk",
415
+
.parent_hws = (const struct clk_hw*[]) {
416
+
&gpu_cc_hub_clk_src.clkr.hw,
417
+
},
418
+
.num_parents = 1,
419
+
.flags = CLK_SET_RATE_PARENT,
420
+
.ops = &clk_branch2_aon_ops,
421
+
},
422
+
},
423
+
};
424
+
425
+
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
426
+
.halt_reg = 0x9150,
427
+
.halt_check = BRANCH_HALT_VOTED,
428
+
.clkr = {
429
+
.enable_reg = 0x9150,
430
+
.enable_mask = BIT(0),
431
+
.hw.init = &(const struct clk_init_data) {
432
+
.name = "gpu_cc_memnoc_gfx_clk",
433
+
.ops = &clk_branch2_ops,
434
+
},
435
+
},
436
+
};
437
+
438
+
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
439
+
.halt_reg = 0x9288,
440
+
.halt_check = BRANCH_HALT,
441
+
.clkr = {
442
+
.enable_reg = 0x9288,
443
+
.enable_mask = BIT(0),
444
+
.hw.init = &(const struct clk_init_data) {
445
+
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
446
+
.ops = &clk_branch2_ops,
447
+
},
448
+
},
449
+
};
450
+
451
+
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
452
+
.halt_reg = 0x928c,
453
+
.halt_check = BRANCH_HALT,
454
+
.clkr = {
455
+
.enable_reg = 0x928c,
456
+
.enable_mask = BIT(0),
457
+
.hw.init = &(const struct clk_init_data) {
458
+
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
459
+
.ops = &clk_branch2_ops,
460
+
},
461
+
},
462
+
};
463
+
464
+
static struct clk_branch gpu_cc_sleep_clk = {
465
+
.halt_reg = 0x9134,
466
+
.halt_check = BRANCH_HALT_VOTED,
467
+
.clkr = {
468
+
.enable_reg = 0x9134,
469
+
.enable_mask = BIT(0),
470
+
.hw.init = &(const struct clk_init_data) {
471
+
.name = "gpu_cc_sleep_clk",
472
+
.ops = &clk_branch2_ops,
473
+
},
474
+
},
475
+
};
476
+
477
+
static struct gdsc gpu_cc_cx_gdsc = {
478
+
.gdscr = 0x9108,
479
+
.gds_hw_ctrl = 0x953c,
480
+
.en_rest_wait_val = 0x2,
481
+
.en_few_wait_val = 0x2,
482
+
.clk_dis_wait_val = 0xf,
483
+
.pd = {
484
+
.name = "gpu_cc_cx_gdsc",
485
+
},
486
+
.pwrsts = PWRSTS_OFF_ON,
487
+
.flags = RETAIN_FF_ENABLE | VOTABLE,
488
+
};
489
+
490
+
static struct gdsc gpu_cc_gx_gdsc = {
491
+
.gdscr = 0x905c,
492
+
.clamp_io_ctrl = 0x9504,
493
+
.en_rest_wait_val = 0x2,
494
+
.en_few_wait_val = 0x2,
495
+
.clk_dis_wait_val = 0xf,
496
+
.pd = {
497
+
.name = "gpu_cc_gx_gdsc",
498
+
.power_on = gdsc_gx_do_nothing_enable,
499
+
},
500
+
.pwrsts = PWRSTS_OFF_ON,
501
+
.flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
502
+
};
503
+
504
+
static struct clk_regmap *gpu_cc_sm8550_clocks[] = {
505
+
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
506
+
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
507
+
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
508
+
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
509
+
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
510
+
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
511
+
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
512
+
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
513
+
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
514
+
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
515
+
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
516
+
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
517
+
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
518
+
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
519
+
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
520
+
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
521
+
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
522
+
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
523
+
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
524
+
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
525
+
[GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
526
+
};
527
+
528
+
static struct gdsc *gpu_cc_sm8550_gdscs[] = {
529
+
[GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
530
+
[GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc,
531
+
};
532
+
533
+
static const struct qcom_reset_map gpu_cc_sm8550_resets[] = {
534
+
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
535
+
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
536
+
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
537
+
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
538
+
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
539
+
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
540
+
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
541
+
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
542
+
};
543
+
544
+
static const struct regmap_config gpu_cc_sm8550_regmap_config = {
545
+
.reg_bits = 32,
546
+
.reg_stride = 4,
547
+
.val_bits = 32,
548
+
.max_register = 0x9988,
549
+
.fast_io = true,
550
+
};
551
+
552
+
static const struct qcom_cc_desc gpu_cc_sm8550_desc = {
553
+
.config = &gpu_cc_sm8550_regmap_config,
554
+
.clks = gpu_cc_sm8550_clocks,
555
+
.num_clks = ARRAY_SIZE(gpu_cc_sm8550_clocks),
556
+
.resets = gpu_cc_sm8550_resets,
557
+
.num_resets = ARRAY_SIZE(gpu_cc_sm8550_resets),
558
+
.gdscs = gpu_cc_sm8550_gdscs,
559
+
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8550_gdscs),
560
+
};
561
+
562
+
static const struct of_device_id gpu_cc_sm8550_match_table[] = {
563
+
{ .compatible = "qcom,sm8550-gpucc" },
564
+
{ }
565
+
};
566
+
MODULE_DEVICE_TABLE(of, gpu_cc_sm8550_match_table);
567
+
568
+
static int gpu_cc_sm8550_probe(struct platform_device *pdev)
569
+
{
570
+
struct regmap *regmap;
571
+
572
+
regmap = qcom_cc_map(pdev, &gpu_cc_sm8550_desc);
573
+
if (IS_ERR(regmap))
574
+
return PTR_ERR(regmap);
575
+
576
+
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
577
+
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
578
+
579
+
/*
580
+
* Keep clocks always enabled:
581
+
* gpu_cc_cxo_aon_clk
582
+
* gpu_cc_demet_clk
583
+
*/
584
+
regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0));
585
+
regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0));
586
+
587
+
return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap);
588
+
}
589
+
590
+
static struct platform_driver gpu_cc_sm8550_driver = {
591
+
.probe = gpu_cc_sm8550_probe,
592
+
.driver = {
593
+
.name = "gpu_cc-sm8550",
594
+
.of_match_table = gpu_cc_sm8550_match_table,
595
+
},
596
+
};
597
+
598
+
static int __init gpu_cc_sm8550_init(void)
599
+
{
600
+
return platform_driver_register(&gpu_cc_sm8550_driver);
601
+
}
602
+
subsys_initcall(gpu_cc_sm8550_init);
603
+
604
+
static void __exit gpu_cc_sm8550_exit(void)
605
+
{
606
+
platform_driver_unregister(&gpu_cc_sm8550_driver);
607
+
}
608
+
module_exit(gpu_cc_sm8550_exit);
609
+
610
+
MODULE_DESCRIPTION("QTI GPUCC SM8550 Driver");
611
+
MODULE_LICENSE("GPL");
+87
drivers/clk/qcom/lpasscc-sc8280xp.c
+87
drivers/clk/qcom/lpasscc-sc8280xp.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2022, Linaro Limited
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/err.h>
8
+
#include <linux/kernel.h>
9
+
#include <linux/module.h>
10
+
#include <linux/of_device.h>
11
+
#include <linux/regmap.h>
12
+
13
+
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
14
+
15
+
#include "common.h"
16
+
#include "reset.h"
17
+
18
+
static const struct qcom_reset_map lpass_audiocc_sc8280xp_resets[] = {
19
+
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
20
+
[LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
21
+
[LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 },
22
+
};
23
+
24
+
static struct regmap_config lpass_audiocc_sc8280xp_regmap_config = {
25
+
.reg_bits = 32,
26
+
.reg_stride = 4,
27
+
.val_bits = 32,
28
+
.name = "lpass-audio-csr",
29
+
.max_register = 0x1000,
30
+
};
31
+
32
+
static const struct qcom_cc_desc lpass_audiocc_sc8280xp_reset_desc = {
33
+
.config = &lpass_audiocc_sc8280xp_regmap_config,
34
+
.resets = lpass_audiocc_sc8280xp_resets,
35
+
.num_resets = ARRAY_SIZE(lpass_audiocc_sc8280xp_resets),
36
+
};
37
+
38
+
static const struct qcom_reset_map lpasscc_sc8280xp_resets[] = {
39
+
[LPASS_AUDIO_SWR_TX_CGCR] = { 0xc010, 1 },
40
+
};
41
+
42
+
static struct regmap_config lpasscc_sc8280xp_regmap_config = {
43
+
.reg_bits = 32,
44
+
.reg_stride = 4,
45
+
.val_bits = 32,
46
+
.name = "lpass-tcsr",
47
+
.max_register = 0x12000,
48
+
};
49
+
50
+
static const struct qcom_cc_desc lpasscc_sc8280xp_reset_desc = {
51
+
.config = &lpasscc_sc8280xp_regmap_config,
52
+
.resets = lpasscc_sc8280xp_resets,
53
+
.num_resets = ARRAY_SIZE(lpasscc_sc8280xp_resets),
54
+
};
55
+
56
+
static const struct of_device_id lpasscc_sc8280xp_match_table[] = {
57
+
{
58
+
.compatible = "qcom,sc8280xp-lpassaudiocc",
59
+
.data = &lpass_audiocc_sc8280xp_reset_desc,
60
+
}, {
61
+
.compatible = "qcom,sc8280xp-lpasscc",
62
+
.data = &lpasscc_sc8280xp_reset_desc,
63
+
},
64
+
{ }
65
+
};
66
+
MODULE_DEVICE_TABLE(of, lpasscc_sc8280xp_match_table);
67
+
68
+
static int lpasscc_sc8280xp_probe(struct platform_device *pdev)
69
+
{
70
+
const struct qcom_cc_desc *desc = of_device_get_match_data(&pdev->dev);
71
+
72
+
return qcom_cc_probe_by_index(pdev, 0, desc);
73
+
}
74
+
75
+
static struct platform_driver lpasscc_sc8280xp_driver = {
76
+
.probe = lpasscc_sc8280xp_probe,
77
+
.driver = {
78
+
.name = "lpasscc-sc8280xp",
79
+
.of_match_table = lpasscc_sc8280xp_match_table,
80
+
},
81
+
};
82
+
83
+
module_platform_driver(lpasscc_sc8280xp_driver);
84
+
85
+
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
86
+
MODULE_DESCRIPTION("QTI LPASSCC SC8280XP Driver");
87
+
MODULE_LICENSE("GPL");
+2
-21
drivers/clk/qcom/mmcc-msm8974.c
+2
-21
drivers/clk/qcom/mmcc-msm8974.c
···
485
485
.name = "mdp_clk_src",
486
486
.parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
487
487
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
488
-
.ops = &clk_rcg2_ops,
488
+
.ops = &clk_rcg2_shared_ops,
489
489
},
490
490
};
491
491
···
2204
2204
},
2205
2205
};
2206
2206
2207
-
static struct clk_branch oxili_ocmemgx_clk = {
2208
-
.halt_reg = 0x402c,
2209
-
.clkr = {
2210
-
.enable_reg = 0x402c,
2211
-
.enable_mask = BIT(0),
2212
-
.hw.init = &(struct clk_init_data){
2213
-
.name = "oxili_ocmemgx_clk",
2214
-
.parent_data = (const struct clk_parent_data[]){
2215
-
{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
2216
-
},
2217
-
.num_parents = 1,
2218
-
.flags = CLK_SET_RATE_PARENT,
2219
-
.ops = &clk_branch2_ops,
2220
-
},
2221
-
},
2222
-
};
2223
-
2224
2207
static struct clk_branch ocmemnoc_clk = {
2225
2208
.halt_reg = 0x50b4,
2226
2209
.clkr = {
···
2384
2401
.pd = {
2385
2402
.name = "mdss",
2386
2403
},
2387
-
.pwrsts = PWRSTS_RET_ON,
2404
+
.pwrsts = PWRSTS_OFF_ON,
2388
2405
};
2389
2406
2390
2407
static struct gdsc camss_jpeg_gdsc = {
···
2495
2512
[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2496
2513
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2497
2514
[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2498
-
[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2499
2515
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2500
2516
[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2501
2517
[OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
···
2652
2670
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2653
2671
[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2654
2672
[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2655
-
[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2656
2673
[OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2657
2674
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2658
2675
[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
+552
drivers/clk/qcom/videocc-sm8350.c
+552
drivers/clk/qcom/videocc-sm8350.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#include <linux/clk-provider.h>
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/pm_clock.h>
11
+
#include <linux/pm_runtime.h>
12
+
#include <linux/regmap.h>
13
+
14
+
#include <dt-bindings/clock/qcom,sm8350-videocc.h>
15
+
#include <dt-bindings/reset/qcom,sm8350-videocc.h>
16
+
17
+
#include "clk-alpha-pll.h"
18
+
#include "clk-branch.h"
19
+
#include "clk-rcg.h"
20
+
#include "clk-regmap.h"
21
+
#include "clk-regmap-divider.h"
22
+
#include "common.h"
23
+
#include "reset.h"
24
+
#include "gdsc.h"
25
+
26
+
enum {
27
+
DT_BI_TCXO,
28
+
DT_BI_TCXO_AO,
29
+
DT_SLEEP_CLK,
30
+
};
31
+
32
+
enum {
33
+
P_BI_TCXO,
34
+
P_BI_TCXO_AO,
35
+
P_SLEEP_CLK,
36
+
P_VIDEO_PLL0_OUT_MAIN,
37
+
P_VIDEO_PLL1_OUT_MAIN,
38
+
};
39
+
40
+
static const struct pll_vco lucid_5lpe_vco[] = {
41
+
{ 249600000, 1750000000, 0 },
42
+
};
43
+
44
+
static const struct alpha_pll_config video_pll0_config = {
45
+
.l = 0x25,
46
+
.alpha = 0x8000,
47
+
.config_ctl_val = 0x20485699,
48
+
.config_ctl_hi_val = 0x00002261,
49
+
.config_ctl_hi1_val = 0x2a9a699c,
50
+
.test_ctl_val = 0x00000000,
51
+
.test_ctl_hi_val = 0x00000000,
52
+
.test_ctl_hi1_val = 0x01800000,
53
+
.user_ctl_val = 0x00000000,
54
+
.user_ctl_hi_val = 0x00000805,
55
+
.user_ctl_hi1_val = 0x00000000,
56
+
};
57
+
58
+
static struct clk_alpha_pll video_pll0 = {
59
+
.offset = 0x42c,
60
+
.vco_table = lucid_5lpe_vco,
61
+
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
62
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
63
+
.clkr = {
64
+
.hw.init = &(const struct clk_init_data) {
65
+
.name = "video_pll0",
66
+
.parent_data = &(const struct clk_parent_data){
67
+
.index = DT_BI_TCXO,
68
+
},
69
+
.num_parents = 1,
70
+
.ops = &clk_alpha_pll_lucid_5lpe_ops,
71
+
},
72
+
},
73
+
};
74
+
75
+
static const struct alpha_pll_config video_pll1_config = {
76
+
.l = 0x2b,
77
+
.alpha = 0xc000,
78
+
.config_ctl_val = 0x20485699,
79
+
.config_ctl_hi_val = 0x00002261,
80
+
.config_ctl_hi1_val = 0x2a9a699c,
81
+
.test_ctl_val = 0x00000000,
82
+
.test_ctl_hi_val = 0x00000000,
83
+
.test_ctl_hi1_val = 0x01800000,
84
+
.user_ctl_val = 0x00000000,
85
+
.user_ctl_hi_val = 0x00000805,
86
+
.user_ctl_hi1_val = 0x00000000,
87
+
};
88
+
89
+
static struct clk_alpha_pll video_pll1 = {
90
+
.offset = 0x7d0,
91
+
.vco_table = lucid_5lpe_vco,
92
+
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
93
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
94
+
.clkr = {
95
+
.hw.init = &(const struct clk_init_data) {
96
+
.name = "video_pll1",
97
+
.parent_data = &(const struct clk_parent_data){
98
+
.index = DT_BI_TCXO,
99
+
},
100
+
.num_parents = 1,
101
+
.ops = &clk_alpha_pll_lucid_5lpe_ops,
102
+
},
103
+
},
104
+
};
105
+
106
+
static const struct parent_map video_cc_parent_map_0[] = {
107
+
{ P_BI_TCXO_AO, 0 },
108
+
};
109
+
110
+
static const struct clk_parent_data video_cc_parent_data_0[] = {
111
+
{ .index = DT_BI_TCXO_AO },
112
+
};
113
+
114
+
static const struct parent_map video_cc_parent_map_1[] = {
115
+
{ P_BI_TCXO, 0 },
116
+
{ P_VIDEO_PLL0_OUT_MAIN, 1 },
117
+
};
118
+
119
+
static const struct clk_parent_data video_cc_parent_data_1[] = {
120
+
{ .index = DT_BI_TCXO },
121
+
{ .hw = &video_pll0.clkr.hw },
122
+
};
123
+
124
+
static const struct parent_map video_cc_parent_map_2[] = {
125
+
{ P_BI_TCXO, 0 },
126
+
{ P_VIDEO_PLL1_OUT_MAIN, 1 },
127
+
};
128
+
129
+
static const struct clk_parent_data video_cc_parent_data_2[] = {
130
+
{ .index = DT_BI_TCXO },
131
+
{ .hw = &video_pll1.clkr.hw },
132
+
};
133
+
134
+
static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
135
+
F(19200000, P_BI_TCXO, 1, 0, 0),
136
+
{ }
137
+
};
138
+
139
+
static struct clk_rcg2 video_cc_ahb_clk_src = {
140
+
.cmd_rcgr = 0xbd4,
141
+
.mnd_width = 0,
142
+
.hid_width = 5,
143
+
.parent_map = video_cc_parent_map_0,
144
+
.freq_tbl = ftbl_video_cc_ahb_clk_src,
145
+
.clkr.hw.init = &(const struct clk_init_data) {
146
+
.name = "video_cc_ahb_clk_src",
147
+
.parent_data = video_cc_parent_data_0,
148
+
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
149
+
.flags = CLK_SET_RATE_PARENT,
150
+
.ops = &clk_rcg2_shared_ops,
151
+
},
152
+
};
153
+
154
+
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
155
+
F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
156
+
F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
157
+
F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
158
+
F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
159
+
{ }
160
+
};
161
+
162
+
static struct clk_rcg2 video_cc_mvs0_clk_src = {
163
+
.cmd_rcgr = 0xb94,
164
+
.mnd_width = 0,
165
+
.hid_width = 5,
166
+
.parent_map = video_cc_parent_map_1,
167
+
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
168
+
.clkr.hw.init = &(const struct clk_init_data) {
169
+
.name = "video_cc_mvs0_clk_src",
170
+
.parent_data = video_cc_parent_data_1,
171
+
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
172
+
.flags = CLK_SET_RATE_PARENT,
173
+
.ops = &clk_rcg2_shared_ops,
174
+
},
175
+
};
176
+
177
+
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
178
+
F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
179
+
F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
180
+
F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
181
+
{ }
182
+
};
183
+
184
+
static struct clk_rcg2 video_cc_mvs1_clk_src = {
185
+
.cmd_rcgr = 0xbb4,
186
+
.mnd_width = 0,
187
+
.hid_width = 5,
188
+
.parent_map = video_cc_parent_map_2,
189
+
.freq_tbl = ftbl_video_cc_mvs1_clk_src,
190
+
.clkr.hw.init = &(const struct clk_init_data) {
191
+
.name = "video_cc_mvs1_clk_src",
192
+
.parent_data = video_cc_parent_data_2,
193
+
.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
194
+
.flags = CLK_SET_RATE_PARENT,
195
+
.ops = &clk_rcg2_shared_ops,
196
+
},
197
+
};
198
+
199
+
static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
200
+
F(32000, P_SLEEP_CLK, 1, 0, 0),
201
+
{ }
202
+
};
203
+
204
+
static struct clk_rcg2 video_cc_sleep_clk_src = {
205
+
.cmd_rcgr = 0xef0,
206
+
.mnd_width = 0,
207
+
.hid_width = 5,
208
+
.freq_tbl = ftbl_video_cc_sleep_clk_src,
209
+
.clkr.hw.init = &(const struct clk_init_data) {
210
+
.name = "video_cc_sleep_clk_src",
211
+
.parent_data = &(const struct clk_parent_data){
212
+
.index = DT_SLEEP_CLK,
213
+
},
214
+
.num_parents = 1,
215
+
.flags = CLK_SET_RATE_PARENT,
216
+
.ops = &clk_rcg2_ops,
217
+
},
218
+
};
219
+
220
+
static struct clk_rcg2 video_cc_xo_clk_src = {
221
+
.cmd_rcgr = 0xecc,
222
+
.mnd_width = 0,
223
+
.hid_width = 5,
224
+
.parent_map = video_cc_parent_map_0,
225
+
.freq_tbl = ftbl_video_cc_ahb_clk_src,
226
+
.clkr.hw.init = &(const struct clk_init_data) {
227
+
.name = "video_cc_xo_clk_src",
228
+
.parent_data = video_cc_parent_data_0,
229
+
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
230
+
.flags = CLK_SET_RATE_PARENT,
231
+
.ops = &clk_rcg2_ops,
232
+
},
233
+
};
234
+
235
+
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
236
+
.reg = 0xd54,
237
+
.shift = 0,
238
+
.width = 4,
239
+
.clkr.hw.init = &(const struct clk_init_data) {
240
+
.name = "video_cc_mvs0_div_clk_src",
241
+
.parent_hws = (const struct clk_hw*[]){
242
+
&video_cc_mvs0_clk_src.clkr.hw,
243
+
},
244
+
.num_parents = 1,
245
+
.flags = CLK_SET_RATE_PARENT,
246
+
.ops = &clk_regmap_div_ro_ops,
247
+
},
248
+
};
249
+
250
+
static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
251
+
.reg = 0xc54,
252
+
.shift = 0,
253
+
.width = 4,
254
+
.clkr.hw.init = &(const struct clk_init_data) {
255
+
.name = "video_cc_mvs0c_div2_div_clk_src",
256
+
.parent_hws = (const struct clk_hw*[]){
257
+
&video_cc_mvs0_clk_src.clkr.hw,
258
+
},
259
+
.num_parents = 1,
260
+
.flags = CLK_SET_RATE_PARENT,
261
+
.ops = &clk_regmap_div_ro_ops,
262
+
},
263
+
};
264
+
265
+
static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
266
+
.reg = 0xdd4,
267
+
.shift = 0,
268
+
.width = 4,
269
+
.clkr.hw.init = &(const struct clk_init_data) {
270
+
.name = "video_cc_mvs1_div_clk_src",
271
+
.parent_hws = (const struct clk_hw*[]){
272
+
&video_cc_mvs1_clk_src.clkr.hw,
273
+
},
274
+
.num_parents = 1,
275
+
.flags = CLK_SET_RATE_PARENT,
276
+
.ops = &clk_regmap_div_ro_ops,
277
+
},
278
+
};
279
+
280
+
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
281
+
.reg = 0xcf4,
282
+
.shift = 0,
283
+
.width = 4,
284
+
.clkr.hw.init = &(const struct clk_init_data) {
285
+
.name = "video_cc_mvs1c_div2_div_clk_src",
286
+
.parent_hws = (const struct clk_hw*[]){
287
+
&video_cc_mvs1_clk_src.clkr.hw,
288
+
},
289
+
.num_parents = 1,
290
+
.flags = CLK_SET_RATE_PARENT,
291
+
.ops = &clk_regmap_div_ro_ops,
292
+
},
293
+
};
294
+
295
+
static struct clk_branch video_cc_mvs0_clk = {
296
+
.halt_reg = 0xd34,
297
+
.halt_check = BRANCH_HALT_VOTED,
298
+
.hwcg_reg = 0xd34,
299
+
.hwcg_bit = 1,
300
+
.clkr = {
301
+
.enable_reg = 0xd34,
302
+
.enable_mask = BIT(0),
303
+
.hw.init = &(const struct clk_init_data) {
304
+
.name = "video_cc_mvs0_clk",
305
+
.parent_hws = (const struct clk_hw*[]){
306
+
&video_cc_mvs0_div_clk_src.clkr.hw,
307
+
},
308
+
.num_parents = 1,
309
+
.flags = CLK_SET_RATE_PARENT,
310
+
.ops = &clk_branch2_ops,
311
+
},
312
+
},
313
+
};
314
+
315
+
static struct clk_branch video_cc_mvs0c_clk = {
316
+
.halt_reg = 0xc34,
317
+
.halt_check = BRANCH_HALT,
318
+
.clkr = {
319
+
.enable_reg = 0xc34,
320
+
.enable_mask = BIT(0),
321
+
.hw.init = &(const struct clk_init_data) {
322
+
.name = "video_cc_mvs0c_clk",
323
+
.parent_hws = (const struct clk_hw*[]){
324
+
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
325
+
},
326
+
.num_parents = 1,
327
+
.flags = CLK_SET_RATE_PARENT,
328
+
.ops = &clk_branch2_ops,
329
+
},
330
+
},
331
+
};
332
+
333
+
static struct clk_branch video_cc_mvs1_clk = {
334
+
.halt_reg = 0xdb4,
335
+
.halt_check = BRANCH_HALT_VOTED,
336
+
.hwcg_reg = 0xdb4,
337
+
.hwcg_bit = 1,
338
+
.clkr = {
339
+
.enable_reg = 0xdb4,
340
+
.enable_mask = BIT(0),
341
+
.hw.init = &(const struct clk_init_data) {
342
+
.name = "video_cc_mvs1_clk",
343
+
.parent_hws = (const struct clk_hw*[]){
344
+
&video_cc_mvs1_div_clk_src.clkr.hw,
345
+
},
346
+
.num_parents = 1,
347
+
.flags = CLK_SET_RATE_PARENT,
348
+
.ops = &clk_branch2_ops,
349
+
},
350
+
},
351
+
};
352
+
353
+
static struct clk_branch video_cc_mvs1_div2_clk = {
354
+
.halt_reg = 0xdf4,
355
+
.halt_check = BRANCH_HALT_VOTED,
356
+
.hwcg_reg = 0xdf4,
357
+
.hwcg_bit = 1,
358
+
.clkr = {
359
+
.enable_reg = 0xdf4,
360
+
.enable_mask = BIT(0),
361
+
.hw.init = &(const struct clk_init_data) {
362
+
.name = "video_cc_mvs1_div2_clk",
363
+
.parent_hws = (const struct clk_hw*[]){
364
+
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
365
+
},
366
+
.num_parents = 1,
367
+
.flags = CLK_SET_RATE_PARENT,
368
+
.ops = &clk_branch2_ops,
369
+
},
370
+
},
371
+
};
372
+
373
+
static struct clk_branch video_cc_mvs1c_clk = {
374
+
.halt_reg = 0xcd4,
375
+
.halt_check = BRANCH_HALT,
376
+
.clkr = {
377
+
.enable_reg = 0xcd4,
378
+
.enable_mask = BIT(0),
379
+
.hw.init = &(const struct clk_init_data) {
380
+
.name = "video_cc_mvs1c_clk",
381
+
.parent_hws = (const struct clk_hw*[]){
382
+
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
383
+
},
384
+
.num_parents = 1,
385
+
.flags = CLK_SET_RATE_PARENT,
386
+
.ops = &clk_branch2_ops,
387
+
},
388
+
},
389
+
};
390
+
391
+
static struct clk_branch video_cc_sleep_clk = {
392
+
.halt_reg = 0xf10,
393
+
.halt_check = BRANCH_HALT,
394
+
.clkr = {
395
+
.enable_reg = 0xf10,
396
+
.enable_mask = BIT(0),
397
+
.hw.init = &(const struct clk_init_data) {
398
+
.name = "video_cc_sleep_clk",
399
+
.parent_hws = (const struct clk_hw*[]){
400
+
&video_cc_sleep_clk_src.clkr.hw,
401
+
},
402
+
.num_parents = 1,
403
+
.flags = CLK_SET_RATE_PARENT,
404
+
.ops = &clk_branch2_ops,
405
+
},
406
+
},
407
+
};
408
+
409
+
static struct gdsc mvs0c_gdsc = {
410
+
.gdscr = 0xbf8,
411
+
.pd = {
412
+
.name = "mvs0c_gdsc",
413
+
},
414
+
.flags = RETAIN_FF_ENABLE,
415
+
.pwrsts = PWRSTS_OFF_ON,
416
+
};
417
+
418
+
static struct gdsc mvs1c_gdsc = {
419
+
.gdscr = 0xc98,
420
+
.pd = {
421
+
.name = "mvs1c_gdsc",
422
+
},
423
+
.flags = RETAIN_FF_ENABLE,
424
+
.pwrsts = PWRSTS_OFF_ON,
425
+
};
426
+
427
+
static struct gdsc mvs0_gdsc = {
428
+
.gdscr = 0xd18,
429
+
.pd = {
430
+
.name = "mvs0_gdsc",
431
+
},
432
+
.flags = HW_CTRL | RETAIN_FF_ENABLE,
433
+
.pwrsts = PWRSTS_OFF_ON,
434
+
};
435
+
436
+
static struct gdsc mvs1_gdsc = {
437
+
.gdscr = 0xd98,
438
+
.pd = {
439
+
.name = "mvs1_gdsc",
440
+
},
441
+
.flags = HW_CTRL | RETAIN_FF_ENABLE,
442
+
.pwrsts = PWRSTS_OFF_ON,
443
+
};
444
+
445
+
static struct clk_regmap *video_cc_sm8350_clocks[] = {
446
+
[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
447
+
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
448
+
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
449
+
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
450
+
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
451
+
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
452
+
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
453
+
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
454
+
[VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr,
455
+
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
456
+
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
457
+
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
458
+
[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
459
+
[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
460
+
[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
461
+
[VIDEO_PLL0] = &video_pll0.clkr,
462
+
[VIDEO_PLL1] = &video_pll1.clkr,
463
+
};
464
+
465
+
static const struct qcom_reset_map video_cc_sm8350_resets[] = {
466
+
[VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
467
+
[VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
468
+
[VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
469
+
[VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
470
+
[VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
471
+
[VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
472
+
[VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
473
+
};
474
+
475
+
static struct gdsc *video_cc_sm8350_gdscs[] = {
476
+
[MVS0C_GDSC] = &mvs0c_gdsc,
477
+
[MVS1C_GDSC] = &mvs1c_gdsc,
478
+
[MVS0_GDSC] = &mvs0_gdsc,
479
+
[MVS1_GDSC] = &mvs1_gdsc,
480
+
};
481
+
482
+
static const struct regmap_config video_cc_sm8350_regmap_config = {
483
+
.reg_bits = 32,
484
+
.reg_stride = 4,
485
+
.val_bits = 32,
486
+
.max_register = 0x10000,
487
+
.fast_io = true,
488
+
};
489
+
490
+
static struct qcom_cc_desc video_cc_sm8350_desc = {
491
+
.config = &video_cc_sm8350_regmap_config,
492
+
.clks = video_cc_sm8350_clocks,
493
+
.num_clks = ARRAY_SIZE(video_cc_sm8350_clocks),
494
+
.resets = video_cc_sm8350_resets,
495
+
.num_resets = ARRAY_SIZE(video_cc_sm8350_resets),
496
+
.gdscs = video_cc_sm8350_gdscs,
497
+
.num_gdscs = ARRAY_SIZE(video_cc_sm8350_gdscs),
498
+
};
499
+
500
+
static int video_cc_sm8350_probe(struct platform_device *pdev)
501
+
{
502
+
struct regmap *regmap;
503
+
int ret;
504
+
505
+
ret = devm_pm_runtime_enable(&pdev->dev);
506
+
if (ret)
507
+
return ret;
508
+
509
+
ret = pm_runtime_resume_and_get(&pdev->dev);
510
+
if (ret)
511
+
return ret;
512
+
513
+
regmap = qcom_cc_map(pdev, &video_cc_sm8350_desc);
514
+
if (IS_ERR(regmap)) {
515
+
pm_runtime_put(&pdev->dev);
516
+
return PTR_ERR(regmap);
517
+
}
518
+
519
+
clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
520
+
clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config);
521
+
522
+
/*
523
+
* Keep clocks always enabled:
524
+
* video_cc_ahb_clk
525
+
* video_cc_xo_clk
526
+
*/
527
+
regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
528
+
regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0));
529
+
530
+
ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap);
531
+
pm_runtime_put(&pdev->dev);
532
+
533
+
return ret;
534
+
}
535
+
536
+
static const struct of_device_id video_cc_sm8350_match_table[] = {
537
+
{ .compatible = "qcom,sm8350-videocc" },
538
+
{ }
539
+
};
540
+
MODULE_DEVICE_TABLE(of, video_cc_sm8350_match_table);
541
+
542
+
static struct platform_driver video_cc_sm8350_driver = {
543
+
.probe = video_cc_sm8350_probe,
544
+
.driver = {
545
+
.name = "sm8350-videocc",
546
+
.of_match_table = video_cc_sm8350_match_table,
547
+
},
548
+
};
549
+
module_platform_driver(video_cc_sm8350_driver);
550
+
551
+
MODULE_DESCRIPTION("QTI SM8350 VIDEOCC Driver");
552
+
MODULE_LICENSE("GPL");
+463
drivers/clk/qcom/videocc-sm8450.c
+463
drivers/clk/qcom/videocc-sm8450.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/module.h>
8
+
#include <linux/of_device.h>
9
+
#include <linux/pm_runtime.h>
10
+
#include <linux/regmap.h>
11
+
12
+
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
13
+
14
+
#include "clk-alpha-pll.h"
15
+
#include "clk-branch.h"
16
+
#include "clk-rcg.h"
17
+
#include "clk-regmap.h"
18
+
#include "clk-regmap-divider.h"
19
+
#include "common.h"
20
+
#include "gdsc.h"
21
+
#include "reset.h"
22
+
23
+
enum {
24
+
DT_BI_TCXO,
25
+
};
26
+
27
+
enum {
28
+
P_BI_TCXO,
29
+
P_VIDEO_CC_PLL0_OUT_MAIN,
30
+
P_VIDEO_CC_PLL1_OUT_MAIN,
31
+
};
32
+
33
+
static const struct pll_vco lucid_evo_vco[] = {
34
+
{ 249600000, 2020000000, 0 },
35
+
};
36
+
37
+
static const struct alpha_pll_config video_cc_pll0_config = {
38
+
/* .l includes CAL_L_VAL, L_VAL fields */
39
+
.l = 0x0044001e,
40
+
.alpha = 0x0,
41
+
.config_ctl_val = 0x20485699,
42
+
.config_ctl_hi_val = 0x00182261,
43
+
.config_ctl_hi1_val = 0x32aa299c,
44
+
.user_ctl_val = 0x00000000,
45
+
.user_ctl_hi_val = 0x00000805,
46
+
};
47
+
48
+
static struct clk_alpha_pll video_cc_pll0 = {
49
+
.offset = 0x0,
50
+
.vco_table = lucid_evo_vco,
51
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
52
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
53
+
.clkr = {
54
+
.hw.init = &(const struct clk_init_data) {
55
+
.name = "video_cc_pll0",
56
+
.parent_data = &(const struct clk_parent_data) {
57
+
.index = DT_BI_TCXO,
58
+
},
59
+
.num_parents = 1,
60
+
.ops = &clk_alpha_pll_lucid_evo_ops,
61
+
},
62
+
},
63
+
};
64
+
65
+
static const struct alpha_pll_config video_cc_pll1_config = {
66
+
/* .l includes CAL_L_VAL, L_VAL fields */
67
+
.l = 0x0044002b,
68
+
.alpha = 0xc000,
69
+
.config_ctl_val = 0x20485699,
70
+
.config_ctl_hi_val = 0x00182261,
71
+
.config_ctl_hi1_val = 0x32aa299c,
72
+
.user_ctl_val = 0x00000000,
73
+
.user_ctl_hi_val = 0x00000805,
74
+
};
75
+
76
+
static struct clk_alpha_pll video_cc_pll1 = {
77
+
.offset = 0x1000,
78
+
.vco_table = lucid_evo_vco,
79
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
80
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
81
+
.clkr = {
82
+
.hw.init = &(const struct clk_init_data) {
83
+
.name = "video_cc_pll1",
84
+
.parent_data = &(const struct clk_parent_data) {
85
+
.index = DT_BI_TCXO,
86
+
},
87
+
.num_parents = 1,
88
+
.ops = &clk_alpha_pll_lucid_evo_ops,
89
+
},
90
+
},
91
+
};
92
+
93
+
static const struct parent_map video_cc_parent_map_0[] = {
94
+
{ P_BI_TCXO, 0 },
95
+
{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
96
+
};
97
+
98
+
static const struct clk_parent_data video_cc_parent_data_0[] = {
99
+
{ .index = DT_BI_TCXO },
100
+
{ .hw = &video_cc_pll0.clkr.hw },
101
+
};
102
+
103
+
static const struct parent_map video_cc_parent_map_1[] = {
104
+
{ P_BI_TCXO, 0 },
105
+
{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
106
+
};
107
+
108
+
static const struct clk_parent_data video_cc_parent_data_1[] = {
109
+
{ .index = DT_BI_TCXO },
110
+
{ .hw = &video_cc_pll1.clkr.hw },
111
+
};
112
+
113
+
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
114
+
F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
115
+
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
116
+
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
117
+
F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
118
+
F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
119
+
{ }
120
+
};
121
+
122
+
static struct clk_rcg2 video_cc_mvs0_clk_src = {
123
+
.cmd_rcgr = 0x8000,
124
+
.mnd_width = 0,
125
+
.hid_width = 5,
126
+
.parent_map = video_cc_parent_map_0,
127
+
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
128
+
.clkr.hw.init = &(const struct clk_init_data) {
129
+
.name = "video_cc_mvs0_clk_src",
130
+
.parent_data = video_cc_parent_data_0,
131
+
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
132
+
.flags = CLK_SET_RATE_PARENT,
133
+
.ops = &clk_rcg2_shared_ops,
134
+
},
135
+
};
136
+
137
+
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
138
+
F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
139
+
F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
140
+
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
141
+
F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
142
+
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
143
+
{ }
144
+
};
145
+
146
+
static struct clk_rcg2 video_cc_mvs1_clk_src = {
147
+
.cmd_rcgr = 0x8018,
148
+
.mnd_width = 0,
149
+
.hid_width = 5,
150
+
.parent_map = video_cc_parent_map_1,
151
+
.freq_tbl = ftbl_video_cc_mvs1_clk_src,
152
+
.clkr.hw.init = &(const struct clk_init_data) {
153
+
.name = "video_cc_mvs1_clk_src",
154
+
.parent_data = video_cc_parent_data_1,
155
+
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
156
+
.flags = CLK_SET_RATE_PARENT,
157
+
.ops = &clk_rcg2_shared_ops,
158
+
},
159
+
};
160
+
161
+
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
162
+
.reg = 0x80b8,
163
+
.shift = 0,
164
+
.width = 4,
165
+
.clkr.hw.init = &(const struct clk_init_data) {
166
+
.name = "video_cc_mvs0_div_clk_src",
167
+
.parent_hws = (const struct clk_hw*[]) {
168
+
&video_cc_mvs0_clk_src.clkr.hw,
169
+
},
170
+
.num_parents = 1,
171
+
.flags = CLK_SET_RATE_PARENT,
172
+
.ops = &clk_regmap_div_ro_ops,
173
+
},
174
+
};
175
+
176
+
static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
177
+
.reg = 0x806c,
178
+
.shift = 0,
179
+
.width = 4,
180
+
.clkr.hw.init = &(const struct clk_init_data) {
181
+
.name = "video_cc_mvs0c_div2_div_clk_src",
182
+
.parent_hws = (const struct clk_hw*[]) {
183
+
&video_cc_mvs0_clk_src.clkr.hw,
184
+
},
185
+
.num_parents = 1,
186
+
.flags = CLK_SET_RATE_PARENT,
187
+
.ops = &clk_regmap_div_ro_ops,
188
+
},
189
+
};
190
+
191
+
static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
192
+
.reg = 0x80dc,
193
+
.shift = 0,
194
+
.width = 4,
195
+
.clkr.hw.init = &(const struct clk_init_data) {
196
+
.name = "video_cc_mvs1_div_clk_src",
197
+
.parent_hws = (const struct clk_hw*[]) {
198
+
&video_cc_mvs1_clk_src.clkr.hw,
199
+
},
200
+
.num_parents = 1,
201
+
.flags = CLK_SET_RATE_PARENT,
202
+
.ops = &clk_regmap_div_ro_ops,
203
+
},
204
+
};
205
+
206
+
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
207
+
.reg = 0x8094,
208
+
.shift = 0,
209
+
.width = 4,
210
+
.clkr.hw.init = &(const struct clk_init_data) {
211
+
.name = "video_cc_mvs1c_div2_div_clk_src",
212
+
.parent_hws = (const struct clk_hw*[]) {
213
+
&video_cc_mvs1_clk_src.clkr.hw,
214
+
},
215
+
.num_parents = 1,
216
+
.flags = CLK_SET_RATE_PARENT,
217
+
.ops = &clk_regmap_div_ro_ops,
218
+
},
219
+
};
220
+
221
+
static struct clk_branch video_cc_mvs0_clk = {
222
+
.halt_reg = 0x80b0,
223
+
.halt_check = BRANCH_HALT_SKIP,
224
+
.hwcg_reg = 0x80b0,
225
+
.hwcg_bit = 1,
226
+
.clkr = {
227
+
.enable_reg = 0x80b0,
228
+
.enable_mask = BIT(0),
229
+
.hw.init = &(const struct clk_init_data) {
230
+
.name = "video_cc_mvs0_clk",
231
+
.parent_hws = (const struct clk_hw*[]) {
232
+
&video_cc_mvs0_div_clk_src.clkr.hw,
233
+
},
234
+
.num_parents = 1,
235
+
.flags = CLK_SET_RATE_PARENT,
236
+
.ops = &clk_branch2_ops,
237
+
},
238
+
},
239
+
};
240
+
241
+
static struct clk_branch video_cc_mvs0c_clk = {
242
+
.halt_reg = 0x8064,
243
+
.halt_check = BRANCH_HALT,
244
+
.clkr = {
245
+
.enable_reg = 0x8064,
246
+
.enable_mask = BIT(0),
247
+
.hw.init = &(const struct clk_init_data) {
248
+
.name = "video_cc_mvs0c_clk",
249
+
.parent_hws = (const struct clk_hw*[]) {
250
+
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
251
+
},
252
+
.num_parents = 1,
253
+
.flags = CLK_SET_RATE_PARENT,
254
+
.ops = &clk_branch2_ops,
255
+
},
256
+
},
257
+
};
258
+
259
+
static struct clk_branch video_cc_mvs1_clk = {
260
+
.halt_reg = 0x80d4,
261
+
.halt_check = BRANCH_HALT_SKIP,
262
+
.hwcg_reg = 0x80d4,
263
+
.hwcg_bit = 1,
264
+
.clkr = {
265
+
.enable_reg = 0x80d4,
266
+
.enable_mask = BIT(0),
267
+
.hw.init = &(const struct clk_init_data) {
268
+
.name = "video_cc_mvs1_clk",
269
+
.parent_hws = (const struct clk_hw*[]) {
270
+
&video_cc_mvs1_div_clk_src.clkr.hw,
271
+
},
272
+
.num_parents = 1,
273
+
.flags = CLK_SET_RATE_PARENT,
274
+
.ops = &clk_branch2_ops,
275
+
},
276
+
},
277
+
};
278
+
279
+
static struct clk_branch video_cc_mvs1c_clk = {
280
+
.halt_reg = 0x808c,
281
+
.halt_check = BRANCH_HALT,
282
+
.clkr = {
283
+
.enable_reg = 0x808c,
284
+
.enable_mask = BIT(0),
285
+
.hw.init = &(const struct clk_init_data) {
286
+
.name = "video_cc_mvs1c_clk",
287
+
.parent_hws = (const struct clk_hw*[]) {
288
+
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
289
+
},
290
+
.num_parents = 1,
291
+
.flags = CLK_SET_RATE_PARENT,
292
+
.ops = &clk_branch2_ops,
293
+
},
294
+
},
295
+
};
296
+
297
+
static struct gdsc video_cc_mvs0c_gdsc = {
298
+
.gdscr = 0x804c,
299
+
.en_rest_wait_val = 0x2,
300
+
.en_few_wait_val = 0x2,
301
+
.clk_dis_wait_val = 0x6,
302
+
.pd = {
303
+
.name = "video_cc_mvs0c_gdsc",
304
+
},
305
+
.pwrsts = PWRSTS_OFF_ON,
306
+
.flags = RETAIN_FF_ENABLE,
307
+
};
308
+
309
+
static struct gdsc video_cc_mvs0_gdsc = {
310
+
.gdscr = 0x809c,
311
+
.en_rest_wait_val = 0x2,
312
+
.en_few_wait_val = 0x2,
313
+
.clk_dis_wait_val = 0x6,
314
+
.pd = {
315
+
.name = "video_cc_mvs0_gdsc",
316
+
},
317
+
.pwrsts = PWRSTS_OFF_ON,
318
+
.parent = &video_cc_mvs0c_gdsc.pd,
319
+
.flags = RETAIN_FF_ENABLE | HW_CTRL,
320
+
};
321
+
322
+
static struct gdsc video_cc_mvs1c_gdsc = {
323
+
.gdscr = 0x8074,
324
+
.en_rest_wait_val = 0x2,
325
+
.en_few_wait_val = 0x2,
326
+
.clk_dis_wait_val = 0x6,
327
+
.pd = {
328
+
.name = "video_cc_mvs1c_gdsc",
329
+
},
330
+
.pwrsts = PWRSTS_OFF_ON,
331
+
.flags = RETAIN_FF_ENABLE,
332
+
};
333
+
334
+
static struct gdsc video_cc_mvs1_gdsc = {
335
+
.gdscr = 0x80c0,
336
+
.en_rest_wait_val = 0x2,
337
+
.en_few_wait_val = 0x2,
338
+
.clk_dis_wait_val = 0x6,
339
+
.pd = {
340
+
.name = "video_cc_mvs1_gdsc",
341
+
},
342
+
.pwrsts = PWRSTS_OFF_ON,
343
+
.parent = &video_cc_mvs1c_gdsc.pd,
344
+
.flags = RETAIN_FF_ENABLE | HW_CTRL,
345
+
};
346
+
347
+
static struct clk_regmap *video_cc_sm8450_clocks[] = {
348
+
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
349
+
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
350
+
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
351
+
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
352
+
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
353
+
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
354
+
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
355
+
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
356
+
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
357
+
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
358
+
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
359
+
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
360
+
};
361
+
362
+
static struct gdsc *video_cc_sm8450_gdscs[] = {
363
+
[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
364
+
[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
365
+
[VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
366
+
[VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
367
+
};
368
+
369
+
static const struct qcom_reset_map video_cc_sm8450_resets[] = {
370
+
[CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80e0 },
371
+
[CVP_VIDEO_CC_MVS0_BCR] = { 0x8098 },
372
+
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
373
+
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc },
374
+
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 },
375
+
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
376
+
[VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 },
377
+
};
378
+
379
+
static const struct regmap_config video_cc_sm8450_regmap_config = {
380
+
.reg_bits = 32,
381
+
.reg_stride = 4,
382
+
.val_bits = 32,
383
+
.max_register = 0x9f4c,
384
+
.fast_io = true,
385
+
};
386
+
387
+
static struct qcom_cc_desc video_cc_sm8450_desc = {
388
+
.config = &video_cc_sm8450_regmap_config,
389
+
.clks = video_cc_sm8450_clocks,
390
+
.num_clks = ARRAY_SIZE(video_cc_sm8450_clocks),
391
+
.resets = video_cc_sm8450_resets,
392
+
.num_resets = ARRAY_SIZE(video_cc_sm8450_resets),
393
+
.gdscs = video_cc_sm8450_gdscs,
394
+
.num_gdscs = ARRAY_SIZE(video_cc_sm8450_gdscs),
395
+
};
396
+
397
+
static const struct of_device_id video_cc_sm8450_match_table[] = {
398
+
{ .compatible = "qcom,sm8450-videocc" },
399
+
{ }
400
+
};
401
+
MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table);
402
+
403
+
static int video_cc_sm8450_probe(struct platform_device *pdev)
404
+
{
405
+
struct regmap *regmap;
406
+
int ret;
407
+
408
+
ret = devm_pm_runtime_enable(&pdev->dev);
409
+
if (ret)
410
+
return ret;
411
+
412
+
ret = pm_runtime_resume_and_get(&pdev->dev);
413
+
if (ret)
414
+
return ret;
415
+
416
+
regmap = qcom_cc_map(pdev, &video_cc_sm8450_desc);
417
+
if (IS_ERR(regmap)) {
418
+
pm_runtime_put(&pdev->dev);
419
+
return PTR_ERR(regmap);
420
+
}
421
+
422
+
clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
423
+
clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
424
+
425
+
/*
426
+
* Keep clocks always enabled:
427
+
* video_cc_ahb_clk
428
+
* video_cc_sleep_clk
429
+
* video_cc_xo_clk
430
+
*/
431
+
regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0));
432
+
regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0));
433
+
regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0));
434
+
435
+
ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap);
436
+
437
+
pm_runtime_put(&pdev->dev);
438
+
439
+
return ret;
440
+
}
441
+
442
+
static struct platform_driver video_cc_sm8450_driver = {
443
+
.probe = video_cc_sm8450_probe,
444
+
.driver = {
445
+
.name = "video_cc-sm8450",
446
+
.of_match_table = video_cc_sm8450_match_table,
447
+
},
448
+
};
449
+
450
+
static int __init video_cc_sm8450_init(void)
451
+
{
452
+
return platform_driver_register(&video_cc_sm8450_driver);
453
+
}
454
+
subsys_initcall(video_cc_sm8450_init);
455
+
456
+
static void __exit video_cc_sm8450_exit(void)
457
+
{
458
+
platform_driver_unregister(&video_cc_sm8450_driver);
459
+
}
460
+
module_exit(video_cc_sm8450_exit);
461
+
462
+
MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver");
463
+
MODULE_LICENSE("GPL");
+470
drivers/clk/qcom/videocc-sm8550.c
+470
drivers/clk/qcom/videocc-sm8550.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/module.h>
8
+
#include <linux/of_device.h>
9
+
#include <linux/pm_runtime.h>
10
+
#include <linux/regmap.h>
11
+
12
+
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
13
+
14
+
#include "clk-alpha-pll.h"
15
+
#include "clk-branch.h"
16
+
#include "clk-rcg.h"
17
+
#include "clk-regmap.h"
18
+
#include "clk-regmap-divider.h"
19
+
#include "common.h"
20
+
#include "gdsc.h"
21
+
#include "reset.h"
22
+
23
+
enum {
24
+
DT_BI_TCXO,
25
+
};
26
+
27
+
enum {
28
+
P_BI_TCXO,
29
+
P_VIDEO_CC_PLL0_OUT_MAIN,
30
+
P_VIDEO_CC_PLL1_OUT_MAIN,
31
+
};
32
+
33
+
static const struct pll_vco lucid_ole_vco[] = {
34
+
{ 249600000, 2300000000, 0 },
35
+
};
36
+
37
+
static const struct alpha_pll_config video_cc_pll0_config = {
38
+
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
39
+
.l = 0x44440025,
40
+
.alpha = 0x8000,
41
+
.config_ctl_val = 0x20485699,
42
+
.config_ctl_hi_val = 0x00182261,
43
+
.config_ctl_hi1_val = 0x82aa299c,
44
+
.test_ctl_val = 0x00000000,
45
+
.test_ctl_hi_val = 0x00000003,
46
+
.test_ctl_hi1_val = 0x00009000,
47
+
.test_ctl_hi2_val = 0x00000034,
48
+
.user_ctl_val = 0x00000000,
49
+
.user_ctl_hi_val = 0x00000005,
50
+
};
51
+
52
+
static struct clk_alpha_pll video_cc_pll0 = {
53
+
.offset = 0x0,
54
+
.vco_table = lucid_ole_vco,
55
+
.num_vco = ARRAY_SIZE(lucid_ole_vco),
56
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
57
+
.clkr = {
58
+
.hw.init = &(const struct clk_init_data) {
59
+
.name = "video_cc_pll0",
60
+
.parent_data = &(const struct clk_parent_data) {
61
+
.index = DT_BI_TCXO,
62
+
},
63
+
.num_parents = 1,
64
+
.ops = &clk_alpha_pll_lucid_evo_ops,
65
+
},
66
+
},
67
+
};
68
+
69
+
static const struct alpha_pll_config video_cc_pll1_config = {
70
+
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
71
+
.l = 0x44440036,
72
+
.alpha = 0xb000,
73
+
.config_ctl_val = 0x20485699,
74
+
.config_ctl_hi_val = 0x00182261,
75
+
.config_ctl_hi1_val = 0x82aa299c,
76
+
.test_ctl_val = 0x00000000,
77
+
.test_ctl_hi_val = 0x00000003,
78
+
.test_ctl_hi1_val = 0x00009000,
79
+
.test_ctl_hi2_val = 0x00000034,
80
+
.user_ctl_val = 0x00000000,
81
+
.user_ctl_hi_val = 0x00000005,
82
+
};
83
+
84
+
static struct clk_alpha_pll video_cc_pll1 = {
85
+
.offset = 0x1000,
86
+
.vco_table = lucid_ole_vco,
87
+
.num_vco = ARRAY_SIZE(lucid_ole_vco),
88
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
89
+
.clkr = {
90
+
.hw.init = &(const struct clk_init_data) {
91
+
.name = "video_cc_pll1",
92
+
.parent_data = &(const struct clk_parent_data) {
93
+
.index = DT_BI_TCXO,
94
+
},
95
+
.num_parents = 1,
96
+
.ops = &clk_alpha_pll_lucid_evo_ops,
97
+
},
98
+
},
99
+
};
100
+
101
+
static const struct parent_map video_cc_parent_map_0[] = {
102
+
{ P_BI_TCXO, 0 },
103
+
{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
104
+
};
105
+
106
+
static const struct clk_parent_data video_cc_parent_data_0[] = {
107
+
{ .index = DT_BI_TCXO },
108
+
{ .hw = &video_cc_pll0.clkr.hw },
109
+
};
110
+
111
+
static const struct parent_map video_cc_parent_map_1[] = {
112
+
{ P_BI_TCXO, 0 },
113
+
{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
114
+
};
115
+
116
+
static const struct clk_parent_data video_cc_parent_data_1[] = {
117
+
{ .index = DT_BI_TCXO },
118
+
{ .hw = &video_cc_pll1.clkr.hw },
119
+
};
120
+
121
+
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
122
+
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
123
+
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
124
+
F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
125
+
F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
126
+
F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
127
+
{ }
128
+
};
129
+
130
+
static struct clk_rcg2 video_cc_mvs0_clk_src = {
131
+
.cmd_rcgr = 0x8000,
132
+
.mnd_width = 0,
133
+
.hid_width = 5,
134
+
.parent_map = video_cc_parent_map_0,
135
+
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
136
+
.clkr.hw.init = &(const struct clk_init_data) {
137
+
.name = "video_cc_mvs0_clk_src",
138
+
.parent_data = video_cc_parent_data_0,
139
+
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
140
+
.flags = CLK_SET_RATE_PARENT,
141
+
.ops = &clk_rcg2_shared_ops,
142
+
},
143
+
};
144
+
145
+
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
146
+
F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
147
+
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
148
+
F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
149
+
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
150
+
{ }
151
+
};
152
+
153
+
static struct clk_rcg2 video_cc_mvs1_clk_src = {
154
+
.cmd_rcgr = 0x8018,
155
+
.mnd_width = 0,
156
+
.hid_width = 5,
157
+
.parent_map = video_cc_parent_map_1,
158
+
.freq_tbl = ftbl_video_cc_mvs1_clk_src,
159
+
.clkr.hw.init = &(const struct clk_init_data) {
160
+
.name = "video_cc_mvs1_clk_src",
161
+
.parent_data = video_cc_parent_data_1,
162
+
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
163
+
.flags = CLK_SET_RATE_PARENT,
164
+
.ops = &clk_rcg2_shared_ops,
165
+
},
166
+
};
167
+
168
+
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
169
+
.reg = 0x80c4,
170
+
.shift = 0,
171
+
.width = 4,
172
+
.clkr.hw.init = &(const struct clk_init_data) {
173
+
.name = "video_cc_mvs0_div_clk_src",
174
+
.parent_hws = (const struct clk_hw*[]) {
175
+
&video_cc_mvs0_clk_src.clkr.hw,
176
+
},
177
+
.num_parents = 1,
178
+
.flags = CLK_SET_RATE_PARENT,
179
+
.ops = &clk_regmap_div_ro_ops,
180
+
},
181
+
};
182
+
183
+
static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
184
+
.reg = 0x8070,
185
+
.shift = 0,
186
+
.width = 4,
187
+
.clkr.hw.init = &(const struct clk_init_data) {
188
+
.name = "video_cc_mvs0c_div2_div_clk_src",
189
+
.parent_hws = (const struct clk_hw*[]) {
190
+
&video_cc_mvs0_clk_src.clkr.hw,
191
+
},
192
+
.num_parents = 1,
193
+
.flags = CLK_SET_RATE_PARENT,
194
+
.ops = &clk_regmap_div_ro_ops,
195
+
},
196
+
};
197
+
198
+
static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
199
+
.reg = 0x80ec,
200
+
.shift = 0,
201
+
.width = 4,
202
+
.clkr.hw.init = &(const struct clk_init_data) {
203
+
.name = "video_cc_mvs1_div_clk_src",
204
+
.parent_hws = (const struct clk_hw*[]) {
205
+
&video_cc_mvs1_clk_src.clkr.hw,
206
+
},
207
+
.num_parents = 1,
208
+
.flags = CLK_SET_RATE_PARENT,
209
+
.ops = &clk_regmap_div_ro_ops,
210
+
},
211
+
};
212
+
213
+
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
214
+
.reg = 0x809c,
215
+
.shift = 0,
216
+
.width = 4,
217
+
.clkr.hw.init = &(const struct clk_init_data) {
218
+
.name = "video_cc_mvs1c_div2_div_clk_src",
219
+
.parent_hws = (const struct clk_hw*[]) {
220
+
&video_cc_mvs1_clk_src.clkr.hw,
221
+
},
222
+
.num_parents = 1,
223
+
.flags = CLK_SET_RATE_PARENT,
224
+
.ops = &clk_regmap_div_ro_ops,
225
+
},
226
+
};
227
+
228
+
static struct clk_branch video_cc_mvs0_clk = {
229
+
.halt_reg = 0x80b8,
230
+
.halt_check = BRANCH_HALT_SKIP,
231
+
.hwcg_reg = 0x80b8,
232
+
.hwcg_bit = 1,
233
+
.clkr = {
234
+
.enable_reg = 0x80b8,
235
+
.enable_mask = BIT(0),
236
+
.hw.init = &(const struct clk_init_data) {
237
+
.name = "video_cc_mvs0_clk",
238
+
.parent_hws = (const struct clk_hw*[]) {
239
+
&video_cc_mvs0_div_clk_src.clkr.hw,
240
+
},
241
+
.num_parents = 1,
242
+
.flags = CLK_SET_RATE_PARENT,
243
+
.ops = &clk_branch2_ops,
244
+
},
245
+
},
246
+
};
247
+
248
+
static struct clk_branch video_cc_mvs0c_clk = {
249
+
.halt_reg = 0x8064,
250
+
.halt_check = BRANCH_HALT,
251
+
.clkr = {
252
+
.enable_reg = 0x8064,
253
+
.enable_mask = BIT(0),
254
+
.hw.init = &(const struct clk_init_data) {
255
+
.name = "video_cc_mvs0c_clk",
256
+
.parent_hws = (const struct clk_hw*[]) {
257
+
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
258
+
},
259
+
.num_parents = 1,
260
+
.flags = CLK_SET_RATE_PARENT,
261
+
.ops = &clk_branch2_ops,
262
+
},
263
+
},
264
+
};
265
+
266
+
static struct clk_branch video_cc_mvs1_clk = {
267
+
.halt_reg = 0x80e0,
268
+
.halt_check = BRANCH_HALT_SKIP,
269
+
.hwcg_reg = 0x80e0,
270
+
.hwcg_bit = 1,
271
+
.clkr = {
272
+
.enable_reg = 0x80e0,
273
+
.enable_mask = BIT(0),
274
+
.hw.init = &(const struct clk_init_data) {
275
+
.name = "video_cc_mvs1_clk",
276
+
.parent_hws = (const struct clk_hw*[]) {
277
+
&video_cc_mvs1_div_clk_src.clkr.hw,
278
+
},
279
+
.num_parents = 1,
280
+
.flags = CLK_SET_RATE_PARENT,
281
+
.ops = &clk_branch2_ops,
282
+
},
283
+
},
284
+
};
285
+
286
+
static struct clk_branch video_cc_mvs1c_clk = {
287
+
.halt_reg = 0x8090,
288
+
.halt_check = BRANCH_HALT,
289
+
.clkr = {
290
+
.enable_reg = 0x8090,
291
+
.enable_mask = BIT(0),
292
+
.hw.init = &(const struct clk_init_data) {
293
+
.name = "video_cc_mvs1c_clk",
294
+
.parent_hws = (const struct clk_hw*[]) {
295
+
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
296
+
},
297
+
.num_parents = 1,
298
+
.flags = CLK_SET_RATE_PARENT,
299
+
.ops = &clk_branch2_ops,
300
+
},
301
+
},
302
+
};
303
+
304
+
static struct gdsc video_cc_mvs0c_gdsc = {
305
+
.gdscr = 0x804c,
306
+
.en_rest_wait_val = 0x2,
307
+
.en_few_wait_val = 0x2,
308
+
.clk_dis_wait_val = 0x6,
309
+
.pd = {
310
+
.name = "video_cc_mvs0c_gdsc",
311
+
},
312
+
.pwrsts = PWRSTS_OFF_ON,
313
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
314
+
};
315
+
316
+
static struct gdsc video_cc_mvs0_gdsc = {
317
+
.gdscr = 0x80a4,
318
+
.en_rest_wait_val = 0x2,
319
+
.en_few_wait_val = 0x2,
320
+
.clk_dis_wait_val = 0x6,
321
+
.pd = {
322
+
.name = "video_cc_mvs0_gdsc",
323
+
},
324
+
.pwrsts = PWRSTS_OFF_ON,
325
+
.parent = &video_cc_mvs0c_gdsc.pd,
326
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
327
+
};
328
+
329
+
static struct gdsc video_cc_mvs1c_gdsc = {
330
+
.gdscr = 0x8078,
331
+
.en_rest_wait_val = 0x2,
332
+
.en_few_wait_val = 0x2,
333
+
.clk_dis_wait_val = 0x6,
334
+
.pd = {
335
+
.name = "video_cc_mvs1c_gdsc",
336
+
},
337
+
.pwrsts = PWRSTS_OFF_ON,
338
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
339
+
};
340
+
341
+
static struct gdsc video_cc_mvs1_gdsc = {
342
+
.gdscr = 0x80cc,
343
+
.en_rest_wait_val = 0x2,
344
+
.en_few_wait_val = 0x2,
345
+
.clk_dis_wait_val = 0x6,
346
+
.pd = {
347
+
.name = "video_cc_mvs1_gdsc",
348
+
},
349
+
.pwrsts = PWRSTS_OFF_ON,
350
+
.parent = &video_cc_mvs1c_gdsc.pd,
351
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
352
+
};
353
+
354
+
static struct clk_regmap *video_cc_sm8550_clocks[] = {
355
+
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
356
+
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
357
+
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
358
+
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
359
+
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
360
+
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
361
+
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
362
+
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
363
+
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
364
+
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
365
+
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
366
+
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
367
+
};
368
+
369
+
static struct gdsc *video_cc_sm8550_gdscs[] = {
370
+
[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
371
+
[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
372
+
[VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
373
+
[VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
374
+
};
375
+
376
+
static const struct qcom_reset_map video_cc_sm8550_resets[] = {
377
+
[CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },
378
+
[CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 },
379
+
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
380
+
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
381
+
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
382
+
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
383
+
[VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
384
+
};
385
+
386
+
static const struct regmap_config video_cc_sm8550_regmap_config = {
387
+
.reg_bits = 32,
388
+
.reg_stride = 4,
389
+
.val_bits = 32,
390
+
.max_register = 0x9f4c,
391
+
.fast_io = true,
392
+
};
393
+
394
+
static struct qcom_cc_desc video_cc_sm8550_desc = {
395
+
.config = &video_cc_sm8550_regmap_config,
396
+
.clks = video_cc_sm8550_clocks,
397
+
.num_clks = ARRAY_SIZE(video_cc_sm8550_clocks),
398
+
.resets = video_cc_sm8550_resets,
399
+
.num_resets = ARRAY_SIZE(video_cc_sm8550_resets),
400
+
.gdscs = video_cc_sm8550_gdscs,
401
+
.num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs),
402
+
};
403
+
404
+
static const struct of_device_id video_cc_sm8550_match_table[] = {
405
+
{ .compatible = "qcom,sm8550-videocc" },
406
+
{ }
407
+
};
408
+
MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
409
+
410
+
static int video_cc_sm8550_probe(struct platform_device *pdev)
411
+
{
412
+
struct regmap *regmap;
413
+
int ret;
414
+
415
+
ret = devm_pm_runtime_enable(&pdev->dev);
416
+
if (ret)
417
+
return ret;
418
+
419
+
ret = pm_runtime_resume_and_get(&pdev->dev);
420
+
if (ret)
421
+
return ret;
422
+
423
+
regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc);
424
+
if (IS_ERR(regmap)) {
425
+
pm_runtime_put(&pdev->dev);
426
+
return PTR_ERR(regmap);
427
+
}
428
+
429
+
clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
430
+
clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
431
+
432
+
/*
433
+
* Keep clocks always enabled:
434
+
* video_cc_ahb_clk
435
+
* video_cc_sleep_clk
436
+
* video_cc_xo_clk
437
+
*/
438
+
regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0));
439
+
regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0));
440
+
regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0));
441
+
442
+
ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
443
+
444
+
pm_runtime_put(&pdev->dev);
445
+
446
+
return ret;
447
+
}
448
+
449
+
static struct platform_driver video_cc_sm8550_driver = {
450
+
.probe = video_cc_sm8550_probe,
451
+
.driver = {
452
+
.name = "video_cc-sm8550",
453
+
.of_match_table = video_cc_sm8550_match_table,
454
+
},
455
+
};
456
+
457
+
static int __init video_cc_sm8550_init(void)
458
+
{
459
+
return platform_driver_register(&video_cc_sm8550_driver);
460
+
}
461
+
subsys_initcall(video_cc_sm8550_init);
462
+
463
+
static void __exit video_cc_sm8550_exit(void)
464
+
{
465
+
platform_driver_unregister(&video_cc_sm8550_driver);
466
+
}
467
+
module_exit(video_cc_sm8550_exit);
468
+
469
+
MODULE_DESCRIPTION("QTI VIDEOCC SM8550 Driver");
470
+
MODULE_LICENSE("GPL");
+4
include/dt-bindings/clock/qcom,ipq9574-gcc.h
+4
include/dt-bindings/clock/qcom,ipq9574-gcc.h
···
210
210
#define GCC_SNOC_PCIE1_1LANE_S_CLK 201
211
211
#define GCC_SNOC_PCIE2_2LANE_S_CLK 202
212
212
#define GCC_SNOC_PCIE3_2LANE_S_CLK 203
213
+
#define GCC_CRYPTO_CLK_SRC 204
214
+
#define GCC_CRYPTO_CLK 205
215
+
#define GCC_CRYPTO_AXI_CLK 206
216
+
#define GCC_CRYPTO_AHB_CLK 207
213
217
#endif
+17
include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
+17
include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Ltd.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
7
+
#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
8
+
9
+
/* LPASS AUDIO CC CSR */
10
+
#define LPASS_AUDIO_SWR_RX_CGCR 0
11
+
#define LPASS_AUDIO_SWR_WSA_CGCR 1
12
+
#define LPASS_AUDIO_SWR_WSA2_CGCR 2
13
+
14
+
/* LPASS TCSR */
15
+
#define LPASS_AUDIO_SWR_TX_CGCR 0
16
+
17
+
#endif
+193
include/dt-bindings/clock/qcom,sdx75-gcc.h
+193
include/dt-bindings/clock/qcom,sdx75-gcc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
7
+
#define _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
8
+
9
+
/* GCC clocks */
10
+
#define GPLL0 0
11
+
#define GPLL0_OUT_EVEN 1
12
+
#define GPLL4 2
13
+
#define GPLL5 3
14
+
#define GPLL6 4
15
+
#define GPLL8 5
16
+
#define GCC_AHB_PCIE_LINK_CLK 6
17
+
#define GCC_BOOT_ROM_AHB_CLK 7
18
+
#define GCC_EEE_EMAC0_CLK 8
19
+
#define GCC_EEE_EMAC0_CLK_SRC 9
20
+
#define GCC_EEE_EMAC1_CLK 10
21
+
#define GCC_EEE_EMAC1_CLK_SRC 11
22
+
#define GCC_EMAC0_AXI_CLK 12
23
+
#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 13
24
+
#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 14
25
+
#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 15
26
+
#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 16
27
+
#define GCC_EMAC0_PHY_AUX_CLK 17
28
+
#define GCC_EMAC0_PHY_AUX_CLK_SRC 18
29
+
#define GCC_EMAC0_PTP_CLK 19
30
+
#define GCC_EMAC0_PTP_CLK_SRC 20
31
+
#define GCC_EMAC0_RGMII_CLK 21
32
+
#define GCC_EMAC0_RGMII_CLK_SRC 22
33
+
#define GCC_EMAC0_RPCS_RX_CLK 23
34
+
#define GCC_EMAC0_RPCS_TX_CLK 24
35
+
#define GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC 25
36
+
#define GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC 26
37
+
#define GCC_EMAC0_SLV_AHB_CLK 27
38
+
#define GCC_EMAC0_XGXS_RX_CLK 28
39
+
#define GCC_EMAC0_XGXS_TX_CLK 29
40
+
#define GCC_EMAC1_AXI_CLK 30
41
+
#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 31
42
+
#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 32
43
+
#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 33
44
+
#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 34
45
+
#define GCC_EMAC1_PHY_AUX_CLK 35
46
+
#define GCC_EMAC1_PHY_AUX_CLK_SRC 36
47
+
#define GCC_EMAC1_PTP_CLK 37
48
+
#define GCC_EMAC1_PTP_CLK_SRC 38
49
+
#define GCC_EMAC1_RGMII_CLK 39
50
+
#define GCC_EMAC1_RGMII_CLK_SRC 40
51
+
#define GCC_EMAC1_RPCS_RX_CLK 41
52
+
#define GCC_EMAC1_RPCS_TX_CLK 42
53
+
#define GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC 43
54
+
#define GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC 44
55
+
#define GCC_EMAC1_SLV_AHB_CLK 45
56
+
#define GCC_EMAC1_XGXS_RX_CLK 46
57
+
#define GCC_EMAC1_XGXS_TX_CLK 47
58
+
#define GCC_EMAC_0_CLKREF_EN 48
59
+
#define GCC_EMAC_1_CLKREF_EN 49
60
+
#define GCC_GP1_CLK 50
61
+
#define GCC_GP1_CLK_SRC 51
62
+
#define GCC_GP2_CLK 52
63
+
#define GCC_GP2_CLK_SRC 53
64
+
#define GCC_GP3_CLK 54
65
+
#define GCC_GP3_CLK_SRC 55
66
+
#define GCC_PCIE_0_CLKREF_EN 56
67
+
#define GCC_PCIE_1_AUX_CLK 57
68
+
#define GCC_PCIE_1_AUX_PHY_CLK_SRC 58
69
+
#define GCC_PCIE_1_CFG_AHB_CLK 59
70
+
#define GCC_PCIE_1_CLKREF_EN 60
71
+
#define GCC_PCIE_1_MSTR_AXI_CLK 61
72
+
#define GCC_PCIE_1_PHY_RCHNG_CLK 62
73
+
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 63
74
+
#define GCC_PCIE_1_PIPE_CLK 64
75
+
#define GCC_PCIE_1_PIPE_CLK_SRC 65
76
+
#define GCC_PCIE_1_PIPE_DIV2_CLK 66
77
+
#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 67
78
+
#define GCC_PCIE_1_SLV_AXI_CLK 68
79
+
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 69
80
+
#define GCC_PCIE_2_AUX_CLK 70
81
+
#define GCC_PCIE_2_AUX_PHY_CLK_SRC 71
82
+
#define GCC_PCIE_2_CFG_AHB_CLK 72
83
+
#define GCC_PCIE_2_CLKREF_EN 73
84
+
#define GCC_PCIE_2_MSTR_AXI_CLK 74
85
+
#define GCC_PCIE_2_PHY_RCHNG_CLK 75
86
+
#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 76
87
+
#define GCC_PCIE_2_PIPE_CLK 77
88
+
#define GCC_PCIE_2_PIPE_CLK_SRC 78
89
+
#define GCC_PCIE_2_PIPE_DIV2_CLK 79
90
+
#define GCC_PCIE_2_PIPE_DIV2_CLK_SRC 80
91
+
#define GCC_PCIE_2_SLV_AXI_CLK 81
92
+
#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 82
93
+
#define GCC_PCIE_AUX_CLK 83
94
+
#define GCC_PCIE_AUX_CLK_SRC 84
95
+
#define GCC_PCIE_AUX_PHY_CLK_SRC 85
96
+
#define GCC_PCIE_CFG_AHB_CLK 86
97
+
#define GCC_PCIE_MSTR_AXI_CLK 87
98
+
#define GCC_PCIE_PIPE_CLK 88
99
+
#define GCC_PCIE_PIPE_CLK_SRC 89
100
+
#define GCC_PCIE_RCHNG_PHY_CLK 90
101
+
#define GCC_PCIE_RCHNG_PHY_CLK_SRC 91
102
+
#define GCC_PCIE_SLEEP_CLK 92
103
+
#define GCC_PCIE_SLV_AXI_CLK 93
104
+
#define GCC_PCIE_SLV_Q2A_AXI_CLK 94
105
+
#define GCC_PDM2_CLK 95
106
+
#define GCC_PDM2_CLK_SRC 96
107
+
#define GCC_PDM_AHB_CLK 97
108
+
#define GCC_PDM_XO4_CLK 98
109
+
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 99
110
+
#define GCC_QUPV3_WRAP0_CORE_CLK 100
111
+
#define GCC_QUPV3_WRAP0_S0_CLK 101
112
+
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 102
113
+
#define GCC_QUPV3_WRAP0_S1_CLK 103
114
+
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 104
115
+
#define GCC_QUPV3_WRAP0_S2_CLK 105
116
+
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 106
117
+
#define GCC_QUPV3_WRAP0_S3_CLK 107
118
+
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 108
119
+
#define GCC_QUPV3_WRAP0_S4_CLK 109
120
+
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 110
121
+
#define GCC_QUPV3_WRAP0_S5_CLK 111
122
+
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 112
123
+
#define GCC_QUPV3_WRAP0_S6_CLK 113
124
+
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 114
125
+
#define GCC_QUPV3_WRAP0_S7_CLK 115
126
+
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 116
127
+
#define GCC_QUPV3_WRAP0_S8_CLK 117
128
+
#define GCC_QUPV3_WRAP0_S8_CLK_SRC 118
129
+
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 119
130
+
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 120
131
+
#define GCC_SDCC1_AHB_CLK 121
132
+
#define GCC_SDCC1_APPS_CLK 122
133
+
#define GCC_SDCC1_APPS_CLK_SRC 123
134
+
#define GCC_SDCC2_AHB_CLK 124
135
+
#define GCC_SDCC2_APPS_CLK 125
136
+
#define GCC_SDCC2_APPS_CLK_SRC 126
137
+
#define GCC_USB2_CLKREF_EN 127
138
+
#define GCC_USB30_MASTER_CLK 128
139
+
#define GCC_USB30_MASTER_CLK_SRC 129
140
+
#define GCC_USB30_MOCK_UTMI_CLK 130
141
+
#define GCC_USB30_MOCK_UTMI_CLK_SRC 131
142
+
#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 132
143
+
#define GCC_USB30_MSTR_AXI_CLK 133
144
+
#define GCC_USB30_SLEEP_CLK 134
145
+
#define GCC_USB30_SLV_AHB_CLK 135
146
+
#define GCC_USB3_PHY_AUX_CLK 136
147
+
#define GCC_USB3_PHY_AUX_CLK_SRC 137
148
+
#define GCC_USB3_PHY_PIPE_CLK 138
149
+
#define GCC_USB3_PHY_PIPE_CLK_SRC 139
150
+
#define GCC_USB3_PRIM_CLKREF_EN 140
151
+
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 141
152
+
#define GCC_XO_PCIE_LINK_CLK 142
153
+
154
+
/* GCC power domains */
155
+
#define GCC_EMAC0_GDSC 0
156
+
#define GCC_EMAC1_GDSC 1
157
+
#define GCC_PCIE_1_GDSC 2
158
+
#define GCC_PCIE_1_PHY_GDSC 3
159
+
#define GCC_PCIE_2_GDSC 4
160
+
#define GCC_PCIE_2_PHY_GDSC 5
161
+
#define GCC_PCIE_GDSC 6
162
+
#define GCC_PCIE_PHY_GDSC 7
163
+
#define GCC_USB30_GDSC 8
164
+
#define GCC_USB3_PHY_GDSC 9
165
+
166
+
/* GCC resets */
167
+
#define GCC_EMAC0_BCR 0
168
+
#define GCC_EMAC1_BCR 1
169
+
#define GCC_EMMC_BCR 2
170
+
#define GCC_PCIE_1_BCR 3
171
+
#define GCC_PCIE_1_LINK_DOWN_BCR 4
172
+
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 5
173
+
#define GCC_PCIE_1_PHY_BCR 6
174
+
#define GCC_PCIE_2_BCR 7
175
+
#define GCC_PCIE_2_LINK_DOWN_BCR 8
176
+
#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 9
177
+
#define GCC_PCIE_2_PHY_BCR 10
178
+
#define GCC_PCIE_BCR 11
179
+
#define GCC_PCIE_LINK_DOWN_BCR 12
180
+
#define GCC_PCIE_NOCSR_COM_PHY_BCR 13
181
+
#define GCC_PCIE_PHY_BCR 14
182
+
#define GCC_PCIE_PHY_CFG_AHB_BCR 15
183
+
#define GCC_PCIE_PHY_COM_BCR 16
184
+
#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 17
185
+
#define GCC_QUSB2PHY_BCR 18
186
+
#define GCC_TCSR_PCIE_BCR 19
187
+
#define GCC_USB30_BCR 20
188
+
#define GCC_USB3_PHY_BCR 21
189
+
#define GCC_USB3PHY_PHY_BCR 22
190
+
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
191
+
#define GCC_EMAC0_RGMII_CLK_ARES 24
192
+
193
+
#endif
+35
include/dt-bindings/clock/qcom,sm8350-videocc.h
+35
include/dt-bindings/clock/qcom,sm8350-videocc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H
8
+
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H
9
+
10
+
/* Clocks */
11
+
#define VIDEO_CC_AHB_CLK_SRC 0
12
+
#define VIDEO_CC_MVS0_CLK 1
13
+
#define VIDEO_CC_MVS0_CLK_SRC 2
14
+
#define VIDEO_CC_MVS0_DIV_CLK_SRC 3
15
+
#define VIDEO_CC_MVS0C_CLK 4
16
+
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 5
17
+
#define VIDEO_CC_MVS1_CLK 6
18
+
#define VIDEO_CC_MVS1_CLK_SRC 7
19
+
#define VIDEO_CC_MVS1_DIV2_CLK 8
20
+
#define VIDEO_CC_MVS1_DIV_CLK_SRC 9
21
+
#define VIDEO_CC_MVS1C_CLK 10
22
+
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11
23
+
#define VIDEO_CC_SLEEP_CLK 12
24
+
#define VIDEO_CC_SLEEP_CLK_SRC 13
25
+
#define VIDEO_CC_XO_CLK_SRC 14
26
+
#define VIDEO_PLL0 15
27
+
#define VIDEO_PLL1 16
28
+
29
+
/* GDSCs */
30
+
#define MVS0C_GDSC 0
31
+
#define MVS1C_GDSC 1
32
+
#define MVS0_GDSC 2
33
+
#define MVS1_GDSC 3
34
+
35
+
#endif
+48
include/dt-bindings/clock/qcom,sm8450-gpucc.h
+48
include/dt-bindings/clock/qcom,sm8450-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H
8
+
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H
9
+
10
+
/* Clocks */
11
+
#define GPU_CC_AHB_CLK 0
12
+
#define GPU_CC_CRC_AHB_CLK 1
13
+
#define GPU_CC_CX_APB_CLK 2
14
+
#define GPU_CC_CX_FF_CLK 3
15
+
#define GPU_CC_CX_GMU_CLK 4
16
+
#define GPU_CC_CX_SNOC_DVM_CLK 5
17
+
#define GPU_CC_CXO_AON_CLK 6
18
+
#define GPU_CC_CXO_CLK 7
19
+
#define GPU_CC_DEMET_CLK 8
20
+
#define GPU_CC_DEMET_DIV_CLK_SRC 9
21
+
#define GPU_CC_FF_CLK_SRC 10
22
+
#define GPU_CC_FREQ_MEASURE_CLK 11
23
+
#define GPU_CC_GMU_CLK_SRC 12
24
+
#define GPU_CC_GX_FF_CLK 13
25
+
#define GPU_CC_GX_GFX3D_CLK 14
26
+
#define GPU_CC_GX_GFX3D_RDVM_CLK 15
27
+
#define GPU_CC_GX_GMU_CLK 16
28
+
#define GPU_CC_GX_VSENSE_CLK 17
29
+
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18
30
+
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 19
31
+
#define GPU_CC_HUB_AON_CLK 20
32
+
#define GPU_CC_HUB_CLK_SRC 21
33
+
#define GPU_CC_HUB_CX_INT_CLK 22
34
+
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 23
35
+
#define GPU_CC_MEMNOC_GFX_CLK 24
36
+
#define GPU_CC_MND1X_0_GFX3D_CLK 25
37
+
#define GPU_CC_MND1X_1_GFX3D_CLK 26
38
+
#define GPU_CC_PLL0 27
39
+
#define GPU_CC_PLL1 28
40
+
#define GPU_CC_SLEEP_CLK 29
41
+
#define GPU_CC_XO_CLK_SRC 30
42
+
#define GPU_CC_XO_DIV_CLK_SRC 31
43
+
44
+
/* GDSCs */
45
+
#define GPU_GX_GDSC 0
46
+
#define GPU_CX_GDSC 1
47
+
48
+
#endif
+38
include/dt-bindings/clock/qcom,sm8450-videocc.h
+38
include/dt-bindings/clock/qcom,sm8450-videocc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
7
+
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
8
+
9
+
/* VIDEO_CC clocks */
10
+
#define VIDEO_CC_MVS0_CLK 0
11
+
#define VIDEO_CC_MVS0_CLK_SRC 1
12
+
#define VIDEO_CC_MVS0_DIV_CLK_SRC 2
13
+
#define VIDEO_CC_MVS0C_CLK 3
14
+
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4
15
+
#define VIDEO_CC_MVS1_CLK 5
16
+
#define VIDEO_CC_MVS1_CLK_SRC 6
17
+
#define VIDEO_CC_MVS1_DIV_CLK_SRC 7
18
+
#define VIDEO_CC_MVS1C_CLK 8
19
+
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9
20
+
#define VIDEO_CC_PLL0 10
21
+
#define VIDEO_CC_PLL1 11
22
+
23
+
/* VIDEO_CC power domains */
24
+
#define VIDEO_CC_MVS0C_GDSC 0
25
+
#define VIDEO_CC_MVS0_GDSC 1
26
+
#define VIDEO_CC_MVS1C_GDSC 2
27
+
#define VIDEO_CC_MVS1_GDSC 3
28
+
29
+
/* VIDEO_CC resets */
30
+
#define CVP_VIDEO_CC_INTERFACE_BCR 0
31
+
#define CVP_VIDEO_CC_MVS0_BCR 1
32
+
#define CVP_VIDEO_CC_MVS0C_BCR 2
33
+
#define CVP_VIDEO_CC_MVS1_BCR 3
34
+
#define CVP_VIDEO_CC_MVS1C_BCR 4
35
+
#define VIDEO_CC_MVS0C_CLK_ARES 5
36
+
#define VIDEO_CC_MVS1C_CLK_ARES 6
37
+
38
+
#endif
+48
include/dt-bindings/clock/qcom,sm8550-gpucc.h
+48
include/dt-bindings/clock/qcom,sm8550-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
7
+
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
8
+
9
+
/* GPU_CC clocks */
10
+
#define GPU_CC_AHB_CLK 0
11
+
#define GPU_CC_CRC_AHB_CLK 1
12
+
#define GPU_CC_CX_FF_CLK 2
13
+
#define GPU_CC_CX_GMU_CLK 3
14
+
#define GPU_CC_CXO_AON_CLK 4
15
+
#define GPU_CC_CXO_CLK 5
16
+
#define GPU_CC_DEMET_CLK 6
17
+
#define GPU_CC_DEMET_DIV_CLK_SRC 7
18
+
#define GPU_CC_FF_CLK_SRC 8
19
+
#define GPU_CC_FREQ_MEASURE_CLK 9
20
+
#define GPU_CC_GMU_CLK_SRC 10
21
+
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11
22
+
#define GPU_CC_HUB_AON_CLK 12
23
+
#define GPU_CC_HUB_CLK_SRC 13
24
+
#define GPU_CC_HUB_CX_INT_CLK 14
25
+
#define GPU_CC_MEMNOC_GFX_CLK 15
26
+
#define GPU_CC_MND1X_0_GFX3D_CLK 16
27
+
#define GPU_CC_MND1X_1_GFX3D_CLK 17
28
+
#define GPU_CC_PLL0 18
29
+
#define GPU_CC_PLL1 19
30
+
#define GPU_CC_SLEEP_CLK 20
31
+
#define GPU_CC_XO_CLK_SRC 21
32
+
#define GPU_CC_XO_DIV_CLK_SRC 22
33
+
34
+
/* GPU_CC power domains */
35
+
#define GPU_CC_CX_GDSC 0
36
+
#define GPU_CC_GX_GDSC 1
37
+
38
+
/* GPU_CC resets */
39
+
#define GPUCC_GPU_CC_ACD_BCR 0
40
+
#define GPUCC_GPU_CC_CX_BCR 1
41
+
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
42
+
#define GPUCC_GPU_CC_FF_BCR 3
43
+
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
44
+
#define GPUCC_GPU_CC_GMU_BCR 5
45
+
#define GPUCC_GPU_CC_GX_BCR 6
46
+
#define GPUCC_GPU_CC_XO_BCR 7
47
+
48
+
#endif
+1
include/dt-bindings/reset/qcom,ipq9574-gcc.h
+1
include/dt-bindings/reset/qcom,ipq9574-gcc.h
+18
include/dt-bindings/reset/qcom,sm8350-videocc.h
+18
include/dt-bindings/reset/qcom,sm8350-videocc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H
8
+
#define _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H
9
+
10
+
#define VIDEO_CC_CVP_INTERFACE_BCR 0
11
+
#define VIDEO_CC_CVP_MVS0_BCR 1
12
+
#define VIDEO_CC_MVS0C_CLK_ARES 2
13
+
#define VIDEO_CC_CVP_MVS0C_BCR 3
14
+
#define VIDEO_CC_CVP_MVS1_BCR 4
15
+
#define VIDEO_CC_MVS1C_CLK_ARES 5
16
+
#define VIDEO_CC_CVP_MVS1C_BCR 6
17
+
18
+
#endif
+20
include/dt-bindings/reset/qcom,sm8450-gpucc.h
+20
include/dt-bindings/reset/qcom,sm8450-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H
8
+
#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H
9
+
10
+
#define GPUCC_GPU_CC_ACD_BCR 0
11
+
#define GPUCC_GPU_CC_CX_BCR 1
12
+
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
13
+
#define GPUCC_GPU_CC_FF_BCR 3
14
+
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
15
+
#define GPUCC_GPU_CC_GMU_BCR 5
16
+
#define GPUCC_GPU_CC_GX_BCR 6
17
+
#define GPUCC_GPU_CC_XO_BCR 7
18
+
#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8
19
+
20
+
#endif