tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amd/display: Remove useless comparison of unsigned int vs. 0

[WHY & HOW]
The comparisons of unsigned int with 0 can have no meanings, i.e.
unsigned int >= 0 (always true) or unsigned int < 0 (always false), and
therefore they are removed.

This fixes 12 NO_EFFECT issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Alex Hung and committed by
Alex Deucher 82c94233 97dc6a48

+20 -25
+4 -4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
··· 320 320 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; 321 321 322 322 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; 323 - if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4) 323 + if (regs_and_bypass->dppclk_bypass > 4) 324 324 regs_and_bypass->dppclk_bypass = 0; 325 325 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; 326 - if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4) 326 + if (regs_and_bypass->dcfclk_bypass > 4) 327 327 regs_and_bypass->dcfclk_bypass = 0; 328 328 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; 329 - if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4) 329 + if (regs_and_bypass->dispclk_bypass > 4) 330 330 regs_and_bypass->dispclk_bypass = 0; 331 331 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; 332 - if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4) 332 + if (regs_and_bypass->dprefclk_bypass > 4) 333 333 regs_and_bypass->dprefclk_bypass = 0; 334 334 335 335 if (log_info->enabled) {
+4 -4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
··· 252 252 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; 253 253 254 254 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; 255 - if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4) 255 + if (regs_and_bypass->dppclk_bypass > 4) 256 256 regs_and_bypass->dppclk_bypass = 0; 257 257 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; 258 - if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4) 258 + if (regs_and_bypass->dcfclk_bypass > 4) 259 259 regs_and_bypass->dcfclk_bypass = 0; 260 260 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; 261 - if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4) 261 + if (regs_and_bypass->dispclk_bypass > 4) 262 262 regs_and_bypass->dispclk_bypass = 0; 263 263 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; 264 - if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4) 264 + if (regs_and_bypass->dprefclk_bypass > 4) 265 265 regs_and_bypass->dprefclk_bypass = 0; 266 266 267 267 if (log_info->enabled) {
+2 -4
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
··· 642 642 program_tiling(dce_mi, tiling_info); 643 643 program_size_and_rotation(dce_mi, rotation, plane_size); 644 644 645 - if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN && 646 - format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 645 + if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 647 646 program_grph_pixel_format(dce_mi, format); 648 647 } 649 648 ··· 662 663 program_tiling(dce_mi, tiling_info); 663 664 dce60_program_size(dce_mi, rotation, plane_size); 664 665 665 - if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN && 666 - format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 666 + if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 667 667 program_grph_pixel_format(dce_mi, format); 668 668 } 669 669 #endif
+3 -3
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c
··· 359 359 if (pg_cntl->ctx->dc->idle_optimizations_allowed) 360 360 return; 361 361 362 - if (mpcc_inst >= 0 && mpcc_inst < MAX_PIPES) 362 + if (mpcc_inst < MAX_PIPES) 363 363 pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on; 364 364 } 365 365 ··· 369 369 if (pg_cntl->ctx->dc->idle_optimizations_allowed) 370 370 return; 371 371 372 - if (opp_inst >= 0 && opp_inst < MAX_PIPES) 372 + if (opp_inst < MAX_PIPES) 373 373 pg_cntl->pg_pipe_res_enable[PG_OPP][opp_inst] = power_on; 374 374 } 375 375 ··· 379 379 if (pg_cntl->ctx->dc->idle_optimizations_allowed) 380 380 return; 381 381 382 - if (optc_inst >= 0 && optc_inst < MAX_PIPES) 382 + if (optc_inst < MAX_PIPES) 383 383 pg_cntl->pg_pipe_res_enable[PG_OPTC][optc_inst] = power_on; 384 384 } 385 385
+4 -7
drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
··· 170 170 171 171 return GPIO_RESULT_OK; 172 172 case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT: 173 - if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 174 - (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 173 + if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) { 175 174 REG_UPDATE_3(ddc_setup, 176 175 DC_I2C_DDC1_ENABLE, 1, 177 176 DC_I2C_DDC1_EDID_DETECT_ENABLE, 1, ··· 179 180 } 180 181 break; 181 182 case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT: 182 - if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 183 - (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 183 + if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) { 184 184 REG_UPDATE_3(ddc_setup, 185 185 DC_I2C_DDC1_ENABLE, 1, 186 186 DC_I2C_DDC1_EDID_DETECT_ENABLE, 1, ··· 188 190 } 189 191 break; 190 192 case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING: 191 - if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 192 - (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 193 + if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) { 193 194 REG_UPDATE_2(ddc_setup, 194 195 DC_I2C_DDC1_ENABLE, 0, 195 196 DC_I2C_DDC1_EDID_DETECT_ENABLE, 0); ··· 228 231 enum gpio_id id, 229 232 uint32_t en) 230 233 { 231 - if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) { 234 + if (en > GPIO_DDC_LINE_MAX) { 232 235 ASSERT_CRITICAL(false); 233 236 *hw_ddc = NULL; 234 237 }
+1 -1
drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
··· 106 106 enum gpio_id id, 107 107 uint32_t en) 108 108 { 109 - if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) { 109 + if (en > GPIO_DDC_LINE_MAX) { 110 110 ASSERT_CRITICAL(false); 111 111 *hw_generic = NULL; 112 112 }
+1 -1
drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
··· 127 127 enum gpio_id id, 128 128 uint32_t en) 129 129 { 130 - if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) { 130 + if (en > GPIO_DDC_LINE_MAX) { 131 131 ASSERT_CRITICAL(false); 132 132 *hw_hpd = NULL; 133 133 }
+1 -1
drivers/gpu/drm/amd/display/dc/irq/irq_service.c
··· 76 76 struct irq_service *irq_service, 77 77 enum dc_irq_source source) 78 78 { 79 - if (source >= DAL_IRQ_SOURCES_NUMBER || source < DC_IRQ_SOURCE_INVALID) 79 + if (source >= DAL_IRQ_SOURCES_NUMBER) 80 80 return NULL; 81 81 82 82 return &irq_service->info[source];