tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: memory: tegra20: Add memory client IDs
Each memory client has unique hardware ID, add these IDs.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
authored by
Dmitry Osipenko
and committed by
Thierry Reding
825c7f4a
3650b228
+53
+53
include/dt-bindings/memory/tegra20-mc.h
+53
include/dt-bindings/memory/tegra20-mc.h
···
18
18
#define TEGRA20_MC_RESET_VDE 13
19
19
#define TEGRA20_MC_RESET_VI 14
20
20
21
+
#define TEGRA20_MC_DISPLAY0A 0
22
+
#define TEGRA20_MC_DISPLAY0AB 1
23
+
#define TEGRA20_MC_DISPLAY0B 2
24
+
#define TEGRA20_MC_DISPLAY0BB 3
25
+
#define TEGRA20_MC_DISPLAY0C 4
26
+
#define TEGRA20_MC_DISPLAY0CB 5
27
+
#define TEGRA20_MC_DISPLAY1B 6
28
+
#define TEGRA20_MC_DISPLAY1BB 7
29
+
#define TEGRA20_MC_EPPUP 8
30
+
#define TEGRA20_MC_G2PR 9
31
+
#define TEGRA20_MC_G2SR 10
32
+
#define TEGRA20_MC_MPEUNIFBR 11
33
+
#define TEGRA20_MC_VIRUV 12
34
+
#define TEGRA20_MC_AVPCARM7R 13
35
+
#define TEGRA20_MC_DISPLAYHC 14
36
+
#define TEGRA20_MC_DISPLAYHCB 15
37
+
#define TEGRA20_MC_FDCDRD 16
38
+
#define TEGRA20_MC_G2DR 17
39
+
#define TEGRA20_MC_HOST1XDMAR 18
40
+
#define TEGRA20_MC_HOST1XR 19
41
+
#define TEGRA20_MC_IDXSRD 20
42
+
#define TEGRA20_MC_MPCORER 21
43
+
#define TEGRA20_MC_MPE_IPRED 22
44
+
#define TEGRA20_MC_MPEAMEMRD 23
45
+
#define TEGRA20_MC_MPECSRD 24
46
+
#define TEGRA20_MC_PPCSAHBDMAR 25
47
+
#define TEGRA20_MC_PPCSAHBSLVR 26
48
+
#define TEGRA20_MC_TEXSRD 27
49
+
#define TEGRA20_MC_VDEBSEVR 28
50
+
#define TEGRA20_MC_VDEMBER 29
51
+
#define TEGRA20_MC_VDEMCER 30
52
+
#define TEGRA20_MC_VDETPER 31
53
+
#define TEGRA20_MC_EPPU 32
54
+
#define TEGRA20_MC_EPPV 33
55
+
#define TEGRA20_MC_EPPY 34
56
+
#define TEGRA20_MC_MPEUNIFBW 35
57
+
#define TEGRA20_MC_VIWSB 36
58
+
#define TEGRA20_MC_VIWU 37
59
+
#define TEGRA20_MC_VIWV 38
60
+
#define TEGRA20_MC_VIWY 39
61
+
#define TEGRA20_MC_G2DW 40
62
+
#define TEGRA20_MC_AVPCARM7W 41
63
+
#define TEGRA20_MC_FDCDWR 42
64
+
#define TEGRA20_MC_HOST1XW 43
65
+
#define TEGRA20_MC_ISPW 44
66
+
#define TEGRA20_MC_MPCOREW 45
67
+
#define TEGRA20_MC_MPECSWR 46
68
+
#define TEGRA20_MC_PPCSAHBDMAW 47
69
+
#define TEGRA20_MC_PPCSAHBSLVW 48
70
+
#define TEGRA20_MC_VDEBSEVW 49
71
+
#define TEGRA20_MC_VDEMBEW 50
72
+
#define TEGRA20_MC_VDETPMW 51
73
+
21
74
#endif