tjh.dev
+5
-2
Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
+5
-2
Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
···
1
1
* Advanced Interrupt Controller (AIC)
2
2
3
3
Required properties:
4
-
- compatible: Should be "atmel,<chip>-aic"
5
-
<chip> can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4"
4
+
- compatible: Should be:
5
+
- "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
6
+
"sama5d3" or "sama5d4"
7
+
- "microchip,<chip>-aic" where <chip> can be "sam9x60"
8
+
6
9
- interrupt-controller: Identifies the node as an interrupt controller.
7
10
- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
8
11
The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
+12
drivers/irqchip/irq-al-fic.c
+12
drivers/irqchip/irq-al-fic.c
···
15
15
16
16
/* FIC Registers */
17
17
#define AL_FIC_CAUSE 0x00
18
+
#define AL_FIC_SET_CAUSE 0x08
18
19
#define AL_FIC_MASK 0x10
19
20
#define AL_FIC_CONTROL 0x28
20
21
···
127
126
chained_irq_exit(irqchip, desc);
128
127
}
129
128
129
+
static int al_fic_irq_retrigger(struct irq_data *data)
130
+
{
131
+
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
132
+
struct al_fic *fic = gc->private;
133
+
134
+
writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE);
135
+
136
+
return 1;
137
+
}
138
+
130
139
static int al_fic_register(struct device_node *node,
131
140
struct al_fic *fic)
132
141
{
···
170
159
gc->chip_types->chip.irq_unmask = irq_gc_mask_clr_bit;
171
160
gc->chip_types->chip.irq_ack = irq_gc_ack_clr_bit;
172
161
gc->chip_types->chip.irq_set_type = al_fic_irq_set_type;
162
+
gc->chip_types->chip.irq_retrigger = al_fic_irq_retrigger;
173
163
gc->chip_types->chip.flags = IRQCHIP_SKIP_SET_WAKE;
174
164
gc->private = fic;
175
165
+10
drivers/irqchip/irq-atmel-aic5.c
+10
drivers/irqchip/irq-atmel-aic5.c
···
313
313
static const struct of_device_id aic5_irq_fixups[] __initconst = {
314
314
{ .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup },
315
315
{ .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup },
316
+
{ .compatible = "microchip,sam9x60", .data = sama5d3_aic_irq_fixup },
316
317
{ /* sentinel */ },
317
318
};
318
319
···
391
390
return aic5_of_init(node, parent, NR_SAMA5D4_IRQS);
392
391
}
393
392
IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init);
393
+
394
+
#define NR_SAM9X60_IRQS 50
395
+
396
+
static int __init sam9x60_aic5_of_init(struct device_node *node,
397
+
struct device_node *parent)
398
+
{
399
+
return aic5_of_init(node, parent, NR_SAM9X60_IRQS);
400
+
}
401
+
IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init);
+1
-1
drivers/irqchip/irq-gic-v3.c
+1
-1
drivers/irqchip/irq-gic-v3.c
···
59
59
static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
60
60
61
61
#define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
62
-
#define GIC_LINE_NR max(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
62
+
#define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
63
63
#define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
64
64
65
65
/*
+15
-14
drivers/irqchip/irq-sifive-plic.c
+15
-14
drivers/irqchip/irq-sifive-plic.c
···
97
97
}
98
98
}
99
99
100
-
static void plic_irq_enable(struct irq_data *d)
100
+
static void plic_irq_unmask(struct irq_data *d)
101
101
{
102
102
unsigned int cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
103
103
cpu_online_mask);
···
106
106
plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);
107
107
}
108
108
109
-
static void plic_irq_disable(struct irq_data *d)
109
+
static void plic_irq_mask(struct irq_data *d)
110
110
{
111
111
plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);
112
112
}
···
125
125
if (cpu >= nr_cpu_ids)
126
126
return -EINVAL;
127
127
128
-
if (!irqd_irq_disabled(d)) {
129
-
plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);
130
-
plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);
131
-
}
128
+
plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);
129
+
plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);
132
130
133
131
irq_data_update_effective_affinity(d, cpumask_of(cpu));
134
132
···
134
136
}
135
137
#endif
136
138
139
+
static void plic_irq_eoi(struct irq_data *d)
140
+
{
141
+
struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
142
+
143
+
writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
144
+
}
145
+
137
146
static struct irq_chip plic_chip = {
138
147
.name = "SiFive PLIC",
139
-
/*
140
-
* There is no need to mask/unmask PLIC interrupts. They are "masked"
141
-
* by reading claim and "unmasked" when writing it back.
142
-
*/
143
-
.irq_enable = plic_irq_enable,
144
-
.irq_disable = plic_irq_disable,
148
+
.irq_mask = plic_irq_mask,
149
+
.irq_unmask = plic_irq_unmask,
150
+
.irq_eoi = plic_irq_eoi,
145
151
#ifdef CONFIG_SMP
146
152
.irq_set_affinity = plic_set_affinity,
147
153
#endif
···
154
152
static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
155
153
irq_hw_number_t hwirq)
156
154
{
157
-
irq_set_chip_and_handler(irq, &plic_chip, handle_simple_irq);
155
+
irq_set_chip_and_handler(irq, &plic_chip, handle_fasteoi_irq);
158
156
irq_set_chip_data(irq, NULL);
159
157
irq_set_noprobe(irq);
160
158
return 0;
···
190
188
hwirq);
191
189
else
192
190
generic_handle_irq(irq);
193
-
writel(hwirq, claim);
194
191
}
195
192
csr_set(sie, SIE_SEIE);
196
193
}